1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@st.com> 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-direction.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/spinlock.h> 30 #include <linux/sysrq.h> 31 #include <linux/tty_flip.h> 32 #include <linux/tty.h> 33 34 #include "serial_mctrl_gpio.h" 35 #include "stm32-usart.h" 36 37 static void stm32_stop_tx(struct uart_port *port); 38 static void stm32_transmit_chars(struct uart_port *port); 39 40 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41 { 42 return container_of(port, struct stm32_port, port); 43 } 44 45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 46 { 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52 } 53 54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55 { 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61 } 62 63 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 64 u32 delay_DDE, u32 baud) 65 { 66 u32 rs485_deat_dedt; 67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 68 bool over8; 69 70 *cr3 |= USART_CR3_DEM; 71 over8 = *cr1 & USART_CR1_OVER8; 72 73 if (over8) 74 rs485_deat_dedt = delay_ADE * baud * 8; 75 else 76 rs485_deat_dedt = delay_ADE * baud * 16; 77 78 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 79 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 80 rs485_deat_dedt_max : rs485_deat_dedt; 81 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 82 USART_CR1_DEAT_MASK; 83 *cr1 |= rs485_deat_dedt; 84 85 if (over8) 86 rs485_deat_dedt = delay_DDE * baud * 8; 87 else 88 rs485_deat_dedt = delay_DDE * baud * 16; 89 90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 92 rs485_deat_dedt_max : rs485_deat_dedt; 93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 94 USART_CR1_DEDT_MASK; 95 *cr1 |= rs485_deat_dedt; 96 } 97 98 static int stm32_config_rs485(struct uart_port *port, 99 struct serial_rs485 *rs485conf) 100 { 101 struct stm32_port *stm32_port = to_stm32_port(port); 102 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 103 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 104 u32 usartdiv, baud, cr1, cr3; 105 bool over8; 106 107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 108 109 port->rs485 = *rs485conf; 110 111 rs485conf->flags |= SER_RS485_RX_DURING_TX; 112 113 if (rs485conf->flags & SER_RS485_ENABLED) { 114 cr1 = readl_relaxed(port->membase + ofs->cr1); 115 cr3 = readl_relaxed(port->membase + ofs->cr3); 116 usartdiv = readl_relaxed(port->membase + ofs->brr); 117 usartdiv = usartdiv & GENMASK(15, 0); 118 over8 = cr1 & USART_CR1_OVER8; 119 120 if (over8) 121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 122 << USART_BRR_04_R_SHIFT; 123 124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 125 stm32_config_reg_rs485(&cr1, &cr3, 126 rs485conf->delay_rts_before_send, 127 rs485conf->delay_rts_after_send, baud); 128 129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 130 cr3 &= ~USART_CR3_DEP; 131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 132 } else { 133 cr3 |= USART_CR3_DEP; 134 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 135 } 136 137 writel_relaxed(cr3, port->membase + ofs->cr3); 138 writel_relaxed(cr1, port->membase + ofs->cr1); 139 } else { 140 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); 141 stm32_clr_bits(port, ofs->cr1, 142 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 143 } 144 145 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 146 147 return 0; 148 } 149 150 static int stm32_init_rs485(struct uart_port *port, 151 struct platform_device *pdev) 152 { 153 struct serial_rs485 *rs485conf = &port->rs485; 154 155 rs485conf->flags = 0; 156 rs485conf->delay_rts_before_send = 0; 157 rs485conf->delay_rts_after_send = 0; 158 159 if (!pdev->dev.of_node) 160 return -ENODEV; 161 162 uart_get_rs485_mode(&pdev->dev, rs485conf); 163 164 return 0; 165 } 166 167 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 168 bool threaded) 169 { 170 struct stm32_port *stm32_port = to_stm32_port(port); 171 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 172 enum dma_status status; 173 struct dma_tx_state state; 174 175 *sr = readl_relaxed(port->membase + ofs->isr); 176 177 if (threaded && stm32_port->rx_ch) { 178 status = dmaengine_tx_status(stm32_port->rx_ch, 179 stm32_port->rx_ch->cookie, 180 &state); 181 if ((status == DMA_IN_PROGRESS) && 182 (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c; 218 u32 sr; 219 char flag; 220 221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 222 pm_wakeup_event(tport->tty->dev, 0); 223 224 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 225 sr |= USART_SR_DUMMY_RX; 226 flag = TTY_NORMAL; 227 228 /* 229 * Status bits has to be cleared before reading the RDR: 230 * In FIFO mode, reading the RDR will pop the next data 231 * (if any) along with its status bits into the SR. 232 * Not doing so leads to misalignement between RDR and SR, 233 * and clear status bits of the next rx data. 234 * 235 * Clear errors flags for stm32f7 and stm32h7 compatible 236 * devices. On stm32f4 compatible devices, the error bit is 237 * cleared by the sequence [read SR - read DR]. 238 */ 239 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 240 writel_relaxed(sr & USART_SR_ERR_MASK, 241 port->membase + ofs->icr); 242 243 c = stm32_get_char(port, &sr, &stm32_port->last_res); 244 port->icount.rx++; 245 if (sr & USART_SR_ERR_MASK) { 246 if (sr & USART_SR_ORE) { 247 port->icount.overrun++; 248 } else if (sr & USART_SR_PE) { 249 port->icount.parity++; 250 } else if (sr & USART_SR_FE) { 251 /* Break detection if character is null */ 252 if (!c) { 253 port->icount.brk++; 254 if (uart_handle_break(port)) 255 continue; 256 } else { 257 port->icount.frame++; 258 } 259 } 260 261 sr &= port->read_status_mask; 262 263 if (sr & USART_SR_PE) { 264 flag = TTY_PARITY; 265 } else if (sr & USART_SR_FE) { 266 if (!c) 267 flag = TTY_BREAK; 268 else 269 flag = TTY_FRAME; 270 } 271 } 272 273 if (uart_handle_sysrq_char(port, c)) 274 continue; 275 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 276 } 277 278 spin_unlock(&port->lock); 279 tty_flip_buffer_push(tport); 280 spin_lock(&port->lock); 281 } 282 283 static void stm32_tx_dma_complete(void *arg) 284 { 285 struct uart_port *port = arg; 286 struct stm32_port *stm32port = to_stm32_port(port); 287 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 288 289 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 290 stm32port->tx_dma_busy = false; 291 292 /* Let's see if we have pending data to send */ 293 stm32_transmit_chars(port); 294 } 295 296 static void stm32_tx_interrupt_enable(struct uart_port *port) 297 { 298 struct stm32_port *stm32_port = to_stm32_port(port); 299 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 300 301 /* 302 * Enables TX FIFO threashold irq when FIFO is enabled, 303 * or TX empty irq when FIFO is disabled 304 */ 305 if (stm32_port->fifoen) 306 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 307 else 308 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 309 } 310 311 static void stm32_tx_interrupt_disable(struct uart_port *port) 312 { 313 struct stm32_port *stm32_port = to_stm32_port(port); 314 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 315 316 if (stm32_port->fifoen) 317 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 318 else 319 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 320 } 321 322 static void stm32_transmit_chars_pio(struct uart_port *port) 323 { 324 struct stm32_port *stm32_port = to_stm32_port(port); 325 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 326 struct circ_buf *xmit = &port->state->xmit; 327 328 if (stm32_port->tx_dma_busy) { 329 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 330 stm32_port->tx_dma_busy = false; 331 } 332 333 while (!uart_circ_empty(xmit)) { 334 /* Check that TDR is empty before filling FIFO */ 335 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 336 break; 337 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 338 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 339 port->icount.tx++; 340 } 341 342 /* rely on TXE irq (mask or unmask) for sending remaining data */ 343 if (uart_circ_empty(xmit)) 344 stm32_tx_interrupt_disable(port); 345 else 346 stm32_tx_interrupt_enable(port); 347 } 348 349 static void stm32_transmit_chars_dma(struct uart_port *port) 350 { 351 struct stm32_port *stm32port = to_stm32_port(port); 352 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 353 struct circ_buf *xmit = &port->state->xmit; 354 struct dma_async_tx_descriptor *desc = NULL; 355 dma_cookie_t cookie; 356 unsigned int count, i; 357 358 if (stm32port->tx_dma_busy) 359 return; 360 361 stm32port->tx_dma_busy = true; 362 363 count = uart_circ_chars_pending(xmit); 364 365 if (count > TX_BUF_L) 366 count = TX_BUF_L; 367 368 if (xmit->tail < xmit->head) { 369 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 370 } else { 371 size_t one = UART_XMIT_SIZE - xmit->tail; 372 size_t two; 373 374 if (one > count) 375 one = count; 376 two = count - one; 377 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 379 if (two) 380 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 381 } 382 383 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 384 stm32port->tx_dma_buf, 385 count, 386 DMA_MEM_TO_DEV, 387 DMA_PREP_INTERRUPT); 388 389 if (!desc) { 390 for (i = count; i > 0; i--) 391 stm32_transmit_chars_pio(port); 392 return; 393 } 394 395 desc->callback = stm32_tx_dma_complete; 396 desc->callback_param = port; 397 398 /* Push current DMA TX transaction in the pending queue */ 399 cookie = dmaengine_submit(desc); 400 401 /* Issue pending DMA TX requests */ 402 dma_async_issue_pending(stm32port->tx_ch); 403 404 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 405 406 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 407 port->icount.tx += count; 408 } 409 410 static void stm32_transmit_chars(struct uart_port *port) 411 { 412 struct stm32_port *stm32_port = to_stm32_port(port); 413 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 414 struct circ_buf *xmit = &port->state->xmit; 415 416 if (port->x_char) { 417 if (stm32_port->tx_dma_busy) 418 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 419 writel_relaxed(port->x_char, port->membase + ofs->tdr); 420 port->x_char = 0; 421 port->icount.tx++; 422 if (stm32_port->tx_dma_busy) 423 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 424 return; 425 } 426 427 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 428 stm32_tx_interrupt_disable(port); 429 return; 430 } 431 432 if (ofs->icr == UNDEF_REG) 433 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 434 else 435 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 436 437 if (stm32_port->tx_ch) 438 stm32_transmit_chars_dma(port); 439 else 440 stm32_transmit_chars_pio(port); 441 442 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 443 uart_write_wakeup(port); 444 445 if (uart_circ_empty(xmit)) 446 stm32_tx_interrupt_disable(port); 447 } 448 449 static irqreturn_t stm32_interrupt(int irq, void *ptr) 450 { 451 struct uart_port *port = ptr; 452 struct stm32_port *stm32_port = to_stm32_port(port); 453 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 454 u32 sr; 455 456 spin_lock(&port->lock); 457 458 sr = readl_relaxed(port->membase + ofs->isr); 459 460 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 461 writel_relaxed(USART_ICR_RTOCF, 462 port->membase + ofs->icr); 463 464 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 465 writel_relaxed(USART_ICR_WUCF, 466 port->membase + ofs->icr); 467 468 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 469 stm32_receive_chars(port, false); 470 471 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 472 stm32_transmit_chars(port); 473 474 spin_unlock(&port->lock); 475 476 if (stm32_port->rx_ch) 477 return IRQ_WAKE_THREAD; 478 else 479 return IRQ_HANDLED; 480 } 481 482 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 483 { 484 struct uart_port *port = ptr; 485 struct stm32_port *stm32_port = to_stm32_port(port); 486 487 spin_lock(&port->lock); 488 489 if (stm32_port->rx_ch) 490 stm32_receive_chars(port, true); 491 492 spin_unlock(&port->lock); 493 494 return IRQ_HANDLED; 495 } 496 497 static unsigned int stm32_tx_empty(struct uart_port *port) 498 { 499 struct stm32_port *stm32_port = to_stm32_port(port); 500 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 501 502 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 503 } 504 505 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 506 { 507 struct stm32_port *stm32_port = to_stm32_port(port); 508 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 509 510 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 511 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 512 else 513 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 514 515 mctrl_gpio_set(stm32_port->gpios, mctrl); 516 } 517 518 static unsigned int stm32_get_mctrl(struct uart_port *port) 519 { 520 struct stm32_port *stm32_port = to_stm32_port(port); 521 unsigned int ret; 522 523 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 524 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 525 526 return mctrl_gpio_get(stm32_port->gpios, &ret); 527 } 528 529 static void stm32_enable_ms(struct uart_port *port) 530 { 531 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 532 } 533 534 static void stm32_disable_ms(struct uart_port *port) 535 { 536 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 537 } 538 539 /* Transmit stop */ 540 static void stm32_stop_tx(struct uart_port *port) 541 { 542 stm32_tx_interrupt_disable(port); 543 } 544 545 /* There are probably characters waiting to be transmitted. */ 546 static void stm32_start_tx(struct uart_port *port) 547 { 548 struct circ_buf *xmit = &port->state->xmit; 549 550 if (uart_circ_empty(xmit)) 551 return; 552 553 stm32_transmit_chars(port); 554 } 555 556 /* Throttle the remote when input buffer is about to overflow. */ 557 static void stm32_throttle(struct uart_port *port) 558 { 559 struct stm32_port *stm32_port = to_stm32_port(port); 560 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 561 unsigned long flags; 562 563 spin_lock_irqsave(&port->lock, flags); 564 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 565 if (stm32_port->cr3_irq) 566 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 567 568 spin_unlock_irqrestore(&port->lock, flags); 569 } 570 571 /* Unthrottle the remote, the input buffer can now accept data. */ 572 static void stm32_unthrottle(struct uart_port *port) 573 { 574 struct stm32_port *stm32_port = to_stm32_port(port); 575 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 576 unsigned long flags; 577 578 spin_lock_irqsave(&port->lock, flags); 579 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 580 if (stm32_port->cr3_irq) 581 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 582 583 spin_unlock_irqrestore(&port->lock, flags); 584 } 585 586 /* Receive stop */ 587 static void stm32_stop_rx(struct uart_port *port) 588 { 589 struct stm32_port *stm32_port = to_stm32_port(port); 590 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 591 592 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 593 if (stm32_port->cr3_irq) 594 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 595 596 } 597 598 /* Handle breaks - ignored by us */ 599 static void stm32_break_ctl(struct uart_port *port, int break_state) 600 { 601 } 602 603 static int stm32_startup(struct uart_port *port) 604 { 605 struct stm32_port *stm32_port = to_stm32_port(port); 606 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 607 const char *name = to_platform_device(port->dev)->name; 608 u32 val; 609 int ret; 610 611 ret = request_threaded_irq(port->irq, stm32_interrupt, 612 stm32_threaded_interrupt, 613 IRQF_NO_SUSPEND, name, port); 614 if (ret) 615 return ret; 616 617 /* RX FIFO Flush */ 618 if (ofs->rqr != UNDEF_REG) 619 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 620 621 /* Tx and RX FIFO configuration */ 622 if (stm32_port->fifoen) { 623 val = readl_relaxed(port->membase + ofs->cr3); 624 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 625 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 626 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 627 writel_relaxed(val, port->membase + ofs->cr3); 628 } 629 630 /* RX FIFO enabling */ 631 val = stm32_port->cr1_irq | USART_CR1_RE; 632 if (stm32_port->fifoen) 633 val |= USART_CR1_FIFOEN; 634 stm32_set_bits(port, ofs->cr1, val); 635 636 return 0; 637 } 638 639 static void stm32_shutdown(struct uart_port *port) 640 { 641 struct stm32_port *stm32_port = to_stm32_port(port); 642 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 643 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 644 u32 val, isr; 645 int ret; 646 647 /* Disable modem control interrupts */ 648 stm32_disable_ms(port); 649 650 val = USART_CR1_TXEIE | USART_CR1_TE; 651 val |= stm32_port->cr1_irq | USART_CR1_RE; 652 val |= BIT(cfg->uart_enable_bit); 653 if (stm32_port->fifoen) 654 val |= USART_CR1_FIFOEN; 655 656 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 657 isr, (isr & USART_SR_TC), 658 10, 100000); 659 660 if (ret) 661 dev_err(port->dev, "transmission complete not set\n"); 662 663 stm32_clr_bits(port, ofs->cr1, val); 664 665 free_irq(port->irq, port); 666 } 667 668 static unsigned int stm32_get_databits(struct ktermios *termios) 669 { 670 unsigned int bits; 671 672 tcflag_t cflag = termios->c_cflag; 673 674 switch (cflag & CSIZE) { 675 /* 676 * CSIZE settings are not necessarily supported in hardware. 677 * CSIZE unsupported configurations are handled here to set word length 678 * to 8 bits word as default configuration and to print debug message. 679 */ 680 case CS5: 681 bits = 5; 682 break; 683 case CS6: 684 bits = 6; 685 break; 686 case CS7: 687 bits = 7; 688 break; 689 /* default including CS8 */ 690 default: 691 bits = 8; 692 break; 693 } 694 695 return bits; 696 } 697 698 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 699 struct ktermios *old) 700 { 701 struct stm32_port *stm32_port = to_stm32_port(port); 702 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 703 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 704 struct serial_rs485 *rs485conf = &port->rs485; 705 unsigned int baud, bits; 706 u32 usartdiv, mantissa, fraction, oversampling; 707 tcflag_t cflag = termios->c_cflag; 708 u32 cr1, cr2, cr3; 709 unsigned long flags; 710 711 if (!stm32_port->hw_flow_control) 712 cflag &= ~CRTSCTS; 713 714 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 715 716 spin_lock_irqsave(&port->lock, flags); 717 718 /* Stop serial port and reset value */ 719 writel_relaxed(0, port->membase + ofs->cr1); 720 721 /* flush RX & TX FIFO */ 722 if (ofs->rqr != UNDEF_REG) 723 stm32_set_bits(port, ofs->rqr, 724 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 725 726 cr1 = USART_CR1_TE | USART_CR1_RE; 727 if (stm32_port->fifoen) 728 cr1 |= USART_CR1_FIFOEN; 729 cr2 = 0; 730 cr3 = readl_relaxed(port->membase + ofs->cr3); 731 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 732 | USART_CR3_TXFTCFG_MASK; 733 734 if (cflag & CSTOPB) 735 cr2 |= USART_CR2_STOP_2B; 736 737 bits = stm32_get_databits(termios); 738 stm32_port->rdr_mask = (BIT(bits) - 1); 739 740 if (cflag & PARENB) { 741 bits++; 742 cr1 |= USART_CR1_PCE; 743 } 744 745 /* 746 * Word length configuration: 747 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 748 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 749 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 750 * M0 and M1 already cleared by cr1 initialization. 751 */ 752 if (bits == 9) 753 cr1 |= USART_CR1_M0; 754 else if ((bits == 7) && cfg->has_7bits_data) 755 cr1 |= USART_CR1_M1; 756 else if (bits != 8) 757 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 758 , bits); 759 760 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 761 stm32_port->fifoen)) { 762 if (cflag & CSTOPB) 763 bits = bits + 3; /* 1 start bit + 2 stop bits */ 764 else 765 bits = bits + 2; /* 1 start bit + 1 stop bit */ 766 767 /* RX timeout irq to occur after last stop bit + bits */ 768 stm32_port->cr1_irq = USART_CR1_RTOIE; 769 writel_relaxed(bits, port->membase + ofs->rtor); 770 cr2 |= USART_CR2_RTOEN; 771 /* Not using dma, enable fifo threshold irq */ 772 if (!stm32_port->rx_ch) 773 stm32_port->cr3_irq = USART_CR3_RXFTIE; 774 } 775 776 cr1 |= stm32_port->cr1_irq; 777 cr3 |= stm32_port->cr3_irq; 778 779 if (cflag & PARODD) 780 cr1 |= USART_CR1_PS; 781 782 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 783 if (cflag & CRTSCTS) { 784 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 785 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 786 } 787 788 /* Handle modem control interrupts */ 789 if (UART_ENABLE_MS(port, termios->c_cflag)) 790 stm32_enable_ms(port); 791 else 792 stm32_disable_ms(port); 793 794 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 795 796 /* 797 * The USART supports 16 or 8 times oversampling. 798 * By default we prefer 16 times oversampling, so that the receiver 799 * has a better tolerance to clock deviations. 800 * 8 times oversampling is only used to achieve higher speeds. 801 */ 802 if (usartdiv < 16) { 803 oversampling = 8; 804 cr1 |= USART_CR1_OVER8; 805 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 806 } else { 807 oversampling = 16; 808 cr1 &= ~USART_CR1_OVER8; 809 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 810 } 811 812 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 813 fraction = usartdiv % oversampling; 814 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 815 816 uart_update_timeout(port, cflag, baud); 817 818 port->read_status_mask = USART_SR_ORE; 819 if (termios->c_iflag & INPCK) 820 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 821 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 822 port->read_status_mask |= USART_SR_FE; 823 824 /* Characters to ignore */ 825 port->ignore_status_mask = 0; 826 if (termios->c_iflag & IGNPAR) 827 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 828 if (termios->c_iflag & IGNBRK) { 829 port->ignore_status_mask |= USART_SR_FE; 830 /* 831 * If we're ignoring parity and break indicators, 832 * ignore overruns too (for real raw support). 833 */ 834 if (termios->c_iflag & IGNPAR) 835 port->ignore_status_mask |= USART_SR_ORE; 836 } 837 838 /* Ignore all characters if CREAD is not set */ 839 if ((termios->c_cflag & CREAD) == 0) 840 port->ignore_status_mask |= USART_SR_DUMMY_RX; 841 842 if (stm32_port->rx_ch) 843 cr3 |= USART_CR3_DMAR; 844 845 if (rs485conf->flags & SER_RS485_ENABLED) { 846 stm32_config_reg_rs485(&cr1, &cr3, 847 rs485conf->delay_rts_before_send, 848 rs485conf->delay_rts_after_send, baud); 849 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 850 cr3 &= ~USART_CR3_DEP; 851 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 852 } else { 853 cr3 |= USART_CR3_DEP; 854 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 855 } 856 857 } else { 858 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 859 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 860 } 861 862 writel_relaxed(cr3, port->membase + ofs->cr3); 863 writel_relaxed(cr2, port->membase + ofs->cr2); 864 writel_relaxed(cr1, port->membase + ofs->cr1); 865 866 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 867 spin_unlock_irqrestore(&port->lock, flags); 868 } 869 870 static const char *stm32_type(struct uart_port *port) 871 { 872 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 873 } 874 875 static void stm32_release_port(struct uart_port *port) 876 { 877 } 878 879 static int stm32_request_port(struct uart_port *port) 880 { 881 return 0; 882 } 883 884 static void stm32_config_port(struct uart_port *port, int flags) 885 { 886 if (flags & UART_CONFIG_TYPE) 887 port->type = PORT_STM32; 888 } 889 890 static int 891 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 892 { 893 /* No user changeable parameters */ 894 return -EINVAL; 895 } 896 897 static void stm32_pm(struct uart_port *port, unsigned int state, 898 unsigned int oldstate) 899 { 900 struct stm32_port *stm32port = container_of(port, 901 struct stm32_port, port); 902 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 903 struct stm32_usart_config *cfg = &stm32port->info->cfg; 904 unsigned long flags = 0; 905 906 switch (state) { 907 case UART_PM_STATE_ON: 908 pm_runtime_get_sync(port->dev); 909 break; 910 case UART_PM_STATE_OFF: 911 spin_lock_irqsave(&port->lock, flags); 912 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 913 spin_unlock_irqrestore(&port->lock, flags); 914 pm_runtime_put_sync(port->dev); 915 break; 916 } 917 } 918 919 static const struct uart_ops stm32_uart_ops = { 920 .tx_empty = stm32_tx_empty, 921 .set_mctrl = stm32_set_mctrl, 922 .get_mctrl = stm32_get_mctrl, 923 .stop_tx = stm32_stop_tx, 924 .start_tx = stm32_start_tx, 925 .throttle = stm32_throttle, 926 .unthrottle = stm32_unthrottle, 927 .stop_rx = stm32_stop_rx, 928 .enable_ms = stm32_enable_ms, 929 .break_ctl = stm32_break_ctl, 930 .startup = stm32_startup, 931 .shutdown = stm32_shutdown, 932 .set_termios = stm32_set_termios, 933 .pm = stm32_pm, 934 .type = stm32_type, 935 .release_port = stm32_release_port, 936 .request_port = stm32_request_port, 937 .config_port = stm32_config_port, 938 .verify_port = stm32_verify_port, 939 }; 940 941 static int stm32_init_port(struct stm32_port *stm32port, 942 struct platform_device *pdev) 943 { 944 struct uart_port *port = &stm32port->port; 945 struct resource *res; 946 int ret; 947 948 port->iotype = UPIO_MEM; 949 port->flags = UPF_BOOT_AUTOCONF; 950 port->ops = &stm32_uart_ops; 951 port->dev = &pdev->dev; 952 port->fifosize = stm32port->info->cfg.fifosize; 953 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 954 955 ret = platform_get_irq(pdev, 0); 956 if (ret <= 0) 957 return ret ? : -ENODEV; 958 port->irq = ret; 959 960 port->rs485_config = stm32_config_rs485; 961 962 stm32_init_rs485(port, pdev); 963 964 if (stm32port->info->cfg.has_wakeup) { 965 stm32port->wakeirq = platform_get_irq(pdev, 1); 966 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 967 return stm32port->wakeirq ? : -ENODEV; 968 } 969 970 stm32port->fifoen = stm32port->info->cfg.has_fifo; 971 972 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 973 port->membase = devm_ioremap_resource(&pdev->dev, res); 974 if (IS_ERR(port->membase)) 975 return PTR_ERR(port->membase); 976 port->mapbase = res->start; 977 978 spin_lock_init(&port->lock); 979 980 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 981 if (IS_ERR(stm32port->clk)) 982 return PTR_ERR(stm32port->clk); 983 984 /* Ensure that clk rate is correct by enabling the clk */ 985 ret = clk_prepare_enable(stm32port->clk); 986 if (ret) 987 return ret; 988 989 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 990 if (!stm32port->port.uartclk) { 991 ret = -EINVAL; 992 goto err_clk; 993 } 994 995 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 996 if (IS_ERR(stm32port->gpios)) { 997 ret = PTR_ERR(stm32port->gpios); 998 goto err_clk; 999 } 1000 1001 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ 1002 if (stm32port->hw_flow_control) { 1003 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1004 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1005 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1006 ret = -EINVAL; 1007 goto err_clk; 1008 } 1009 } 1010 1011 return ret; 1012 1013 err_clk: 1014 clk_disable_unprepare(stm32port->clk); 1015 1016 return ret; 1017 } 1018 1019 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 1020 { 1021 struct device_node *np = pdev->dev.of_node; 1022 int id; 1023 1024 if (!np) 1025 return NULL; 1026 1027 id = of_alias_get_id(np, "serial"); 1028 if (id < 0) { 1029 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1030 return NULL; 1031 } 1032 1033 if (WARN_ON(id >= STM32_MAX_PORTS)) 1034 return NULL; 1035 1036 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 1037 "st,hw-flow-ctrl"); 1038 stm32_ports[id].port.line = id; 1039 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1040 stm32_ports[id].cr3_irq = 0; 1041 stm32_ports[id].last_res = RX_BUF_L; 1042 return &stm32_ports[id]; 1043 } 1044 1045 #ifdef CONFIG_OF 1046 static const struct of_device_id stm32_match[] = { 1047 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1048 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1049 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1050 {}, 1051 }; 1052 1053 MODULE_DEVICE_TABLE(of, stm32_match); 1054 #endif 1055 1056 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 1057 struct platform_device *pdev) 1058 { 1059 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1060 struct uart_port *port = &stm32port->port; 1061 struct device *dev = &pdev->dev; 1062 struct dma_slave_config config; 1063 struct dma_async_tx_descriptor *desc = NULL; 1064 dma_cookie_t cookie; 1065 int ret; 1066 1067 /* Request DMA RX channel */ 1068 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1069 if (!stm32port->rx_ch) { 1070 dev_info(dev, "rx dma alloc failed\n"); 1071 return -ENODEV; 1072 } 1073 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1074 &stm32port->rx_dma_buf, 1075 GFP_KERNEL); 1076 if (!stm32port->rx_buf) { 1077 ret = -ENOMEM; 1078 goto alloc_err; 1079 } 1080 1081 /* Configure DMA channel */ 1082 memset(&config, 0, sizeof(config)); 1083 config.src_addr = port->mapbase + ofs->rdr; 1084 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1085 1086 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1087 if (ret < 0) { 1088 dev_err(dev, "rx dma channel config failed\n"); 1089 ret = -ENODEV; 1090 goto config_err; 1091 } 1092 1093 /* Prepare a DMA cyclic transaction */ 1094 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1095 stm32port->rx_dma_buf, 1096 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1097 DMA_PREP_INTERRUPT); 1098 if (!desc) { 1099 dev_err(dev, "rx dma prep cyclic failed\n"); 1100 ret = -ENODEV; 1101 goto config_err; 1102 } 1103 1104 /* No callback as dma buffer is drained on usart interrupt */ 1105 desc->callback = NULL; 1106 desc->callback_param = NULL; 1107 1108 /* Push current DMA transaction in the pending queue */ 1109 cookie = dmaengine_submit(desc); 1110 1111 /* Issue pending DMA requests */ 1112 dma_async_issue_pending(stm32port->rx_ch); 1113 1114 return 0; 1115 1116 config_err: 1117 dma_free_coherent(&pdev->dev, 1118 RX_BUF_L, stm32port->rx_buf, 1119 stm32port->rx_dma_buf); 1120 1121 alloc_err: 1122 dma_release_channel(stm32port->rx_ch); 1123 stm32port->rx_ch = NULL; 1124 1125 return ret; 1126 } 1127 1128 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 1129 struct platform_device *pdev) 1130 { 1131 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1132 struct uart_port *port = &stm32port->port; 1133 struct device *dev = &pdev->dev; 1134 struct dma_slave_config config; 1135 int ret; 1136 1137 stm32port->tx_dma_busy = false; 1138 1139 /* Request DMA TX channel */ 1140 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1141 if (!stm32port->tx_ch) { 1142 dev_info(dev, "tx dma alloc failed\n"); 1143 return -ENODEV; 1144 } 1145 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1146 &stm32port->tx_dma_buf, 1147 GFP_KERNEL); 1148 if (!stm32port->tx_buf) { 1149 ret = -ENOMEM; 1150 goto alloc_err; 1151 } 1152 1153 /* Configure DMA channel */ 1154 memset(&config, 0, sizeof(config)); 1155 config.dst_addr = port->mapbase + ofs->tdr; 1156 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1157 1158 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1159 if (ret < 0) { 1160 dev_err(dev, "tx dma channel config failed\n"); 1161 ret = -ENODEV; 1162 goto config_err; 1163 } 1164 1165 return 0; 1166 1167 config_err: 1168 dma_free_coherent(&pdev->dev, 1169 TX_BUF_L, stm32port->tx_buf, 1170 stm32port->tx_dma_buf); 1171 1172 alloc_err: 1173 dma_release_channel(stm32port->tx_ch); 1174 stm32port->tx_ch = NULL; 1175 1176 return ret; 1177 } 1178 1179 static int stm32_serial_probe(struct platform_device *pdev) 1180 { 1181 const struct of_device_id *match; 1182 struct stm32_port *stm32port; 1183 int ret; 1184 1185 stm32port = stm32_of_get_stm32_port(pdev); 1186 if (!stm32port) 1187 return -ENODEV; 1188 1189 match = of_match_device(stm32_match, &pdev->dev); 1190 if (match && match->data) 1191 stm32port->info = (struct stm32_usart_info *)match->data; 1192 else 1193 return -EINVAL; 1194 1195 ret = stm32_init_port(stm32port, pdev); 1196 if (ret) 1197 return ret; 1198 1199 if (stm32port->wakeirq > 0) { 1200 ret = device_init_wakeup(&pdev->dev, true); 1201 if (ret) 1202 goto err_uninit; 1203 1204 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1205 stm32port->wakeirq); 1206 if (ret) 1207 goto err_nowup; 1208 1209 device_set_wakeup_enable(&pdev->dev, false); 1210 } 1211 1212 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1213 if (ret) 1214 goto err_wirq; 1215 1216 ret = stm32_of_dma_rx_probe(stm32port, pdev); 1217 if (ret) 1218 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1219 1220 ret = stm32_of_dma_tx_probe(stm32port, pdev); 1221 if (ret) 1222 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1223 1224 platform_set_drvdata(pdev, &stm32port->port); 1225 1226 pm_runtime_get_noresume(&pdev->dev); 1227 pm_runtime_set_active(&pdev->dev); 1228 pm_runtime_enable(&pdev->dev); 1229 pm_runtime_put_sync(&pdev->dev); 1230 1231 return 0; 1232 1233 err_wirq: 1234 if (stm32port->wakeirq > 0) 1235 dev_pm_clear_wake_irq(&pdev->dev); 1236 1237 err_nowup: 1238 if (stm32port->wakeirq > 0) 1239 device_init_wakeup(&pdev->dev, false); 1240 1241 err_uninit: 1242 clk_disable_unprepare(stm32port->clk); 1243 1244 return ret; 1245 } 1246 1247 static int stm32_serial_remove(struct platform_device *pdev) 1248 { 1249 struct uart_port *port = platform_get_drvdata(pdev); 1250 struct stm32_port *stm32_port = to_stm32_port(port); 1251 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1252 int err; 1253 1254 pm_runtime_get_sync(&pdev->dev); 1255 1256 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1257 1258 if (stm32_port->rx_ch) 1259 dma_release_channel(stm32_port->rx_ch); 1260 1261 if (stm32_port->rx_dma_buf) 1262 dma_free_coherent(&pdev->dev, 1263 RX_BUF_L, stm32_port->rx_buf, 1264 stm32_port->rx_dma_buf); 1265 1266 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1267 1268 if (stm32_port->tx_ch) 1269 dma_release_channel(stm32_port->tx_ch); 1270 1271 if (stm32_port->tx_dma_buf) 1272 dma_free_coherent(&pdev->dev, 1273 TX_BUF_L, stm32_port->tx_buf, 1274 stm32_port->tx_dma_buf); 1275 1276 if (stm32_port->wakeirq > 0) { 1277 dev_pm_clear_wake_irq(&pdev->dev); 1278 device_init_wakeup(&pdev->dev, false); 1279 } 1280 1281 clk_disable_unprepare(stm32_port->clk); 1282 1283 err = uart_remove_one_port(&stm32_usart_driver, port); 1284 1285 pm_runtime_disable(&pdev->dev); 1286 pm_runtime_put_noidle(&pdev->dev); 1287 1288 return err; 1289 } 1290 1291 1292 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1293 static void stm32_console_putchar(struct uart_port *port, int ch) 1294 { 1295 struct stm32_port *stm32_port = to_stm32_port(port); 1296 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1297 1298 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1299 cpu_relax(); 1300 1301 writel_relaxed(ch, port->membase + ofs->tdr); 1302 } 1303 1304 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 1305 { 1306 struct uart_port *port = &stm32_ports[co->index].port; 1307 struct stm32_port *stm32_port = to_stm32_port(port); 1308 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1309 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1310 unsigned long flags; 1311 u32 old_cr1, new_cr1; 1312 int locked = 1; 1313 1314 local_irq_save(flags); 1315 if (port->sysrq) 1316 locked = 0; 1317 else if (oops_in_progress) 1318 locked = spin_trylock(&port->lock); 1319 else 1320 spin_lock(&port->lock); 1321 1322 /* Save and disable interrupts, enable the transmitter */ 1323 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1324 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1325 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1326 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1327 1328 uart_console_write(port, s, cnt, stm32_console_putchar); 1329 1330 /* Restore interrupt state */ 1331 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1332 1333 if (locked) 1334 spin_unlock(&port->lock); 1335 local_irq_restore(flags); 1336 } 1337 1338 static int stm32_console_setup(struct console *co, char *options) 1339 { 1340 struct stm32_port *stm32port; 1341 int baud = 9600; 1342 int bits = 8; 1343 int parity = 'n'; 1344 int flow = 'n'; 1345 1346 if (co->index >= STM32_MAX_PORTS) 1347 return -ENODEV; 1348 1349 stm32port = &stm32_ports[co->index]; 1350 1351 /* 1352 * This driver does not support early console initialization 1353 * (use ARM early printk support instead), so we only expect 1354 * this to be called during the uart port registration when the 1355 * driver gets probed and the port should be mapped at that point. 1356 */ 1357 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 1358 return -ENXIO; 1359 1360 if (options) 1361 uart_parse_options(options, &baud, &parity, &bits, &flow); 1362 1363 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1364 } 1365 1366 static struct console stm32_console = { 1367 .name = STM32_SERIAL_NAME, 1368 .device = uart_console_device, 1369 .write = stm32_console_write, 1370 .setup = stm32_console_setup, 1371 .flags = CON_PRINTBUFFER, 1372 .index = -1, 1373 .data = &stm32_usart_driver, 1374 }; 1375 1376 #define STM32_SERIAL_CONSOLE (&stm32_console) 1377 1378 #else 1379 #define STM32_SERIAL_CONSOLE NULL 1380 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1381 1382 static struct uart_driver stm32_usart_driver = { 1383 .driver_name = DRIVER_NAME, 1384 .dev_name = STM32_SERIAL_NAME, 1385 .major = 0, 1386 .minor = 0, 1387 .nr = STM32_MAX_PORTS, 1388 .cons = STM32_SERIAL_CONSOLE, 1389 }; 1390 1391 static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port, 1392 bool enable) 1393 { 1394 struct stm32_port *stm32_port = to_stm32_port(port); 1395 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1396 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1397 u32 val; 1398 1399 if (stm32_port->wakeirq <= 0) 1400 return; 1401 1402 if (enable) { 1403 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1404 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1405 val = readl_relaxed(port->membase + ofs->cr3); 1406 val &= ~USART_CR3_WUS_MASK; 1407 /* Enable Wake up interrupt from low power on start bit */ 1408 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1409 writel_relaxed(val, port->membase + ofs->cr3); 1410 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1411 } else { 1412 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1413 } 1414 } 1415 1416 static int __maybe_unused stm32_serial_suspend(struct device *dev) 1417 { 1418 struct uart_port *port = dev_get_drvdata(dev); 1419 1420 uart_suspend_port(&stm32_usart_driver, port); 1421 1422 if (device_may_wakeup(dev)) 1423 stm32_serial_enable_wakeup(port, true); 1424 else 1425 stm32_serial_enable_wakeup(port, false); 1426 1427 pinctrl_pm_select_sleep_state(dev); 1428 1429 return 0; 1430 } 1431 1432 static int __maybe_unused stm32_serial_resume(struct device *dev) 1433 { 1434 struct uart_port *port = dev_get_drvdata(dev); 1435 1436 pinctrl_pm_select_default_state(dev); 1437 1438 if (device_may_wakeup(dev)) 1439 stm32_serial_enable_wakeup(port, false); 1440 1441 return uart_resume_port(&stm32_usart_driver, port); 1442 } 1443 1444 static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev) 1445 { 1446 struct uart_port *port = dev_get_drvdata(dev); 1447 struct stm32_port *stm32port = container_of(port, 1448 struct stm32_port, port); 1449 1450 clk_disable_unprepare(stm32port->clk); 1451 1452 return 0; 1453 } 1454 1455 static int __maybe_unused stm32_serial_runtime_resume(struct device *dev) 1456 { 1457 struct uart_port *port = dev_get_drvdata(dev); 1458 struct stm32_port *stm32port = container_of(port, 1459 struct stm32_port, port); 1460 1461 return clk_prepare_enable(stm32port->clk); 1462 } 1463 1464 static const struct dev_pm_ops stm32_serial_pm_ops = { 1465 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend, 1466 stm32_serial_runtime_resume, NULL) 1467 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1468 }; 1469 1470 static struct platform_driver stm32_serial_driver = { 1471 .probe = stm32_serial_probe, 1472 .remove = stm32_serial_remove, 1473 .driver = { 1474 .name = DRIVER_NAME, 1475 .pm = &stm32_serial_pm_ops, 1476 .of_match_table = of_match_ptr(stm32_match), 1477 }, 1478 }; 1479 1480 static int __init usart_init(void) 1481 { 1482 static char banner[] __initdata = "STM32 USART driver initialized"; 1483 int ret; 1484 1485 pr_info("%s\n", banner); 1486 1487 ret = uart_register_driver(&stm32_usart_driver); 1488 if (ret) 1489 return ret; 1490 1491 ret = platform_driver_register(&stm32_serial_driver); 1492 if (ret) 1493 uart_unregister_driver(&stm32_usart_driver); 1494 1495 return ret; 1496 } 1497 1498 static void __exit usart_exit(void) 1499 { 1500 platform_driver_unregister(&stm32_serial_driver); 1501 uart_unregister_driver(&stm32_usart_driver); 1502 } 1503 1504 module_init(usart_init); 1505 module_exit(usart_exit); 1506 1507 MODULE_ALIAS("platform:" DRIVER_NAME); 1508 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1509 MODULE_LICENSE("GPL v2"); 1510