1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) STMicroelectronics SA 2017 4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Gerald Baeza <gerald.baeza@st.com> 6 * License terms: GNU General Public License (GPL), version 2 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/clk.h> 16 #include <linux/console.h> 17 #include <linux/delay.h> 18 #include <linux/dma-direction.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/irq.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/serial_core.h> 30 #include <linux/serial.h> 31 #include <linux/spinlock.h> 32 #include <linux/sysrq.h> 33 #include <linux/tty_flip.h> 34 #include <linux/tty.h> 35 36 #include "stm32-usart.h" 37 38 static void stm32_stop_tx(struct uart_port *port); 39 static void stm32_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 65 bool threaded) 66 { 67 struct stm32_port *stm32_port = to_stm32_port(port); 68 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 69 enum dma_status status; 70 struct dma_tx_state state; 71 72 *sr = readl_relaxed(port->membase + ofs->isr); 73 74 if (threaded && stm32_port->rx_ch) { 75 status = dmaengine_tx_status(stm32_port->rx_ch, 76 stm32_port->rx_ch->cookie, 77 &state); 78 if ((status == DMA_IN_PROGRESS) && 79 (*last_res != state.residue)) 80 return 1; 81 else 82 return 0; 83 } else if (*sr & USART_SR_RXNE) { 84 return 1; 85 } 86 return 0; 87 } 88 89 static unsigned long 90 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) 91 { 92 struct stm32_port *stm32_port = to_stm32_port(port); 93 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 94 unsigned long c; 95 96 if (stm32_port->rx_ch) { 97 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 98 if ((*last_res) == 0) 99 *last_res = RX_BUF_L; 100 return c; 101 } else { 102 return readl_relaxed(port->membase + ofs->rdr); 103 } 104 } 105 106 static void stm32_receive_chars(struct uart_port *port, bool threaded) 107 { 108 struct tty_port *tport = &port->state->port; 109 struct stm32_port *stm32_port = to_stm32_port(port); 110 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 111 unsigned long c; 112 u32 sr; 113 char flag; 114 static int last_res = RX_BUF_L; 115 116 if (port->irq_wake) 117 pm_wakeup_event(tport->tty->dev, 0); 118 119 while (stm32_pending_rx(port, &sr, &last_res, threaded)) { 120 sr |= USART_SR_DUMMY_RX; 121 c = stm32_get_char(port, &sr, &last_res); 122 flag = TTY_NORMAL; 123 port->icount.rx++; 124 125 if (sr & USART_SR_ERR_MASK) { 126 if (sr & USART_SR_LBD) { 127 port->icount.brk++; 128 if (uart_handle_break(port)) 129 continue; 130 } else if (sr & USART_SR_ORE) { 131 if (ofs->icr != UNDEF_REG) 132 writel_relaxed(USART_ICR_ORECF, 133 port->membase + 134 ofs->icr); 135 port->icount.overrun++; 136 } else if (sr & USART_SR_PE) { 137 port->icount.parity++; 138 } else if (sr & USART_SR_FE) { 139 port->icount.frame++; 140 } 141 142 sr &= port->read_status_mask; 143 144 if (sr & USART_SR_LBD) 145 flag = TTY_BREAK; 146 else if (sr & USART_SR_PE) 147 flag = TTY_PARITY; 148 else if (sr & USART_SR_FE) 149 flag = TTY_FRAME; 150 } 151 152 if (uart_handle_sysrq_char(port, c)) 153 continue; 154 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 155 } 156 157 spin_unlock(&port->lock); 158 tty_flip_buffer_push(tport); 159 spin_lock(&port->lock); 160 } 161 162 static void stm32_tx_dma_complete(void *arg) 163 { 164 struct uart_port *port = arg; 165 struct stm32_port *stm32port = to_stm32_port(port); 166 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 167 unsigned int isr; 168 int ret; 169 170 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 171 isr, 172 (isr & USART_SR_TC), 173 10, 100000); 174 175 if (ret) 176 dev_err(port->dev, "terminal count not set\n"); 177 178 if (ofs->icr == UNDEF_REG) 179 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 180 else 181 stm32_set_bits(port, ofs->icr, USART_CR_TC); 182 183 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 184 stm32port->tx_dma_busy = false; 185 186 /* Let's see if we have pending data to send */ 187 stm32_transmit_chars(port); 188 } 189 190 static void stm32_transmit_chars_pio(struct uart_port *port) 191 { 192 struct stm32_port *stm32_port = to_stm32_port(port); 193 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 194 struct circ_buf *xmit = &port->state->xmit; 195 unsigned int isr; 196 int ret; 197 198 if (stm32_port->tx_dma_busy) { 199 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 200 stm32_port->tx_dma_busy = false; 201 } 202 203 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 204 isr, 205 (isr & USART_SR_TXE), 206 10, 100); 207 208 if (ret) 209 dev_err(port->dev, "tx empty not set\n"); 210 211 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 212 213 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 214 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 215 port->icount.tx++; 216 } 217 218 static void stm32_transmit_chars_dma(struct uart_port *port) 219 { 220 struct stm32_port *stm32port = to_stm32_port(port); 221 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 222 struct circ_buf *xmit = &port->state->xmit; 223 struct dma_async_tx_descriptor *desc = NULL; 224 dma_cookie_t cookie; 225 unsigned int count, i; 226 227 if (stm32port->tx_dma_busy) 228 return; 229 230 stm32port->tx_dma_busy = true; 231 232 count = uart_circ_chars_pending(xmit); 233 234 if (count > TX_BUF_L) 235 count = TX_BUF_L; 236 237 if (xmit->tail < xmit->head) { 238 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 239 } else { 240 size_t one = UART_XMIT_SIZE - xmit->tail; 241 size_t two; 242 243 if (one > count) 244 one = count; 245 two = count - one; 246 247 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 248 if (two) 249 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 250 } 251 252 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 253 stm32port->tx_dma_buf, 254 count, 255 DMA_MEM_TO_DEV, 256 DMA_PREP_INTERRUPT); 257 258 if (!desc) { 259 for (i = count; i > 0; i--) 260 stm32_transmit_chars_pio(port); 261 return; 262 } 263 264 desc->callback = stm32_tx_dma_complete; 265 desc->callback_param = port; 266 267 /* Push current DMA TX transaction in the pending queue */ 268 cookie = dmaengine_submit(desc); 269 270 /* Issue pending DMA TX requests */ 271 dma_async_issue_pending(stm32port->tx_ch); 272 273 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 274 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 275 276 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 277 port->icount.tx += count; 278 } 279 280 static void stm32_transmit_chars(struct uart_port *port) 281 { 282 struct stm32_port *stm32_port = to_stm32_port(port); 283 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 284 struct circ_buf *xmit = &port->state->xmit; 285 286 if (port->x_char) { 287 if (stm32_port->tx_dma_busy) 288 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 289 writel_relaxed(port->x_char, port->membase + ofs->tdr); 290 port->x_char = 0; 291 port->icount.tx++; 292 if (stm32_port->tx_dma_busy) 293 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 294 return; 295 } 296 297 if (uart_tx_stopped(port)) { 298 stm32_stop_tx(port); 299 return; 300 } 301 302 if (uart_circ_empty(xmit)) { 303 stm32_stop_tx(port); 304 return; 305 } 306 307 if (stm32_port->tx_ch) 308 stm32_transmit_chars_dma(port); 309 else 310 stm32_transmit_chars_pio(port); 311 312 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 313 uart_write_wakeup(port); 314 315 if (uart_circ_empty(xmit)) 316 stm32_stop_tx(port); 317 } 318 319 static irqreturn_t stm32_interrupt(int irq, void *ptr) 320 { 321 struct uart_port *port = ptr; 322 struct stm32_port *stm32_port = to_stm32_port(port); 323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 324 u32 sr; 325 326 spin_lock(&port->lock); 327 328 sr = readl_relaxed(port->membase + ofs->isr); 329 330 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 331 stm32_receive_chars(port, false); 332 333 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 334 stm32_transmit_chars(port); 335 336 spin_unlock(&port->lock); 337 338 if (stm32_port->rx_ch) 339 return IRQ_WAKE_THREAD; 340 else 341 return IRQ_HANDLED; 342 } 343 344 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 345 { 346 struct uart_port *port = ptr; 347 struct stm32_port *stm32_port = to_stm32_port(port); 348 349 spin_lock(&port->lock); 350 351 if (stm32_port->rx_ch) 352 stm32_receive_chars(port, true); 353 354 spin_unlock(&port->lock); 355 356 return IRQ_HANDLED; 357 } 358 359 static unsigned int stm32_tx_empty(struct uart_port *port) 360 { 361 struct stm32_port *stm32_port = to_stm32_port(port); 362 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 363 364 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 365 } 366 367 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 368 { 369 struct stm32_port *stm32_port = to_stm32_port(port); 370 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 371 372 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 373 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 374 else 375 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 376 } 377 378 static unsigned int stm32_get_mctrl(struct uart_port *port) 379 { 380 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 381 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 382 } 383 384 /* Transmit stop */ 385 static void stm32_stop_tx(struct uart_port *port) 386 { 387 struct stm32_port *stm32_port = to_stm32_port(port); 388 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 389 390 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 391 } 392 393 /* There are probably characters waiting to be transmitted. */ 394 static void stm32_start_tx(struct uart_port *port) 395 { 396 struct circ_buf *xmit = &port->state->xmit; 397 398 if (uart_circ_empty(xmit)) 399 return; 400 401 stm32_transmit_chars(port); 402 } 403 404 /* Throttle the remote when input buffer is about to overflow. */ 405 static void stm32_throttle(struct uart_port *port) 406 { 407 struct stm32_port *stm32_port = to_stm32_port(port); 408 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 409 unsigned long flags; 410 411 spin_lock_irqsave(&port->lock, flags); 412 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 413 spin_unlock_irqrestore(&port->lock, flags); 414 } 415 416 /* Unthrottle the remote, the input buffer can now accept data. */ 417 static void stm32_unthrottle(struct uart_port *port) 418 { 419 struct stm32_port *stm32_port = to_stm32_port(port); 420 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 421 unsigned long flags; 422 423 spin_lock_irqsave(&port->lock, flags); 424 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 425 spin_unlock_irqrestore(&port->lock, flags); 426 } 427 428 /* Receive stop */ 429 static void stm32_stop_rx(struct uart_port *port) 430 { 431 struct stm32_port *stm32_port = to_stm32_port(port); 432 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 433 434 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 435 } 436 437 /* Handle breaks - ignored by us */ 438 static void stm32_break_ctl(struct uart_port *port, int break_state) 439 { 440 } 441 442 static int stm32_startup(struct uart_port *port) 443 { 444 struct stm32_port *stm32_port = to_stm32_port(port); 445 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 446 const char *name = to_platform_device(port->dev)->name; 447 u32 val; 448 int ret; 449 450 ret = request_threaded_irq(port->irq, stm32_interrupt, 451 stm32_threaded_interrupt, 452 IRQF_NO_SUSPEND, name, port); 453 if (ret) 454 return ret; 455 456 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 457 stm32_set_bits(port, ofs->cr1, val); 458 459 return 0; 460 } 461 462 static void stm32_shutdown(struct uart_port *port) 463 { 464 struct stm32_port *stm32_port = to_stm32_port(port); 465 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 466 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 467 u32 val; 468 469 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 470 val |= BIT(cfg->uart_enable_bit); 471 stm32_clr_bits(port, ofs->cr1, val); 472 473 free_irq(port->irq, port); 474 } 475 476 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 477 struct ktermios *old) 478 { 479 struct stm32_port *stm32_port = to_stm32_port(port); 480 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 481 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 482 unsigned int baud; 483 u32 usartdiv, mantissa, fraction, oversampling; 484 tcflag_t cflag = termios->c_cflag; 485 u32 cr1, cr2, cr3; 486 unsigned long flags; 487 488 if (!stm32_port->hw_flow_control) 489 cflag &= ~CRTSCTS; 490 491 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 492 493 spin_lock_irqsave(&port->lock, flags); 494 495 /* Stop serial port and reset value */ 496 writel_relaxed(0, port->membase + ofs->cr1); 497 498 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 499 cr1 |= BIT(cfg->uart_enable_bit); 500 cr2 = 0; 501 cr3 = 0; 502 503 if (cflag & CSTOPB) 504 cr2 |= USART_CR2_STOP_2B; 505 506 if (cflag & PARENB) { 507 cr1 |= USART_CR1_PCE; 508 if ((cflag & CSIZE) == CS8) { 509 if (cfg->has_7bits_data) 510 cr1 |= USART_CR1_M0; 511 else 512 cr1 |= USART_CR1_M; 513 } 514 } 515 516 if (cflag & PARODD) 517 cr1 |= USART_CR1_PS; 518 519 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 520 if (cflag & CRTSCTS) { 521 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 522 cr3 |= USART_CR3_CTSE; 523 } 524 525 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 526 527 /* 528 * The USART supports 16 or 8 times oversampling. 529 * By default we prefer 16 times oversampling, so that the receiver 530 * has a better tolerance to clock deviations. 531 * 8 times oversampling is only used to achieve higher speeds. 532 */ 533 if (usartdiv < 16) { 534 oversampling = 8; 535 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 536 } else { 537 oversampling = 16; 538 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 539 } 540 541 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 542 fraction = usartdiv % oversampling; 543 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 544 545 uart_update_timeout(port, cflag, baud); 546 547 port->read_status_mask = USART_SR_ORE; 548 if (termios->c_iflag & INPCK) 549 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 550 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 551 port->read_status_mask |= USART_SR_LBD; 552 553 /* Characters to ignore */ 554 port->ignore_status_mask = 0; 555 if (termios->c_iflag & IGNPAR) 556 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 557 if (termios->c_iflag & IGNBRK) { 558 port->ignore_status_mask |= USART_SR_LBD; 559 /* 560 * If we're ignoring parity and break indicators, 561 * ignore overruns too (for real raw support). 562 */ 563 if (termios->c_iflag & IGNPAR) 564 port->ignore_status_mask |= USART_SR_ORE; 565 } 566 567 /* Ignore all characters if CREAD is not set */ 568 if ((termios->c_cflag & CREAD) == 0) 569 port->ignore_status_mask |= USART_SR_DUMMY_RX; 570 571 if (stm32_port->rx_ch) 572 cr3 |= USART_CR3_DMAR; 573 574 writel_relaxed(cr3, port->membase + ofs->cr3); 575 writel_relaxed(cr2, port->membase + ofs->cr2); 576 writel_relaxed(cr1, port->membase + ofs->cr1); 577 578 spin_unlock_irqrestore(&port->lock, flags); 579 } 580 581 static const char *stm32_type(struct uart_port *port) 582 { 583 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 584 } 585 586 static void stm32_release_port(struct uart_port *port) 587 { 588 } 589 590 static int stm32_request_port(struct uart_port *port) 591 { 592 return 0; 593 } 594 595 static void stm32_config_port(struct uart_port *port, int flags) 596 { 597 if (flags & UART_CONFIG_TYPE) 598 port->type = PORT_STM32; 599 } 600 601 static int 602 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 603 { 604 /* No user changeable parameters */ 605 return -EINVAL; 606 } 607 608 static void stm32_pm(struct uart_port *port, unsigned int state, 609 unsigned int oldstate) 610 { 611 struct stm32_port *stm32port = container_of(port, 612 struct stm32_port, port); 613 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 614 struct stm32_usart_config *cfg = &stm32port->info->cfg; 615 unsigned long flags = 0; 616 617 switch (state) { 618 case UART_PM_STATE_ON: 619 clk_prepare_enable(stm32port->clk); 620 break; 621 case UART_PM_STATE_OFF: 622 spin_lock_irqsave(&port->lock, flags); 623 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 624 spin_unlock_irqrestore(&port->lock, flags); 625 clk_disable_unprepare(stm32port->clk); 626 break; 627 } 628 } 629 630 static const struct uart_ops stm32_uart_ops = { 631 .tx_empty = stm32_tx_empty, 632 .set_mctrl = stm32_set_mctrl, 633 .get_mctrl = stm32_get_mctrl, 634 .stop_tx = stm32_stop_tx, 635 .start_tx = stm32_start_tx, 636 .throttle = stm32_throttle, 637 .unthrottle = stm32_unthrottle, 638 .stop_rx = stm32_stop_rx, 639 .break_ctl = stm32_break_ctl, 640 .startup = stm32_startup, 641 .shutdown = stm32_shutdown, 642 .set_termios = stm32_set_termios, 643 .pm = stm32_pm, 644 .type = stm32_type, 645 .release_port = stm32_release_port, 646 .request_port = stm32_request_port, 647 .config_port = stm32_config_port, 648 .verify_port = stm32_verify_port, 649 }; 650 651 static int stm32_init_port(struct stm32_port *stm32port, 652 struct platform_device *pdev) 653 { 654 struct uart_port *port = &stm32port->port; 655 struct resource *res; 656 int ret; 657 658 port->iotype = UPIO_MEM; 659 port->flags = UPF_BOOT_AUTOCONF; 660 port->ops = &stm32_uart_ops; 661 port->dev = &pdev->dev; 662 port->irq = platform_get_irq(pdev, 0); 663 664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 665 port->membase = devm_ioremap_resource(&pdev->dev, res); 666 if (IS_ERR(port->membase)) 667 return PTR_ERR(port->membase); 668 port->mapbase = res->start; 669 670 spin_lock_init(&port->lock); 671 672 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 673 if (IS_ERR(stm32port->clk)) 674 return PTR_ERR(stm32port->clk); 675 676 /* Ensure that clk rate is correct by enabling the clk */ 677 ret = clk_prepare_enable(stm32port->clk); 678 if (ret) 679 return ret; 680 681 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 682 if (!stm32port->port.uartclk) 683 ret = -EINVAL; 684 685 return ret; 686 } 687 688 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 689 { 690 struct device_node *np = pdev->dev.of_node; 691 int id; 692 693 if (!np) 694 return NULL; 695 696 id = of_alias_get_id(np, "serial"); 697 if (id < 0) 698 id = 0; 699 700 if (WARN_ON(id >= STM32_MAX_PORTS)) 701 return NULL; 702 703 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 704 "st,hw-flow-ctrl"); 705 stm32_ports[id].port.line = id; 706 return &stm32_ports[id]; 707 } 708 709 #ifdef CONFIG_OF 710 static const struct of_device_id stm32_match[] = { 711 { .compatible = "st,stm32-usart", .data = &stm32f4_info}, 712 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 713 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info}, 714 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 715 {}, 716 }; 717 718 MODULE_DEVICE_TABLE(of, stm32_match); 719 #endif 720 721 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 722 struct platform_device *pdev) 723 { 724 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 725 struct uart_port *port = &stm32port->port; 726 struct device *dev = &pdev->dev; 727 struct dma_slave_config config; 728 struct dma_async_tx_descriptor *desc = NULL; 729 dma_cookie_t cookie; 730 int ret; 731 732 /* Request DMA RX channel */ 733 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 734 if (!stm32port->rx_ch) { 735 dev_info(dev, "rx dma alloc failed\n"); 736 return -ENODEV; 737 } 738 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 739 &stm32port->rx_dma_buf, 740 GFP_KERNEL); 741 if (!stm32port->rx_buf) { 742 ret = -ENOMEM; 743 goto alloc_err; 744 } 745 746 /* Configure DMA channel */ 747 memset(&config, 0, sizeof(config)); 748 config.src_addr = port->mapbase + ofs->rdr; 749 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 750 751 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 752 if (ret < 0) { 753 dev_err(dev, "rx dma channel config failed\n"); 754 ret = -ENODEV; 755 goto config_err; 756 } 757 758 /* Prepare a DMA cyclic transaction */ 759 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 760 stm32port->rx_dma_buf, 761 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 762 DMA_PREP_INTERRUPT); 763 if (!desc) { 764 dev_err(dev, "rx dma prep cyclic failed\n"); 765 ret = -ENODEV; 766 goto config_err; 767 } 768 769 /* No callback as dma buffer is drained on usart interrupt */ 770 desc->callback = NULL; 771 desc->callback_param = NULL; 772 773 /* Push current DMA transaction in the pending queue */ 774 cookie = dmaengine_submit(desc); 775 776 /* Issue pending DMA requests */ 777 dma_async_issue_pending(stm32port->rx_ch); 778 779 return 0; 780 781 config_err: 782 dma_free_coherent(&pdev->dev, 783 RX_BUF_L, stm32port->rx_buf, 784 stm32port->rx_dma_buf); 785 786 alloc_err: 787 dma_release_channel(stm32port->rx_ch); 788 stm32port->rx_ch = NULL; 789 790 return ret; 791 } 792 793 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 794 struct platform_device *pdev) 795 { 796 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 797 struct uart_port *port = &stm32port->port; 798 struct device *dev = &pdev->dev; 799 struct dma_slave_config config; 800 int ret; 801 802 stm32port->tx_dma_busy = false; 803 804 /* Request DMA TX channel */ 805 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 806 if (!stm32port->tx_ch) { 807 dev_info(dev, "tx dma alloc failed\n"); 808 return -ENODEV; 809 } 810 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 811 &stm32port->tx_dma_buf, 812 GFP_KERNEL); 813 if (!stm32port->tx_buf) { 814 ret = -ENOMEM; 815 goto alloc_err; 816 } 817 818 /* Configure DMA channel */ 819 memset(&config, 0, sizeof(config)); 820 config.dst_addr = port->mapbase + ofs->tdr; 821 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 822 823 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 824 if (ret < 0) { 825 dev_err(dev, "tx dma channel config failed\n"); 826 ret = -ENODEV; 827 goto config_err; 828 } 829 830 return 0; 831 832 config_err: 833 dma_free_coherent(&pdev->dev, 834 TX_BUF_L, stm32port->tx_buf, 835 stm32port->tx_dma_buf); 836 837 alloc_err: 838 dma_release_channel(stm32port->tx_ch); 839 stm32port->tx_ch = NULL; 840 841 return ret; 842 } 843 844 static int stm32_serial_probe(struct platform_device *pdev) 845 { 846 const struct of_device_id *match; 847 struct stm32_port *stm32port; 848 int ret; 849 850 stm32port = stm32_of_get_stm32_port(pdev); 851 if (!stm32port) 852 return -ENODEV; 853 854 match = of_match_device(stm32_match, &pdev->dev); 855 if (match && match->data) 856 stm32port->info = (struct stm32_usart_info *)match->data; 857 else 858 return -EINVAL; 859 860 ret = stm32_init_port(stm32port, pdev); 861 if (ret) 862 return ret; 863 864 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 865 if (ret) 866 return ret; 867 868 ret = stm32_of_dma_rx_probe(stm32port, pdev); 869 if (ret) 870 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 871 872 ret = stm32_of_dma_tx_probe(stm32port, pdev); 873 if (ret) 874 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 875 876 platform_set_drvdata(pdev, &stm32port->port); 877 878 return 0; 879 } 880 881 static int stm32_serial_remove(struct platform_device *pdev) 882 { 883 struct uart_port *port = platform_get_drvdata(pdev); 884 struct stm32_port *stm32_port = to_stm32_port(port); 885 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 886 887 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 888 889 if (stm32_port->rx_ch) 890 dma_release_channel(stm32_port->rx_ch); 891 892 if (stm32_port->rx_dma_buf) 893 dma_free_coherent(&pdev->dev, 894 RX_BUF_L, stm32_port->rx_buf, 895 stm32_port->rx_dma_buf); 896 897 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 898 899 if (stm32_port->tx_ch) 900 dma_release_channel(stm32_port->tx_ch); 901 902 if (stm32_port->tx_dma_buf) 903 dma_free_coherent(&pdev->dev, 904 TX_BUF_L, stm32_port->tx_buf, 905 stm32_port->tx_dma_buf); 906 907 clk_disable_unprepare(stm32_port->clk); 908 909 return uart_remove_one_port(&stm32_usart_driver, port); 910 } 911 912 913 #ifdef CONFIG_SERIAL_STM32_CONSOLE 914 static void stm32_console_putchar(struct uart_port *port, int ch) 915 { 916 struct stm32_port *stm32_port = to_stm32_port(port); 917 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 918 919 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 920 cpu_relax(); 921 922 writel_relaxed(ch, port->membase + ofs->tdr); 923 } 924 925 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 926 { 927 struct uart_port *port = &stm32_ports[co->index].port; 928 struct stm32_port *stm32_port = to_stm32_port(port); 929 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 930 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 931 unsigned long flags; 932 u32 old_cr1, new_cr1; 933 int locked = 1; 934 935 local_irq_save(flags); 936 if (port->sysrq) 937 locked = 0; 938 else if (oops_in_progress) 939 locked = spin_trylock(&port->lock); 940 else 941 spin_lock(&port->lock); 942 943 /* Save and disable interrupts, enable the transmitter */ 944 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 945 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 946 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 947 writel_relaxed(new_cr1, port->membase + ofs->cr1); 948 949 uart_console_write(port, s, cnt, stm32_console_putchar); 950 951 /* Restore interrupt state */ 952 writel_relaxed(old_cr1, port->membase + ofs->cr1); 953 954 if (locked) 955 spin_unlock(&port->lock); 956 local_irq_restore(flags); 957 } 958 959 static int stm32_console_setup(struct console *co, char *options) 960 { 961 struct stm32_port *stm32port; 962 int baud = 9600; 963 int bits = 8; 964 int parity = 'n'; 965 int flow = 'n'; 966 967 if (co->index >= STM32_MAX_PORTS) 968 return -ENODEV; 969 970 stm32port = &stm32_ports[co->index]; 971 972 /* 973 * This driver does not support early console initialization 974 * (use ARM early printk support instead), so we only expect 975 * this to be called during the uart port registration when the 976 * driver gets probed and the port should be mapped at that point. 977 */ 978 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 979 return -ENXIO; 980 981 if (options) 982 uart_parse_options(options, &baud, &parity, &bits, &flow); 983 984 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 985 } 986 987 static struct console stm32_console = { 988 .name = STM32_SERIAL_NAME, 989 .device = uart_console_device, 990 .write = stm32_console_write, 991 .setup = stm32_console_setup, 992 .flags = CON_PRINTBUFFER, 993 .index = -1, 994 .data = &stm32_usart_driver, 995 }; 996 997 #define STM32_SERIAL_CONSOLE (&stm32_console) 998 999 #else 1000 #define STM32_SERIAL_CONSOLE NULL 1001 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1002 1003 static struct uart_driver stm32_usart_driver = { 1004 .driver_name = DRIVER_NAME, 1005 .dev_name = STM32_SERIAL_NAME, 1006 .major = 0, 1007 .minor = 0, 1008 .nr = STM32_MAX_PORTS, 1009 .cons = STM32_SERIAL_CONSOLE, 1010 }; 1011 1012 static struct platform_driver stm32_serial_driver = { 1013 .probe = stm32_serial_probe, 1014 .remove = stm32_serial_remove, 1015 .driver = { 1016 .name = DRIVER_NAME, 1017 .of_match_table = of_match_ptr(stm32_match), 1018 }, 1019 }; 1020 1021 static int __init usart_init(void) 1022 { 1023 static char banner[] __initdata = "STM32 USART driver initialized"; 1024 int ret; 1025 1026 pr_info("%s\n", banner); 1027 1028 ret = uart_register_driver(&stm32_usart_driver); 1029 if (ret) 1030 return ret; 1031 1032 ret = platform_driver_register(&stm32_serial_driver); 1033 if (ret) 1034 uart_unregister_driver(&stm32_usart_driver); 1035 1036 return ret; 1037 } 1038 1039 static void __exit usart_exit(void) 1040 { 1041 platform_driver_unregister(&stm32_serial_driver); 1042 uart_unregister_driver(&stm32_usart_driver); 1043 } 1044 1045 module_init(usart_init); 1046 module_exit(usart_exit); 1047 1048 MODULE_ALIAS("platform:" DRIVER_NAME); 1049 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1050 MODULE_LICENSE("GPL v2"); 1051