1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c, flags; 218 u32 sr; 219 char flag; 220 221 if (threaded) 222 spin_lock_irqsave(&port->lock, flags); 223 else 224 spin_lock(&port->lock); 225 226 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 227 threaded)) { 228 sr |= USART_SR_DUMMY_RX; 229 flag = TTY_NORMAL; 230 231 /* 232 * Status bits has to be cleared before reading the RDR: 233 * In FIFO mode, reading the RDR will pop the next data 234 * (if any) along with its status bits into the SR. 235 * Not doing so leads to misalignement between RDR and SR, 236 * and clear status bits of the next rx data. 237 * 238 * Clear errors flags for stm32f7 and stm32h7 compatible 239 * devices. On stm32f4 compatible devices, the error bit is 240 * cleared by the sequence [read SR - read DR]. 241 */ 242 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 243 writel_relaxed(sr & USART_SR_ERR_MASK, 244 port->membase + ofs->icr); 245 246 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 247 port->icount.rx++; 248 if (sr & USART_SR_ERR_MASK) { 249 if (sr & USART_SR_ORE) { 250 port->icount.overrun++; 251 } else if (sr & USART_SR_PE) { 252 port->icount.parity++; 253 } else if (sr & USART_SR_FE) { 254 /* Break detection if character is null */ 255 if (!c) { 256 port->icount.brk++; 257 if (uart_handle_break(port)) 258 continue; 259 } else { 260 port->icount.frame++; 261 } 262 } 263 264 sr &= port->read_status_mask; 265 266 if (sr & USART_SR_PE) { 267 flag = TTY_PARITY; 268 } else if (sr & USART_SR_FE) { 269 if (!c) 270 flag = TTY_BREAK; 271 else 272 flag = TTY_FRAME; 273 } 274 } 275 276 if (uart_handle_sysrq_char(port, c)) 277 continue; 278 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 279 } 280 281 if (threaded) 282 spin_unlock_irqrestore(&port->lock, flags); 283 else 284 spin_unlock(&port->lock); 285 286 tty_flip_buffer_push(tport); 287 } 288 289 static void stm32_usart_tx_dma_complete(void *arg) 290 { 291 struct uart_port *port = arg; 292 struct stm32_port *stm32port = to_stm32_port(port); 293 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 294 unsigned long flags; 295 296 dmaengine_terminate_async(stm32port->tx_ch); 297 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 298 stm32port->tx_dma_busy = false; 299 300 /* Let's see if we have pending data to send */ 301 spin_lock_irqsave(&port->lock, flags); 302 stm32_usart_transmit_chars(port); 303 spin_unlock_irqrestore(&port->lock, flags); 304 } 305 306 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 307 { 308 struct stm32_port *stm32_port = to_stm32_port(port); 309 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 310 311 /* 312 * Enables TX FIFO threashold irq when FIFO is enabled, 313 * or TX empty irq when FIFO is disabled 314 */ 315 if (stm32_port->fifoen) 316 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 317 else 318 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 319 } 320 321 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 322 { 323 struct stm32_port *stm32_port = to_stm32_port(port); 324 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 325 326 if (stm32_port->fifoen) 327 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 328 else 329 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 330 } 331 332 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 333 { 334 struct stm32_port *stm32_port = to_stm32_port(port); 335 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 336 struct circ_buf *xmit = &port->state->xmit; 337 338 if (stm32_port->tx_dma_busy) { 339 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 340 stm32_port->tx_dma_busy = false; 341 } 342 343 while (!uart_circ_empty(xmit)) { 344 /* Check that TDR is empty before filling FIFO */ 345 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 346 break; 347 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 348 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 349 port->icount.tx++; 350 } 351 352 /* rely on TXE irq (mask or unmask) for sending remaining data */ 353 if (uart_circ_empty(xmit)) 354 stm32_usart_tx_interrupt_disable(port); 355 else 356 stm32_usart_tx_interrupt_enable(port); 357 } 358 359 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 360 { 361 struct stm32_port *stm32port = to_stm32_port(port); 362 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 363 struct circ_buf *xmit = &port->state->xmit; 364 struct dma_async_tx_descriptor *desc = NULL; 365 unsigned int count, i; 366 367 if (stm32port->tx_dma_busy) 368 return; 369 370 stm32port->tx_dma_busy = true; 371 372 count = uart_circ_chars_pending(xmit); 373 374 if (count > TX_BUF_L) 375 count = TX_BUF_L; 376 377 if (xmit->tail < xmit->head) { 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 379 } else { 380 size_t one = UART_XMIT_SIZE - xmit->tail; 381 size_t two; 382 383 if (one > count) 384 one = count; 385 two = count - one; 386 387 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 388 if (two) 389 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 390 } 391 392 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 393 stm32port->tx_dma_buf, 394 count, 395 DMA_MEM_TO_DEV, 396 DMA_PREP_INTERRUPT); 397 398 if (!desc) 399 goto fallback_err; 400 401 desc->callback = stm32_usart_tx_dma_complete; 402 desc->callback_param = port; 403 404 /* Push current DMA TX transaction in the pending queue */ 405 if (dma_submit_error(dmaengine_submit(desc))) { 406 /* dma no yet started, safe to free resources */ 407 dmaengine_terminate_async(stm32port->tx_ch); 408 goto fallback_err; 409 } 410 411 /* Issue pending DMA TX requests */ 412 dma_async_issue_pending(stm32port->tx_ch); 413 414 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 415 416 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 417 port->icount.tx += count; 418 return; 419 420 fallback_err: 421 for (i = count; i > 0; i--) 422 stm32_usart_transmit_chars_pio(port); 423 } 424 425 static void stm32_usart_transmit_chars(struct uart_port *port) 426 { 427 struct stm32_port *stm32_port = to_stm32_port(port); 428 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 429 struct circ_buf *xmit = &port->state->xmit; 430 431 if (port->x_char) { 432 if (stm32_port->tx_dma_busy) 433 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 434 writel_relaxed(port->x_char, port->membase + ofs->tdr); 435 port->x_char = 0; 436 port->icount.tx++; 437 if (stm32_port->tx_dma_busy) 438 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 439 return; 440 } 441 442 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 443 stm32_usart_tx_interrupt_disable(port); 444 return; 445 } 446 447 if (ofs->icr == UNDEF_REG) 448 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 449 else 450 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 451 452 if (stm32_port->tx_ch) 453 stm32_usart_transmit_chars_dma(port); 454 else 455 stm32_usart_transmit_chars_pio(port); 456 457 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 458 uart_write_wakeup(port); 459 460 if (uart_circ_empty(xmit)) 461 stm32_usart_tx_interrupt_disable(port); 462 } 463 464 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 465 { 466 struct uart_port *port = ptr; 467 struct tty_port *tport = &port->state->port; 468 struct stm32_port *stm32_port = to_stm32_port(port); 469 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 470 u32 sr; 471 472 sr = readl_relaxed(port->membase + ofs->isr); 473 474 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 475 writel_relaxed(USART_ICR_RTOCF, 476 port->membase + ofs->icr); 477 478 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 479 /* Clear wake up flag and disable wake up interrupt */ 480 writel_relaxed(USART_ICR_WUCF, 481 port->membase + ofs->icr); 482 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 483 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 484 pm_wakeup_event(tport->tty->dev, 0); 485 } 486 487 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 488 stm32_usart_receive_chars(port, false); 489 490 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 491 spin_lock(&port->lock); 492 stm32_usart_transmit_chars(port); 493 spin_unlock(&port->lock); 494 } 495 496 if (stm32_port->rx_ch) 497 return IRQ_WAKE_THREAD; 498 else 499 return IRQ_HANDLED; 500 } 501 502 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 503 { 504 struct uart_port *port = ptr; 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 507 if (stm32_port->rx_ch) 508 stm32_usart_receive_chars(port, true); 509 510 return IRQ_HANDLED; 511 } 512 513 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 514 { 515 struct stm32_port *stm32_port = to_stm32_port(port); 516 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 517 518 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 519 return TIOCSER_TEMT; 520 521 return 0; 522 } 523 524 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 528 529 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 530 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 531 else 532 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 533 534 mctrl_gpio_set(stm32_port->gpios, mctrl); 535 } 536 537 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 538 { 539 struct stm32_port *stm32_port = to_stm32_port(port); 540 unsigned int ret; 541 542 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 543 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 544 545 return mctrl_gpio_get(stm32_port->gpios, &ret); 546 } 547 548 static void stm32_usart_enable_ms(struct uart_port *port) 549 { 550 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 551 } 552 553 static void stm32_usart_disable_ms(struct uart_port *port) 554 { 555 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 556 } 557 558 /* Transmit stop */ 559 static void stm32_usart_stop_tx(struct uart_port *port) 560 { 561 struct stm32_port *stm32_port = to_stm32_port(port); 562 struct serial_rs485 *rs485conf = &port->rs485; 563 564 stm32_usart_tx_interrupt_disable(port); 565 566 if (rs485conf->flags & SER_RS485_ENABLED) { 567 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 568 mctrl_gpio_set(stm32_port->gpios, 569 stm32_port->port.mctrl & ~TIOCM_RTS); 570 } else { 571 mctrl_gpio_set(stm32_port->gpios, 572 stm32_port->port.mctrl | TIOCM_RTS); 573 } 574 } 575 } 576 577 /* There are probably characters waiting to be transmitted. */ 578 static void stm32_usart_start_tx(struct uart_port *port) 579 { 580 struct stm32_port *stm32_port = to_stm32_port(port); 581 struct serial_rs485 *rs485conf = &port->rs485; 582 struct circ_buf *xmit = &port->state->xmit; 583 584 if (uart_circ_empty(xmit)) 585 return; 586 587 if (rs485conf->flags & SER_RS485_ENABLED) { 588 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 589 mctrl_gpio_set(stm32_port->gpios, 590 stm32_port->port.mctrl | TIOCM_RTS); 591 } else { 592 mctrl_gpio_set(stm32_port->gpios, 593 stm32_port->port.mctrl & ~TIOCM_RTS); 594 } 595 } 596 597 stm32_usart_transmit_chars(port); 598 } 599 600 /* Throttle the remote when input buffer is about to overflow. */ 601 static void stm32_usart_throttle(struct uart_port *port) 602 { 603 struct stm32_port *stm32_port = to_stm32_port(port); 604 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 605 unsigned long flags; 606 607 spin_lock_irqsave(&port->lock, flags); 608 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 609 if (stm32_port->cr3_irq) 610 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 611 612 spin_unlock_irqrestore(&port->lock, flags); 613 } 614 615 /* Unthrottle the remote, the input buffer can now accept data. */ 616 static void stm32_usart_unthrottle(struct uart_port *port) 617 { 618 struct stm32_port *stm32_port = to_stm32_port(port); 619 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 620 unsigned long flags; 621 622 spin_lock_irqsave(&port->lock, flags); 623 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 624 if (stm32_port->cr3_irq) 625 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 626 627 spin_unlock_irqrestore(&port->lock, flags); 628 } 629 630 /* Receive stop */ 631 static void stm32_usart_stop_rx(struct uart_port *port) 632 { 633 struct stm32_port *stm32_port = to_stm32_port(port); 634 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 635 636 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 637 if (stm32_port->cr3_irq) 638 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 639 } 640 641 /* Handle breaks - ignored by us */ 642 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 643 { 644 } 645 646 static int stm32_usart_startup(struct uart_port *port) 647 { 648 struct stm32_port *stm32_port = to_stm32_port(port); 649 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 650 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 651 const char *name = to_platform_device(port->dev)->name; 652 u32 val; 653 int ret; 654 655 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 656 stm32_usart_threaded_interrupt, 657 IRQF_NO_SUSPEND, name, port); 658 if (ret) 659 return ret; 660 661 /* RX FIFO Flush */ 662 if (ofs->rqr != UNDEF_REG) 663 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 664 665 /* RX enabling */ 666 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 667 stm32_usart_set_bits(port, ofs->cr1, val); 668 669 return 0; 670 } 671 672 static void stm32_usart_shutdown(struct uart_port *port) 673 { 674 struct stm32_port *stm32_port = to_stm32_port(port); 675 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 676 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 677 u32 val, isr; 678 int ret; 679 680 /* Disable modem control interrupts */ 681 stm32_usart_disable_ms(port); 682 683 val = USART_CR1_TXEIE | USART_CR1_TE; 684 val |= stm32_port->cr1_irq | USART_CR1_RE; 685 val |= BIT(cfg->uart_enable_bit); 686 if (stm32_port->fifoen) 687 val |= USART_CR1_FIFOEN; 688 689 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 690 isr, (isr & USART_SR_TC), 691 10, 100000); 692 693 /* Send the TC error message only when ISR_TC is not set */ 694 if (ret) 695 dev_err(port->dev, "Transmission is not complete\n"); 696 697 /* flush RX & TX FIFO */ 698 if (ofs->rqr != UNDEF_REG) 699 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 700 port->membase + ofs->rqr); 701 702 stm32_usart_clr_bits(port, ofs->cr1, val); 703 704 free_irq(port->irq, port); 705 } 706 707 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 708 { 709 unsigned int bits; 710 711 tcflag_t cflag = termios->c_cflag; 712 713 switch (cflag & CSIZE) { 714 /* 715 * CSIZE settings are not necessarily supported in hardware. 716 * CSIZE unsupported configurations are handled here to set word length 717 * to 8 bits word as default configuration and to print debug message. 718 */ 719 case CS5: 720 bits = 5; 721 break; 722 case CS6: 723 bits = 6; 724 break; 725 case CS7: 726 bits = 7; 727 break; 728 /* default including CS8 */ 729 default: 730 bits = 8; 731 break; 732 } 733 734 return bits; 735 } 736 737 static void stm32_usart_set_termios(struct uart_port *port, 738 struct ktermios *termios, 739 struct ktermios *old) 740 { 741 struct stm32_port *stm32_port = to_stm32_port(port); 742 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 743 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 744 struct serial_rs485 *rs485conf = &port->rs485; 745 unsigned int baud, bits; 746 u32 usartdiv, mantissa, fraction, oversampling; 747 tcflag_t cflag = termios->c_cflag; 748 u32 cr1, cr2, cr3, isr; 749 unsigned long flags; 750 int ret; 751 752 if (!stm32_port->hw_flow_control) 753 cflag &= ~CRTSCTS; 754 755 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 756 757 spin_lock_irqsave(&port->lock, flags); 758 759 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 760 isr, 761 (isr & USART_SR_TC), 762 10, 100000); 763 764 /* Send the TC error message only when ISR_TC is not set. */ 765 if (ret) 766 dev_err(port->dev, "Transmission is not complete\n"); 767 768 /* Stop serial port and reset value */ 769 writel_relaxed(0, port->membase + ofs->cr1); 770 771 /* flush RX & TX FIFO */ 772 if (ofs->rqr != UNDEF_REG) 773 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 774 port->membase + ofs->rqr); 775 776 cr1 = USART_CR1_TE | USART_CR1_RE; 777 if (stm32_port->fifoen) 778 cr1 |= USART_CR1_FIFOEN; 779 cr2 = 0; 780 781 /* Tx and RX FIFO configuration */ 782 cr3 = readl_relaxed(port->membase + ofs->cr3); 783 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 784 if (stm32_port->fifoen) { 785 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 786 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 787 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 788 } 789 790 if (cflag & CSTOPB) 791 cr2 |= USART_CR2_STOP_2B; 792 793 bits = stm32_usart_get_databits(termios); 794 stm32_port->rdr_mask = (BIT(bits) - 1); 795 796 if (cflag & PARENB) { 797 bits++; 798 cr1 |= USART_CR1_PCE; 799 } 800 801 /* 802 * Word length configuration: 803 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 804 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 805 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 806 * M0 and M1 already cleared by cr1 initialization. 807 */ 808 if (bits == 9) 809 cr1 |= USART_CR1_M0; 810 else if ((bits == 7) && cfg->has_7bits_data) 811 cr1 |= USART_CR1_M1; 812 else if (bits != 8) 813 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 814 , bits); 815 816 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 817 stm32_port->fifoen)) { 818 if (cflag & CSTOPB) 819 bits = bits + 3; /* 1 start bit + 2 stop bits */ 820 else 821 bits = bits + 2; /* 1 start bit + 1 stop bit */ 822 823 /* RX timeout irq to occur after last stop bit + bits */ 824 stm32_port->cr1_irq = USART_CR1_RTOIE; 825 writel_relaxed(bits, port->membase + ofs->rtor); 826 cr2 |= USART_CR2_RTOEN; 827 /* Not using dma, enable fifo threshold irq */ 828 if (!stm32_port->rx_ch) 829 stm32_port->cr3_irq = USART_CR3_RXFTIE; 830 } 831 832 cr1 |= stm32_port->cr1_irq; 833 cr3 |= stm32_port->cr3_irq; 834 835 if (cflag & PARODD) 836 cr1 |= USART_CR1_PS; 837 838 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 839 if (cflag & CRTSCTS) { 840 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 841 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 842 } 843 844 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 845 846 /* 847 * The USART supports 16 or 8 times oversampling. 848 * By default we prefer 16 times oversampling, so that the receiver 849 * has a better tolerance to clock deviations. 850 * 8 times oversampling is only used to achieve higher speeds. 851 */ 852 if (usartdiv < 16) { 853 oversampling = 8; 854 cr1 |= USART_CR1_OVER8; 855 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 856 } else { 857 oversampling = 16; 858 cr1 &= ~USART_CR1_OVER8; 859 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 860 } 861 862 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 863 fraction = usartdiv % oversampling; 864 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 865 866 uart_update_timeout(port, cflag, baud); 867 868 port->read_status_mask = USART_SR_ORE; 869 if (termios->c_iflag & INPCK) 870 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 871 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 872 port->read_status_mask |= USART_SR_FE; 873 874 /* Characters to ignore */ 875 port->ignore_status_mask = 0; 876 if (termios->c_iflag & IGNPAR) 877 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 878 if (termios->c_iflag & IGNBRK) { 879 port->ignore_status_mask |= USART_SR_FE; 880 /* 881 * If we're ignoring parity and break indicators, 882 * ignore overruns too (for real raw support). 883 */ 884 if (termios->c_iflag & IGNPAR) 885 port->ignore_status_mask |= USART_SR_ORE; 886 } 887 888 /* Ignore all characters if CREAD is not set */ 889 if ((termios->c_cflag & CREAD) == 0) 890 port->ignore_status_mask |= USART_SR_DUMMY_RX; 891 892 if (stm32_port->rx_ch) 893 cr3 |= USART_CR3_DMAR; 894 895 if (rs485conf->flags & SER_RS485_ENABLED) { 896 stm32_usart_config_reg_rs485(&cr1, &cr3, 897 rs485conf->delay_rts_before_send, 898 rs485conf->delay_rts_after_send, 899 baud); 900 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 901 cr3 &= ~USART_CR3_DEP; 902 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 903 } else { 904 cr3 |= USART_CR3_DEP; 905 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 906 } 907 908 } else { 909 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 910 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 911 } 912 913 /* Configure wake up from low power on start bit detection */ 914 if (stm32_port->wakeirq > 0) { 915 cr3 &= ~USART_CR3_WUS_MASK; 916 cr3 |= USART_CR3_WUS_START_BIT; 917 } 918 919 writel_relaxed(cr3, port->membase + ofs->cr3); 920 writel_relaxed(cr2, port->membase + ofs->cr2); 921 writel_relaxed(cr1, port->membase + ofs->cr1); 922 923 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 924 spin_unlock_irqrestore(&port->lock, flags); 925 926 /* Handle modem control interrupts */ 927 if (UART_ENABLE_MS(port, termios->c_cflag)) 928 stm32_usart_enable_ms(port); 929 else 930 stm32_usart_disable_ms(port); 931 } 932 933 static const char *stm32_usart_type(struct uart_port *port) 934 { 935 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 936 } 937 938 static void stm32_usart_release_port(struct uart_port *port) 939 { 940 } 941 942 static int stm32_usart_request_port(struct uart_port *port) 943 { 944 return 0; 945 } 946 947 static void stm32_usart_config_port(struct uart_port *port, int flags) 948 { 949 if (flags & UART_CONFIG_TYPE) 950 port->type = PORT_STM32; 951 } 952 953 static int 954 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 955 { 956 /* No user changeable parameters */ 957 return -EINVAL; 958 } 959 960 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 961 unsigned int oldstate) 962 { 963 struct stm32_port *stm32port = container_of(port, 964 struct stm32_port, port); 965 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 966 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 967 unsigned long flags = 0; 968 969 switch (state) { 970 case UART_PM_STATE_ON: 971 pm_runtime_get_sync(port->dev); 972 break; 973 case UART_PM_STATE_OFF: 974 spin_lock_irqsave(&port->lock, flags); 975 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 976 spin_unlock_irqrestore(&port->lock, flags); 977 pm_runtime_put_sync(port->dev); 978 break; 979 } 980 } 981 982 static const struct uart_ops stm32_uart_ops = { 983 .tx_empty = stm32_usart_tx_empty, 984 .set_mctrl = stm32_usart_set_mctrl, 985 .get_mctrl = stm32_usart_get_mctrl, 986 .stop_tx = stm32_usart_stop_tx, 987 .start_tx = stm32_usart_start_tx, 988 .throttle = stm32_usart_throttle, 989 .unthrottle = stm32_usart_unthrottle, 990 .stop_rx = stm32_usart_stop_rx, 991 .enable_ms = stm32_usart_enable_ms, 992 .break_ctl = stm32_usart_break_ctl, 993 .startup = stm32_usart_startup, 994 .shutdown = stm32_usart_shutdown, 995 .set_termios = stm32_usart_set_termios, 996 .pm = stm32_usart_pm, 997 .type = stm32_usart_type, 998 .release_port = stm32_usart_release_port, 999 .request_port = stm32_usart_request_port, 1000 .config_port = stm32_usart_config_port, 1001 .verify_port = stm32_usart_verify_port, 1002 }; 1003 1004 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1005 { 1006 clk_disable_unprepare(stm32port->clk); 1007 } 1008 1009 static int stm32_usart_init_port(struct stm32_port *stm32port, 1010 struct platform_device *pdev) 1011 { 1012 struct uart_port *port = &stm32port->port; 1013 struct resource *res; 1014 int ret, irq; 1015 1016 irq = platform_get_irq(pdev, 0); 1017 if (irq <= 0) 1018 return irq ? : -ENODEV; 1019 1020 port->iotype = UPIO_MEM; 1021 port->flags = UPF_BOOT_AUTOCONF; 1022 port->ops = &stm32_uart_ops; 1023 port->dev = &pdev->dev; 1024 port->fifosize = stm32port->info->cfg.fifosize; 1025 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1026 port->irq = irq; 1027 port->rs485_config = stm32_usart_config_rs485; 1028 1029 ret = stm32_usart_init_rs485(port, pdev); 1030 if (ret) 1031 return ret; 1032 1033 if (stm32port->info->cfg.has_wakeup) { 1034 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1035 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1036 return stm32port->wakeirq ? : -ENODEV; 1037 } 1038 1039 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1040 1041 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1042 port->membase = devm_ioremap_resource(&pdev->dev, res); 1043 if (IS_ERR(port->membase)) 1044 return PTR_ERR(port->membase); 1045 port->mapbase = res->start; 1046 1047 spin_lock_init(&port->lock); 1048 1049 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1050 if (IS_ERR(stm32port->clk)) 1051 return PTR_ERR(stm32port->clk); 1052 1053 /* Ensure that clk rate is correct by enabling the clk */ 1054 ret = clk_prepare_enable(stm32port->clk); 1055 if (ret) 1056 return ret; 1057 1058 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1059 if (!stm32port->port.uartclk) { 1060 ret = -EINVAL; 1061 goto err_clk; 1062 } 1063 1064 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1065 if (IS_ERR(stm32port->gpios)) { 1066 ret = PTR_ERR(stm32port->gpios); 1067 goto err_clk; 1068 } 1069 1070 /* 1071 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1072 * properties should not be specified. 1073 */ 1074 if (stm32port->hw_flow_control) { 1075 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1076 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1077 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1078 ret = -EINVAL; 1079 goto err_clk; 1080 } 1081 } 1082 1083 return ret; 1084 1085 err_clk: 1086 clk_disable_unprepare(stm32port->clk); 1087 1088 return ret; 1089 } 1090 1091 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1092 { 1093 struct device_node *np = pdev->dev.of_node; 1094 int id; 1095 1096 if (!np) 1097 return NULL; 1098 1099 id = of_alias_get_id(np, "serial"); 1100 if (id < 0) { 1101 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1102 return NULL; 1103 } 1104 1105 if (WARN_ON(id >= STM32_MAX_PORTS)) 1106 return NULL; 1107 1108 stm32_ports[id].hw_flow_control = 1109 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1110 of_property_read_bool (np, "uart-has-rtscts"); 1111 stm32_ports[id].port.line = id; 1112 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1113 stm32_ports[id].cr3_irq = 0; 1114 stm32_ports[id].last_res = RX_BUF_L; 1115 return &stm32_ports[id]; 1116 } 1117 1118 #ifdef CONFIG_OF 1119 static const struct of_device_id stm32_match[] = { 1120 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1121 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1122 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1123 {}, 1124 }; 1125 1126 MODULE_DEVICE_TABLE(of, stm32_match); 1127 #endif 1128 1129 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1130 struct platform_device *pdev) 1131 { 1132 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1133 struct uart_port *port = &stm32port->port; 1134 struct device *dev = &pdev->dev; 1135 struct dma_slave_config config; 1136 struct dma_async_tx_descriptor *desc = NULL; 1137 int ret; 1138 1139 /* Request DMA RX channel */ 1140 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1141 if (!stm32port->rx_ch) { 1142 dev_info(dev, "rx dma alloc failed\n"); 1143 return -ENODEV; 1144 } 1145 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1146 &stm32port->rx_dma_buf, 1147 GFP_KERNEL); 1148 if (!stm32port->rx_buf) { 1149 ret = -ENOMEM; 1150 goto alloc_err; 1151 } 1152 1153 /* Configure DMA channel */ 1154 memset(&config, 0, sizeof(config)); 1155 config.src_addr = port->mapbase + ofs->rdr; 1156 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1157 1158 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1159 if (ret < 0) { 1160 dev_err(dev, "rx dma channel config failed\n"); 1161 ret = -ENODEV; 1162 goto config_err; 1163 } 1164 1165 /* Prepare a DMA cyclic transaction */ 1166 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1167 stm32port->rx_dma_buf, 1168 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1169 DMA_PREP_INTERRUPT); 1170 if (!desc) { 1171 dev_err(dev, "rx dma prep cyclic failed\n"); 1172 ret = -ENODEV; 1173 goto config_err; 1174 } 1175 1176 /* No callback as dma buffer is drained on usart interrupt */ 1177 desc->callback = NULL; 1178 desc->callback_param = NULL; 1179 1180 /* Push current DMA transaction in the pending queue */ 1181 ret = dma_submit_error(dmaengine_submit(desc)); 1182 if (ret) { 1183 dmaengine_terminate_sync(stm32port->rx_ch); 1184 goto config_err; 1185 } 1186 1187 /* Issue pending DMA requests */ 1188 dma_async_issue_pending(stm32port->rx_ch); 1189 1190 return 0; 1191 1192 config_err: 1193 dma_free_coherent(&pdev->dev, 1194 RX_BUF_L, stm32port->rx_buf, 1195 stm32port->rx_dma_buf); 1196 1197 alloc_err: 1198 dma_release_channel(stm32port->rx_ch); 1199 stm32port->rx_ch = NULL; 1200 1201 return ret; 1202 } 1203 1204 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1205 struct platform_device *pdev) 1206 { 1207 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1208 struct uart_port *port = &stm32port->port; 1209 struct device *dev = &pdev->dev; 1210 struct dma_slave_config config; 1211 int ret; 1212 1213 stm32port->tx_dma_busy = false; 1214 1215 /* Request DMA TX channel */ 1216 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1217 if (!stm32port->tx_ch) { 1218 dev_info(dev, "tx dma alloc failed\n"); 1219 return -ENODEV; 1220 } 1221 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1222 &stm32port->tx_dma_buf, 1223 GFP_KERNEL); 1224 if (!stm32port->tx_buf) { 1225 ret = -ENOMEM; 1226 goto alloc_err; 1227 } 1228 1229 /* Configure DMA channel */ 1230 memset(&config, 0, sizeof(config)); 1231 config.dst_addr = port->mapbase + ofs->tdr; 1232 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1233 1234 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1235 if (ret < 0) { 1236 dev_err(dev, "tx dma channel config failed\n"); 1237 ret = -ENODEV; 1238 goto config_err; 1239 } 1240 1241 return 0; 1242 1243 config_err: 1244 dma_free_coherent(&pdev->dev, 1245 TX_BUF_L, stm32port->tx_buf, 1246 stm32port->tx_dma_buf); 1247 1248 alloc_err: 1249 dma_release_channel(stm32port->tx_ch); 1250 stm32port->tx_ch = NULL; 1251 1252 return ret; 1253 } 1254 1255 static int stm32_usart_serial_probe(struct platform_device *pdev) 1256 { 1257 struct stm32_port *stm32port; 1258 int ret; 1259 1260 stm32port = stm32_usart_of_get_port(pdev); 1261 if (!stm32port) 1262 return -ENODEV; 1263 1264 stm32port->info = of_device_get_match_data(&pdev->dev); 1265 if (!stm32port->info) 1266 return -EINVAL; 1267 1268 ret = stm32_usart_init_port(stm32port, pdev); 1269 if (ret) 1270 return ret; 1271 1272 if (stm32port->wakeirq > 0) { 1273 ret = device_init_wakeup(&pdev->dev, true); 1274 if (ret) 1275 goto err_uninit; 1276 1277 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1278 stm32port->wakeirq); 1279 if (ret) 1280 goto err_nowup; 1281 1282 device_set_wakeup_enable(&pdev->dev, false); 1283 } 1284 1285 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1286 if (ret) 1287 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1288 1289 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1290 if (ret) 1291 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1292 1293 platform_set_drvdata(pdev, &stm32port->port); 1294 1295 pm_runtime_get_noresume(&pdev->dev); 1296 pm_runtime_set_active(&pdev->dev); 1297 pm_runtime_enable(&pdev->dev); 1298 1299 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1300 if (ret) 1301 goto err_port; 1302 1303 pm_runtime_put_sync(&pdev->dev); 1304 1305 return 0; 1306 1307 err_port: 1308 pm_runtime_disable(&pdev->dev); 1309 pm_runtime_set_suspended(&pdev->dev); 1310 pm_runtime_put_noidle(&pdev->dev); 1311 1312 if (stm32port->rx_ch) { 1313 dmaengine_terminate_async(stm32port->rx_ch); 1314 dma_release_channel(stm32port->rx_ch); 1315 } 1316 1317 if (stm32port->rx_dma_buf) 1318 dma_free_coherent(&pdev->dev, 1319 RX_BUF_L, stm32port->rx_buf, 1320 stm32port->rx_dma_buf); 1321 1322 if (stm32port->tx_ch) { 1323 dmaengine_terminate_async(stm32port->tx_ch); 1324 dma_release_channel(stm32port->tx_ch); 1325 } 1326 1327 if (stm32port->tx_dma_buf) 1328 dma_free_coherent(&pdev->dev, 1329 TX_BUF_L, stm32port->tx_buf, 1330 stm32port->tx_dma_buf); 1331 1332 if (stm32port->wakeirq > 0) 1333 dev_pm_clear_wake_irq(&pdev->dev); 1334 1335 err_nowup: 1336 if (stm32port->wakeirq > 0) 1337 device_init_wakeup(&pdev->dev, false); 1338 1339 err_uninit: 1340 stm32_usart_deinit_port(stm32port); 1341 1342 return ret; 1343 } 1344 1345 static int stm32_usart_serial_remove(struct platform_device *pdev) 1346 { 1347 struct uart_port *port = platform_get_drvdata(pdev); 1348 struct stm32_port *stm32_port = to_stm32_port(port); 1349 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1350 int err; 1351 1352 pm_runtime_get_sync(&pdev->dev); 1353 err = uart_remove_one_port(&stm32_usart_driver, port); 1354 if (err) 1355 return(err); 1356 1357 pm_runtime_disable(&pdev->dev); 1358 pm_runtime_set_suspended(&pdev->dev); 1359 pm_runtime_put_noidle(&pdev->dev); 1360 1361 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1362 1363 if (stm32_port->rx_ch) { 1364 dmaengine_terminate_async(stm32_port->rx_ch); 1365 dma_release_channel(stm32_port->rx_ch); 1366 } 1367 1368 if (stm32_port->rx_dma_buf) 1369 dma_free_coherent(&pdev->dev, 1370 RX_BUF_L, stm32_port->rx_buf, 1371 stm32_port->rx_dma_buf); 1372 1373 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1374 1375 if (stm32_port->tx_ch) { 1376 dmaengine_terminate_async(stm32_port->tx_ch); 1377 dma_release_channel(stm32_port->tx_ch); 1378 } 1379 1380 if (stm32_port->tx_dma_buf) 1381 dma_free_coherent(&pdev->dev, 1382 TX_BUF_L, stm32_port->tx_buf, 1383 stm32_port->tx_dma_buf); 1384 1385 if (stm32_port->wakeirq > 0) { 1386 dev_pm_clear_wake_irq(&pdev->dev); 1387 device_init_wakeup(&pdev->dev, false); 1388 } 1389 1390 stm32_usart_deinit_port(stm32_port); 1391 1392 return 0; 1393 } 1394 1395 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1396 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1397 { 1398 struct stm32_port *stm32_port = to_stm32_port(port); 1399 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1400 1401 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1402 cpu_relax(); 1403 1404 writel_relaxed(ch, port->membase + ofs->tdr); 1405 } 1406 1407 static void stm32_usart_console_write(struct console *co, const char *s, 1408 unsigned int cnt) 1409 { 1410 struct uart_port *port = &stm32_ports[co->index].port; 1411 struct stm32_port *stm32_port = to_stm32_port(port); 1412 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1413 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1414 unsigned long flags; 1415 u32 old_cr1, new_cr1; 1416 int locked = 1; 1417 1418 local_irq_save(flags); 1419 if (port->sysrq) 1420 locked = 0; 1421 else if (oops_in_progress) 1422 locked = spin_trylock(&port->lock); 1423 else 1424 spin_lock(&port->lock); 1425 1426 /* Save and disable interrupts, enable the transmitter */ 1427 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1428 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1429 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1430 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1431 1432 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1433 1434 /* Restore interrupt state */ 1435 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1436 1437 if (locked) 1438 spin_unlock(&port->lock); 1439 local_irq_restore(flags); 1440 } 1441 1442 static int stm32_usart_console_setup(struct console *co, char *options) 1443 { 1444 struct stm32_port *stm32port; 1445 int baud = 9600; 1446 int bits = 8; 1447 int parity = 'n'; 1448 int flow = 'n'; 1449 1450 if (co->index >= STM32_MAX_PORTS) 1451 return -ENODEV; 1452 1453 stm32port = &stm32_ports[co->index]; 1454 1455 /* 1456 * This driver does not support early console initialization 1457 * (use ARM early printk support instead), so we only expect 1458 * this to be called during the uart port registration when the 1459 * driver gets probed and the port should be mapped at that point. 1460 */ 1461 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1462 return -ENXIO; 1463 1464 if (options) 1465 uart_parse_options(options, &baud, &parity, &bits, &flow); 1466 1467 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1468 } 1469 1470 static struct console stm32_console = { 1471 .name = STM32_SERIAL_NAME, 1472 .device = uart_console_device, 1473 .write = stm32_usart_console_write, 1474 .setup = stm32_usart_console_setup, 1475 .flags = CON_PRINTBUFFER, 1476 .index = -1, 1477 .data = &stm32_usart_driver, 1478 }; 1479 1480 #define STM32_SERIAL_CONSOLE (&stm32_console) 1481 1482 #else 1483 #define STM32_SERIAL_CONSOLE NULL 1484 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1485 1486 static struct uart_driver stm32_usart_driver = { 1487 .driver_name = DRIVER_NAME, 1488 .dev_name = STM32_SERIAL_NAME, 1489 .major = 0, 1490 .minor = 0, 1491 .nr = STM32_MAX_PORTS, 1492 .cons = STM32_SERIAL_CONSOLE, 1493 }; 1494 1495 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1496 bool enable) 1497 { 1498 struct stm32_port *stm32_port = to_stm32_port(port); 1499 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1500 1501 if (stm32_port->wakeirq <= 0) 1502 return; 1503 1504 /* 1505 * Enable low-power wake-up and wake-up irq if argument is set to 1506 * "enable", disable low-power wake-up and wake-up irq otherwise 1507 */ 1508 if (enable) { 1509 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1510 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1511 } else { 1512 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1513 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 1514 } 1515 } 1516 1517 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1518 { 1519 struct uart_port *port = dev_get_drvdata(dev); 1520 1521 uart_suspend_port(&stm32_usart_driver, port); 1522 1523 if (device_may_wakeup(dev)) 1524 stm32_usart_serial_en_wakeup(port, true); 1525 else 1526 stm32_usart_serial_en_wakeup(port, false); 1527 1528 /* 1529 * When "no_console_suspend" is enabled, keep the pinctrl default state 1530 * and rely on bootloader stage to restore this state upon resume. 1531 * Otherwise, apply the idle or sleep states depending on wakeup 1532 * capabilities. 1533 */ 1534 if (console_suspend_enabled || !uart_console(port)) { 1535 if (device_may_wakeup(dev)) 1536 pinctrl_pm_select_idle_state(dev); 1537 else 1538 pinctrl_pm_select_sleep_state(dev); 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1545 { 1546 struct uart_port *port = dev_get_drvdata(dev); 1547 1548 pinctrl_pm_select_default_state(dev); 1549 1550 if (device_may_wakeup(dev)) 1551 stm32_usart_serial_en_wakeup(port, false); 1552 1553 return uart_resume_port(&stm32_usart_driver, port); 1554 } 1555 1556 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1557 { 1558 struct uart_port *port = dev_get_drvdata(dev); 1559 struct stm32_port *stm32port = container_of(port, 1560 struct stm32_port, port); 1561 1562 clk_disable_unprepare(stm32port->clk); 1563 1564 return 0; 1565 } 1566 1567 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1568 { 1569 struct uart_port *port = dev_get_drvdata(dev); 1570 struct stm32_port *stm32port = container_of(port, 1571 struct stm32_port, port); 1572 1573 return clk_prepare_enable(stm32port->clk); 1574 } 1575 1576 static const struct dev_pm_ops stm32_serial_pm_ops = { 1577 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1578 stm32_usart_runtime_resume, NULL) 1579 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1580 stm32_usart_serial_resume) 1581 }; 1582 1583 static struct platform_driver stm32_serial_driver = { 1584 .probe = stm32_usart_serial_probe, 1585 .remove = stm32_usart_serial_remove, 1586 .driver = { 1587 .name = DRIVER_NAME, 1588 .pm = &stm32_serial_pm_ops, 1589 .of_match_table = of_match_ptr(stm32_match), 1590 }, 1591 }; 1592 1593 static int __init stm32_usart_init(void) 1594 { 1595 static char banner[] __initdata = "STM32 USART driver initialized"; 1596 int ret; 1597 1598 pr_info("%s\n", banner); 1599 1600 ret = uart_register_driver(&stm32_usart_driver); 1601 if (ret) 1602 return ret; 1603 1604 ret = platform_driver_register(&stm32_serial_driver); 1605 if (ret) 1606 uart_unregister_driver(&stm32_usart_driver); 1607 1608 return ret; 1609 } 1610 1611 static void __exit stm32_usart_exit(void) 1612 { 1613 platform_driver_unregister(&stm32_serial_driver); 1614 uart_unregister_driver(&stm32_usart_driver); 1615 } 1616 1617 module_init(stm32_usart_init); 1618 module_exit(stm32_usart_exit); 1619 1620 MODULE_ALIAS("platform:" DRIVER_NAME); 1621 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1622 MODULE_LICENSE("GPL v2"); 1623