1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 248a6092fSMaxime Coquelin /* 348a6092fSMaxime Coquelin * Copyright (C) Maxime Coquelin 2015 43e5fcbacSBich HEMON * Copyright (C) STMicroelectronics SA 2017 5ada8618fSAlexandre TORGUE * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 68ebd9665SErwan Le Ray * Gerald Baeza <gerald.baeza@foss.st.com> 78ebd9665SErwan Le Ray * Erwan Le Ray <erwan.leray@foss.st.com> 848a6092fSMaxime Coquelin * 948a6092fSMaxime Coquelin * Inspired by st-asc.c from STMicroelectronics (c) 1048a6092fSMaxime Coquelin */ 1148a6092fSMaxime Coquelin 1234891872SAlexandre TORGUE #include <linux/clk.h> 1348a6092fSMaxime Coquelin #include <linux/console.h> 1448a6092fSMaxime Coquelin #include <linux/delay.h> 1534891872SAlexandre TORGUE #include <linux/dma-direction.h> 1634891872SAlexandre TORGUE #include <linux/dmaengine.h> 1734891872SAlexandre TORGUE #include <linux/dma-mapping.h> 1834891872SAlexandre TORGUE #include <linux/io.h> 1934891872SAlexandre TORGUE #include <linux/iopoll.h> 2034891872SAlexandre TORGUE #include <linux/irq.h> 2134891872SAlexandre TORGUE #include <linux/module.h> 2248a6092fSMaxime Coquelin #include <linux/of.h> 2348a6092fSMaxime Coquelin #include <linux/of_platform.h> 2494616d9aSErwan Le Ray #include <linux/pinctrl/consumer.h> 2534891872SAlexandre TORGUE #include <linux/platform_device.h> 2634891872SAlexandre TORGUE #include <linux/pm_runtime.h> 27270e5a74SFabrice Gasnier #include <linux/pm_wakeirq.h> 2848a6092fSMaxime Coquelin #include <linux/serial_core.h> 2934891872SAlexandre TORGUE #include <linux/serial.h> 3034891872SAlexandre TORGUE #include <linux/spinlock.h> 3134891872SAlexandre TORGUE #include <linux/sysrq.h> 3234891872SAlexandre TORGUE #include <linux/tty_flip.h> 3334891872SAlexandre TORGUE #include <linux/tty.h> 3448a6092fSMaxime Coquelin 356cf61b9bSManivannan Sadhasivam #include "serial_mctrl_gpio.h" 36bc5a0b55SAlexandre TORGUE #include "stm32-usart.h" 3748a6092fSMaxime Coquelin 38c7039ce9SBen Dooks 39c7039ce9SBen Dooks /* Register offsets */ 40dfdabd38SRen Zhijie static struct stm32_usart_info __maybe_unused stm32f4_info = { 41c7039ce9SBen Dooks .ofs = { 42c7039ce9SBen Dooks .isr = 0x00, 43c7039ce9SBen Dooks .rdr = 0x04, 44c7039ce9SBen Dooks .tdr = 0x04, 45c7039ce9SBen Dooks .brr = 0x08, 46c7039ce9SBen Dooks .cr1 = 0x0c, 47c7039ce9SBen Dooks .cr2 = 0x10, 48c7039ce9SBen Dooks .cr3 = 0x14, 49c7039ce9SBen Dooks .gtpr = 0x18, 50c7039ce9SBen Dooks .rtor = UNDEF_REG, 51c7039ce9SBen Dooks .rqr = UNDEF_REG, 52c7039ce9SBen Dooks .icr = UNDEF_REG, 53c7039ce9SBen Dooks }, 54c7039ce9SBen Dooks .cfg = { 55c7039ce9SBen Dooks .uart_enable_bit = 13, 56c7039ce9SBen Dooks .has_7bits_data = false, 57c7039ce9SBen Dooks .fifosize = 1, 58c7039ce9SBen Dooks } 59c7039ce9SBen Dooks }; 60c7039ce9SBen Dooks 61dfdabd38SRen Zhijie static struct stm32_usart_info __maybe_unused stm32f7_info = { 62c7039ce9SBen Dooks .ofs = { 63c7039ce9SBen Dooks .cr1 = 0x00, 64c7039ce9SBen Dooks .cr2 = 0x04, 65c7039ce9SBen Dooks .cr3 = 0x08, 66c7039ce9SBen Dooks .brr = 0x0c, 67c7039ce9SBen Dooks .gtpr = 0x10, 68c7039ce9SBen Dooks .rtor = 0x14, 69c7039ce9SBen Dooks .rqr = 0x18, 70c7039ce9SBen Dooks .isr = 0x1c, 71c7039ce9SBen Dooks .icr = 0x20, 72c7039ce9SBen Dooks .rdr = 0x24, 73c7039ce9SBen Dooks .tdr = 0x28, 74c7039ce9SBen Dooks }, 75c7039ce9SBen Dooks .cfg = { 76c7039ce9SBen Dooks .uart_enable_bit = 0, 77c7039ce9SBen Dooks .has_7bits_data = true, 78c7039ce9SBen Dooks .has_swap = true, 79c7039ce9SBen Dooks .fifosize = 1, 80c7039ce9SBen Dooks } 81c7039ce9SBen Dooks }; 82c7039ce9SBen Dooks 83dfdabd38SRen Zhijie static struct stm32_usart_info __maybe_unused stm32h7_info = { 84c7039ce9SBen Dooks .ofs = { 85c7039ce9SBen Dooks .cr1 = 0x00, 86c7039ce9SBen Dooks .cr2 = 0x04, 87c7039ce9SBen Dooks .cr3 = 0x08, 88c7039ce9SBen Dooks .brr = 0x0c, 89c7039ce9SBen Dooks .gtpr = 0x10, 90c7039ce9SBen Dooks .rtor = 0x14, 91c7039ce9SBen Dooks .rqr = 0x18, 92c7039ce9SBen Dooks .isr = 0x1c, 93c7039ce9SBen Dooks .icr = 0x20, 94c7039ce9SBen Dooks .rdr = 0x24, 95c7039ce9SBen Dooks .tdr = 0x28, 96c7039ce9SBen Dooks }, 97c7039ce9SBen Dooks .cfg = { 98c7039ce9SBen Dooks .uart_enable_bit = 0, 99c7039ce9SBen Dooks .has_7bits_data = true, 100c7039ce9SBen Dooks .has_swap = true, 101c7039ce9SBen Dooks .has_wakeup = true, 102c7039ce9SBen Dooks .has_fifo = true, 103c7039ce9SBen Dooks .fifosize = 16, 104c7039ce9SBen Dooks } 105c7039ce9SBen Dooks }; 106c7039ce9SBen Dooks 10756f9a76cSErwan Le Ray static void stm32_usart_stop_tx(struct uart_port *port); 10856f9a76cSErwan Le Ray static void stm32_usart_transmit_chars(struct uart_port *port); 1091f507b3aSValentin Caron static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch); 11048a6092fSMaxime Coquelin 11148a6092fSMaxime Coquelin static inline struct stm32_port *to_stm32_port(struct uart_port *port) 11248a6092fSMaxime Coquelin { 11348a6092fSMaxime Coquelin return container_of(port, struct stm32_port, port); 11448a6092fSMaxime Coquelin } 11548a6092fSMaxime Coquelin 11656f9a76cSErwan Le Ray static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 11748a6092fSMaxime Coquelin { 11848a6092fSMaxime Coquelin u32 val; 11948a6092fSMaxime Coquelin 12048a6092fSMaxime Coquelin val = readl_relaxed(port->membase + reg); 12148a6092fSMaxime Coquelin val |= bits; 12248a6092fSMaxime Coquelin writel_relaxed(val, port->membase + reg); 12348a6092fSMaxime Coquelin } 12448a6092fSMaxime Coquelin 12556f9a76cSErwan Le Ray static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 12648a6092fSMaxime Coquelin { 12748a6092fSMaxime Coquelin u32 val; 12848a6092fSMaxime Coquelin 12948a6092fSMaxime Coquelin val = readl_relaxed(port->membase + reg); 13048a6092fSMaxime Coquelin val &= ~bits; 13148a6092fSMaxime Coquelin writel_relaxed(val, port->membase + reg); 13248a6092fSMaxime Coquelin } 13348a6092fSMaxime Coquelin 134adafbbf6SLukas Wunner static unsigned int stm32_usart_tx_empty(struct uart_port *port) 135adafbbf6SLukas Wunner { 136adafbbf6SLukas Wunner struct stm32_port *stm32_port = to_stm32_port(port); 137adafbbf6SLukas Wunner const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 138adafbbf6SLukas Wunner 139adafbbf6SLukas Wunner if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 140adafbbf6SLukas Wunner return TIOCSER_TEMT; 141adafbbf6SLukas Wunner 142adafbbf6SLukas Wunner return 0; 143adafbbf6SLukas Wunner } 144adafbbf6SLukas Wunner 145adafbbf6SLukas Wunner static void stm32_usart_rs485_rts_enable(struct uart_port *port) 146adafbbf6SLukas Wunner { 147adafbbf6SLukas Wunner struct stm32_port *stm32_port = to_stm32_port(port); 148adafbbf6SLukas Wunner struct serial_rs485 *rs485conf = &port->rs485; 149adafbbf6SLukas Wunner 150adafbbf6SLukas Wunner if (stm32_port->hw_flow_control || 151adafbbf6SLukas Wunner !(rs485conf->flags & SER_RS485_ENABLED)) 152adafbbf6SLukas Wunner return; 153adafbbf6SLukas Wunner 154adafbbf6SLukas Wunner if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 155adafbbf6SLukas Wunner mctrl_gpio_set(stm32_port->gpios, 156adafbbf6SLukas Wunner stm32_port->port.mctrl | TIOCM_RTS); 157adafbbf6SLukas Wunner } else { 158adafbbf6SLukas Wunner mctrl_gpio_set(stm32_port->gpios, 159adafbbf6SLukas Wunner stm32_port->port.mctrl & ~TIOCM_RTS); 160adafbbf6SLukas Wunner } 161adafbbf6SLukas Wunner } 162adafbbf6SLukas Wunner 163adafbbf6SLukas Wunner static void stm32_usart_rs485_rts_disable(struct uart_port *port) 164adafbbf6SLukas Wunner { 165adafbbf6SLukas Wunner struct stm32_port *stm32_port = to_stm32_port(port); 166adafbbf6SLukas Wunner struct serial_rs485 *rs485conf = &port->rs485; 167adafbbf6SLukas Wunner 168adafbbf6SLukas Wunner if (stm32_port->hw_flow_control || 169adafbbf6SLukas Wunner !(rs485conf->flags & SER_RS485_ENABLED)) 170adafbbf6SLukas Wunner return; 171adafbbf6SLukas Wunner 172adafbbf6SLukas Wunner if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 173adafbbf6SLukas Wunner mctrl_gpio_set(stm32_port->gpios, 174adafbbf6SLukas Wunner stm32_port->port.mctrl & ~TIOCM_RTS); 175adafbbf6SLukas Wunner } else { 176adafbbf6SLukas Wunner mctrl_gpio_set(stm32_port->gpios, 177adafbbf6SLukas Wunner stm32_port->port.mctrl | TIOCM_RTS); 178adafbbf6SLukas Wunner } 179adafbbf6SLukas Wunner } 180adafbbf6SLukas Wunner 18156f9a76cSErwan Le Ray static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 1821bcda09dSBich HEMON u32 delay_DDE, u32 baud) 1831bcda09dSBich HEMON { 1841bcda09dSBich HEMON u32 rs485_deat_dedt; 1851bcda09dSBich HEMON u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 1861bcda09dSBich HEMON bool over8; 1871bcda09dSBich HEMON 1881bcda09dSBich HEMON *cr3 |= USART_CR3_DEM; 1891bcda09dSBich HEMON over8 = *cr1 & USART_CR1_OVER8; 1901bcda09dSBich HEMON 1915c5f44e3SIlpo Järvinen *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 1925c5f44e3SIlpo Järvinen 1931bcda09dSBich HEMON if (over8) 1941bcda09dSBich HEMON rs485_deat_dedt = delay_ADE * baud * 8; 1951bcda09dSBich HEMON else 1961bcda09dSBich HEMON rs485_deat_dedt = delay_ADE * baud * 16; 1971bcda09dSBich HEMON 1981bcda09dSBich HEMON rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 1991bcda09dSBich HEMON rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 2001bcda09dSBich HEMON rs485_deat_dedt_max : rs485_deat_dedt; 2011bcda09dSBich HEMON rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 2021bcda09dSBich HEMON USART_CR1_DEAT_MASK; 2031bcda09dSBich HEMON *cr1 |= rs485_deat_dedt; 2041bcda09dSBich HEMON 2051bcda09dSBich HEMON if (over8) 2061bcda09dSBich HEMON rs485_deat_dedt = delay_DDE * baud * 8; 2071bcda09dSBich HEMON else 2081bcda09dSBich HEMON rs485_deat_dedt = delay_DDE * baud * 16; 2091bcda09dSBich HEMON 2101bcda09dSBich HEMON rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 2111bcda09dSBich HEMON rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 2121bcda09dSBich HEMON rs485_deat_dedt_max : rs485_deat_dedt; 2131bcda09dSBich HEMON rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 2141bcda09dSBich HEMON USART_CR1_DEDT_MASK; 2151bcda09dSBich HEMON *cr1 |= rs485_deat_dedt; 2161bcda09dSBich HEMON } 2171bcda09dSBich HEMON 218ae50bb27SIlpo Järvinen static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios, 2191bcda09dSBich HEMON struct serial_rs485 *rs485conf) 2201bcda09dSBich HEMON { 2211bcda09dSBich HEMON struct stm32_port *stm32_port = to_stm32_port(port); 222d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 223d825f0beSStephen Boyd const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 2241bcda09dSBich HEMON u32 usartdiv, baud, cr1, cr3; 2251bcda09dSBich HEMON bool over8; 2261bcda09dSBich HEMON 22756f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 2281bcda09dSBich HEMON 229c54d4854SChristoph Niedermaier if (port->rs485_rx_during_tx_gpio) 230c54d4854SChristoph Niedermaier gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, 231c54d4854SChristoph Niedermaier !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); 232c54d4854SChristoph Niedermaier else 2331bcda09dSBich HEMON rs485conf->flags |= SER_RS485_RX_DURING_TX; 2341bcda09dSBich HEMON 2351bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_ENABLED) { 2361bcda09dSBich HEMON cr1 = readl_relaxed(port->membase + ofs->cr1); 2371bcda09dSBich HEMON cr3 = readl_relaxed(port->membase + ofs->cr3); 2381bcda09dSBich HEMON usartdiv = readl_relaxed(port->membase + ofs->brr); 2391bcda09dSBich HEMON usartdiv = usartdiv & GENMASK(15, 0); 2401bcda09dSBich HEMON over8 = cr1 & USART_CR1_OVER8; 2411bcda09dSBich HEMON 2421bcda09dSBich HEMON if (over8) 2431bcda09dSBich HEMON usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 2441bcda09dSBich HEMON << USART_BRR_04_R_SHIFT; 2451bcda09dSBich HEMON 2461bcda09dSBich HEMON baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 24756f9a76cSErwan Le Ray stm32_usart_config_reg_rs485(&cr1, &cr3, 2481bcda09dSBich HEMON rs485conf->delay_rts_before_send, 24956f9a76cSErwan Le Ray rs485conf->delay_rts_after_send, 25056f9a76cSErwan Le Ray baud); 2511bcda09dSBich HEMON 252f633eb29SLino Sanfilippo if (rs485conf->flags & SER_RS485_RTS_ON_SEND) 2531bcda09dSBich HEMON cr3 &= ~USART_CR3_DEP; 254f633eb29SLino Sanfilippo else 2551bcda09dSBich HEMON cr3 |= USART_CR3_DEP; 2561bcda09dSBich HEMON 2571bcda09dSBich HEMON writel_relaxed(cr3, port->membase + ofs->cr3); 2581bcda09dSBich HEMON writel_relaxed(cr1, port->membase + ofs->cr1); 2591bcda09dSBich HEMON } else { 26056f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, 26156f9a76cSErwan Le Ray USART_CR3_DEM | USART_CR3_DEP); 26256f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, 2631bcda09dSBich HEMON USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 2641bcda09dSBich HEMON } 2651bcda09dSBich HEMON 26656f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 2671bcda09dSBich HEMON 268adafbbf6SLukas Wunner /* Adjust RTS polarity in case it's driven in software */ 269adafbbf6SLukas Wunner if (stm32_usart_tx_empty(port)) 270adafbbf6SLukas Wunner stm32_usart_rs485_rts_disable(port); 271adafbbf6SLukas Wunner else 272adafbbf6SLukas Wunner stm32_usart_rs485_rts_enable(port); 273adafbbf6SLukas Wunner 2741bcda09dSBich HEMON return 0; 2751bcda09dSBich HEMON } 2761bcda09dSBich HEMON 27756f9a76cSErwan Le Ray static int stm32_usart_init_rs485(struct uart_port *port, 2781bcda09dSBich HEMON struct platform_device *pdev) 2791bcda09dSBich HEMON { 2801bcda09dSBich HEMON struct serial_rs485 *rs485conf = &port->rs485; 2811bcda09dSBich HEMON 2821bcda09dSBich HEMON rs485conf->flags = 0; 2831bcda09dSBich HEMON rs485conf->delay_rts_before_send = 0; 2841bcda09dSBich HEMON rs485conf->delay_rts_after_send = 0; 2851bcda09dSBich HEMON 2861bcda09dSBich HEMON if (!pdev->dev.of_node) 2871bcda09dSBich HEMON return -ENODEV; 2881bcda09dSBich HEMON 289c150c0f3SLukas Wunner return uart_get_rs485_mode(port); 2901bcda09dSBich HEMON } 2911bcda09dSBich HEMON 29233bb2f6aSErwan Le Ray static bool stm32_usart_rx_dma_enabled(struct uart_port *port) 29334891872SAlexandre TORGUE { 29434891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 295d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 29633bb2f6aSErwan Le Ray 29733bb2f6aSErwan Le Ray if (!stm32_port->rx_ch) 29833bb2f6aSErwan Le Ray return false; 29933bb2f6aSErwan Le Ray 30033bb2f6aSErwan Le Ray return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR); 30133bb2f6aSErwan Le Ray } 30233bb2f6aSErwan Le Ray 30333bb2f6aSErwan Le Ray /* Return true when data is pending (in pio mode), and false when no data is pending. */ 30433bb2f6aSErwan Le Ray static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr) 30533bb2f6aSErwan Le Ray { 30633bb2f6aSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 30733bb2f6aSErwan Le Ray const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 30834891872SAlexandre TORGUE 30934891872SAlexandre TORGUE *sr = readl_relaxed(port->membase + ofs->isr); 31033bb2f6aSErwan Le Ray /* Get pending characters in RDR or FIFO */ 31133bb2f6aSErwan Le Ray if (*sr & USART_SR_RXNE) { 31233bb2f6aSErwan Le Ray /* Get all pending characters from the RDR or the FIFO when using interrupts */ 31333bb2f6aSErwan Le Ray if (!stm32_usart_rx_dma_enabled(port)) 31433bb2f6aSErwan Le Ray return true; 31534891872SAlexandre TORGUE 31633bb2f6aSErwan Le Ray /* Handle only RX data errors when using DMA */ 31733bb2f6aSErwan Le Ray if (*sr & USART_SR_ERR_MASK) 31833bb2f6aSErwan Le Ray return true; 31934891872SAlexandre TORGUE } 32034891872SAlexandre TORGUE 32133bb2f6aSErwan Le Ray return false; 32233bb2f6aSErwan Le Ray } 32333bb2f6aSErwan Le Ray 32433bb2f6aSErwan Le Ray static unsigned long stm32_usart_get_char_pio(struct uart_port *port) 32534891872SAlexandre TORGUE { 32634891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 327d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 32834891872SAlexandre TORGUE unsigned long c; 32934891872SAlexandre TORGUE 3306c5962f3SErwan Le Ray c = readl_relaxed(port->membase + ofs->rdr); 33133bb2f6aSErwan Le Ray /* Apply RDR data mask */ 3326c5962f3SErwan Le Ray c &= stm32_port->rdr_mask; 3336c5962f3SErwan Le Ray 3346c5962f3SErwan Le Ray return c; 33534891872SAlexandre TORGUE } 33634891872SAlexandre TORGUE 3376333a485SErwan Le Ray static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port) 33848a6092fSMaxime Coquelin { 339ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 340d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 34133bb2f6aSErwan Le Ray unsigned long c; 3426333a485SErwan Le Ray unsigned int size = 0; 34348a6092fSMaxime Coquelin u32 sr; 34448a6092fSMaxime Coquelin char flag; 34548a6092fSMaxime Coquelin 34633bb2f6aSErwan Le Ray while (stm32_usart_pending_rx_pio(port, &sr)) { 34748a6092fSMaxime Coquelin sr |= USART_SR_DUMMY_RX; 34848a6092fSMaxime Coquelin flag = TTY_NORMAL; 34948a6092fSMaxime Coquelin 3504f01d833SErwan Le Ray /* 3514f01d833SErwan Le Ray * Status bits has to be cleared before reading the RDR: 3524f01d833SErwan Le Ray * In FIFO mode, reading the RDR will pop the next data 3534f01d833SErwan Le Ray * (if any) along with its status bits into the SR. 3544f01d833SErwan Le Ray * Not doing so leads to misalignement between RDR and SR, 3554f01d833SErwan Le Ray * and clear status bits of the next rx data. 3564f01d833SErwan Le Ray * 3574f01d833SErwan Le Ray * Clear errors flags for stm32f7 and stm32h7 compatible 3584f01d833SErwan Le Ray * devices. On stm32f4 compatible devices, the error bit is 3594f01d833SErwan Le Ray * cleared by the sequence [read SR - read DR]. 3604f01d833SErwan Le Ray */ 3614f01d833SErwan Le Ray if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 3621250ed71SFabrice Gasnier writel_relaxed(sr & USART_SR_ERR_MASK, 3631250ed71SFabrice Gasnier port->membase + ofs->icr); 3644f01d833SErwan Le Ray 36533bb2f6aSErwan Le Ray c = stm32_usart_get_char_pio(port); 3664f01d833SErwan Le Ray port->icount.rx++; 3676333a485SErwan Le Ray size++; 36848a6092fSMaxime Coquelin if (sr & USART_SR_ERR_MASK) { 3694f01d833SErwan Le Ray if (sr & USART_SR_ORE) { 37048a6092fSMaxime Coquelin port->icount.overrun++; 37148a6092fSMaxime Coquelin } else if (sr & USART_SR_PE) { 37248a6092fSMaxime Coquelin port->icount.parity++; 37348a6092fSMaxime Coquelin } else if (sr & USART_SR_FE) { 3744f01d833SErwan Le Ray /* Break detection if character is null */ 3754f01d833SErwan Le Ray if (!c) { 3764f01d833SErwan Le Ray port->icount.brk++; 3774f01d833SErwan Le Ray if (uart_handle_break(port)) 3784f01d833SErwan Le Ray continue; 3794f01d833SErwan Le Ray } else { 38048a6092fSMaxime Coquelin port->icount.frame++; 38148a6092fSMaxime Coquelin } 3824f01d833SErwan Le Ray } 38348a6092fSMaxime Coquelin 38448a6092fSMaxime Coquelin sr &= port->read_status_mask; 38548a6092fSMaxime Coquelin 3864f01d833SErwan Le Ray if (sr & USART_SR_PE) { 38748a6092fSMaxime Coquelin flag = TTY_PARITY; 3884f01d833SErwan Le Ray } else if (sr & USART_SR_FE) { 3894f01d833SErwan Le Ray if (!c) 3904f01d833SErwan Le Ray flag = TTY_BREAK; 3914f01d833SErwan Le Ray else 39248a6092fSMaxime Coquelin flag = TTY_FRAME; 39348a6092fSMaxime Coquelin } 3944f01d833SErwan Le Ray } 39548a6092fSMaxime Coquelin 396cea37afdSJohan Hovold if (uart_prepare_sysrq_char(port, c)) 39748a6092fSMaxime Coquelin continue; 39848a6092fSMaxime Coquelin uart_insert_char(port, sr, USART_SR_ORE, c, flag); 39948a6092fSMaxime Coquelin } 4006333a485SErwan Le Ray 4016333a485SErwan Le Ray return size; 40233bb2f6aSErwan Le Ray } 40333bb2f6aSErwan Le Ray 40433bb2f6aSErwan Le Ray static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size) 40533bb2f6aSErwan Le Ray { 40633bb2f6aSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 40733bb2f6aSErwan Le Ray struct tty_port *ttyport = &stm32_port->port.state->port; 40833bb2f6aSErwan Le Ray unsigned char *dma_start; 40933bb2f6aSErwan Le Ray int dma_count, i; 41033bb2f6aSErwan Le Ray 41133bb2f6aSErwan Le Ray dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); 41233bb2f6aSErwan Le Ray 41333bb2f6aSErwan Le Ray /* 41433bb2f6aSErwan Le Ray * Apply rdr_mask on buffer in order to mask parity bit. 41533bb2f6aSErwan Le Ray * This loop is useless in cs8 mode because DMA copies only 41633bb2f6aSErwan Le Ray * 8 bits and already ignores parity bit. 41733bb2f6aSErwan Le Ray */ 41833bb2f6aSErwan Le Ray if (!(stm32_port->rdr_mask == (BIT(8) - 1))) 41933bb2f6aSErwan Le Ray for (i = 0; i < dma_size; i++) 42033bb2f6aSErwan Le Ray *(dma_start + i) &= stm32_port->rdr_mask; 42133bb2f6aSErwan Le Ray 42233bb2f6aSErwan Le Ray dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size); 42333bb2f6aSErwan Le Ray port->icount.rx += dma_count; 42433bb2f6aSErwan Le Ray if (dma_count != dma_size) 42533bb2f6aSErwan Le Ray port->icount.buf_overrun++; 42633bb2f6aSErwan Le Ray stm32_port->last_res -= dma_count; 42733bb2f6aSErwan Le Ray if (stm32_port->last_res == 0) 42833bb2f6aSErwan Le Ray stm32_port->last_res = RX_BUF_L; 42933bb2f6aSErwan Le Ray } 43033bb2f6aSErwan Le Ray 4316333a485SErwan Le Ray static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port) 43233bb2f6aSErwan Le Ray { 43333bb2f6aSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 4346333a485SErwan Le Ray unsigned int dma_size, size = 0; 43533bb2f6aSErwan Le Ray 43633bb2f6aSErwan Le Ray /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */ 43733bb2f6aSErwan Le Ray if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { 43833bb2f6aSErwan Le Ray /* Conditional first part: from last_res to end of DMA buffer */ 43933bb2f6aSErwan Le Ray dma_size = stm32_port->last_res; 44033bb2f6aSErwan Le Ray stm32_usart_push_buffer_dma(port, dma_size); 4416333a485SErwan Le Ray size = dma_size; 44233bb2f6aSErwan Le Ray } 44333bb2f6aSErwan Le Ray 44433bb2f6aSErwan Le Ray dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; 44533bb2f6aSErwan Le Ray stm32_usart_push_buffer_dma(port, dma_size); 4466333a485SErwan Le Ray size += dma_size; 4476333a485SErwan Le Ray 4486333a485SErwan Le Ray return size; 44933bb2f6aSErwan Le Ray } 45033bb2f6aSErwan Le Ray 4516333a485SErwan Le Ray static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush) 45233bb2f6aSErwan Le Ray { 45333bb2f6aSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 45433bb2f6aSErwan Le Ray const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 45533bb2f6aSErwan Le Ray enum dma_status rx_dma_status; 45633bb2f6aSErwan Le Ray u32 sr; 4576333a485SErwan Le Ray unsigned int size = 0; 45833bb2f6aSErwan Le Ray 4596333a485SErwan Le Ray if (stm32_usart_rx_dma_enabled(port) || force_dma_flush) { 46033bb2f6aSErwan Le Ray rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, 46133bb2f6aSErwan Le Ray stm32_port->rx_ch->cookie, 46233bb2f6aSErwan Le Ray &stm32_port->rx_dma_state); 46333bb2f6aSErwan Le Ray if (rx_dma_status == DMA_IN_PROGRESS) { 46433bb2f6aSErwan Le Ray /* Empty DMA buffer */ 4656333a485SErwan Le Ray size = stm32_usart_receive_chars_dma(port); 46633bb2f6aSErwan Le Ray sr = readl_relaxed(port->membase + ofs->isr); 46733bb2f6aSErwan Le Ray if (sr & USART_SR_ERR_MASK) { 46833bb2f6aSErwan Le Ray /* Disable DMA request line */ 46933bb2f6aSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 47033bb2f6aSErwan Le Ray 47133bb2f6aSErwan Le Ray /* Switch to PIO mode to handle the errors */ 4726333a485SErwan Le Ray size += stm32_usart_receive_chars_pio(port); 47333bb2f6aSErwan Le Ray 47433bb2f6aSErwan Le Ray /* Switch back to DMA mode */ 47533bb2f6aSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 47633bb2f6aSErwan Le Ray } 47733bb2f6aSErwan Le Ray } else { 47833bb2f6aSErwan Le Ray /* Disable RX DMA */ 47933bb2f6aSErwan Le Ray dmaengine_terminate_async(stm32_port->rx_ch); 48033bb2f6aSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 48133bb2f6aSErwan Le Ray /* Fall back to interrupt mode */ 48233bb2f6aSErwan Le Ray dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); 4836333a485SErwan Le Ray size = stm32_usart_receive_chars_pio(port); 48433bb2f6aSErwan Le Ray } 48533bb2f6aSErwan Le Ray } else { 4866333a485SErwan Le Ray size = stm32_usart_receive_chars_pio(port); 48733bb2f6aSErwan Le Ray } 48848a6092fSMaxime Coquelin 4896333a485SErwan Le Ray return size; 49048a6092fSMaxime Coquelin } 49148a6092fSMaxime Coquelin 4929a135f16SValentin Caron static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port) 4939a135f16SValentin Caron { 4949a135f16SValentin Caron dmaengine_terminate_async(stm32_port->tx_ch); 4959a135f16SValentin Caron stm32_port->tx_dma_busy = false; 4969a135f16SValentin Caron } 4979a135f16SValentin Caron 4989a135f16SValentin Caron static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port) 4999a135f16SValentin Caron { 5009a135f16SValentin Caron /* 5019a135f16SValentin Caron * We cannot use the function "dmaengine_tx_status" to know the 5029a135f16SValentin Caron * status of DMA. This function does not show if the "dma complete" 5039a135f16SValentin Caron * callback of the DMA transaction has been called. So we prefer 5049a135f16SValentin Caron * to use "tx_dma_busy" flag to prevent dual DMA transaction at the 5059a135f16SValentin Caron * same time. 5069a135f16SValentin Caron */ 5079a135f16SValentin Caron return stm32_port->tx_dma_busy; 5089a135f16SValentin Caron } 5099a135f16SValentin Caron 5109a135f16SValentin Caron static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port) 5119a135f16SValentin Caron { 5129a135f16SValentin Caron const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 5139a135f16SValentin Caron 5149a135f16SValentin Caron return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT); 5159a135f16SValentin Caron } 5169a135f16SValentin Caron 51756f9a76cSErwan Le Ray static void stm32_usart_tx_dma_complete(void *arg) 51834891872SAlexandre TORGUE { 51934891872SAlexandre TORGUE struct uart_port *port = arg; 52034891872SAlexandre TORGUE struct stm32_port *stm32port = to_stm32_port(port); 521d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 522f16b90c2SErwan Le Ray unsigned long flags; 52334891872SAlexandre TORGUE 52456f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 5259a135f16SValentin Caron stm32_usart_tx_dma_terminate(stm32port); 52634891872SAlexandre TORGUE 52734891872SAlexandre TORGUE /* Let's see if we have pending data to send */ 528f16b90c2SErwan Le Ray spin_lock_irqsave(&port->lock, flags); 52956f9a76cSErwan Le Ray stm32_usart_transmit_chars(port); 530f16b90c2SErwan Le Ray spin_unlock_irqrestore(&port->lock, flags); 53134891872SAlexandre TORGUE } 53234891872SAlexandre TORGUE 53356f9a76cSErwan Le Ray static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 534d075719eSErwan Le Ray { 535d075719eSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 536d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 537d075719eSErwan Le Ray 538d075719eSErwan Le Ray /* 539d075719eSErwan Le Ray * Enables TX FIFO threashold irq when FIFO is enabled, 540d075719eSErwan Le Ray * or TX empty irq when FIFO is disabled 541d075719eSErwan Le Ray */ 5422aa1bbb2SFabrice Gasnier if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 54356f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 544d075719eSErwan Le Ray else 54556f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 546d075719eSErwan Le Ray } 547d075719eSErwan Le Ray 548d7c76716SMarek Vasut static void stm32_usart_tc_interrupt_enable(struct uart_port *port) 549d7c76716SMarek Vasut { 550d7c76716SMarek Vasut struct stm32_port *stm32_port = to_stm32_port(port); 551d7c76716SMarek Vasut const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 552d7c76716SMarek Vasut 553d7c76716SMarek Vasut stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); 554d7c76716SMarek Vasut } 555d7c76716SMarek Vasut 55633bb2f6aSErwan Le Ray static void stm32_usart_rx_dma_complete(void *arg) 55733bb2f6aSErwan Le Ray { 55833bb2f6aSErwan Le Ray struct uart_port *port = arg; 5596333a485SErwan Le Ray struct tty_port *tport = &port->state->port; 5606333a485SErwan Le Ray unsigned int size; 5616333a485SErwan Le Ray unsigned long flags; 56233bb2f6aSErwan Le Ray 5636333a485SErwan Le Ray spin_lock_irqsave(&port->lock, flags); 5646333a485SErwan Le Ray size = stm32_usart_receive_chars(port, false); 5656333a485SErwan Le Ray uart_unlock_and_check_sysrq_irqrestore(port, flags); 5666333a485SErwan Le Ray if (size) 5676333a485SErwan Le Ray tty_flip_buffer_push(tport); 56833bb2f6aSErwan Le Ray } 56933bb2f6aSErwan Le Ray 57056f9a76cSErwan Le Ray static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 571d075719eSErwan Le Ray { 572d075719eSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 573d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 574d075719eSErwan Le Ray 5752aa1bbb2SFabrice Gasnier if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 57656f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 577d075719eSErwan Le Ray else 57856f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 579d075719eSErwan Le Ray } 580d075719eSErwan Le Ray 581d7c76716SMarek Vasut static void stm32_usart_tc_interrupt_disable(struct uart_port *port) 582d7c76716SMarek Vasut { 583d7c76716SMarek Vasut struct stm32_port *stm32_port = to_stm32_port(port); 584d7c76716SMarek Vasut const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 585d7c76716SMarek Vasut 586d7c76716SMarek Vasut stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); 587d7c76716SMarek Vasut } 588d7c76716SMarek Vasut 58956f9a76cSErwan Le Ray static void stm32_usart_transmit_chars_pio(struct uart_port *port) 59034891872SAlexandre TORGUE { 59134891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 592d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 59334891872SAlexandre TORGUE struct circ_buf *xmit = &port->state->xmit; 59434891872SAlexandre TORGUE 5959a135f16SValentin Caron if (stm32_usart_tx_dma_enabled(stm32_port)) 59656f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 59734891872SAlexandre TORGUE 5985d9176edSErwan Le Ray while (!uart_circ_empty(xmit)) { 5995d9176edSErwan Le Ray /* Check that TDR is empty before filling FIFO */ 6005d9176edSErwan Le Ray if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 6015d9176edSErwan Le Ray break; 60234891872SAlexandre TORGUE writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 60329d8c07bSIlpo Järvinen uart_xmit_advance(port, 1); 60434891872SAlexandre TORGUE } 60534891872SAlexandre TORGUE 6065d9176edSErwan Le Ray /* rely on TXE irq (mask or unmask) for sending remaining data */ 6075d9176edSErwan Le Ray if (uart_circ_empty(xmit)) 60856f9a76cSErwan Le Ray stm32_usart_tx_interrupt_disable(port); 6095d9176edSErwan Le Ray else 61056f9a76cSErwan Le Ray stm32_usart_tx_interrupt_enable(port); 6115d9176edSErwan Le Ray } 6125d9176edSErwan Le Ray 61356f9a76cSErwan Le Ray static void stm32_usart_transmit_chars_dma(struct uart_port *port) 61434891872SAlexandre TORGUE { 61534891872SAlexandre TORGUE struct stm32_port *stm32port = to_stm32_port(port); 616d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 61734891872SAlexandre TORGUE struct circ_buf *xmit = &port->state->xmit; 61834891872SAlexandre TORGUE struct dma_async_tx_descriptor *desc = NULL; 619195437d1SValentin Caron unsigned int count; 62034891872SAlexandre TORGUE 6219a135f16SValentin Caron if (stm32_usart_tx_dma_started(stm32port)) { 6229a135f16SValentin Caron if (!stm32_usart_tx_dma_enabled(stm32port)) 6239a135f16SValentin Caron stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 62434891872SAlexandre TORGUE return; 6259a135f16SValentin Caron } 62634891872SAlexandre TORGUE 62734891872SAlexandre TORGUE count = uart_circ_chars_pending(xmit); 62834891872SAlexandre TORGUE 62934891872SAlexandre TORGUE if (count > TX_BUF_L) 63034891872SAlexandre TORGUE count = TX_BUF_L; 63134891872SAlexandre TORGUE 63234891872SAlexandre TORGUE if (xmit->tail < xmit->head) { 63334891872SAlexandre TORGUE memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 63434891872SAlexandre TORGUE } else { 63534891872SAlexandre TORGUE size_t one = UART_XMIT_SIZE - xmit->tail; 63634891872SAlexandre TORGUE size_t two; 63734891872SAlexandre TORGUE 63834891872SAlexandre TORGUE if (one > count) 63934891872SAlexandre TORGUE one = count; 64034891872SAlexandre TORGUE two = count - one; 64134891872SAlexandre TORGUE 64234891872SAlexandre TORGUE memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 64334891872SAlexandre TORGUE if (two) 64434891872SAlexandre TORGUE memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 64534891872SAlexandre TORGUE } 64634891872SAlexandre TORGUE 64734891872SAlexandre TORGUE desc = dmaengine_prep_slave_single(stm32port->tx_ch, 64834891872SAlexandre TORGUE stm32port->tx_dma_buf, 64934891872SAlexandre TORGUE count, 65034891872SAlexandre TORGUE DMA_MEM_TO_DEV, 65134891872SAlexandre TORGUE DMA_PREP_INTERRUPT); 65234891872SAlexandre TORGUE 653e7997f7fSErwan Le Ray if (!desc) 654e7997f7fSErwan Le Ray goto fallback_err; 65534891872SAlexandre TORGUE 6569a135f16SValentin Caron /* 6579a135f16SValentin Caron * Set "tx_dma_busy" flag. This flag will be released when 6589a135f16SValentin Caron * dmaengine_terminate_async will be called. This flag helps 6599a135f16SValentin Caron * transmit_chars_dma not to start another DMA transaction 6609a135f16SValentin Caron * if the callback of the previous is not yet called. 6619a135f16SValentin Caron */ 6629a135f16SValentin Caron stm32port->tx_dma_busy = true; 6639a135f16SValentin Caron 66456f9a76cSErwan Le Ray desc->callback = stm32_usart_tx_dma_complete; 66534891872SAlexandre TORGUE desc->callback_param = port; 66634891872SAlexandre TORGUE 66734891872SAlexandre TORGUE /* Push current DMA TX transaction in the pending queue */ 668e7997f7fSErwan Le Ray if (dma_submit_error(dmaengine_submit(desc))) { 669e7997f7fSErwan Le Ray /* dma no yet started, safe to free resources */ 6709a135f16SValentin Caron stm32_usart_tx_dma_terminate(stm32port); 671e7997f7fSErwan Le Ray goto fallback_err; 672e7997f7fSErwan Le Ray } 67334891872SAlexandre TORGUE 67434891872SAlexandre TORGUE /* Issue pending DMA TX requests */ 67534891872SAlexandre TORGUE dma_async_issue_pending(stm32port->tx_ch); 67634891872SAlexandre TORGUE 67756f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 67834891872SAlexandre TORGUE 67929d8c07bSIlpo Järvinen uart_xmit_advance(port, count); 68029d8c07bSIlpo Järvinen 681e7997f7fSErwan Le Ray return; 682e7997f7fSErwan Le Ray 683e7997f7fSErwan Le Ray fallback_err: 68456f9a76cSErwan Le Ray stm32_usart_transmit_chars_pio(port); 68534891872SAlexandre TORGUE } 68634891872SAlexandre TORGUE 68756f9a76cSErwan Le Ray static void stm32_usart_transmit_chars(struct uart_port *port) 68848a6092fSMaxime Coquelin { 689ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 690d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 69148a6092fSMaxime Coquelin struct circ_buf *xmit = &port->state->xmit; 692d3d079bdSValentin Caron u32 isr; 693d3d079bdSValentin Caron int ret; 69448a6092fSMaxime Coquelin 695d7c76716SMarek Vasut if (!stm32_port->hw_flow_control && 696c47527cbSMarek Vasut port->rs485.flags & SER_RS485_ENABLED && 697c47527cbSMarek Vasut (port->x_char || 698c47527cbSMarek Vasut !(uart_circ_empty(xmit) || uart_tx_stopped(port)))) { 699d7c76716SMarek Vasut stm32_usart_tc_interrupt_disable(port); 700d7c76716SMarek Vasut stm32_usart_rs485_rts_enable(port); 701d7c76716SMarek Vasut } 702d7c76716SMarek Vasut 70348a6092fSMaxime Coquelin if (port->x_char) { 7049a135f16SValentin Caron if (stm32_usart_tx_dma_started(stm32_port) && 7059a135f16SValentin Caron stm32_usart_tx_dma_enabled(stm32_port)) 70656f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 707d3d079bdSValentin Caron 708d3d079bdSValentin Caron /* Check that TDR is empty before filling FIFO */ 709d3d079bdSValentin Caron ret = 710d3d079bdSValentin Caron readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 711d3d079bdSValentin Caron isr, 712d3d079bdSValentin Caron (isr & USART_SR_TXE), 713d3d079bdSValentin Caron 10, 1000); 714d3d079bdSValentin Caron if (ret) 715d3d079bdSValentin Caron dev_warn(port->dev, "1 character may be erased\n"); 716d3d079bdSValentin Caron 717ada8618fSAlexandre TORGUE writel_relaxed(port->x_char, port->membase + ofs->tdr); 71848a6092fSMaxime Coquelin port->x_char = 0; 71948a6092fSMaxime Coquelin port->icount.tx++; 7209a135f16SValentin Caron if (stm32_usart_tx_dma_started(stm32_port)) 72156f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 72248a6092fSMaxime Coquelin return; 72348a6092fSMaxime Coquelin } 72448a6092fSMaxime Coquelin 725b83b957cSErwan Le Ray if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 72656f9a76cSErwan Le Ray stm32_usart_tx_interrupt_disable(port); 72748a6092fSMaxime Coquelin return; 72848a6092fSMaxime Coquelin } 72948a6092fSMaxime Coquelin 73064c32eabSErwan Le Ray if (ofs->icr == UNDEF_REG) 73156f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 73264c32eabSErwan Le Ray else 7331250ed71SFabrice Gasnier writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 73464c32eabSErwan Le Ray 73534891872SAlexandre TORGUE if (stm32_port->tx_ch) 73656f9a76cSErwan Le Ray stm32_usart_transmit_chars_dma(port); 73734891872SAlexandre TORGUE else 73856f9a76cSErwan Le Ray stm32_usart_transmit_chars_pio(port); 73948a6092fSMaxime Coquelin 74048a6092fSMaxime Coquelin if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 74148a6092fSMaxime Coquelin uart_write_wakeup(port); 74248a6092fSMaxime Coquelin 743d7c76716SMarek Vasut if (uart_circ_empty(xmit)) { 74456f9a76cSErwan Le Ray stm32_usart_tx_interrupt_disable(port); 745d7c76716SMarek Vasut if (!stm32_port->hw_flow_control && 746d7c76716SMarek Vasut port->rs485.flags & SER_RS485_ENABLED) { 747d7c76716SMarek Vasut stm32_usart_tc_interrupt_enable(port); 748d7c76716SMarek Vasut } 749d7c76716SMarek Vasut } 75048a6092fSMaxime Coquelin } 75148a6092fSMaxime Coquelin 75256f9a76cSErwan Le Ray static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 75348a6092fSMaxime Coquelin { 75448a6092fSMaxime Coquelin struct uart_port *port = ptr; 75512761869SErwan Le Ray struct tty_port *tport = &port->state->port; 756ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 757d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 75848a6092fSMaxime Coquelin u32 sr; 7596333a485SErwan Le Ray unsigned int size; 76048a6092fSMaxime Coquelin 761ada8618fSAlexandre TORGUE sr = readl_relaxed(port->membase + ofs->isr); 76248a6092fSMaxime Coquelin 763d7c76716SMarek Vasut if (!stm32_port->hw_flow_control && 764d7c76716SMarek Vasut port->rs485.flags & SER_RS485_ENABLED && 765d7c76716SMarek Vasut (sr & USART_SR_TC)) { 766d7c76716SMarek Vasut stm32_usart_tc_interrupt_disable(port); 767d7c76716SMarek Vasut stm32_usart_rs485_rts_disable(port); 768d7c76716SMarek Vasut } 769d7c76716SMarek Vasut 7704cc0ed62SErwan Le Ray if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 7714cc0ed62SErwan Le Ray writel_relaxed(USART_ICR_RTOCF, 7724cc0ed62SErwan Le Ray port->membase + ofs->icr); 7734cc0ed62SErwan Le Ray 77412761869SErwan Le Ray if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 77512761869SErwan Le Ray /* Clear wake up flag and disable wake up interrupt */ 776270e5a74SFabrice Gasnier writel_relaxed(USART_ICR_WUCF, 777270e5a74SFabrice Gasnier port->membase + ofs->icr); 77812761869SErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 77912761869SErwan Le Ray if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 78012761869SErwan Le Ray pm_wakeup_event(tport->tty->dev, 0); 78112761869SErwan Le Ray } 782270e5a74SFabrice Gasnier 78333bb2f6aSErwan Le Ray /* 78433bb2f6aSErwan Le Ray * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request 78533bb2f6aSErwan Le Ray * line has been masked by HW and rx data are stacking in FIFO. 78633bb2f6aSErwan Le Ray */ 787d1ec8a2eSErwan Le Ray if (!stm32_port->throttled) { 78833bb2f6aSErwan Le Ray if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_enabled(port)) || 789d1ec8a2eSErwan Le Ray ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_enabled(port))) { 7906333a485SErwan Le Ray spin_lock(&port->lock); 7916333a485SErwan Le Ray size = stm32_usart_receive_chars(port, false); 7926333a485SErwan Le Ray uart_unlock_and_check_sysrq(port); 7936333a485SErwan Le Ray if (size) 7946333a485SErwan Le Ray tty_flip_buffer_push(tport); 795d1ec8a2eSErwan Le Ray } 796d1ec8a2eSErwan Le Ray } 79748a6092fSMaxime Coquelin 798ad767681SErwan Le Ray if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 799ad767681SErwan Le Ray spin_lock(&port->lock); 80056f9a76cSErwan Le Ray stm32_usart_transmit_chars(port); 80101d32d71SAlexandre TORGUE spin_unlock(&port->lock); 802ad767681SErwan Le Ray } 80301d32d71SAlexandre TORGUE 804cc58d0a3SErwan Le Ray /* Receiver timeout irq for DMA RX */ 8053f6c02faSMarek Vasut if (stm32_usart_rx_dma_enabled(port) && !stm32_port->throttled) { 8063f6c02faSMarek Vasut spin_lock(&port->lock); 8076333a485SErwan Le Ray size = stm32_usart_receive_chars(port, false); 8083f6c02faSMarek Vasut uart_unlock_and_check_sysrq(port); 8096333a485SErwan Le Ray if (size) 8106333a485SErwan Le Ray tty_flip_buffer_push(tport); 8116333a485SErwan Le Ray } 81234891872SAlexandre TORGUE 81348a6092fSMaxime Coquelin return IRQ_HANDLED; 81448a6092fSMaxime Coquelin } 81548a6092fSMaxime Coquelin 81656f9a76cSErwan Le Ray static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 81748a6092fSMaxime Coquelin { 818ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 819d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 820ada8618fSAlexandre TORGUE 82148a6092fSMaxime Coquelin if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 82256f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 82348a6092fSMaxime Coquelin else 82456f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 8256cf61b9bSManivannan Sadhasivam 8266cf61b9bSManivannan Sadhasivam mctrl_gpio_set(stm32_port->gpios, mctrl); 82748a6092fSMaxime Coquelin } 82848a6092fSMaxime Coquelin 82956f9a76cSErwan Le Ray static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 83048a6092fSMaxime Coquelin { 8316cf61b9bSManivannan Sadhasivam struct stm32_port *stm32_port = to_stm32_port(port); 8326cf61b9bSManivannan Sadhasivam unsigned int ret; 8336cf61b9bSManivannan Sadhasivam 83448a6092fSMaxime Coquelin /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 8356cf61b9bSManivannan Sadhasivam ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 8366cf61b9bSManivannan Sadhasivam 8376cf61b9bSManivannan Sadhasivam return mctrl_gpio_get(stm32_port->gpios, &ret); 8386cf61b9bSManivannan Sadhasivam } 8396cf61b9bSManivannan Sadhasivam 84056f9a76cSErwan Le Ray static void stm32_usart_enable_ms(struct uart_port *port) 8416cf61b9bSManivannan Sadhasivam { 8426cf61b9bSManivannan Sadhasivam mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 8436cf61b9bSManivannan Sadhasivam } 8446cf61b9bSManivannan Sadhasivam 84556f9a76cSErwan Le Ray static void stm32_usart_disable_ms(struct uart_port *port) 8466cf61b9bSManivannan Sadhasivam { 8476cf61b9bSManivannan Sadhasivam mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 84848a6092fSMaxime Coquelin } 84948a6092fSMaxime Coquelin 85048a6092fSMaxime Coquelin /* Transmit stop */ 85156f9a76cSErwan Le Ray static void stm32_usart_stop_tx(struct uart_port *port) 85248a6092fSMaxime Coquelin { 853ad0c2748SMarek Vasut struct stm32_port *stm32_port = to_stm32_port(port); 8542a3bcfe0SValentin Caron const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 855ad0c2748SMarek Vasut 85656f9a76cSErwan Le Ray stm32_usart_tx_interrupt_disable(port); 8572a3bcfe0SValentin Caron if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port)) 8582a3bcfe0SValentin Caron stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 859ad0c2748SMarek Vasut 8603bcea529SMarek Vasut stm32_usart_rs485_rts_disable(port); 86148a6092fSMaxime Coquelin } 86248a6092fSMaxime Coquelin 86348a6092fSMaxime Coquelin /* There are probably characters waiting to be transmitted. */ 86456f9a76cSErwan Le Ray static void stm32_usart_start_tx(struct uart_port *port) 86548a6092fSMaxime Coquelin { 86648a6092fSMaxime Coquelin struct circ_buf *xmit = &port->state->xmit; 86748a6092fSMaxime Coquelin 868d7c76716SMarek Vasut if (uart_circ_empty(xmit) && !port->x_char) { 869d7c76716SMarek Vasut stm32_usart_rs485_rts_disable(port); 87048a6092fSMaxime Coquelin return; 871d7c76716SMarek Vasut } 87248a6092fSMaxime Coquelin 8733bcea529SMarek Vasut stm32_usart_rs485_rts_enable(port); 874ad0c2748SMarek Vasut 87556f9a76cSErwan Le Ray stm32_usart_transmit_chars(port); 87648a6092fSMaxime Coquelin } 87748a6092fSMaxime Coquelin 8783d82be8bSErwan Le Ray /* Flush the transmit buffer. */ 8793d82be8bSErwan Le Ray static void stm32_usart_flush_buffer(struct uart_port *port) 8803d82be8bSErwan Le Ray { 8813d82be8bSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 8823d82be8bSErwan Le Ray const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 8833d82be8bSErwan Le Ray 8843d82be8bSErwan Le Ray if (stm32_port->tx_ch) { 8859a135f16SValentin Caron stm32_usart_tx_dma_terminate(stm32_port); 8863d82be8bSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 8873d82be8bSErwan Le Ray } 8883d82be8bSErwan Le Ray } 8893d82be8bSErwan Le Ray 89048a6092fSMaxime Coquelin /* Throttle the remote when input buffer is about to overflow. */ 89156f9a76cSErwan Le Ray static void stm32_usart_throttle(struct uart_port *port) 89248a6092fSMaxime Coquelin { 893ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 894d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 89548a6092fSMaxime Coquelin unsigned long flags; 89648a6092fSMaxime Coquelin 89748a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 898d1ec8a2eSErwan Le Ray 899d1ec8a2eSErwan Le Ray /* 900d1ec8a2eSErwan Le Ray * Disable DMA request line if enabled, so the RX data gets queued into the FIFO. 901d1ec8a2eSErwan Le Ray * Hardware flow control is triggered when RX FIFO is full. 902d1ec8a2eSErwan Le Ray */ 903d1ec8a2eSErwan Le Ray if (stm32_usart_rx_dma_enabled(port)) 904d1ec8a2eSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 905d1ec8a2eSErwan Le Ray 90656f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 907d0a6a7bcSErwan Le Ray if (stm32_port->cr3_irq) 90856f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 909d0a6a7bcSErwan Le Ray 910d1ec8a2eSErwan Le Ray stm32_port->throttled = true; 91148a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 91248a6092fSMaxime Coquelin } 91348a6092fSMaxime Coquelin 91448a6092fSMaxime Coquelin /* Unthrottle the remote, the input buffer can now accept data. */ 91556f9a76cSErwan Le Ray static void stm32_usart_unthrottle(struct uart_port *port) 91648a6092fSMaxime Coquelin { 917ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 918d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 91948a6092fSMaxime Coquelin unsigned long flags; 92048a6092fSMaxime Coquelin 92148a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 92256f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 923d0a6a7bcSErwan Le Ray if (stm32_port->cr3_irq) 92456f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 925d0a6a7bcSErwan Le Ray 926d1ec8a2eSErwan Le Ray /* 927d1ec8a2eSErwan Le Ray * Switch back to DMA mode (re-enable DMA request line). 928d1ec8a2eSErwan Le Ray * Hardware flow control is stopped when FIFO is not full any more. 929d1ec8a2eSErwan Le Ray */ 930d1ec8a2eSErwan Le Ray if (stm32_port->rx_ch) 931d1ec8a2eSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 932d1ec8a2eSErwan Le Ray 933d1ec8a2eSErwan Le Ray stm32_port->throttled = false; 93448a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 93548a6092fSMaxime Coquelin } 93648a6092fSMaxime Coquelin 93748a6092fSMaxime Coquelin /* Receive stop */ 93856f9a76cSErwan Le Ray static void stm32_usart_stop_rx(struct uart_port *port) 93948a6092fSMaxime Coquelin { 940ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 941d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 942ada8618fSAlexandre TORGUE 943e0abc903SErwan Le Ray /* Disable DMA request line. */ 944e0abc903SErwan Le Ray if (stm32_port->rx_ch) 945e0abc903SErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 946e0abc903SErwan Le Ray 94756f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 948d0a6a7bcSErwan Le Ray if (stm32_port->cr3_irq) 94956f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 95048a6092fSMaxime Coquelin } 95148a6092fSMaxime Coquelin 95248a6092fSMaxime Coquelin /* Handle breaks - ignored by us */ 95356f9a76cSErwan Le Ray static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 95448a6092fSMaxime Coquelin { 95548a6092fSMaxime Coquelin } 95648a6092fSMaxime Coquelin 9576eeb348cSErwan Le Ray static int stm32_usart_start_rx_dma_cyclic(struct uart_port *port) 9586eeb348cSErwan Le Ray { 9596eeb348cSErwan Le Ray struct stm32_port *stm32_port = to_stm32_port(port); 9606eeb348cSErwan Le Ray const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 9616eeb348cSErwan Le Ray struct dma_async_tx_descriptor *desc; 9626eeb348cSErwan Le Ray int ret; 9636eeb348cSErwan Le Ray 9646eeb348cSErwan Le Ray stm32_port->last_res = RX_BUF_L; 9656eeb348cSErwan Le Ray /* Prepare a DMA cyclic transaction */ 9666eeb348cSErwan Le Ray desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, 9676eeb348cSErwan Le Ray stm32_port->rx_dma_buf, 9686eeb348cSErwan Le Ray RX_BUF_L, RX_BUF_P, 9696eeb348cSErwan Le Ray DMA_DEV_TO_MEM, 9706eeb348cSErwan Le Ray DMA_PREP_INTERRUPT); 9716eeb348cSErwan Le Ray if (!desc) { 9726eeb348cSErwan Le Ray dev_err(port->dev, "rx dma prep cyclic failed\n"); 9736eeb348cSErwan Le Ray return -ENODEV; 9746eeb348cSErwan Le Ray } 9756eeb348cSErwan Le Ray 9766eeb348cSErwan Le Ray desc->callback = stm32_usart_rx_dma_complete; 9776eeb348cSErwan Le Ray desc->callback_param = port; 9786eeb348cSErwan Le Ray 9796eeb348cSErwan Le Ray /* Push current DMA transaction in the pending queue */ 9806eeb348cSErwan Le Ray ret = dma_submit_error(dmaengine_submit(desc)); 9816eeb348cSErwan Le Ray if (ret) { 9826eeb348cSErwan Le Ray dmaengine_terminate_sync(stm32_port->rx_ch); 9836eeb348cSErwan Le Ray return ret; 9846eeb348cSErwan Le Ray } 9856eeb348cSErwan Le Ray 9866eeb348cSErwan Le Ray /* Issue pending DMA requests */ 9876eeb348cSErwan Le Ray dma_async_issue_pending(stm32_port->rx_ch); 9886eeb348cSErwan Le Ray 9896eeb348cSErwan Le Ray /* 9906eeb348cSErwan Le Ray * DMA request line not re-enabled at resume when port is throttled. 9916eeb348cSErwan Le Ray * It will be re-enabled by unthrottle ops. 9926eeb348cSErwan Le Ray */ 9936eeb348cSErwan Le Ray if (!stm32_port->throttled) 9946eeb348cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 9956eeb348cSErwan Le Ray 9966eeb348cSErwan Le Ray return 0; 9976eeb348cSErwan Le Ray } 9986eeb348cSErwan Le Ray 99956f9a76cSErwan Le Ray static int stm32_usart_startup(struct uart_port *port) 100048a6092fSMaxime Coquelin { 1001ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1002d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1003f4518a8aSErwan Le Ray const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 100448a6092fSMaxime Coquelin const char *name = to_platform_device(port->dev)->name; 100548a6092fSMaxime Coquelin u32 val; 100648a6092fSMaxime Coquelin int ret; 100748a6092fSMaxime Coquelin 10083f6c02faSMarek Vasut ret = request_irq(port->irq, stm32_usart_interrupt, 10093f6c02faSMarek Vasut IRQF_NO_SUSPEND, name, port); 101048a6092fSMaxime Coquelin if (ret) 101148a6092fSMaxime Coquelin return ret; 101248a6092fSMaxime Coquelin 10133cd66593SMartin Devera if (stm32_port->swap) { 10143cd66593SMartin Devera val = readl_relaxed(port->membase + ofs->cr2); 10153cd66593SMartin Devera val |= USART_CR2_SWAP; 10163cd66593SMartin Devera writel_relaxed(val, port->membase + ofs->cr2); 10173cd66593SMartin Devera } 10183cd66593SMartin Devera 101984872dc4SErwan Le Ray /* RX FIFO Flush */ 102084872dc4SErwan Le Ray if (ofs->rqr != UNDEF_REG) 1021315e2d8aSErwan Le Ray writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 102248a6092fSMaxime Coquelin 1023e0abc903SErwan Le Ray if (stm32_port->rx_ch) { 10246eeb348cSErwan Le Ray ret = stm32_usart_start_rx_dma_cyclic(port); 1025e0abc903SErwan Le Ray if (ret) { 10266eeb348cSErwan Le Ray free_irq(port->irq, port); 10276eeb348cSErwan Le Ray return ret; 1028e0abc903SErwan Le Ray } 1029e0abc903SErwan Le Ray } 1030d1ec8a2eSErwan Le Ray 103125a8e761SErwan Le Ray /* RX enabling */ 1032f4518a8aSErwan Le Ray val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 103356f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, val); 103484872dc4SErwan Le Ray 103548a6092fSMaxime Coquelin return 0; 103648a6092fSMaxime Coquelin } 103748a6092fSMaxime Coquelin 103856f9a76cSErwan Le Ray static void stm32_usart_shutdown(struct uart_port *port) 103948a6092fSMaxime Coquelin { 1040ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1041d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1042d825f0beSStephen Boyd const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 104364c32eabSErwan Le Ray u32 val, isr; 104464c32eabSErwan Le Ray int ret; 104548a6092fSMaxime Coquelin 10469a135f16SValentin Caron if (stm32_usart_tx_dma_enabled(stm32_port)) 104756a23f93SValentin Caron stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 10489a135f16SValentin Caron 10499a135f16SValentin Caron if (stm32_usart_tx_dma_started(stm32_port)) 10509a135f16SValentin Caron stm32_usart_tx_dma_terminate(stm32_port); 105156a23f93SValentin Caron 10526cf61b9bSManivannan Sadhasivam /* Disable modem control interrupts */ 105356f9a76cSErwan Le Ray stm32_usart_disable_ms(port); 10546cf61b9bSManivannan Sadhasivam 10554cc0ed62SErwan Le Ray val = USART_CR1_TXEIE | USART_CR1_TE; 10564cc0ed62SErwan Le Ray val |= stm32_port->cr1_irq | USART_CR1_RE; 105787f1f809SAlexandre TORGUE val |= BIT(cfg->uart_enable_bit); 1058351a762aSGerald Baeza if (stm32_port->fifoen) 1059351a762aSGerald Baeza val |= USART_CR1_FIFOEN; 106064c32eabSErwan Le Ray 106164c32eabSErwan Le Ray ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 106264c32eabSErwan Le Ray isr, (isr & USART_SR_TC), 106364c32eabSErwan Le Ray 10, 100000); 106464c32eabSErwan Le Ray 1065c31c3ea0SErwan Le Ray /* Send the TC error message only when ISR_TC is not set */ 106664c32eabSErwan Le Ray if (ret) 1067c31c3ea0SErwan Le Ray dev_err(port->dev, "Transmission is not complete\n"); 106864c32eabSErwan Le Ray 1069e0abc903SErwan Le Ray /* Disable RX DMA. */ 1070e0abc903SErwan Le Ray if (stm32_port->rx_ch) 1071e0abc903SErwan Le Ray dmaengine_terminate_async(stm32_port->rx_ch); 1072e0abc903SErwan Le Ray 10739f77d192SErwan Le Ray /* flush RX & TX FIFO */ 10749f77d192SErwan Le Ray if (ofs->rqr != UNDEF_REG) 10759f77d192SErwan Le Ray writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 10769f77d192SErwan Le Ray port->membase + ofs->rqr); 10779f77d192SErwan Le Ray 107856f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, val); 107948a6092fSMaxime Coquelin 108048a6092fSMaxime Coquelin free_irq(port->irq, port); 108148a6092fSMaxime Coquelin } 108248a6092fSMaxime Coquelin 108356f9a76cSErwan Le Ray static void stm32_usart_set_termios(struct uart_port *port, 108456f9a76cSErwan Le Ray struct ktermios *termios, 1085bec5b814SIlpo Järvinen const struct ktermios *old) 108648a6092fSMaxime Coquelin { 108748a6092fSMaxime Coquelin struct stm32_port *stm32_port = to_stm32_port(port); 1088d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1089d825f0beSStephen Boyd const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 10901bcda09dSBich HEMON struct serial_rs485 *rs485conf = &port->rs485; 1091c8a9d043SErwan Le Ray unsigned int baud, bits; 109248a6092fSMaxime Coquelin u32 usartdiv, mantissa, fraction, oversampling; 109348a6092fSMaxime Coquelin tcflag_t cflag = termios->c_cflag; 1094f264c6f6SErwan Le Ray u32 cr1, cr2, cr3, isr; 109548a6092fSMaxime Coquelin unsigned long flags; 1096f264c6f6SErwan Le Ray int ret; 109748a6092fSMaxime Coquelin 109848a6092fSMaxime Coquelin if (!stm32_port->hw_flow_control) 109948a6092fSMaxime Coquelin cflag &= ~CRTSCTS; 110048a6092fSMaxime Coquelin 110148a6092fSMaxime Coquelin baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 110248a6092fSMaxime Coquelin 110348a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 110448a6092fSMaxime Coquelin 1105f264c6f6SErwan Le Ray ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 1106f264c6f6SErwan Le Ray isr, 1107f264c6f6SErwan Le Ray (isr & USART_SR_TC), 1108f264c6f6SErwan Le Ray 10, 100000); 1109f264c6f6SErwan Le Ray 1110f264c6f6SErwan Le Ray /* Send the TC error message only when ISR_TC is not set. */ 1111f264c6f6SErwan Le Ray if (ret) 1112f264c6f6SErwan Le Ray dev_err(port->dev, "Transmission is not complete\n"); 1113f264c6f6SErwan Le Ray 111448a6092fSMaxime Coquelin /* Stop serial port and reset value */ 1115ada8618fSAlexandre TORGUE writel_relaxed(0, port->membase + ofs->cr1); 111648a6092fSMaxime Coquelin 111784872dc4SErwan Le Ray /* flush RX & TX FIFO */ 111884872dc4SErwan Le Ray if (ofs->rqr != UNDEF_REG) 1119315e2d8aSErwan Le Ray writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1120315e2d8aSErwan Le Ray port->membase + ofs->rqr); 11211bcda09dSBich HEMON 112284872dc4SErwan Le Ray cr1 = USART_CR1_TE | USART_CR1_RE; 1123351a762aSGerald Baeza if (stm32_port->fifoen) 1124351a762aSGerald Baeza cr1 |= USART_CR1_FIFOEN; 11253cd66593SMartin Devera cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; 112625a8e761SErwan Le Ray 112725a8e761SErwan Le Ray /* Tx and RX FIFO configuration */ 1128d075719eSErwan Le Ray cr3 = readl_relaxed(port->membase + ofs->cr3); 112925a8e761SErwan Le Ray cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 113025a8e761SErwan Le Ray if (stm32_port->fifoen) { 11312aa1bbb2SFabrice Gasnier if (stm32_port->txftcfg >= 0) 11322aa1bbb2SFabrice Gasnier cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; 11332aa1bbb2SFabrice Gasnier if (stm32_port->rxftcfg >= 0) 11342aa1bbb2SFabrice Gasnier cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; 113525a8e761SErwan Le Ray } 113648a6092fSMaxime Coquelin 113748a6092fSMaxime Coquelin if (cflag & CSTOPB) 113848a6092fSMaxime Coquelin cr2 |= USART_CR2_STOP_2B; 113948a6092fSMaxime Coquelin 11403ec2ff37SJiri Slaby bits = tty_get_char_size(cflag); 11416c5962f3SErwan Le Ray stm32_port->rdr_mask = (BIT(bits) - 1); 1142c8a9d043SErwan Le Ray 114348a6092fSMaxime Coquelin if (cflag & PARENB) { 1144c8a9d043SErwan Le Ray bits++; 114548a6092fSMaxime Coquelin cr1 |= USART_CR1_PCE; 1146c8a9d043SErwan Le Ray } 1147c8a9d043SErwan Le Ray 1148c8a9d043SErwan Le Ray /* 1149c8a9d043SErwan Le Ray * Word length configuration: 1150c8a9d043SErwan Le Ray * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 1151c8a9d043SErwan Le Ray * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 1152c8a9d043SErwan Le Ray * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 1153c8a9d043SErwan Le Ray * M0 and M1 already cleared by cr1 initialization. 1154c8a9d043SErwan Le Ray */ 11551deeda8dSIlpo Järvinen if (bits == 9) { 1156ada8618fSAlexandre TORGUE cr1 |= USART_CR1_M0; 11571deeda8dSIlpo Järvinen } else if ((bits == 7) && cfg->has_7bits_data) { 1158c8a9d043SErwan Le Ray cr1 |= USART_CR1_M1; 11591deeda8dSIlpo Järvinen } else if (bits != 8) { 1160c8a9d043SErwan Le Ray dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 1161c8a9d043SErwan Le Ray , bits); 11621deeda8dSIlpo Järvinen cflag &= ~CSIZE; 11631deeda8dSIlpo Järvinen cflag |= CS8; 11641deeda8dSIlpo Järvinen termios->c_cflag = cflag; 11651deeda8dSIlpo Järvinen bits = 8; 11661deeda8dSIlpo Järvinen if (cflag & PARENB) { 11671deeda8dSIlpo Järvinen bits++; 11681deeda8dSIlpo Järvinen cr1 |= USART_CR1_M0; 11691deeda8dSIlpo Järvinen } 11701deeda8dSIlpo Järvinen } 117148a6092fSMaxime Coquelin 11724cc0ed62SErwan Le Ray if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 11732aa1bbb2SFabrice Gasnier (stm32_port->fifoen && 11742aa1bbb2SFabrice Gasnier stm32_port->rxftcfg >= 0))) { 11754cc0ed62SErwan Le Ray if (cflag & CSTOPB) 11764cc0ed62SErwan Le Ray bits = bits + 3; /* 1 start bit + 2 stop bits */ 11774cc0ed62SErwan Le Ray else 11784cc0ed62SErwan Le Ray bits = bits + 2; /* 1 start bit + 1 stop bit */ 11794cc0ed62SErwan Le Ray 11804cc0ed62SErwan Le Ray /* RX timeout irq to occur after last stop bit + bits */ 11814cc0ed62SErwan Le Ray stm32_port->cr1_irq = USART_CR1_RTOIE; 11824cc0ed62SErwan Le Ray writel_relaxed(bits, port->membase + ofs->rtor); 11834cc0ed62SErwan Le Ray cr2 |= USART_CR2_RTOEN; 118433bb2f6aSErwan Le Ray /* 118533bb2f6aSErwan Le Ray * Enable fifo threshold irq in two cases, either when there is no DMA, or when 118633bb2f6aSErwan Le Ray * wake up over usart, from low power until the DMA gets re-enabled by resume. 118733bb2f6aSErwan Le Ray */ 1188d0a6a7bcSErwan Le Ray stm32_port->cr3_irq = USART_CR3_RXFTIE; 11894cc0ed62SErwan Le Ray } 11904cc0ed62SErwan Le Ray 1191d0a6a7bcSErwan Le Ray cr1 |= stm32_port->cr1_irq; 1192d0a6a7bcSErwan Le Ray cr3 |= stm32_port->cr3_irq; 1193d0a6a7bcSErwan Le Ray 119448a6092fSMaxime Coquelin if (cflag & PARODD) 119548a6092fSMaxime Coquelin cr1 |= USART_CR1_PS; 119648a6092fSMaxime Coquelin 119748a6092fSMaxime Coquelin port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 119848a6092fSMaxime Coquelin if (cflag & CRTSCTS) { 119948a6092fSMaxime Coquelin port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 120035abe98fSBich HEMON cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 120148a6092fSMaxime Coquelin } 120248a6092fSMaxime Coquelin 120348a6092fSMaxime Coquelin usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 120448a6092fSMaxime Coquelin 120548a6092fSMaxime Coquelin /* 120648a6092fSMaxime Coquelin * The USART supports 16 or 8 times oversampling. 120748a6092fSMaxime Coquelin * By default we prefer 16 times oversampling, so that the receiver 120848a6092fSMaxime Coquelin * has a better tolerance to clock deviations. 120948a6092fSMaxime Coquelin * 8 times oversampling is only used to achieve higher speeds. 121048a6092fSMaxime Coquelin */ 121148a6092fSMaxime Coquelin if (usartdiv < 16) { 121248a6092fSMaxime Coquelin oversampling = 8; 12131bcda09dSBich HEMON cr1 |= USART_CR1_OVER8; 121456f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 121548a6092fSMaxime Coquelin } else { 121648a6092fSMaxime Coquelin oversampling = 16; 12171bcda09dSBich HEMON cr1 &= ~USART_CR1_OVER8; 121856f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 121948a6092fSMaxime Coquelin } 122048a6092fSMaxime Coquelin 122148a6092fSMaxime Coquelin mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 122248a6092fSMaxime Coquelin fraction = usartdiv % oversampling; 1223ada8618fSAlexandre TORGUE writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 122448a6092fSMaxime Coquelin 122548a6092fSMaxime Coquelin uart_update_timeout(port, cflag, baud); 122648a6092fSMaxime Coquelin 122748a6092fSMaxime Coquelin port->read_status_mask = USART_SR_ORE; 122848a6092fSMaxime Coquelin if (termios->c_iflag & INPCK) 122948a6092fSMaxime Coquelin port->read_status_mask |= USART_SR_PE | USART_SR_FE; 123048a6092fSMaxime Coquelin if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 12314f01d833SErwan Le Ray port->read_status_mask |= USART_SR_FE; 123248a6092fSMaxime Coquelin 123348a6092fSMaxime Coquelin /* Characters to ignore */ 123448a6092fSMaxime Coquelin port->ignore_status_mask = 0; 123548a6092fSMaxime Coquelin if (termios->c_iflag & IGNPAR) 123648a6092fSMaxime Coquelin port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 123748a6092fSMaxime Coquelin if (termios->c_iflag & IGNBRK) { 12384f01d833SErwan Le Ray port->ignore_status_mask |= USART_SR_FE; 123948a6092fSMaxime Coquelin /* 124048a6092fSMaxime Coquelin * If we're ignoring parity and break indicators, 124148a6092fSMaxime Coquelin * ignore overruns too (for real raw support). 124248a6092fSMaxime Coquelin */ 124348a6092fSMaxime Coquelin if (termios->c_iflag & IGNPAR) 124448a6092fSMaxime Coquelin port->ignore_status_mask |= USART_SR_ORE; 124548a6092fSMaxime Coquelin } 124648a6092fSMaxime Coquelin 124748a6092fSMaxime Coquelin /* Ignore all characters if CREAD is not set */ 124848a6092fSMaxime Coquelin if ((termios->c_cflag & CREAD) == 0) 124948a6092fSMaxime Coquelin port->ignore_status_mask |= USART_SR_DUMMY_RX; 125048a6092fSMaxime Coquelin 125133bb2f6aSErwan Le Ray if (stm32_port->rx_ch) { 125233bb2f6aSErwan Le Ray /* 125333bb2f6aSErwan Le Ray * Setup DMA to collect only valid data and enable error irqs. 125433bb2f6aSErwan Le Ray * This also enables break reception when using DMA. 125533bb2f6aSErwan Le Ray */ 125633bb2f6aSErwan Le Ray cr1 |= USART_CR1_PEIE; 125733bb2f6aSErwan Le Ray cr3 |= USART_CR3_EIE; 125834891872SAlexandre TORGUE cr3 |= USART_CR3_DMAR; 125933bb2f6aSErwan Le Ray cr3 |= USART_CR3_DDRE; 126033bb2f6aSErwan Le Ray } 126134891872SAlexandre TORGUE 12621bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_ENABLED) { 126356f9a76cSErwan Le Ray stm32_usart_config_reg_rs485(&cr1, &cr3, 12641bcda09dSBich HEMON rs485conf->delay_rts_before_send, 126556f9a76cSErwan Le Ray rs485conf->delay_rts_after_send, 126656f9a76cSErwan Le Ray baud); 12671bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 12681bcda09dSBich HEMON cr3 &= ~USART_CR3_DEP; 12691bcda09dSBich HEMON rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 12701bcda09dSBich HEMON } else { 12711bcda09dSBich HEMON cr3 |= USART_CR3_DEP; 12721bcda09dSBich HEMON rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 12731bcda09dSBich HEMON } 12741bcda09dSBich HEMON 12751bcda09dSBich HEMON } else { 12761bcda09dSBich HEMON cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 12771bcda09dSBich HEMON cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 12781bcda09dSBich HEMON } 12791bcda09dSBich HEMON 128012761869SErwan Le Ray /* Configure wake up from low power on start bit detection */ 12813d530017SAlexandre Torgue if (stm32_port->wakeup_src) { 128212761869SErwan Le Ray cr3 &= ~USART_CR3_WUS_MASK; 128312761869SErwan Le Ray cr3 |= USART_CR3_WUS_START_BIT; 128412761869SErwan Le Ray } 128512761869SErwan Le Ray 1286ada8618fSAlexandre TORGUE writel_relaxed(cr3, port->membase + ofs->cr3); 1287ada8618fSAlexandre TORGUE writel_relaxed(cr2, port->membase + ofs->cr2); 1288ada8618fSAlexandre TORGUE writel_relaxed(cr1, port->membase + ofs->cr1); 128948a6092fSMaxime Coquelin 129056f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 129148a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 1292436c9793SErwan Le Ray 1293436c9793SErwan Le Ray /* Handle modem control interrupts */ 1294436c9793SErwan Le Ray if (UART_ENABLE_MS(port, termios->c_cflag)) 1295436c9793SErwan Le Ray stm32_usart_enable_ms(port); 1296436c9793SErwan Le Ray else 1297436c9793SErwan Le Ray stm32_usart_disable_ms(port); 129848a6092fSMaxime Coquelin } 129948a6092fSMaxime Coquelin 130056f9a76cSErwan Le Ray static const char *stm32_usart_type(struct uart_port *port) 130148a6092fSMaxime Coquelin { 130248a6092fSMaxime Coquelin return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 130348a6092fSMaxime Coquelin } 130448a6092fSMaxime Coquelin 130556f9a76cSErwan Le Ray static void stm32_usart_release_port(struct uart_port *port) 130648a6092fSMaxime Coquelin { 130748a6092fSMaxime Coquelin } 130848a6092fSMaxime Coquelin 130956f9a76cSErwan Le Ray static int stm32_usart_request_port(struct uart_port *port) 131048a6092fSMaxime Coquelin { 131148a6092fSMaxime Coquelin return 0; 131248a6092fSMaxime Coquelin } 131348a6092fSMaxime Coquelin 131456f9a76cSErwan Le Ray static void stm32_usart_config_port(struct uart_port *port, int flags) 131548a6092fSMaxime Coquelin { 131648a6092fSMaxime Coquelin if (flags & UART_CONFIG_TYPE) 131748a6092fSMaxime Coquelin port->type = PORT_STM32; 131848a6092fSMaxime Coquelin } 131948a6092fSMaxime Coquelin 132048a6092fSMaxime Coquelin static int 132156f9a76cSErwan Le Ray stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 132248a6092fSMaxime Coquelin { 132348a6092fSMaxime Coquelin /* No user changeable parameters */ 132448a6092fSMaxime Coquelin return -EINVAL; 132548a6092fSMaxime Coquelin } 132648a6092fSMaxime Coquelin 132756f9a76cSErwan Le Ray static void stm32_usart_pm(struct uart_port *port, unsigned int state, 132848a6092fSMaxime Coquelin unsigned int oldstate) 132948a6092fSMaxime Coquelin { 133048a6092fSMaxime Coquelin struct stm32_port *stm32port = container_of(port, 133148a6092fSMaxime Coquelin struct stm32_port, port); 1332d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1333d825f0beSStephen Boyd const struct stm32_usart_config *cfg = &stm32port->info->cfg; 133418ee37e1SJohan Hovold unsigned long flags; 133548a6092fSMaxime Coquelin 133648a6092fSMaxime Coquelin switch (state) { 133748a6092fSMaxime Coquelin case UART_PM_STATE_ON: 1338fb6dcef6SErwan Le Ray pm_runtime_get_sync(port->dev); 133948a6092fSMaxime Coquelin break; 134048a6092fSMaxime Coquelin case UART_PM_STATE_OFF: 134148a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 134256f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 134348a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 1344fb6dcef6SErwan Le Ray pm_runtime_put_sync(port->dev); 134548a6092fSMaxime Coquelin break; 134648a6092fSMaxime Coquelin } 134748a6092fSMaxime Coquelin } 134848a6092fSMaxime Coquelin 13491f507b3aSValentin Caron #if defined(CONFIG_CONSOLE_POLL) 13501f507b3aSValentin Caron 13511f507b3aSValentin Caron /* Callbacks for characters polling in debug context (i.e. KGDB). */ 13521f507b3aSValentin Caron static int stm32_usart_poll_init(struct uart_port *port) 13531f507b3aSValentin Caron { 13541f507b3aSValentin Caron struct stm32_port *stm32_port = to_stm32_port(port); 13551f507b3aSValentin Caron 13561f507b3aSValentin Caron return clk_prepare_enable(stm32_port->clk); 13571f507b3aSValentin Caron } 13581f507b3aSValentin Caron 13591f507b3aSValentin Caron static int stm32_usart_poll_get_char(struct uart_port *port) 13601f507b3aSValentin Caron { 13611f507b3aSValentin Caron struct stm32_port *stm32_port = to_stm32_port(port); 13621f507b3aSValentin Caron const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 13631f507b3aSValentin Caron 13641f507b3aSValentin Caron if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) 13651f507b3aSValentin Caron return NO_POLL_CHAR; 13661f507b3aSValentin Caron 13671f507b3aSValentin Caron return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; 13681f507b3aSValentin Caron } 13691f507b3aSValentin Caron 13701f507b3aSValentin Caron static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch) 13711f507b3aSValentin Caron { 13721f507b3aSValentin Caron stm32_usart_console_putchar(port, ch); 13731f507b3aSValentin Caron } 13741f507b3aSValentin Caron #endif /* CONFIG_CONSOLE_POLL */ 13751f507b3aSValentin Caron 137648a6092fSMaxime Coquelin static const struct uart_ops stm32_uart_ops = { 137756f9a76cSErwan Le Ray .tx_empty = stm32_usart_tx_empty, 137856f9a76cSErwan Le Ray .set_mctrl = stm32_usart_set_mctrl, 137956f9a76cSErwan Le Ray .get_mctrl = stm32_usart_get_mctrl, 138056f9a76cSErwan Le Ray .stop_tx = stm32_usart_stop_tx, 138156f9a76cSErwan Le Ray .start_tx = stm32_usart_start_tx, 138256f9a76cSErwan Le Ray .throttle = stm32_usart_throttle, 138356f9a76cSErwan Le Ray .unthrottle = stm32_usart_unthrottle, 138456f9a76cSErwan Le Ray .stop_rx = stm32_usart_stop_rx, 138556f9a76cSErwan Le Ray .enable_ms = stm32_usart_enable_ms, 138656f9a76cSErwan Le Ray .break_ctl = stm32_usart_break_ctl, 138756f9a76cSErwan Le Ray .startup = stm32_usart_startup, 138856f9a76cSErwan Le Ray .shutdown = stm32_usart_shutdown, 13893d82be8bSErwan Le Ray .flush_buffer = stm32_usart_flush_buffer, 139056f9a76cSErwan Le Ray .set_termios = stm32_usart_set_termios, 139156f9a76cSErwan Le Ray .pm = stm32_usart_pm, 139256f9a76cSErwan Le Ray .type = stm32_usart_type, 139356f9a76cSErwan Le Ray .release_port = stm32_usart_release_port, 139456f9a76cSErwan Le Ray .request_port = stm32_usart_request_port, 139556f9a76cSErwan Le Ray .config_port = stm32_usart_config_port, 139656f9a76cSErwan Le Ray .verify_port = stm32_usart_verify_port, 13971f507b3aSValentin Caron #if defined(CONFIG_CONSOLE_POLL) 13981f507b3aSValentin Caron .poll_init = stm32_usart_poll_init, 13991f507b3aSValentin Caron .poll_get_char = stm32_usart_poll_get_char, 14001f507b3aSValentin Caron .poll_put_char = stm32_usart_poll_put_char, 14011f507b3aSValentin Caron #endif /* CONFIG_CONSOLE_POLL */ 140248a6092fSMaxime Coquelin }; 140348a6092fSMaxime Coquelin 14042aa1bbb2SFabrice Gasnier /* 14052aa1bbb2SFabrice Gasnier * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG) 14062aa1bbb2SFabrice Gasnier * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case, 14072aa1bbb2SFabrice Gasnier * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE. 14082aa1bbb2SFabrice Gasnier * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1. 14092aa1bbb2SFabrice Gasnier */ 14102aa1bbb2SFabrice Gasnier static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 }; 14112aa1bbb2SFabrice Gasnier 14122aa1bbb2SFabrice Gasnier static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p, 14132aa1bbb2SFabrice Gasnier int *ftcfg) 14142aa1bbb2SFabrice Gasnier { 14152aa1bbb2SFabrice Gasnier u32 bytes, i; 14162aa1bbb2SFabrice Gasnier 14172aa1bbb2SFabrice Gasnier /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ 14182aa1bbb2SFabrice Gasnier if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) 14192aa1bbb2SFabrice Gasnier bytes = 8; 14202aa1bbb2SFabrice Gasnier 14212aa1bbb2SFabrice Gasnier for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++) 14222aa1bbb2SFabrice Gasnier if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes) 14232aa1bbb2SFabrice Gasnier break; 14242aa1bbb2SFabrice Gasnier if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg)) 14252aa1bbb2SFabrice Gasnier i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; 14262aa1bbb2SFabrice Gasnier 14272aa1bbb2SFabrice Gasnier dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, 14282aa1bbb2SFabrice Gasnier stm32h7_usart_fifo_thresh_cfg[i]); 14292aa1bbb2SFabrice Gasnier 14302aa1bbb2SFabrice Gasnier /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */ 14312aa1bbb2SFabrice Gasnier if (i) 14322aa1bbb2SFabrice Gasnier *ftcfg = i - 1; 14332aa1bbb2SFabrice Gasnier else 14342aa1bbb2SFabrice Gasnier *ftcfg = -EINVAL; 14352aa1bbb2SFabrice Gasnier } 14362aa1bbb2SFabrice Gasnier 143797f3a085SErwan Le Ray static void stm32_usart_deinit_port(struct stm32_port *stm32port) 143897f3a085SErwan Le Ray { 143997f3a085SErwan Le Ray clk_disable_unprepare(stm32port->clk); 144097f3a085SErwan Le Ray } 144197f3a085SErwan Le Ray 1442aeae8f22SIlpo Järvinen static const struct serial_rs485 stm32_rs485_supported = { 1443aeae8f22SIlpo Järvinen .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1444aeae8f22SIlpo Järvinen SER_RS485_RX_DURING_TX, 1445aeae8f22SIlpo Järvinen .delay_rts_before_send = 1, 1446aeae8f22SIlpo Järvinen .delay_rts_after_send = 1, 1447aeae8f22SIlpo Järvinen }; 1448aeae8f22SIlpo Järvinen 144956f9a76cSErwan Le Ray static int stm32_usart_init_port(struct stm32_port *stm32port, 145048a6092fSMaxime Coquelin struct platform_device *pdev) 145148a6092fSMaxime Coquelin { 145248a6092fSMaxime Coquelin struct uart_port *port = &stm32port->port; 145348a6092fSMaxime Coquelin struct resource *res; 1454e0f2a902SErwan Le Ray int ret, irq; 145548a6092fSMaxime Coquelin 1456e0f2a902SErwan Le Ray irq = platform_get_irq(pdev, 0); 1457217b04c6STang Bin if (irq < 0) 1458217b04c6STang Bin return irq; 145992fc0023SErwan Le Ray 146048a6092fSMaxime Coquelin port->iotype = UPIO_MEM; 146148a6092fSMaxime Coquelin port->flags = UPF_BOOT_AUTOCONF; 146248a6092fSMaxime Coquelin port->ops = &stm32_uart_ops; 146348a6092fSMaxime Coquelin port->dev = &pdev->dev; 1464d075719eSErwan Le Ray port->fifosize = stm32port->info->cfg.fifosize; 14659feedaa7SDmitry Safonov port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1466e0f2a902SErwan Le Ray port->irq = irq; 146756f9a76cSErwan Le Ray port->rs485_config = stm32_usart_config_rs485; 14680139da50SIlpo Järvinen port->rs485_supported = stm32_rs485_supported; 14697d8f6861SBich HEMON 147056f9a76cSErwan Le Ray ret = stm32_usart_init_rs485(port, pdev); 1471c150c0f3SLukas Wunner if (ret) 1472c150c0f3SLukas Wunner return ret; 14737d8f6861SBich HEMON 14743d530017SAlexandre Torgue stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && 14753d530017SAlexandre Torgue of_property_read_bool(pdev->dev.of_node, "wakeup-source"); 14762c58e560SErwan Le Ray 14773cd66593SMartin Devera stm32port->swap = stm32port->info->cfg.has_swap && 14783cd66593SMartin Devera of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); 14793cd66593SMartin Devera 1480351a762aSGerald Baeza stm32port->fifoen = stm32port->info->cfg.has_fifo; 14812aa1bbb2SFabrice Gasnier if (stm32port->fifoen) { 14822aa1bbb2SFabrice Gasnier stm32_usart_get_ftcfg(pdev, "rx-threshold", 14832aa1bbb2SFabrice Gasnier &stm32port->rxftcfg); 14842aa1bbb2SFabrice Gasnier stm32_usart_get_ftcfg(pdev, "tx-threshold", 14852aa1bbb2SFabrice Gasnier &stm32port->txftcfg); 14862aa1bbb2SFabrice Gasnier } 148748a6092fSMaxime Coquelin 14883d881e32STang Bin port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 148948a6092fSMaxime Coquelin if (IS_ERR(port->membase)) 149048a6092fSMaxime Coquelin return PTR_ERR(port->membase); 149148a6092fSMaxime Coquelin port->mapbase = res->start; 149248a6092fSMaxime Coquelin 149348a6092fSMaxime Coquelin spin_lock_init(&port->lock); 149448a6092fSMaxime Coquelin 149548a6092fSMaxime Coquelin stm32port->clk = devm_clk_get(&pdev->dev, NULL); 149648a6092fSMaxime Coquelin if (IS_ERR(stm32port->clk)) 149748a6092fSMaxime Coquelin return PTR_ERR(stm32port->clk); 149848a6092fSMaxime Coquelin 149948a6092fSMaxime Coquelin /* Ensure that clk rate is correct by enabling the clk */ 150048a6092fSMaxime Coquelin ret = clk_prepare_enable(stm32port->clk); 150148a6092fSMaxime Coquelin if (ret) 150248a6092fSMaxime Coquelin return ret; 150348a6092fSMaxime Coquelin 150448a6092fSMaxime Coquelin stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1505ada80043SFabrice Gasnier if (!stm32port->port.uartclk) { 150648a6092fSMaxime Coquelin ret = -EINVAL; 15076cf61b9bSManivannan Sadhasivam goto err_clk; 1508ada80043SFabrice Gasnier } 150948a6092fSMaxime Coquelin 15106cf61b9bSManivannan Sadhasivam stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 15116cf61b9bSManivannan Sadhasivam if (IS_ERR(stm32port->gpios)) { 15126cf61b9bSManivannan Sadhasivam ret = PTR_ERR(stm32port->gpios); 15136cf61b9bSManivannan Sadhasivam goto err_clk; 15146cf61b9bSManivannan Sadhasivam } 15156cf61b9bSManivannan Sadhasivam 15169359369aSErwan Le Ray /* 15179359369aSErwan Le Ray * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 15189359369aSErwan Le Ray * properties should not be specified. 15199359369aSErwan Le Ray */ 15206cf61b9bSManivannan Sadhasivam if (stm32port->hw_flow_control) { 15216cf61b9bSManivannan Sadhasivam if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 15226cf61b9bSManivannan Sadhasivam mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 15236cf61b9bSManivannan Sadhasivam dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 15246cf61b9bSManivannan Sadhasivam ret = -EINVAL; 15256cf61b9bSManivannan Sadhasivam goto err_clk; 15266cf61b9bSManivannan Sadhasivam } 15276cf61b9bSManivannan Sadhasivam } 15286cf61b9bSManivannan Sadhasivam 15296cf61b9bSManivannan Sadhasivam return ret; 15306cf61b9bSManivannan Sadhasivam 15316cf61b9bSManivannan Sadhasivam err_clk: 15326cf61b9bSManivannan Sadhasivam clk_disable_unprepare(stm32port->clk); 15336cf61b9bSManivannan Sadhasivam 153448a6092fSMaxime Coquelin return ret; 153548a6092fSMaxime Coquelin } 153648a6092fSMaxime Coquelin 153756f9a76cSErwan Le Ray static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 153848a6092fSMaxime Coquelin { 153948a6092fSMaxime Coquelin struct device_node *np = pdev->dev.of_node; 154048a6092fSMaxime Coquelin int id; 154148a6092fSMaxime Coquelin 154248a6092fSMaxime Coquelin if (!np) 154348a6092fSMaxime Coquelin return NULL; 154448a6092fSMaxime Coquelin 154548a6092fSMaxime Coquelin id = of_alias_get_id(np, "serial"); 1546e5707915SGerald Baeza if (id < 0) { 1547e5707915SGerald Baeza dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1548e5707915SGerald Baeza return NULL; 1549e5707915SGerald Baeza } 155048a6092fSMaxime Coquelin 155148a6092fSMaxime Coquelin if (WARN_ON(id >= STM32_MAX_PORTS)) 155248a6092fSMaxime Coquelin return NULL; 155348a6092fSMaxime Coquelin 15546fd9fffbSErwan Le Ray stm32_ports[id].hw_flow_control = 15556fd9fffbSErwan Le Ray of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 15566fd9fffbSErwan Le Ray of_property_read_bool (np, "uart-has-rtscts"); 155748a6092fSMaxime Coquelin stm32_ports[id].port.line = id; 15584cc0ed62SErwan Le Ray stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1559d0a6a7bcSErwan Le Ray stm32_ports[id].cr3_irq = 0; 1560e5707915SGerald Baeza stm32_ports[id].last_res = RX_BUF_L; 156148a6092fSMaxime Coquelin return &stm32_ports[id]; 156248a6092fSMaxime Coquelin } 156348a6092fSMaxime Coquelin 156448a6092fSMaxime Coquelin #ifdef CONFIG_OF 156548a6092fSMaxime Coquelin static const struct of_device_id stm32_match[] = { 1566ada8618fSAlexandre TORGUE { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1567ada8618fSAlexandre TORGUE { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1568270e5a74SFabrice Gasnier { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 156948a6092fSMaxime Coquelin {}, 157048a6092fSMaxime Coquelin }; 157148a6092fSMaxime Coquelin 157248a6092fSMaxime Coquelin MODULE_DEVICE_TABLE(of, stm32_match); 157348a6092fSMaxime Coquelin #endif 157448a6092fSMaxime Coquelin 1575a7770a4bSErwan Le Ray static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port, 1576a7770a4bSErwan Le Ray struct platform_device *pdev) 1577a7770a4bSErwan Le Ray { 1578a7770a4bSErwan Le Ray if (stm32port->rx_buf) 1579a7770a4bSErwan Le Ray dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, 1580a7770a4bSErwan Le Ray stm32port->rx_dma_buf); 1581a7770a4bSErwan Le Ray } 1582a7770a4bSErwan Le Ray 158356f9a76cSErwan Le Ray static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 158434891872SAlexandre TORGUE struct platform_device *pdev) 158534891872SAlexandre TORGUE { 1586d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 158734891872SAlexandre TORGUE struct uart_port *port = &stm32port->port; 158834891872SAlexandre TORGUE struct device *dev = &pdev->dev; 158934891872SAlexandre TORGUE struct dma_slave_config config; 159034891872SAlexandre TORGUE int ret; 159134891872SAlexandre TORGUE 159259bd4eedSTang Bin stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, 159334891872SAlexandre TORGUE &stm32port->rx_dma_buf, 159434891872SAlexandre TORGUE GFP_KERNEL); 1595a7770a4bSErwan Le Ray if (!stm32port->rx_buf) 1596a7770a4bSErwan Le Ray return -ENOMEM; 159734891872SAlexandre TORGUE 159834891872SAlexandre TORGUE /* Configure DMA channel */ 159934891872SAlexandre TORGUE memset(&config, 0, sizeof(config)); 16008e5481d9SArnd Bergmann config.src_addr = port->mapbase + ofs->rdr; 160134891872SAlexandre TORGUE config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 160234891872SAlexandre TORGUE 160334891872SAlexandre TORGUE ret = dmaengine_slave_config(stm32port->rx_ch, &config); 160434891872SAlexandre TORGUE if (ret < 0) { 160534891872SAlexandre TORGUE dev_err(dev, "rx dma channel config failed\n"); 1606a7770a4bSErwan Le Ray stm32_usart_of_dma_rx_remove(stm32port, pdev); 1607a7770a4bSErwan Le Ray return ret; 160834891872SAlexandre TORGUE } 160934891872SAlexandre TORGUE 161034891872SAlexandre TORGUE return 0; 1611a7770a4bSErwan Le Ray } 161234891872SAlexandre TORGUE 1613a7770a4bSErwan Le Ray static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port, 1614a7770a4bSErwan Le Ray struct platform_device *pdev) 1615a7770a4bSErwan Le Ray { 1616a7770a4bSErwan Le Ray if (stm32port->tx_buf) 1617a7770a4bSErwan Le Ray dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, 1618a7770a4bSErwan Le Ray stm32port->tx_dma_buf); 161934891872SAlexandre TORGUE } 162034891872SAlexandre TORGUE 162156f9a76cSErwan Le Ray static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 162234891872SAlexandre TORGUE struct platform_device *pdev) 162334891872SAlexandre TORGUE { 1624d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 162534891872SAlexandre TORGUE struct uart_port *port = &stm32port->port; 162634891872SAlexandre TORGUE struct device *dev = &pdev->dev; 162734891872SAlexandre TORGUE struct dma_slave_config config; 162834891872SAlexandre TORGUE int ret; 162934891872SAlexandre TORGUE 163059bd4eedSTang Bin stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, 163134891872SAlexandre TORGUE &stm32port->tx_dma_buf, 163234891872SAlexandre TORGUE GFP_KERNEL); 1633a7770a4bSErwan Le Ray if (!stm32port->tx_buf) 1634a7770a4bSErwan Le Ray return -ENOMEM; 163534891872SAlexandre TORGUE 163634891872SAlexandre TORGUE /* Configure DMA channel */ 163734891872SAlexandre TORGUE memset(&config, 0, sizeof(config)); 16388e5481d9SArnd Bergmann config.dst_addr = port->mapbase + ofs->tdr; 163934891872SAlexandre TORGUE config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 164034891872SAlexandre TORGUE 164134891872SAlexandre TORGUE ret = dmaengine_slave_config(stm32port->tx_ch, &config); 164234891872SAlexandre TORGUE if (ret < 0) { 164334891872SAlexandre TORGUE dev_err(dev, "tx dma channel config failed\n"); 1644a7770a4bSErwan Le Ray stm32_usart_of_dma_tx_remove(stm32port, pdev); 1645a7770a4bSErwan Le Ray return ret; 164634891872SAlexandre TORGUE } 164734891872SAlexandre TORGUE 164834891872SAlexandre TORGUE return 0; 164934891872SAlexandre TORGUE } 165034891872SAlexandre TORGUE 165156f9a76cSErwan Le Ray static int stm32_usart_serial_probe(struct platform_device *pdev) 165248a6092fSMaxime Coquelin { 165348a6092fSMaxime Coquelin struct stm32_port *stm32port; 1654ada8618fSAlexandre TORGUE int ret; 165548a6092fSMaxime Coquelin 165656f9a76cSErwan Le Ray stm32port = stm32_usart_of_get_port(pdev); 165748a6092fSMaxime Coquelin if (!stm32port) 165848a6092fSMaxime Coquelin return -ENODEV; 165948a6092fSMaxime Coquelin 1660d825f0beSStephen Boyd stm32port->info = of_device_get_match_data(&pdev->dev); 1661d825f0beSStephen Boyd if (!stm32port->info) 1662ada8618fSAlexandre TORGUE return -EINVAL; 1663ada8618fSAlexandre TORGUE 1664a7770a4bSErwan Le Ray stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); 16650d114e9fSValentin Caron if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) 16660d114e9fSValentin Caron return -EPROBE_DEFER; 16670d114e9fSValentin Caron 1668a7770a4bSErwan Le Ray /* Fall back in interrupt mode for any non-deferral error */ 1669a7770a4bSErwan Le Ray if (IS_ERR(stm32port->rx_ch)) 1670a7770a4bSErwan Le Ray stm32port->rx_ch = NULL; 167134891872SAlexandre TORGUE 1672a7770a4bSErwan Le Ray stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); 1673a7770a4bSErwan Le Ray if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { 1674a7770a4bSErwan Le Ray ret = -EPROBE_DEFER; 1675a7770a4bSErwan Le Ray goto err_dma_rx; 1676a7770a4bSErwan Le Ray } 1677a7770a4bSErwan Le Ray /* Fall back in interrupt mode for any non-deferral error */ 1678a7770a4bSErwan Le Ray if (IS_ERR(stm32port->tx_ch)) 1679a7770a4bSErwan Le Ray stm32port->tx_ch = NULL; 1680a7770a4bSErwan Le Ray 16810d114e9fSValentin Caron ret = stm32_usart_init_port(stm32port, pdev); 16820d114e9fSValentin Caron if (ret) 16830d114e9fSValentin Caron goto err_dma_tx; 16840d114e9fSValentin Caron 16850d114e9fSValentin Caron if (stm32port->wakeup_src) { 16860d114e9fSValentin Caron device_set_wakeup_capable(&pdev->dev, true); 16870d114e9fSValentin Caron ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 16880d114e9fSValentin Caron if (ret) 16890d114e9fSValentin Caron goto err_deinit_port; 16900d114e9fSValentin Caron } 16910d114e9fSValentin Caron 1692a7770a4bSErwan Le Ray if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { 1693a7770a4bSErwan Le Ray /* Fall back in interrupt mode */ 1694a7770a4bSErwan Le Ray dma_release_channel(stm32port->rx_ch); 1695a7770a4bSErwan Le Ray stm32port->rx_ch = NULL; 1696a7770a4bSErwan Le Ray } 1697a7770a4bSErwan Le Ray 1698a7770a4bSErwan Le Ray if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { 1699a7770a4bSErwan Le Ray /* Fall back in interrupt mode */ 1700a7770a4bSErwan Le Ray dma_release_channel(stm32port->tx_ch); 1701a7770a4bSErwan Le Ray stm32port->tx_ch = NULL; 1702a7770a4bSErwan Le Ray } 1703a7770a4bSErwan Le Ray 1704a7770a4bSErwan Le Ray if (!stm32port->rx_ch) 1705a7770a4bSErwan Le Ray dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); 1706a7770a4bSErwan Le Ray if (!stm32port->tx_ch) 1707a7770a4bSErwan Le Ray dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); 170834891872SAlexandre TORGUE 170948a6092fSMaxime Coquelin platform_set_drvdata(pdev, &stm32port->port); 171048a6092fSMaxime Coquelin 1711fb6dcef6SErwan Le Ray pm_runtime_get_noresume(&pdev->dev); 1712fb6dcef6SErwan Le Ray pm_runtime_set_active(&pdev->dev); 1713fb6dcef6SErwan Le Ray pm_runtime_enable(&pdev->dev); 171487fd0741SErwan Le Ray 171587fd0741SErwan Le Ray ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 171687fd0741SErwan Le Ray if (ret) 171787fd0741SErwan Le Ray goto err_port; 171887fd0741SErwan Le Ray 1719fb6dcef6SErwan Le Ray pm_runtime_put_sync(&pdev->dev); 1720fb6dcef6SErwan Le Ray 172148a6092fSMaxime Coquelin return 0; 1722ada80043SFabrice Gasnier 172387fd0741SErwan Le Ray err_port: 172487fd0741SErwan Le Ray pm_runtime_disable(&pdev->dev); 172587fd0741SErwan Le Ray pm_runtime_set_suspended(&pdev->dev); 172687fd0741SErwan Le Ray pm_runtime_put_noidle(&pdev->dev); 172787fd0741SErwan Le Ray 17280d114e9fSValentin Caron if (stm32port->tx_ch) 1729a7770a4bSErwan Le Ray stm32_usart_of_dma_tx_remove(stm32port, pdev); 1730a7770a4bSErwan Le Ray if (stm32port->rx_ch) 1731a7770a4bSErwan Le Ray stm32_usart_of_dma_rx_remove(stm32port, pdev); 173287fd0741SErwan Le Ray 17333d530017SAlexandre Torgue if (stm32port->wakeup_src) 17345297f274SErwan Le Ray dev_pm_clear_wake_irq(&pdev->dev); 17355297f274SErwan Le Ray 1736a7770a4bSErwan Le Ray err_deinit_port: 17373d530017SAlexandre Torgue if (stm32port->wakeup_src) 17383d530017SAlexandre Torgue device_set_wakeup_capable(&pdev->dev, false); 1739270e5a74SFabrice Gasnier 174097f3a085SErwan Le Ray stm32_usart_deinit_port(stm32port); 1741ada80043SFabrice Gasnier 17420d114e9fSValentin Caron err_dma_tx: 17430d114e9fSValentin Caron if (stm32port->tx_ch) 17440d114e9fSValentin Caron dma_release_channel(stm32port->tx_ch); 17450d114e9fSValentin Caron 17460d114e9fSValentin Caron err_dma_rx: 17470d114e9fSValentin Caron if (stm32port->rx_ch) 17480d114e9fSValentin Caron dma_release_channel(stm32port->rx_ch); 17490d114e9fSValentin Caron 1750ada80043SFabrice Gasnier return ret; 175148a6092fSMaxime Coquelin } 175248a6092fSMaxime Coquelin 175356f9a76cSErwan Le Ray static int stm32_usart_serial_remove(struct platform_device *pdev) 175448a6092fSMaxime Coquelin { 175548a6092fSMaxime Coquelin struct uart_port *port = platform_get_drvdata(pdev); 1756511c7b1bSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1757d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 175833bb2f6aSErwan Le Ray u32 cr3; 1759fb6dcef6SErwan Le Ray 1760fb6dcef6SErwan Le Ray pm_runtime_get_sync(&pdev->dev); 1761*6bd6cd29SUwe Kleine-König uart_remove_one_port(&stm32_usart_driver, port); 176287fd0741SErwan Le Ray 176387fd0741SErwan Le Ray pm_runtime_disable(&pdev->dev); 176487fd0741SErwan Le Ray pm_runtime_set_suspended(&pdev->dev); 176587fd0741SErwan Le Ray pm_runtime_put_noidle(&pdev->dev); 176634891872SAlexandre TORGUE 176733bb2f6aSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); 176833bb2f6aSErwan Le Ray cr3 = readl_relaxed(port->membase + ofs->cr3); 176933bb2f6aSErwan Le Ray cr3 &= ~USART_CR3_EIE; 177033bb2f6aSErwan Le Ray cr3 &= ~USART_CR3_DMAR; 177133bb2f6aSErwan Le Ray cr3 &= ~USART_CR3_DDRE; 177233bb2f6aSErwan Le Ray writel_relaxed(cr3, port->membase + ofs->cr3); 177334891872SAlexandre TORGUE 177487fd0741SErwan Le Ray if (stm32_port->tx_ch) { 1775a7770a4bSErwan Le Ray stm32_usart_of_dma_tx_remove(stm32_port, pdev); 177634891872SAlexandre TORGUE dma_release_channel(stm32_port->tx_ch); 177787fd0741SErwan Le Ray } 177834891872SAlexandre TORGUE 1779a7770a4bSErwan Le Ray if (stm32_port->rx_ch) { 1780a7770a4bSErwan Le Ray stm32_usart_of_dma_rx_remove(stm32_port, pdev); 1781a7770a4bSErwan Le Ray dma_release_channel(stm32_port->rx_ch); 1782a7770a4bSErwan Le Ray } 1783a7770a4bSErwan Le Ray 1784a7770a4bSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1785511c7b1bSAlexandre TORGUE 17863d530017SAlexandre Torgue if (stm32_port->wakeup_src) { 17875297f274SErwan Le Ray dev_pm_clear_wake_irq(&pdev->dev); 1788270e5a74SFabrice Gasnier device_init_wakeup(&pdev->dev, false); 17895297f274SErwan Le Ray } 1790270e5a74SFabrice Gasnier 179197f3a085SErwan Le Ray stm32_usart_deinit_port(stm32_port); 179248a6092fSMaxime Coquelin 179387fd0741SErwan Le Ray return 0; 179448a6092fSMaxime Coquelin } 179548a6092fSMaxime Coquelin 17961f507b3aSValentin Caron static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 179748a6092fSMaxime Coquelin { 1798ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1799d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 180028fb1a92SValentin Caron u32 isr; 180128fb1a92SValentin Caron int ret; 1802ada8618fSAlexandre TORGUE 180328fb1a92SValentin Caron ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, 180428fb1a92SValentin Caron (isr & USART_SR_TXE), 100, 180528fb1a92SValentin Caron STM32_USART_TIMEOUT_USEC); 180628fb1a92SValentin Caron if (ret != 0) { 180728fb1a92SValentin Caron dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); 180828fb1a92SValentin Caron return; 180928fb1a92SValentin Caron } 1810ada8618fSAlexandre TORGUE writel_relaxed(ch, port->membase + ofs->tdr); 181148a6092fSMaxime Coquelin } 181248a6092fSMaxime Coquelin 18131f507b3aSValentin Caron #ifdef CONFIG_SERIAL_STM32_CONSOLE 181456f9a76cSErwan Le Ray static void stm32_usart_console_write(struct console *co, const char *s, 181592fc0023SErwan Le Ray unsigned int cnt) 181648a6092fSMaxime Coquelin { 181748a6092fSMaxime Coquelin struct uart_port *port = &stm32_ports[co->index].port; 1818ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1819d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1820d825f0beSStephen Boyd const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 182148a6092fSMaxime Coquelin unsigned long flags; 182248a6092fSMaxime Coquelin u32 old_cr1, new_cr1; 182348a6092fSMaxime Coquelin int locked = 1; 182448a6092fSMaxime Coquelin 1825cea37afdSJohan Hovold if (oops_in_progress) 1826cea37afdSJohan Hovold locked = spin_trylock_irqsave(&port->lock, flags); 182748a6092fSMaxime Coquelin else 1828cea37afdSJohan Hovold spin_lock_irqsave(&port->lock, flags); 182948a6092fSMaxime Coquelin 183087f1f809SAlexandre TORGUE /* Save and disable interrupts, enable the transmitter */ 1831ada8618fSAlexandre TORGUE old_cr1 = readl_relaxed(port->membase + ofs->cr1); 183248a6092fSMaxime Coquelin new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 183387f1f809SAlexandre TORGUE new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1834ada8618fSAlexandre TORGUE writel_relaxed(new_cr1, port->membase + ofs->cr1); 183548a6092fSMaxime Coquelin 183656f9a76cSErwan Le Ray uart_console_write(port, s, cnt, stm32_usart_console_putchar); 183748a6092fSMaxime Coquelin 183848a6092fSMaxime Coquelin /* Restore interrupt state */ 1839ada8618fSAlexandre TORGUE writel_relaxed(old_cr1, port->membase + ofs->cr1); 184048a6092fSMaxime Coquelin 184148a6092fSMaxime Coquelin if (locked) 1842cea37afdSJohan Hovold spin_unlock_irqrestore(&port->lock, flags); 184348a6092fSMaxime Coquelin } 184448a6092fSMaxime Coquelin 184556f9a76cSErwan Le Ray static int stm32_usart_console_setup(struct console *co, char *options) 184648a6092fSMaxime Coquelin { 184748a6092fSMaxime Coquelin struct stm32_port *stm32port; 184848a6092fSMaxime Coquelin int baud = 9600; 184948a6092fSMaxime Coquelin int bits = 8; 185048a6092fSMaxime Coquelin int parity = 'n'; 185148a6092fSMaxime Coquelin int flow = 'n'; 185248a6092fSMaxime Coquelin 185348a6092fSMaxime Coquelin if (co->index >= STM32_MAX_PORTS) 185448a6092fSMaxime Coquelin return -ENODEV; 185548a6092fSMaxime Coquelin 185648a6092fSMaxime Coquelin stm32port = &stm32_ports[co->index]; 185748a6092fSMaxime Coquelin 185848a6092fSMaxime Coquelin /* 185948a6092fSMaxime Coquelin * This driver does not support early console initialization 186048a6092fSMaxime Coquelin * (use ARM early printk support instead), so we only expect 186148a6092fSMaxime Coquelin * this to be called during the uart port registration when the 186248a6092fSMaxime Coquelin * driver gets probed and the port should be mapped at that point. 186348a6092fSMaxime Coquelin */ 186492fc0023SErwan Le Ray if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 186548a6092fSMaxime Coquelin return -ENXIO; 186648a6092fSMaxime Coquelin 186748a6092fSMaxime Coquelin if (options) 186848a6092fSMaxime Coquelin uart_parse_options(options, &baud, &parity, &bits, &flow); 186948a6092fSMaxime Coquelin 187048a6092fSMaxime Coquelin return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 187148a6092fSMaxime Coquelin } 187248a6092fSMaxime Coquelin 187348a6092fSMaxime Coquelin static struct console stm32_console = { 187448a6092fSMaxime Coquelin .name = STM32_SERIAL_NAME, 187548a6092fSMaxime Coquelin .device = uart_console_device, 187656f9a76cSErwan Le Ray .write = stm32_usart_console_write, 187756f9a76cSErwan Le Ray .setup = stm32_usart_console_setup, 187848a6092fSMaxime Coquelin .flags = CON_PRINTBUFFER, 187948a6092fSMaxime Coquelin .index = -1, 188048a6092fSMaxime Coquelin .data = &stm32_usart_driver, 188148a6092fSMaxime Coquelin }; 188248a6092fSMaxime Coquelin 188348a6092fSMaxime Coquelin #define STM32_SERIAL_CONSOLE (&stm32_console) 188448a6092fSMaxime Coquelin 188548a6092fSMaxime Coquelin #else 188648a6092fSMaxime Coquelin #define STM32_SERIAL_CONSOLE NULL 188748a6092fSMaxime Coquelin #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 188848a6092fSMaxime Coquelin 18898043b16fSValentin Caron #ifdef CONFIG_SERIAL_EARLYCON 18908043b16fSValentin Caron static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 18918043b16fSValentin Caron { 18928043b16fSValentin Caron struct stm32_usart_info *info = port->private_data; 18938043b16fSValentin Caron 18948043b16fSValentin Caron while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) 18958043b16fSValentin Caron cpu_relax(); 18968043b16fSValentin Caron 18978043b16fSValentin Caron writel_relaxed(ch, port->membase + info->ofs.tdr); 18988043b16fSValentin Caron } 18998043b16fSValentin Caron 19008043b16fSValentin Caron static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count) 19018043b16fSValentin Caron { 19028043b16fSValentin Caron struct earlycon_device *device = console->data; 19038043b16fSValentin Caron struct uart_port *port = &device->port; 19048043b16fSValentin Caron 19058043b16fSValentin Caron uart_console_write(port, s, count, early_stm32_usart_console_putchar); 19068043b16fSValentin Caron } 19078043b16fSValentin Caron 19088043b16fSValentin Caron static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options) 19098043b16fSValentin Caron { 19108043b16fSValentin Caron if (!(device->port.membase || device->port.iobase)) 19118043b16fSValentin Caron return -ENODEV; 19128043b16fSValentin Caron device->port.private_data = &stm32h7_info; 19138043b16fSValentin Caron device->con->write = early_stm32_serial_write; 19148043b16fSValentin Caron return 0; 19158043b16fSValentin Caron } 19168043b16fSValentin Caron 19178043b16fSValentin Caron static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options) 19188043b16fSValentin Caron { 19198043b16fSValentin Caron if (!(device->port.membase || device->port.iobase)) 19208043b16fSValentin Caron return -ENODEV; 19218043b16fSValentin Caron device->port.private_data = &stm32f7_info; 19228043b16fSValentin Caron device->con->write = early_stm32_serial_write; 19238043b16fSValentin Caron return 0; 19248043b16fSValentin Caron } 19258043b16fSValentin Caron 19268043b16fSValentin Caron static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options) 19278043b16fSValentin Caron { 19288043b16fSValentin Caron if (!(device->port.membase || device->port.iobase)) 19298043b16fSValentin Caron return -ENODEV; 19308043b16fSValentin Caron device->port.private_data = &stm32f4_info; 19318043b16fSValentin Caron device->con->write = early_stm32_serial_write; 19328043b16fSValentin Caron return 0; 19338043b16fSValentin Caron } 19348043b16fSValentin Caron 19358043b16fSValentin Caron OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup); 19368043b16fSValentin Caron OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup); 19378043b16fSValentin Caron OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup); 19388043b16fSValentin Caron #endif /* CONFIG_SERIAL_EARLYCON */ 19398043b16fSValentin Caron 194048a6092fSMaxime Coquelin static struct uart_driver stm32_usart_driver = { 194148a6092fSMaxime Coquelin .driver_name = DRIVER_NAME, 194248a6092fSMaxime Coquelin .dev_name = STM32_SERIAL_NAME, 194348a6092fSMaxime Coquelin .major = 0, 194448a6092fSMaxime Coquelin .minor = 0, 194548a6092fSMaxime Coquelin .nr = STM32_MAX_PORTS, 194648a6092fSMaxime Coquelin .cons = STM32_SERIAL_CONSOLE, 194748a6092fSMaxime Coquelin }; 194848a6092fSMaxime Coquelin 19496eeb348cSErwan Le Ray static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1950fe94347dSErwan Le Ray bool enable) 1951270e5a74SFabrice Gasnier { 1952270e5a74SFabrice Gasnier struct stm32_port *stm32_port = to_stm32_port(port); 1953d825f0beSStephen Boyd const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 19546eeb348cSErwan Le Ray struct tty_port *tport = &port->state->port; 19556eeb348cSErwan Le Ray int ret; 19566333a485SErwan Le Ray unsigned int size; 19576333a485SErwan Le Ray unsigned long flags; 1958270e5a74SFabrice Gasnier 19596eeb348cSErwan Le Ray if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) 19606eeb348cSErwan Le Ray return 0; 1961270e5a74SFabrice Gasnier 196212761869SErwan Le Ray /* 196312761869SErwan Le Ray * Enable low-power wake-up and wake-up irq if argument is set to 196412761869SErwan Le Ray * "enable", disable low-power wake-up and wake-up irq otherwise 196512761869SErwan Le Ray */ 1966270e5a74SFabrice Gasnier if (enable) { 196756f9a76cSErwan Le Ray stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 196812761869SErwan Le Ray stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 19697547d9abSErwan Le Ray mctrl_gpio_enable_irq_wake(stm32_port->gpios); 19706eeb348cSErwan Le Ray 19716eeb348cSErwan Le Ray /* 19726eeb348cSErwan Le Ray * When DMA is used for reception, it must be disabled before 19736eeb348cSErwan Le Ray * entering low-power mode and re-enabled when exiting from 19746eeb348cSErwan Le Ray * low-power mode. 19756eeb348cSErwan Le Ray */ 19766eeb348cSErwan Le Ray if (stm32_port->rx_ch) { 19776333a485SErwan Le Ray spin_lock_irqsave(&port->lock, flags); 19786333a485SErwan Le Ray /* Avoid race with RX IRQ when DMAR is cleared */ 19796eeb348cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 19806333a485SErwan Le Ray /* Poll data from DMA RX buffer if any */ 19816333a485SErwan Le Ray size = stm32_usart_receive_chars(port, true); 19826333a485SErwan Le Ray dmaengine_terminate_async(stm32_port->rx_ch); 19836333a485SErwan Le Ray uart_unlock_and_check_sysrq_irqrestore(port, flags); 19846333a485SErwan Le Ray if (size) 19856333a485SErwan Le Ray tty_flip_buffer_push(tport); 19866eeb348cSErwan Le Ray } 19876eeb348cSErwan Le Ray 19886eeb348cSErwan Le Ray /* Poll data from RX FIFO if any */ 19896eeb348cSErwan Le Ray stm32_usart_receive_chars(port, false); 1990270e5a74SFabrice Gasnier } else { 19916eeb348cSErwan Le Ray if (stm32_port->rx_ch) { 19926eeb348cSErwan Le Ray ret = stm32_usart_start_rx_dma_cyclic(port); 19936eeb348cSErwan Le Ray if (ret) 19946eeb348cSErwan Le Ray return ret; 19956eeb348cSErwan Le Ray } 19967547d9abSErwan Le Ray mctrl_gpio_disable_irq_wake(stm32_port->gpios); 199756f9a76cSErwan Le Ray stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 199812761869SErwan Le Ray stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 1999270e5a74SFabrice Gasnier } 20006eeb348cSErwan Le Ray 20016eeb348cSErwan Le Ray return 0; 2002270e5a74SFabrice Gasnier } 2003270e5a74SFabrice Gasnier 200456f9a76cSErwan Le Ray static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 2005270e5a74SFabrice Gasnier { 2006270e5a74SFabrice Gasnier struct uart_port *port = dev_get_drvdata(dev); 20076eeb348cSErwan Le Ray int ret; 2008270e5a74SFabrice Gasnier 2009270e5a74SFabrice Gasnier uart_suspend_port(&stm32_usart_driver, port); 2010270e5a74SFabrice Gasnier 20116eeb348cSErwan Le Ray if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 20126eeb348cSErwan Le Ray ret = stm32_usart_serial_en_wakeup(port, true); 20136eeb348cSErwan Le Ray if (ret) 20146eeb348cSErwan Le Ray return ret; 20156eeb348cSErwan Le Ray } 2016270e5a74SFabrice Gasnier 201755484fccSErwan Le Ray /* 201855484fccSErwan Le Ray * When "no_console_suspend" is enabled, keep the pinctrl default state 201955484fccSErwan Le Ray * and rely on bootloader stage to restore this state upon resume. 202055484fccSErwan Le Ray * Otherwise, apply the idle or sleep states depending on wakeup 202155484fccSErwan Le Ray * capabilities. 202255484fccSErwan Le Ray */ 202355484fccSErwan Le Ray if (console_suspend_enabled || !uart_console(port)) { 20241631eeeaSErwan Le Ray if (device_may_wakeup(dev) || device_wakeup_path(dev)) 202555484fccSErwan Le Ray pinctrl_pm_select_idle_state(dev); 202655484fccSErwan Le Ray else 202794616d9aSErwan Le Ray pinctrl_pm_select_sleep_state(dev); 202855484fccSErwan Le Ray } 202994616d9aSErwan Le Ray 2030270e5a74SFabrice Gasnier return 0; 2031270e5a74SFabrice Gasnier } 2032270e5a74SFabrice Gasnier 203356f9a76cSErwan Le Ray static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 2034270e5a74SFabrice Gasnier { 2035270e5a74SFabrice Gasnier struct uart_port *port = dev_get_drvdata(dev); 20366eeb348cSErwan Le Ray int ret; 2037270e5a74SFabrice Gasnier 203894616d9aSErwan Le Ray pinctrl_pm_select_default_state(dev); 203994616d9aSErwan Le Ray 20406eeb348cSErwan Le Ray if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 20416eeb348cSErwan Le Ray ret = stm32_usart_serial_en_wakeup(port, false); 20426eeb348cSErwan Le Ray if (ret) 20436eeb348cSErwan Le Ray return ret; 20446eeb348cSErwan Le Ray } 2045270e5a74SFabrice Gasnier 2046270e5a74SFabrice Gasnier return uart_resume_port(&stm32_usart_driver, port); 2047270e5a74SFabrice Gasnier } 2048270e5a74SFabrice Gasnier 204956f9a76cSErwan Le Ray static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 2050fb6dcef6SErwan Le Ray { 2051fb6dcef6SErwan Le Ray struct uart_port *port = dev_get_drvdata(dev); 2052fb6dcef6SErwan Le Ray struct stm32_port *stm32port = container_of(port, 2053fb6dcef6SErwan Le Ray struct stm32_port, port); 2054fb6dcef6SErwan Le Ray 2055fb6dcef6SErwan Le Ray clk_disable_unprepare(stm32port->clk); 2056fb6dcef6SErwan Le Ray 2057fb6dcef6SErwan Le Ray return 0; 2058fb6dcef6SErwan Le Ray } 2059fb6dcef6SErwan Le Ray 206056f9a76cSErwan Le Ray static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 2061fb6dcef6SErwan Le Ray { 2062fb6dcef6SErwan Le Ray struct uart_port *port = dev_get_drvdata(dev); 2063fb6dcef6SErwan Le Ray struct stm32_port *stm32port = container_of(port, 2064fb6dcef6SErwan Le Ray struct stm32_port, port); 2065fb6dcef6SErwan Le Ray 2066fb6dcef6SErwan Le Ray return clk_prepare_enable(stm32port->clk); 2067fb6dcef6SErwan Le Ray } 2068fb6dcef6SErwan Le Ray 2069270e5a74SFabrice Gasnier static const struct dev_pm_ops stm32_serial_pm_ops = { 207056f9a76cSErwan Le Ray SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 207156f9a76cSErwan Le Ray stm32_usart_runtime_resume, NULL) 207256f9a76cSErwan Le Ray SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 207356f9a76cSErwan Le Ray stm32_usart_serial_resume) 2074270e5a74SFabrice Gasnier }; 2075270e5a74SFabrice Gasnier 207648a6092fSMaxime Coquelin static struct platform_driver stm32_serial_driver = { 207756f9a76cSErwan Le Ray .probe = stm32_usart_serial_probe, 207856f9a76cSErwan Le Ray .remove = stm32_usart_serial_remove, 207948a6092fSMaxime Coquelin .driver = { 208048a6092fSMaxime Coquelin .name = DRIVER_NAME, 2081270e5a74SFabrice Gasnier .pm = &stm32_serial_pm_ops, 208248a6092fSMaxime Coquelin .of_match_table = of_match_ptr(stm32_match), 208348a6092fSMaxime Coquelin }, 208448a6092fSMaxime Coquelin }; 208548a6092fSMaxime Coquelin 208656f9a76cSErwan Le Ray static int __init stm32_usart_init(void) 208748a6092fSMaxime Coquelin { 208848a6092fSMaxime Coquelin static char banner[] __initdata = "STM32 USART driver initialized"; 208948a6092fSMaxime Coquelin int ret; 209048a6092fSMaxime Coquelin 209148a6092fSMaxime Coquelin pr_info("%s\n", banner); 209248a6092fSMaxime Coquelin 209348a6092fSMaxime Coquelin ret = uart_register_driver(&stm32_usart_driver); 209448a6092fSMaxime Coquelin if (ret) 209548a6092fSMaxime Coquelin return ret; 209648a6092fSMaxime Coquelin 209748a6092fSMaxime Coquelin ret = platform_driver_register(&stm32_serial_driver); 209848a6092fSMaxime Coquelin if (ret) 209948a6092fSMaxime Coquelin uart_unregister_driver(&stm32_usart_driver); 210048a6092fSMaxime Coquelin 210148a6092fSMaxime Coquelin return ret; 210248a6092fSMaxime Coquelin } 210348a6092fSMaxime Coquelin 210456f9a76cSErwan Le Ray static void __exit stm32_usart_exit(void) 210548a6092fSMaxime Coquelin { 210648a6092fSMaxime Coquelin platform_driver_unregister(&stm32_serial_driver); 210748a6092fSMaxime Coquelin uart_unregister_driver(&stm32_usart_driver); 210848a6092fSMaxime Coquelin } 210948a6092fSMaxime Coquelin 211056f9a76cSErwan Le Ray module_init(stm32_usart_init); 211156f9a76cSErwan Le Ray module_exit(stm32_usart_exit); 211248a6092fSMaxime Coquelin 211348a6092fSMaxime Coquelin MODULE_ALIAS("platform:" DRIVER_NAME); 211448a6092fSMaxime Coquelin MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 211548a6092fSMaxime Coquelin MODULE_LICENSE("GPL v2"); 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