1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 248a6092fSMaxime Coquelin /* 348a6092fSMaxime Coquelin * Copyright (C) Maxime Coquelin 2015 43e5fcbacSBich HEMON * Copyright (C) STMicroelectronics SA 2017 5ada8618fSAlexandre TORGUE * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6ada8618fSAlexandre TORGUE * Gerald Baeza <gerald.baeza@st.com> 748a6092fSMaxime Coquelin * 848a6092fSMaxime Coquelin * Inspired by st-asc.c from STMicroelectronics (c) 948a6092fSMaxime Coquelin */ 1048a6092fSMaxime Coquelin 116b596a83SMaxime Coquelin #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1248a6092fSMaxime Coquelin #define SUPPORT_SYSRQ 1348a6092fSMaxime Coquelin #endif 1448a6092fSMaxime Coquelin 1534891872SAlexandre TORGUE #include <linux/clk.h> 1648a6092fSMaxime Coquelin #include <linux/console.h> 1748a6092fSMaxime Coquelin #include <linux/delay.h> 1834891872SAlexandre TORGUE #include <linux/dma-direction.h> 1934891872SAlexandre TORGUE #include <linux/dmaengine.h> 2034891872SAlexandre TORGUE #include <linux/dma-mapping.h> 2134891872SAlexandre TORGUE #include <linux/io.h> 2234891872SAlexandre TORGUE #include <linux/iopoll.h> 2334891872SAlexandre TORGUE #include <linux/irq.h> 2434891872SAlexandre TORGUE #include <linux/module.h> 2548a6092fSMaxime Coquelin #include <linux/of.h> 2648a6092fSMaxime Coquelin #include <linux/of_platform.h> 2734891872SAlexandre TORGUE #include <linux/platform_device.h> 2834891872SAlexandre TORGUE #include <linux/pm_runtime.h> 29270e5a74SFabrice Gasnier #include <linux/pm_wakeirq.h> 3048a6092fSMaxime Coquelin #include <linux/serial_core.h> 3134891872SAlexandre TORGUE #include <linux/serial.h> 3234891872SAlexandre TORGUE #include <linux/spinlock.h> 3334891872SAlexandre TORGUE #include <linux/sysrq.h> 3434891872SAlexandre TORGUE #include <linux/tty_flip.h> 3534891872SAlexandre TORGUE #include <linux/tty.h> 3648a6092fSMaxime Coquelin 37bc5a0b55SAlexandre TORGUE #include "stm32-usart.h" 3848a6092fSMaxime Coquelin 3948a6092fSMaxime Coquelin static void stm32_stop_tx(struct uart_port *port); 4034891872SAlexandre TORGUE static void stm32_transmit_chars(struct uart_port *port); 4148a6092fSMaxime Coquelin 4248a6092fSMaxime Coquelin static inline struct stm32_port *to_stm32_port(struct uart_port *port) 4348a6092fSMaxime Coquelin { 4448a6092fSMaxime Coquelin return container_of(port, struct stm32_port, port); 4548a6092fSMaxime Coquelin } 4648a6092fSMaxime Coquelin 4748a6092fSMaxime Coquelin static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 4848a6092fSMaxime Coquelin { 4948a6092fSMaxime Coquelin u32 val; 5048a6092fSMaxime Coquelin 5148a6092fSMaxime Coquelin val = readl_relaxed(port->membase + reg); 5248a6092fSMaxime Coquelin val |= bits; 5348a6092fSMaxime Coquelin writel_relaxed(val, port->membase + reg); 5448a6092fSMaxime Coquelin } 5548a6092fSMaxime Coquelin 5648a6092fSMaxime Coquelin static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 5748a6092fSMaxime Coquelin { 5848a6092fSMaxime Coquelin u32 val; 5948a6092fSMaxime Coquelin 6048a6092fSMaxime Coquelin val = readl_relaxed(port->membase + reg); 6148a6092fSMaxime Coquelin val &= ~bits; 6248a6092fSMaxime Coquelin writel_relaxed(val, port->membase + reg); 6348a6092fSMaxime Coquelin } 6448a6092fSMaxime Coquelin 651bcda09dSBich HEMON static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 661bcda09dSBich HEMON u32 delay_DDE, u32 baud) 671bcda09dSBich HEMON { 681bcda09dSBich HEMON u32 rs485_deat_dedt; 691bcda09dSBich HEMON u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 701bcda09dSBich HEMON bool over8; 711bcda09dSBich HEMON 721bcda09dSBich HEMON *cr3 |= USART_CR3_DEM; 731bcda09dSBich HEMON over8 = *cr1 & USART_CR1_OVER8; 741bcda09dSBich HEMON 751bcda09dSBich HEMON if (over8) 761bcda09dSBich HEMON rs485_deat_dedt = delay_ADE * baud * 8; 771bcda09dSBich HEMON else 781bcda09dSBich HEMON rs485_deat_dedt = delay_ADE * baud * 16; 791bcda09dSBich HEMON 801bcda09dSBich HEMON rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 811bcda09dSBich HEMON rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 821bcda09dSBich HEMON rs485_deat_dedt_max : rs485_deat_dedt; 831bcda09dSBich HEMON rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 841bcda09dSBich HEMON USART_CR1_DEAT_MASK; 851bcda09dSBich HEMON *cr1 |= rs485_deat_dedt; 861bcda09dSBich HEMON 871bcda09dSBich HEMON if (over8) 881bcda09dSBich HEMON rs485_deat_dedt = delay_DDE * baud * 8; 891bcda09dSBich HEMON else 901bcda09dSBich HEMON rs485_deat_dedt = delay_DDE * baud * 16; 911bcda09dSBich HEMON 921bcda09dSBich HEMON rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 931bcda09dSBich HEMON rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 941bcda09dSBich HEMON rs485_deat_dedt_max : rs485_deat_dedt; 951bcda09dSBich HEMON rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 961bcda09dSBich HEMON USART_CR1_DEDT_MASK; 971bcda09dSBich HEMON *cr1 |= rs485_deat_dedt; 981bcda09dSBich HEMON } 991bcda09dSBich HEMON 1001bcda09dSBich HEMON static int stm32_config_rs485(struct uart_port *port, 1011bcda09dSBich HEMON struct serial_rs485 *rs485conf) 1021bcda09dSBich HEMON { 1031bcda09dSBich HEMON struct stm32_port *stm32_port = to_stm32_port(port); 1041bcda09dSBich HEMON struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1051bcda09dSBich HEMON struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1061bcda09dSBich HEMON u32 usartdiv, baud, cr1, cr3; 1071bcda09dSBich HEMON bool over8; 1081bcda09dSBich HEMON unsigned long flags; 1091bcda09dSBich HEMON 1101bcda09dSBich HEMON spin_lock_irqsave(&port->lock, flags); 1111bcda09dSBich HEMON stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1121bcda09dSBich HEMON 1131bcda09dSBich HEMON port->rs485 = *rs485conf; 1141bcda09dSBich HEMON 1151bcda09dSBich HEMON rs485conf->flags |= SER_RS485_RX_DURING_TX; 1161bcda09dSBich HEMON 1171bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_ENABLED) { 1181bcda09dSBich HEMON cr1 = readl_relaxed(port->membase + ofs->cr1); 1191bcda09dSBich HEMON cr3 = readl_relaxed(port->membase + ofs->cr3); 1201bcda09dSBich HEMON usartdiv = readl_relaxed(port->membase + ofs->brr); 1211bcda09dSBich HEMON usartdiv = usartdiv & GENMASK(15, 0); 1221bcda09dSBich HEMON over8 = cr1 & USART_CR1_OVER8; 1231bcda09dSBich HEMON 1241bcda09dSBich HEMON if (over8) 1251bcda09dSBich HEMON usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 1261bcda09dSBich HEMON << USART_BRR_04_R_SHIFT; 1271bcda09dSBich HEMON 1281bcda09dSBich HEMON baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 1291bcda09dSBich HEMON stm32_config_reg_rs485(&cr1, &cr3, 1301bcda09dSBich HEMON rs485conf->delay_rts_before_send, 1311bcda09dSBich HEMON rs485conf->delay_rts_after_send, baud); 1321bcda09dSBich HEMON 1331bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 1341bcda09dSBich HEMON cr3 &= ~USART_CR3_DEP; 1351bcda09dSBich HEMON rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1361bcda09dSBich HEMON } else { 1371bcda09dSBich HEMON cr3 |= USART_CR3_DEP; 1381bcda09dSBich HEMON rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1391bcda09dSBich HEMON } 1401bcda09dSBich HEMON 1411bcda09dSBich HEMON writel_relaxed(cr3, port->membase + ofs->cr3); 1421bcda09dSBich HEMON writel_relaxed(cr1, port->membase + ofs->cr1); 1431bcda09dSBich HEMON } else { 1441bcda09dSBich HEMON stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); 1451bcda09dSBich HEMON stm32_clr_bits(port, ofs->cr1, 1461bcda09dSBich HEMON USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 1471bcda09dSBich HEMON } 1481bcda09dSBich HEMON 1491bcda09dSBich HEMON stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1501bcda09dSBich HEMON spin_unlock_irqrestore(&port->lock, flags); 1511bcda09dSBich HEMON 1521bcda09dSBich HEMON return 0; 1531bcda09dSBich HEMON } 1541bcda09dSBich HEMON 1551bcda09dSBich HEMON static int stm32_init_rs485(struct uart_port *port, 1561bcda09dSBich HEMON struct platform_device *pdev) 1571bcda09dSBich HEMON { 1581bcda09dSBich HEMON struct serial_rs485 *rs485conf = &port->rs485; 1591bcda09dSBich HEMON 1601bcda09dSBich HEMON rs485conf->flags = 0; 1611bcda09dSBich HEMON rs485conf->delay_rts_before_send = 0; 1621bcda09dSBich HEMON rs485conf->delay_rts_after_send = 0; 1631bcda09dSBich HEMON 1641bcda09dSBich HEMON if (!pdev->dev.of_node) 1651bcda09dSBich HEMON return -ENODEV; 1661bcda09dSBich HEMON 1671bcda09dSBich HEMON uart_get_rs485_mode(&pdev->dev, rs485conf); 1681bcda09dSBich HEMON 1691bcda09dSBich HEMON return 0; 1701bcda09dSBich HEMON } 1711bcda09dSBich HEMON 172b97055bcSBaoyou Xie static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 17334891872SAlexandre TORGUE bool threaded) 17434891872SAlexandre TORGUE { 17534891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 17634891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 17734891872SAlexandre TORGUE enum dma_status status; 17834891872SAlexandre TORGUE struct dma_tx_state state; 17934891872SAlexandre TORGUE 18034891872SAlexandre TORGUE *sr = readl_relaxed(port->membase + ofs->isr); 18134891872SAlexandre TORGUE 18234891872SAlexandre TORGUE if (threaded && stm32_port->rx_ch) { 18334891872SAlexandre TORGUE status = dmaengine_tx_status(stm32_port->rx_ch, 18434891872SAlexandre TORGUE stm32_port->rx_ch->cookie, 18534891872SAlexandre TORGUE &state); 18634891872SAlexandre TORGUE if ((status == DMA_IN_PROGRESS) && 18734891872SAlexandre TORGUE (*last_res != state.residue)) 18834891872SAlexandre TORGUE return 1; 18934891872SAlexandre TORGUE else 19034891872SAlexandre TORGUE return 0; 19134891872SAlexandre TORGUE } else if (*sr & USART_SR_RXNE) { 19234891872SAlexandre TORGUE return 1; 19334891872SAlexandre TORGUE } 19434891872SAlexandre TORGUE return 0; 19534891872SAlexandre TORGUE } 19634891872SAlexandre TORGUE 1976c5962f3SErwan Le Ray static unsigned long stm32_get_char(struct uart_port *port, u32 *sr, 1986c5962f3SErwan Le Ray int *last_res) 19934891872SAlexandre TORGUE { 20034891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 20134891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 20234891872SAlexandre TORGUE unsigned long c; 20334891872SAlexandre TORGUE 20434891872SAlexandre TORGUE if (stm32_port->rx_ch) { 20534891872SAlexandre TORGUE c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 20634891872SAlexandre TORGUE if ((*last_res) == 0) 20734891872SAlexandre TORGUE *last_res = RX_BUF_L; 20834891872SAlexandre TORGUE } else { 2096c5962f3SErwan Le Ray c = readl_relaxed(port->membase + ofs->rdr); 2106c5962f3SErwan Le Ray /* apply RDR data mask */ 2116c5962f3SErwan Le Ray c &= stm32_port->rdr_mask; 21234891872SAlexandre TORGUE } 2136c5962f3SErwan Le Ray 2146c5962f3SErwan Le Ray return c; 21534891872SAlexandre TORGUE } 21634891872SAlexandre TORGUE 21734891872SAlexandre TORGUE static void stm32_receive_chars(struct uart_port *port, bool threaded) 21848a6092fSMaxime Coquelin { 21948a6092fSMaxime Coquelin struct tty_port *tport = &port->state->port; 220ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 221ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 22248a6092fSMaxime Coquelin unsigned long c; 22348a6092fSMaxime Coquelin u32 sr; 22448a6092fSMaxime Coquelin char flag; 22548a6092fSMaxime Coquelin 22629d60981SAndy Shevchenko if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 22748a6092fSMaxime Coquelin pm_wakeup_event(tport->tty->dev, 0); 22848a6092fSMaxime Coquelin 229e5707915SGerald Baeza while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 23048a6092fSMaxime Coquelin sr |= USART_SR_DUMMY_RX; 23148a6092fSMaxime Coquelin flag = TTY_NORMAL; 23248a6092fSMaxime Coquelin 2334f01d833SErwan Le Ray /* 2344f01d833SErwan Le Ray * Status bits has to be cleared before reading the RDR: 2354f01d833SErwan Le Ray * In FIFO mode, reading the RDR will pop the next data 2364f01d833SErwan Le Ray * (if any) along with its status bits into the SR. 2374f01d833SErwan Le Ray * Not doing so leads to misalignement between RDR and SR, 2384f01d833SErwan Le Ray * and clear status bits of the next rx data. 2394f01d833SErwan Le Ray * 2404f01d833SErwan Le Ray * Clear errors flags for stm32f7 and stm32h7 compatible 2414f01d833SErwan Le Ray * devices. On stm32f4 compatible devices, the error bit is 2424f01d833SErwan Le Ray * cleared by the sequence [read SR - read DR]. 2434f01d833SErwan Le Ray */ 2444f01d833SErwan Le Ray if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 2454f01d833SErwan Le Ray stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF | 2464f01d833SErwan Le Ray USART_ICR_PECF | USART_ICR_FECF); 2474f01d833SErwan Le Ray 2484f01d833SErwan Le Ray c = stm32_get_char(port, &sr, &stm32_port->last_res); 2494f01d833SErwan Le Ray port->icount.rx++; 25048a6092fSMaxime Coquelin if (sr & USART_SR_ERR_MASK) { 2514f01d833SErwan Le Ray if (sr & USART_SR_ORE) { 25248a6092fSMaxime Coquelin port->icount.overrun++; 25348a6092fSMaxime Coquelin } else if (sr & USART_SR_PE) { 25448a6092fSMaxime Coquelin port->icount.parity++; 25548a6092fSMaxime Coquelin } else if (sr & USART_SR_FE) { 2564f01d833SErwan Le Ray /* Break detection if character is null */ 2574f01d833SErwan Le Ray if (!c) { 2584f01d833SErwan Le Ray port->icount.brk++; 2594f01d833SErwan Le Ray if (uart_handle_break(port)) 2604f01d833SErwan Le Ray continue; 2614f01d833SErwan Le Ray } else { 26248a6092fSMaxime Coquelin port->icount.frame++; 26348a6092fSMaxime Coquelin } 2644f01d833SErwan Le Ray } 26548a6092fSMaxime Coquelin 26648a6092fSMaxime Coquelin sr &= port->read_status_mask; 26748a6092fSMaxime Coquelin 2684f01d833SErwan Le Ray if (sr & USART_SR_PE) { 26948a6092fSMaxime Coquelin flag = TTY_PARITY; 2704f01d833SErwan Le Ray } else if (sr & USART_SR_FE) { 2714f01d833SErwan Le Ray if (!c) 2724f01d833SErwan Le Ray flag = TTY_BREAK; 2734f01d833SErwan Le Ray else 27448a6092fSMaxime Coquelin flag = TTY_FRAME; 27548a6092fSMaxime Coquelin } 2764f01d833SErwan Le Ray } 27748a6092fSMaxime Coquelin 27848a6092fSMaxime Coquelin if (uart_handle_sysrq_char(port, c)) 27948a6092fSMaxime Coquelin continue; 28048a6092fSMaxime Coquelin uart_insert_char(port, sr, USART_SR_ORE, c, flag); 28148a6092fSMaxime Coquelin } 28248a6092fSMaxime Coquelin 28348a6092fSMaxime Coquelin spin_unlock(&port->lock); 28448a6092fSMaxime Coquelin tty_flip_buffer_push(tport); 28548a6092fSMaxime Coquelin spin_lock(&port->lock); 28648a6092fSMaxime Coquelin } 28748a6092fSMaxime Coquelin 28834891872SAlexandre TORGUE static void stm32_tx_dma_complete(void *arg) 28934891872SAlexandre TORGUE { 29034891872SAlexandre TORGUE struct uart_port *port = arg; 29134891872SAlexandre TORGUE struct stm32_port *stm32port = to_stm32_port(port); 29234891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 29334891872SAlexandre TORGUE 29434891872SAlexandre TORGUE stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 29534891872SAlexandre TORGUE stm32port->tx_dma_busy = false; 29634891872SAlexandre TORGUE 29734891872SAlexandre TORGUE /* Let's see if we have pending data to send */ 29834891872SAlexandre TORGUE stm32_transmit_chars(port); 29934891872SAlexandre TORGUE } 30034891872SAlexandre TORGUE 30134891872SAlexandre TORGUE static void stm32_transmit_chars_pio(struct uart_port *port) 30234891872SAlexandre TORGUE { 30334891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 30434891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 30534891872SAlexandre TORGUE struct circ_buf *xmit = &port->state->xmit; 30634891872SAlexandre TORGUE unsigned int isr; 30734891872SAlexandre TORGUE int ret; 30834891872SAlexandre TORGUE 30934891872SAlexandre TORGUE if (stm32_port->tx_dma_busy) { 31034891872SAlexandre TORGUE stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 31134891872SAlexandre TORGUE stm32_port->tx_dma_busy = false; 31234891872SAlexandre TORGUE } 31334891872SAlexandre TORGUE 31434891872SAlexandre TORGUE ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 31534891872SAlexandre TORGUE isr, 31634891872SAlexandre TORGUE (isr & USART_SR_TXE), 317a61d9e6eSGerald Baeza 10, 100000); 31834891872SAlexandre TORGUE 31934891872SAlexandre TORGUE if (ret) 32034891872SAlexandre TORGUE dev_err(port->dev, "tx empty not set\n"); 32134891872SAlexandre TORGUE 32234891872SAlexandre TORGUE stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 32334891872SAlexandre TORGUE 32434891872SAlexandre TORGUE writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 32534891872SAlexandre TORGUE xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 32634891872SAlexandre TORGUE port->icount.tx++; 32734891872SAlexandre TORGUE } 32834891872SAlexandre TORGUE 32934891872SAlexandre TORGUE static void stm32_transmit_chars_dma(struct uart_port *port) 33034891872SAlexandre TORGUE { 33134891872SAlexandre TORGUE struct stm32_port *stm32port = to_stm32_port(port); 33234891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 33334891872SAlexandre TORGUE struct circ_buf *xmit = &port->state->xmit; 33434891872SAlexandre TORGUE struct dma_async_tx_descriptor *desc = NULL; 33534891872SAlexandre TORGUE dma_cookie_t cookie; 33634891872SAlexandre TORGUE unsigned int count, i; 33734891872SAlexandre TORGUE 33834891872SAlexandre TORGUE if (stm32port->tx_dma_busy) 33934891872SAlexandre TORGUE return; 34034891872SAlexandre TORGUE 34134891872SAlexandre TORGUE stm32port->tx_dma_busy = true; 34234891872SAlexandre TORGUE 34334891872SAlexandre TORGUE count = uart_circ_chars_pending(xmit); 34434891872SAlexandre TORGUE 34534891872SAlexandre TORGUE if (count > TX_BUF_L) 34634891872SAlexandre TORGUE count = TX_BUF_L; 34734891872SAlexandre TORGUE 34834891872SAlexandre TORGUE if (xmit->tail < xmit->head) { 34934891872SAlexandre TORGUE memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 35034891872SAlexandre TORGUE } else { 35134891872SAlexandre TORGUE size_t one = UART_XMIT_SIZE - xmit->tail; 35234891872SAlexandre TORGUE size_t two; 35334891872SAlexandre TORGUE 35434891872SAlexandre TORGUE if (one > count) 35534891872SAlexandre TORGUE one = count; 35634891872SAlexandre TORGUE two = count - one; 35734891872SAlexandre TORGUE 35834891872SAlexandre TORGUE memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 35934891872SAlexandre TORGUE if (two) 36034891872SAlexandre TORGUE memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 36134891872SAlexandre TORGUE } 36234891872SAlexandre TORGUE 36334891872SAlexandre TORGUE desc = dmaengine_prep_slave_single(stm32port->tx_ch, 36434891872SAlexandre TORGUE stm32port->tx_dma_buf, 36534891872SAlexandre TORGUE count, 36634891872SAlexandre TORGUE DMA_MEM_TO_DEV, 36734891872SAlexandre TORGUE DMA_PREP_INTERRUPT); 36834891872SAlexandre TORGUE 36934891872SAlexandre TORGUE if (!desc) { 37034891872SAlexandre TORGUE for (i = count; i > 0; i--) 37134891872SAlexandre TORGUE stm32_transmit_chars_pio(port); 37234891872SAlexandre TORGUE return; 37334891872SAlexandre TORGUE } 37434891872SAlexandre TORGUE 37534891872SAlexandre TORGUE desc->callback = stm32_tx_dma_complete; 37634891872SAlexandre TORGUE desc->callback_param = port; 37734891872SAlexandre TORGUE 37834891872SAlexandre TORGUE /* Push current DMA TX transaction in the pending queue */ 37934891872SAlexandre TORGUE cookie = dmaengine_submit(desc); 38034891872SAlexandre TORGUE 38134891872SAlexandre TORGUE /* Issue pending DMA TX requests */ 38234891872SAlexandre TORGUE dma_async_issue_pending(stm32port->tx_ch); 38334891872SAlexandre TORGUE 38434891872SAlexandre TORGUE stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 38534891872SAlexandre TORGUE 38634891872SAlexandre TORGUE xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 38734891872SAlexandre TORGUE port->icount.tx += count; 38834891872SAlexandre TORGUE } 38934891872SAlexandre TORGUE 39048a6092fSMaxime Coquelin static void stm32_transmit_chars(struct uart_port *port) 39148a6092fSMaxime Coquelin { 392ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 393ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 39448a6092fSMaxime Coquelin struct circ_buf *xmit = &port->state->xmit; 39548a6092fSMaxime Coquelin 39648a6092fSMaxime Coquelin if (port->x_char) { 39734891872SAlexandre TORGUE if (stm32_port->tx_dma_busy) 39834891872SAlexandre TORGUE stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 399ada8618fSAlexandre TORGUE writel_relaxed(port->x_char, port->membase + ofs->tdr); 40048a6092fSMaxime Coquelin port->x_char = 0; 40148a6092fSMaxime Coquelin port->icount.tx++; 40234891872SAlexandre TORGUE if (stm32_port->tx_dma_busy) 40334891872SAlexandre TORGUE stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 40448a6092fSMaxime Coquelin return; 40548a6092fSMaxime Coquelin } 40648a6092fSMaxime Coquelin 407b83b957cSErwan Le Ray if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 408b83b957cSErwan Le Ray stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 40948a6092fSMaxime Coquelin return; 41048a6092fSMaxime Coquelin } 41148a6092fSMaxime Coquelin 41264c32eabSErwan Le Ray if (ofs->icr == UNDEF_REG) 41364c32eabSErwan Le Ray stm32_clr_bits(port, ofs->isr, USART_SR_TC); 41464c32eabSErwan Le Ray else 41564c32eabSErwan Le Ray stm32_set_bits(port, ofs->icr, USART_ICR_TCCF); 41664c32eabSErwan Le Ray 41734891872SAlexandre TORGUE if (stm32_port->tx_ch) 41834891872SAlexandre TORGUE stm32_transmit_chars_dma(port); 41934891872SAlexandre TORGUE else 42034891872SAlexandre TORGUE stm32_transmit_chars_pio(port); 42148a6092fSMaxime Coquelin 42248a6092fSMaxime Coquelin if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 42348a6092fSMaxime Coquelin uart_write_wakeup(port); 42448a6092fSMaxime Coquelin 42548a6092fSMaxime Coquelin if (uart_circ_empty(xmit)) 426b83b957cSErwan Le Ray stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 42748a6092fSMaxime Coquelin } 42848a6092fSMaxime Coquelin 42948a6092fSMaxime Coquelin static irqreturn_t stm32_interrupt(int irq, void *ptr) 43048a6092fSMaxime Coquelin { 43148a6092fSMaxime Coquelin struct uart_port *port = ptr; 432ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 433ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 43448a6092fSMaxime Coquelin u32 sr; 43548a6092fSMaxime Coquelin 43601d32d71SAlexandre TORGUE spin_lock(&port->lock); 43701d32d71SAlexandre TORGUE 438ada8618fSAlexandre TORGUE sr = readl_relaxed(port->membase + ofs->isr); 43948a6092fSMaxime Coquelin 440270e5a74SFabrice Gasnier if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 441270e5a74SFabrice Gasnier writel_relaxed(USART_ICR_WUCF, 442270e5a74SFabrice Gasnier port->membase + ofs->icr); 443270e5a74SFabrice Gasnier 44434891872SAlexandre TORGUE if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 44534891872SAlexandre TORGUE stm32_receive_chars(port, false); 44648a6092fSMaxime Coquelin 44734891872SAlexandre TORGUE if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 44848a6092fSMaxime Coquelin stm32_transmit_chars(port); 44948a6092fSMaxime Coquelin 45001d32d71SAlexandre TORGUE spin_unlock(&port->lock); 45101d32d71SAlexandre TORGUE 45234891872SAlexandre TORGUE if (stm32_port->rx_ch) 45334891872SAlexandre TORGUE return IRQ_WAKE_THREAD; 45434891872SAlexandre TORGUE else 45534891872SAlexandre TORGUE return IRQ_HANDLED; 45634891872SAlexandre TORGUE } 45734891872SAlexandre TORGUE 45834891872SAlexandre TORGUE static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 45934891872SAlexandre TORGUE { 46034891872SAlexandre TORGUE struct uart_port *port = ptr; 46134891872SAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 46234891872SAlexandre TORGUE 46334891872SAlexandre TORGUE spin_lock(&port->lock); 46434891872SAlexandre TORGUE 46534891872SAlexandre TORGUE if (stm32_port->rx_ch) 46634891872SAlexandre TORGUE stm32_receive_chars(port, true); 46734891872SAlexandre TORGUE 46848a6092fSMaxime Coquelin spin_unlock(&port->lock); 46948a6092fSMaxime Coquelin 47048a6092fSMaxime Coquelin return IRQ_HANDLED; 47148a6092fSMaxime Coquelin } 47248a6092fSMaxime Coquelin 47348a6092fSMaxime Coquelin static unsigned int stm32_tx_empty(struct uart_port *port) 47448a6092fSMaxime Coquelin { 475ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 476ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 477ada8618fSAlexandre TORGUE 478ada8618fSAlexandre TORGUE return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 47948a6092fSMaxime Coquelin } 48048a6092fSMaxime Coquelin 48148a6092fSMaxime Coquelin static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 48248a6092fSMaxime Coquelin { 483ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 484ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 485ada8618fSAlexandre TORGUE 48648a6092fSMaxime Coquelin if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 487ada8618fSAlexandre TORGUE stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 48848a6092fSMaxime Coquelin else 489ada8618fSAlexandre TORGUE stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 49048a6092fSMaxime Coquelin } 49148a6092fSMaxime Coquelin 49248a6092fSMaxime Coquelin static unsigned int stm32_get_mctrl(struct uart_port *port) 49348a6092fSMaxime Coquelin { 49448a6092fSMaxime Coquelin /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 49548a6092fSMaxime Coquelin return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 49648a6092fSMaxime Coquelin } 49748a6092fSMaxime Coquelin 49848a6092fSMaxime Coquelin /* Transmit stop */ 49948a6092fSMaxime Coquelin static void stm32_stop_tx(struct uart_port *port) 50048a6092fSMaxime Coquelin { 501ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 502ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 503ada8618fSAlexandre TORGUE 504ada8618fSAlexandre TORGUE stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 50548a6092fSMaxime Coquelin } 50648a6092fSMaxime Coquelin 50748a6092fSMaxime Coquelin /* There are probably characters waiting to be transmitted. */ 50848a6092fSMaxime Coquelin static void stm32_start_tx(struct uart_port *port) 50948a6092fSMaxime Coquelin { 51048a6092fSMaxime Coquelin struct circ_buf *xmit = &port->state->xmit; 51148a6092fSMaxime Coquelin 51248a6092fSMaxime Coquelin if (uart_circ_empty(xmit)) 51348a6092fSMaxime Coquelin return; 51448a6092fSMaxime Coquelin 51534891872SAlexandre TORGUE stm32_transmit_chars(port); 51648a6092fSMaxime Coquelin } 51748a6092fSMaxime Coquelin 51848a6092fSMaxime Coquelin /* Throttle the remote when input buffer is about to overflow. */ 51948a6092fSMaxime Coquelin static void stm32_throttle(struct uart_port *port) 52048a6092fSMaxime Coquelin { 521ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 522ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 52348a6092fSMaxime Coquelin unsigned long flags; 52448a6092fSMaxime Coquelin 52548a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 526ada8618fSAlexandre TORGUE stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 52748a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 52848a6092fSMaxime Coquelin } 52948a6092fSMaxime Coquelin 53048a6092fSMaxime Coquelin /* Unthrottle the remote, the input buffer can now accept data. */ 53148a6092fSMaxime Coquelin static void stm32_unthrottle(struct uart_port *port) 53248a6092fSMaxime Coquelin { 533ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 534ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 53548a6092fSMaxime Coquelin unsigned long flags; 53648a6092fSMaxime Coquelin 53748a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 538ada8618fSAlexandre TORGUE stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 53948a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 54048a6092fSMaxime Coquelin } 54148a6092fSMaxime Coquelin 54248a6092fSMaxime Coquelin /* Receive stop */ 54348a6092fSMaxime Coquelin static void stm32_stop_rx(struct uart_port *port) 54448a6092fSMaxime Coquelin { 545ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 546ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 547ada8618fSAlexandre TORGUE 548ada8618fSAlexandre TORGUE stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 54948a6092fSMaxime Coquelin } 55048a6092fSMaxime Coquelin 55148a6092fSMaxime Coquelin /* Handle breaks - ignored by us */ 55248a6092fSMaxime Coquelin static void stm32_break_ctl(struct uart_port *port, int break_state) 55348a6092fSMaxime Coquelin { 55448a6092fSMaxime Coquelin } 55548a6092fSMaxime Coquelin 55648a6092fSMaxime Coquelin static int stm32_startup(struct uart_port *port) 55748a6092fSMaxime Coquelin { 558ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 559ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 56048a6092fSMaxime Coquelin const char *name = to_platform_device(port->dev)->name; 56148a6092fSMaxime Coquelin u32 val; 56248a6092fSMaxime Coquelin int ret; 56348a6092fSMaxime Coquelin 56434891872SAlexandre TORGUE ret = request_threaded_irq(port->irq, stm32_interrupt, 56534891872SAlexandre TORGUE stm32_threaded_interrupt, 56634891872SAlexandre TORGUE IRQF_NO_SUSPEND, name, port); 56748a6092fSMaxime Coquelin if (ret) 56848a6092fSMaxime Coquelin return ret; 56948a6092fSMaxime Coquelin 57048a6092fSMaxime Coquelin val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 571351a762aSGerald Baeza if (stm32_port->fifoen) 572351a762aSGerald Baeza val |= USART_CR1_FIFOEN; 573ada8618fSAlexandre TORGUE stm32_set_bits(port, ofs->cr1, val); 57448a6092fSMaxime Coquelin 57548a6092fSMaxime Coquelin return 0; 57648a6092fSMaxime Coquelin } 57748a6092fSMaxime Coquelin 57848a6092fSMaxime Coquelin static void stm32_shutdown(struct uart_port *port) 57948a6092fSMaxime Coquelin { 580ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 581ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 58287f1f809SAlexandre TORGUE struct stm32_usart_config *cfg = &stm32_port->info->cfg; 58364c32eabSErwan Le Ray u32 val, isr; 58464c32eabSErwan Le Ray int ret; 58548a6092fSMaxime Coquelin 58648a6092fSMaxime Coquelin val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 58787f1f809SAlexandre TORGUE val |= BIT(cfg->uart_enable_bit); 588351a762aSGerald Baeza if (stm32_port->fifoen) 589351a762aSGerald Baeza val |= USART_CR1_FIFOEN; 59064c32eabSErwan Le Ray 59164c32eabSErwan Le Ray ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 59264c32eabSErwan Le Ray isr, (isr & USART_SR_TC), 59364c32eabSErwan Le Ray 10, 100000); 59464c32eabSErwan Le Ray 59564c32eabSErwan Le Ray if (ret) 59664c32eabSErwan Le Ray dev_err(port->dev, "transmission complete not set\n"); 59764c32eabSErwan Le Ray 598a14f66a4SAlexandre TORGUE stm32_clr_bits(port, ofs->cr1, val); 59948a6092fSMaxime Coquelin 60048a6092fSMaxime Coquelin free_irq(port->irq, port); 60148a6092fSMaxime Coquelin } 60248a6092fSMaxime Coquelin 603c8a9d043SErwan Le Ray unsigned int stm32_get_databits(struct ktermios *termios) 604c8a9d043SErwan Le Ray { 605c8a9d043SErwan Le Ray unsigned int bits; 606c8a9d043SErwan Le Ray 607c8a9d043SErwan Le Ray tcflag_t cflag = termios->c_cflag; 608c8a9d043SErwan Le Ray 609c8a9d043SErwan Le Ray switch (cflag & CSIZE) { 610c8a9d043SErwan Le Ray /* 611c8a9d043SErwan Le Ray * CSIZE settings are not necessarily supported in hardware. 612c8a9d043SErwan Le Ray * CSIZE unsupported configurations are handled here to set word length 613c8a9d043SErwan Le Ray * to 8 bits word as default configuration and to print debug message. 614c8a9d043SErwan Le Ray */ 615c8a9d043SErwan Le Ray case CS5: 616c8a9d043SErwan Le Ray bits = 5; 617c8a9d043SErwan Le Ray break; 618c8a9d043SErwan Le Ray case CS6: 619c8a9d043SErwan Le Ray bits = 6; 620c8a9d043SErwan Le Ray break; 621c8a9d043SErwan Le Ray case CS7: 622c8a9d043SErwan Le Ray bits = 7; 623c8a9d043SErwan Le Ray break; 624c8a9d043SErwan Le Ray /* default including CS8 */ 625c8a9d043SErwan Le Ray default: 626c8a9d043SErwan Le Ray bits = 8; 627c8a9d043SErwan Le Ray break; 628c8a9d043SErwan Le Ray } 629c8a9d043SErwan Le Ray 630c8a9d043SErwan Le Ray return bits; 631c8a9d043SErwan Le Ray } 632c8a9d043SErwan Le Ray 63348a6092fSMaxime Coquelin static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 63448a6092fSMaxime Coquelin struct ktermios *old) 63548a6092fSMaxime Coquelin { 63648a6092fSMaxime Coquelin struct stm32_port *stm32_port = to_stm32_port(port); 637ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 638ada8618fSAlexandre TORGUE struct stm32_usart_config *cfg = &stm32_port->info->cfg; 6391bcda09dSBich HEMON struct serial_rs485 *rs485conf = &port->rs485; 640c8a9d043SErwan Le Ray unsigned int baud, bits; 64148a6092fSMaxime Coquelin u32 usartdiv, mantissa, fraction, oversampling; 64248a6092fSMaxime Coquelin tcflag_t cflag = termios->c_cflag; 64348a6092fSMaxime Coquelin u32 cr1, cr2, cr3; 64448a6092fSMaxime Coquelin unsigned long flags; 64548a6092fSMaxime Coquelin 64648a6092fSMaxime Coquelin if (!stm32_port->hw_flow_control) 64748a6092fSMaxime Coquelin cflag &= ~CRTSCTS; 64848a6092fSMaxime Coquelin 64948a6092fSMaxime Coquelin baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 65048a6092fSMaxime Coquelin 65148a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 65248a6092fSMaxime Coquelin 65348a6092fSMaxime Coquelin /* Stop serial port and reset value */ 654ada8618fSAlexandre TORGUE writel_relaxed(0, port->membase + ofs->cr1); 65548a6092fSMaxime Coquelin 656ada8618fSAlexandre TORGUE cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 6571bcda09dSBich HEMON 658351a762aSGerald Baeza if (stm32_port->fifoen) 659351a762aSGerald Baeza cr1 |= USART_CR1_FIFOEN; 66048a6092fSMaxime Coquelin cr2 = 0; 66148a6092fSMaxime Coquelin cr3 = 0; 66248a6092fSMaxime Coquelin 66348a6092fSMaxime Coquelin if (cflag & CSTOPB) 66448a6092fSMaxime Coquelin cr2 |= USART_CR2_STOP_2B; 66548a6092fSMaxime Coquelin 666c8a9d043SErwan Le Ray bits = stm32_get_databits(termios); 6676c5962f3SErwan Le Ray stm32_port->rdr_mask = (BIT(bits) - 1); 668c8a9d043SErwan Le Ray 66948a6092fSMaxime Coquelin if (cflag & PARENB) { 670c8a9d043SErwan Le Ray bits++; 67148a6092fSMaxime Coquelin cr1 |= USART_CR1_PCE; 672c8a9d043SErwan Le Ray } 673c8a9d043SErwan Le Ray 674c8a9d043SErwan Le Ray /* 675c8a9d043SErwan Le Ray * Word length configuration: 676c8a9d043SErwan Le Ray * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 677c8a9d043SErwan Le Ray * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 678c8a9d043SErwan Le Ray * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 679c8a9d043SErwan Le Ray * M0 and M1 already cleared by cr1 initialization. 680c8a9d043SErwan Le Ray */ 681c8a9d043SErwan Le Ray if (bits == 9) 682ada8618fSAlexandre TORGUE cr1 |= USART_CR1_M0; 683c8a9d043SErwan Le Ray else if ((bits == 7) && cfg->has_7bits_data) 684c8a9d043SErwan Le Ray cr1 |= USART_CR1_M1; 685c8a9d043SErwan Le Ray else if (bits != 8) 686c8a9d043SErwan Le Ray dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 687c8a9d043SErwan Le Ray , bits); 68848a6092fSMaxime Coquelin 68948a6092fSMaxime Coquelin if (cflag & PARODD) 69048a6092fSMaxime Coquelin cr1 |= USART_CR1_PS; 69148a6092fSMaxime Coquelin 69248a6092fSMaxime Coquelin port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 69348a6092fSMaxime Coquelin if (cflag & CRTSCTS) { 69448a6092fSMaxime Coquelin port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 69535abe98fSBich HEMON cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 69648a6092fSMaxime Coquelin } 69748a6092fSMaxime Coquelin 69848a6092fSMaxime Coquelin usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 69948a6092fSMaxime Coquelin 70048a6092fSMaxime Coquelin /* 70148a6092fSMaxime Coquelin * The USART supports 16 or 8 times oversampling. 70248a6092fSMaxime Coquelin * By default we prefer 16 times oversampling, so that the receiver 70348a6092fSMaxime Coquelin * has a better tolerance to clock deviations. 70448a6092fSMaxime Coquelin * 8 times oversampling is only used to achieve higher speeds. 70548a6092fSMaxime Coquelin */ 70648a6092fSMaxime Coquelin if (usartdiv < 16) { 70748a6092fSMaxime Coquelin oversampling = 8; 7081bcda09dSBich HEMON cr1 |= USART_CR1_OVER8; 709ada8618fSAlexandre TORGUE stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 71048a6092fSMaxime Coquelin } else { 71148a6092fSMaxime Coquelin oversampling = 16; 7121bcda09dSBich HEMON cr1 &= ~USART_CR1_OVER8; 713ada8618fSAlexandre TORGUE stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 71448a6092fSMaxime Coquelin } 71548a6092fSMaxime Coquelin 71648a6092fSMaxime Coquelin mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 71748a6092fSMaxime Coquelin fraction = usartdiv % oversampling; 718ada8618fSAlexandre TORGUE writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 71948a6092fSMaxime Coquelin 72048a6092fSMaxime Coquelin uart_update_timeout(port, cflag, baud); 72148a6092fSMaxime Coquelin 72248a6092fSMaxime Coquelin port->read_status_mask = USART_SR_ORE; 72348a6092fSMaxime Coquelin if (termios->c_iflag & INPCK) 72448a6092fSMaxime Coquelin port->read_status_mask |= USART_SR_PE | USART_SR_FE; 72548a6092fSMaxime Coquelin if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 7264f01d833SErwan Le Ray port->read_status_mask |= USART_SR_FE; 72748a6092fSMaxime Coquelin 72848a6092fSMaxime Coquelin /* Characters to ignore */ 72948a6092fSMaxime Coquelin port->ignore_status_mask = 0; 73048a6092fSMaxime Coquelin if (termios->c_iflag & IGNPAR) 73148a6092fSMaxime Coquelin port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 73248a6092fSMaxime Coquelin if (termios->c_iflag & IGNBRK) { 7334f01d833SErwan Le Ray port->ignore_status_mask |= USART_SR_FE; 73448a6092fSMaxime Coquelin /* 73548a6092fSMaxime Coquelin * If we're ignoring parity and break indicators, 73648a6092fSMaxime Coquelin * ignore overruns too (for real raw support). 73748a6092fSMaxime Coquelin */ 73848a6092fSMaxime Coquelin if (termios->c_iflag & IGNPAR) 73948a6092fSMaxime Coquelin port->ignore_status_mask |= USART_SR_ORE; 74048a6092fSMaxime Coquelin } 74148a6092fSMaxime Coquelin 74248a6092fSMaxime Coquelin /* Ignore all characters if CREAD is not set */ 74348a6092fSMaxime Coquelin if ((termios->c_cflag & CREAD) == 0) 74448a6092fSMaxime Coquelin port->ignore_status_mask |= USART_SR_DUMMY_RX; 74548a6092fSMaxime Coquelin 74634891872SAlexandre TORGUE if (stm32_port->rx_ch) 74734891872SAlexandre TORGUE cr3 |= USART_CR3_DMAR; 74834891872SAlexandre TORGUE 7491bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_ENABLED) { 7501bcda09dSBich HEMON stm32_config_reg_rs485(&cr1, &cr3, 7511bcda09dSBich HEMON rs485conf->delay_rts_before_send, 7521bcda09dSBich HEMON rs485conf->delay_rts_after_send, baud); 7531bcda09dSBich HEMON if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 7541bcda09dSBich HEMON cr3 &= ~USART_CR3_DEP; 7551bcda09dSBich HEMON rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 7561bcda09dSBich HEMON } else { 7571bcda09dSBich HEMON cr3 |= USART_CR3_DEP; 7581bcda09dSBich HEMON rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 7591bcda09dSBich HEMON } 7601bcda09dSBich HEMON 7611bcda09dSBich HEMON } else { 7621bcda09dSBich HEMON cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 7631bcda09dSBich HEMON cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 7641bcda09dSBich HEMON } 7651bcda09dSBich HEMON 766ada8618fSAlexandre TORGUE writel_relaxed(cr3, port->membase + ofs->cr3); 767ada8618fSAlexandre TORGUE writel_relaxed(cr2, port->membase + ofs->cr2); 768ada8618fSAlexandre TORGUE writel_relaxed(cr1, port->membase + ofs->cr1); 76948a6092fSMaxime Coquelin 7701bcda09dSBich HEMON stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 77148a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 77248a6092fSMaxime Coquelin } 77348a6092fSMaxime Coquelin 77448a6092fSMaxime Coquelin static const char *stm32_type(struct uart_port *port) 77548a6092fSMaxime Coquelin { 77648a6092fSMaxime Coquelin return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 77748a6092fSMaxime Coquelin } 77848a6092fSMaxime Coquelin 77948a6092fSMaxime Coquelin static void stm32_release_port(struct uart_port *port) 78048a6092fSMaxime Coquelin { 78148a6092fSMaxime Coquelin } 78248a6092fSMaxime Coquelin 78348a6092fSMaxime Coquelin static int stm32_request_port(struct uart_port *port) 78448a6092fSMaxime Coquelin { 78548a6092fSMaxime Coquelin return 0; 78648a6092fSMaxime Coquelin } 78748a6092fSMaxime Coquelin 78848a6092fSMaxime Coquelin static void stm32_config_port(struct uart_port *port, int flags) 78948a6092fSMaxime Coquelin { 79048a6092fSMaxime Coquelin if (flags & UART_CONFIG_TYPE) 79148a6092fSMaxime Coquelin port->type = PORT_STM32; 79248a6092fSMaxime Coquelin } 79348a6092fSMaxime Coquelin 79448a6092fSMaxime Coquelin static int 79548a6092fSMaxime Coquelin stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 79648a6092fSMaxime Coquelin { 79748a6092fSMaxime Coquelin /* No user changeable parameters */ 79848a6092fSMaxime Coquelin return -EINVAL; 79948a6092fSMaxime Coquelin } 80048a6092fSMaxime Coquelin 80148a6092fSMaxime Coquelin static void stm32_pm(struct uart_port *port, unsigned int state, 80248a6092fSMaxime Coquelin unsigned int oldstate) 80348a6092fSMaxime Coquelin { 80448a6092fSMaxime Coquelin struct stm32_port *stm32port = container_of(port, 80548a6092fSMaxime Coquelin struct stm32_port, port); 806ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 807ada8618fSAlexandre TORGUE struct stm32_usart_config *cfg = &stm32port->info->cfg; 80848a6092fSMaxime Coquelin unsigned long flags = 0; 80948a6092fSMaxime Coquelin 81048a6092fSMaxime Coquelin switch (state) { 81148a6092fSMaxime Coquelin case UART_PM_STATE_ON: 81248a6092fSMaxime Coquelin clk_prepare_enable(stm32port->clk); 81348a6092fSMaxime Coquelin break; 81448a6092fSMaxime Coquelin case UART_PM_STATE_OFF: 81548a6092fSMaxime Coquelin spin_lock_irqsave(&port->lock, flags); 816ada8618fSAlexandre TORGUE stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 81748a6092fSMaxime Coquelin spin_unlock_irqrestore(&port->lock, flags); 81848a6092fSMaxime Coquelin clk_disable_unprepare(stm32port->clk); 81948a6092fSMaxime Coquelin break; 82048a6092fSMaxime Coquelin } 82148a6092fSMaxime Coquelin } 82248a6092fSMaxime Coquelin 82348a6092fSMaxime Coquelin static const struct uart_ops stm32_uart_ops = { 82448a6092fSMaxime Coquelin .tx_empty = stm32_tx_empty, 82548a6092fSMaxime Coquelin .set_mctrl = stm32_set_mctrl, 82648a6092fSMaxime Coquelin .get_mctrl = stm32_get_mctrl, 82748a6092fSMaxime Coquelin .stop_tx = stm32_stop_tx, 82848a6092fSMaxime Coquelin .start_tx = stm32_start_tx, 82948a6092fSMaxime Coquelin .throttle = stm32_throttle, 83048a6092fSMaxime Coquelin .unthrottle = stm32_unthrottle, 83148a6092fSMaxime Coquelin .stop_rx = stm32_stop_rx, 83248a6092fSMaxime Coquelin .break_ctl = stm32_break_ctl, 83348a6092fSMaxime Coquelin .startup = stm32_startup, 83448a6092fSMaxime Coquelin .shutdown = stm32_shutdown, 83548a6092fSMaxime Coquelin .set_termios = stm32_set_termios, 83648a6092fSMaxime Coquelin .pm = stm32_pm, 83748a6092fSMaxime Coquelin .type = stm32_type, 83848a6092fSMaxime Coquelin .release_port = stm32_release_port, 83948a6092fSMaxime Coquelin .request_port = stm32_request_port, 84048a6092fSMaxime Coquelin .config_port = stm32_config_port, 84148a6092fSMaxime Coquelin .verify_port = stm32_verify_port, 84248a6092fSMaxime Coquelin }; 84348a6092fSMaxime Coquelin 84448a6092fSMaxime Coquelin static int stm32_init_port(struct stm32_port *stm32port, 84548a6092fSMaxime Coquelin struct platform_device *pdev) 84648a6092fSMaxime Coquelin { 84748a6092fSMaxime Coquelin struct uart_port *port = &stm32port->port; 84848a6092fSMaxime Coquelin struct resource *res; 84948a6092fSMaxime Coquelin int ret; 85048a6092fSMaxime Coquelin 85148a6092fSMaxime Coquelin port->iotype = UPIO_MEM; 85248a6092fSMaxime Coquelin port->flags = UPF_BOOT_AUTOCONF; 85348a6092fSMaxime Coquelin port->ops = &stm32_uart_ops; 85448a6092fSMaxime Coquelin port->dev = &pdev->dev; 85548a6092fSMaxime Coquelin port->irq = platform_get_irq(pdev, 0); 8567d8f6861SBich HEMON port->rs485_config = stm32_config_rs485; 8577d8f6861SBich HEMON 8587d8f6861SBich HEMON stm32_init_rs485(port, pdev); 8597d8f6861SBich HEMON 860270e5a74SFabrice Gasnier stm32port->wakeirq = platform_get_irq(pdev, 1); 861351a762aSGerald Baeza stm32port->fifoen = stm32port->info->cfg.has_fifo; 86248a6092fSMaxime Coquelin 86348a6092fSMaxime Coquelin res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 86448a6092fSMaxime Coquelin port->membase = devm_ioremap_resource(&pdev->dev, res); 86548a6092fSMaxime Coquelin if (IS_ERR(port->membase)) 86648a6092fSMaxime Coquelin return PTR_ERR(port->membase); 86748a6092fSMaxime Coquelin port->mapbase = res->start; 86848a6092fSMaxime Coquelin 86948a6092fSMaxime Coquelin spin_lock_init(&port->lock); 87048a6092fSMaxime Coquelin 87148a6092fSMaxime Coquelin stm32port->clk = devm_clk_get(&pdev->dev, NULL); 87248a6092fSMaxime Coquelin if (IS_ERR(stm32port->clk)) 87348a6092fSMaxime Coquelin return PTR_ERR(stm32port->clk); 87448a6092fSMaxime Coquelin 87548a6092fSMaxime Coquelin /* Ensure that clk rate is correct by enabling the clk */ 87648a6092fSMaxime Coquelin ret = clk_prepare_enable(stm32port->clk); 87748a6092fSMaxime Coquelin if (ret) 87848a6092fSMaxime Coquelin return ret; 87948a6092fSMaxime Coquelin 88048a6092fSMaxime Coquelin stm32port->port.uartclk = clk_get_rate(stm32port->clk); 881ada80043SFabrice Gasnier if (!stm32port->port.uartclk) { 882ada80043SFabrice Gasnier clk_disable_unprepare(stm32port->clk); 88348a6092fSMaxime Coquelin ret = -EINVAL; 884ada80043SFabrice Gasnier } 88548a6092fSMaxime Coquelin 88648a6092fSMaxime Coquelin return ret; 88748a6092fSMaxime Coquelin } 88848a6092fSMaxime Coquelin 88948a6092fSMaxime Coquelin static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 89048a6092fSMaxime Coquelin { 89148a6092fSMaxime Coquelin struct device_node *np = pdev->dev.of_node; 89248a6092fSMaxime Coquelin int id; 89348a6092fSMaxime Coquelin 89448a6092fSMaxime Coquelin if (!np) 89548a6092fSMaxime Coquelin return NULL; 89648a6092fSMaxime Coquelin 89748a6092fSMaxime Coquelin id = of_alias_get_id(np, "serial"); 898e5707915SGerald Baeza if (id < 0) { 899e5707915SGerald Baeza dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 900e5707915SGerald Baeza return NULL; 901e5707915SGerald Baeza } 90248a6092fSMaxime Coquelin 90348a6092fSMaxime Coquelin if (WARN_ON(id >= STM32_MAX_PORTS)) 90448a6092fSMaxime Coquelin return NULL; 90548a6092fSMaxime Coquelin 90648a6092fSMaxime Coquelin stm32_ports[id].hw_flow_control = of_property_read_bool(np, 90759bed2dfSAlexandre TORGUE "st,hw-flow-ctrl"); 90848a6092fSMaxime Coquelin stm32_ports[id].port.line = id; 909e5707915SGerald Baeza stm32_ports[id].last_res = RX_BUF_L; 91048a6092fSMaxime Coquelin return &stm32_ports[id]; 91148a6092fSMaxime Coquelin } 91248a6092fSMaxime Coquelin 91348a6092fSMaxime Coquelin #ifdef CONFIG_OF 91448a6092fSMaxime Coquelin static const struct of_device_id stm32_match[] = { 915ada8618fSAlexandre TORGUE { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 916ada8618fSAlexandre TORGUE { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 917270e5a74SFabrice Gasnier { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 91848a6092fSMaxime Coquelin {}, 91948a6092fSMaxime Coquelin }; 92048a6092fSMaxime Coquelin 92148a6092fSMaxime Coquelin MODULE_DEVICE_TABLE(of, stm32_match); 92248a6092fSMaxime Coquelin #endif 92348a6092fSMaxime Coquelin 92434891872SAlexandre TORGUE static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 92534891872SAlexandre TORGUE struct platform_device *pdev) 92634891872SAlexandre TORGUE { 92734891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 92834891872SAlexandre TORGUE struct uart_port *port = &stm32port->port; 92934891872SAlexandre TORGUE struct device *dev = &pdev->dev; 93034891872SAlexandre TORGUE struct dma_slave_config config; 93134891872SAlexandre TORGUE struct dma_async_tx_descriptor *desc = NULL; 93234891872SAlexandre TORGUE dma_cookie_t cookie; 93334891872SAlexandre TORGUE int ret; 93434891872SAlexandre TORGUE 93534891872SAlexandre TORGUE /* Request DMA RX channel */ 93634891872SAlexandre TORGUE stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 93734891872SAlexandre TORGUE if (!stm32port->rx_ch) { 93834891872SAlexandre TORGUE dev_info(dev, "rx dma alloc failed\n"); 93934891872SAlexandre TORGUE return -ENODEV; 94034891872SAlexandre TORGUE } 94134891872SAlexandre TORGUE stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 94234891872SAlexandre TORGUE &stm32port->rx_dma_buf, 94334891872SAlexandre TORGUE GFP_KERNEL); 94434891872SAlexandre TORGUE if (!stm32port->rx_buf) { 94534891872SAlexandre TORGUE ret = -ENOMEM; 94634891872SAlexandre TORGUE goto alloc_err; 94734891872SAlexandre TORGUE } 94834891872SAlexandre TORGUE 94934891872SAlexandre TORGUE /* Configure DMA channel */ 95034891872SAlexandre TORGUE memset(&config, 0, sizeof(config)); 9518e5481d9SArnd Bergmann config.src_addr = port->mapbase + ofs->rdr; 95234891872SAlexandre TORGUE config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 95334891872SAlexandre TORGUE 95434891872SAlexandre TORGUE ret = dmaengine_slave_config(stm32port->rx_ch, &config); 95534891872SAlexandre TORGUE if (ret < 0) { 95634891872SAlexandre TORGUE dev_err(dev, "rx dma channel config failed\n"); 95734891872SAlexandre TORGUE ret = -ENODEV; 95834891872SAlexandre TORGUE goto config_err; 95934891872SAlexandre TORGUE } 96034891872SAlexandre TORGUE 96134891872SAlexandre TORGUE /* Prepare a DMA cyclic transaction */ 96234891872SAlexandre TORGUE desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 96334891872SAlexandre TORGUE stm32port->rx_dma_buf, 96434891872SAlexandre TORGUE RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 96534891872SAlexandre TORGUE DMA_PREP_INTERRUPT); 96634891872SAlexandre TORGUE if (!desc) { 96734891872SAlexandre TORGUE dev_err(dev, "rx dma prep cyclic failed\n"); 96834891872SAlexandre TORGUE ret = -ENODEV; 96934891872SAlexandre TORGUE goto config_err; 97034891872SAlexandre TORGUE } 97134891872SAlexandre TORGUE 97234891872SAlexandre TORGUE /* No callback as dma buffer is drained on usart interrupt */ 97334891872SAlexandre TORGUE desc->callback = NULL; 97434891872SAlexandre TORGUE desc->callback_param = NULL; 97534891872SAlexandre TORGUE 97634891872SAlexandre TORGUE /* Push current DMA transaction in the pending queue */ 97734891872SAlexandre TORGUE cookie = dmaengine_submit(desc); 97834891872SAlexandre TORGUE 97934891872SAlexandre TORGUE /* Issue pending DMA requests */ 98034891872SAlexandre TORGUE dma_async_issue_pending(stm32port->rx_ch); 98134891872SAlexandre TORGUE 98234891872SAlexandre TORGUE return 0; 98334891872SAlexandre TORGUE 98434891872SAlexandre TORGUE config_err: 98534891872SAlexandre TORGUE dma_free_coherent(&pdev->dev, 98634891872SAlexandre TORGUE RX_BUF_L, stm32port->rx_buf, 98734891872SAlexandre TORGUE stm32port->rx_dma_buf); 98834891872SAlexandre TORGUE 98934891872SAlexandre TORGUE alloc_err: 99034891872SAlexandre TORGUE dma_release_channel(stm32port->rx_ch); 99134891872SAlexandre TORGUE stm32port->rx_ch = NULL; 99234891872SAlexandre TORGUE 99334891872SAlexandre TORGUE return ret; 99434891872SAlexandre TORGUE } 99534891872SAlexandre TORGUE 99634891872SAlexandre TORGUE static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 99734891872SAlexandre TORGUE struct platform_device *pdev) 99834891872SAlexandre TORGUE { 99934891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 100034891872SAlexandre TORGUE struct uart_port *port = &stm32port->port; 100134891872SAlexandre TORGUE struct device *dev = &pdev->dev; 100234891872SAlexandre TORGUE struct dma_slave_config config; 100334891872SAlexandre TORGUE int ret; 100434891872SAlexandre TORGUE 100534891872SAlexandre TORGUE stm32port->tx_dma_busy = false; 100634891872SAlexandre TORGUE 100734891872SAlexandre TORGUE /* Request DMA TX channel */ 100834891872SAlexandre TORGUE stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 100934891872SAlexandre TORGUE if (!stm32port->tx_ch) { 101034891872SAlexandre TORGUE dev_info(dev, "tx dma alloc failed\n"); 101134891872SAlexandre TORGUE return -ENODEV; 101234891872SAlexandre TORGUE } 101334891872SAlexandre TORGUE stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 101434891872SAlexandre TORGUE &stm32port->tx_dma_buf, 101534891872SAlexandre TORGUE GFP_KERNEL); 101634891872SAlexandre TORGUE if (!stm32port->tx_buf) { 101734891872SAlexandre TORGUE ret = -ENOMEM; 101834891872SAlexandre TORGUE goto alloc_err; 101934891872SAlexandre TORGUE } 102034891872SAlexandre TORGUE 102134891872SAlexandre TORGUE /* Configure DMA channel */ 102234891872SAlexandre TORGUE memset(&config, 0, sizeof(config)); 10238e5481d9SArnd Bergmann config.dst_addr = port->mapbase + ofs->tdr; 102434891872SAlexandre TORGUE config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 102534891872SAlexandre TORGUE 102634891872SAlexandre TORGUE ret = dmaengine_slave_config(stm32port->tx_ch, &config); 102734891872SAlexandre TORGUE if (ret < 0) { 102834891872SAlexandre TORGUE dev_err(dev, "tx dma channel config failed\n"); 102934891872SAlexandre TORGUE ret = -ENODEV; 103034891872SAlexandre TORGUE goto config_err; 103134891872SAlexandre TORGUE } 103234891872SAlexandre TORGUE 103334891872SAlexandre TORGUE return 0; 103434891872SAlexandre TORGUE 103534891872SAlexandre TORGUE config_err: 103634891872SAlexandre TORGUE dma_free_coherent(&pdev->dev, 103734891872SAlexandre TORGUE TX_BUF_L, stm32port->tx_buf, 103834891872SAlexandre TORGUE stm32port->tx_dma_buf); 103934891872SAlexandre TORGUE 104034891872SAlexandre TORGUE alloc_err: 104134891872SAlexandre TORGUE dma_release_channel(stm32port->tx_ch); 104234891872SAlexandre TORGUE stm32port->tx_ch = NULL; 104334891872SAlexandre TORGUE 104434891872SAlexandre TORGUE return ret; 104534891872SAlexandre TORGUE } 104634891872SAlexandre TORGUE 104748a6092fSMaxime Coquelin static int stm32_serial_probe(struct platform_device *pdev) 104848a6092fSMaxime Coquelin { 1049ada8618fSAlexandre TORGUE const struct of_device_id *match; 105048a6092fSMaxime Coquelin struct stm32_port *stm32port; 1051ada8618fSAlexandre TORGUE int ret; 105248a6092fSMaxime Coquelin 105348a6092fSMaxime Coquelin stm32port = stm32_of_get_stm32_port(pdev); 105448a6092fSMaxime Coquelin if (!stm32port) 105548a6092fSMaxime Coquelin return -ENODEV; 105648a6092fSMaxime Coquelin 1057ada8618fSAlexandre TORGUE match = of_match_device(stm32_match, &pdev->dev); 1058ada8618fSAlexandre TORGUE if (match && match->data) 1059ada8618fSAlexandre TORGUE stm32port->info = (struct stm32_usart_info *)match->data; 1060ada8618fSAlexandre TORGUE else 1061ada8618fSAlexandre TORGUE return -EINVAL; 1062ada8618fSAlexandre TORGUE 106348a6092fSMaxime Coquelin ret = stm32_init_port(stm32port, pdev); 106448a6092fSMaxime Coquelin if (ret) 106548a6092fSMaxime Coquelin return ret; 106648a6092fSMaxime Coquelin 1067270e5a74SFabrice Gasnier if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) { 1068270e5a74SFabrice Gasnier ret = device_init_wakeup(&pdev->dev, true); 106948a6092fSMaxime Coquelin if (ret) 1070ada80043SFabrice Gasnier goto err_uninit; 1071*5297f274SErwan Le Ray 1072*5297f274SErwan Le Ray ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1073*5297f274SErwan Le Ray stm32port->wakeirq); 1074*5297f274SErwan Le Ray if (ret) 1075*5297f274SErwan Le Ray goto err_nowup; 1076*5297f274SErwan Le Ray 1077*5297f274SErwan Le Ray device_set_wakeup_enable(&pdev->dev, false); 1078270e5a74SFabrice Gasnier } 1079270e5a74SFabrice Gasnier 1080270e5a74SFabrice Gasnier ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1081270e5a74SFabrice Gasnier if (ret) 1082*5297f274SErwan Le Ray goto err_wirq; 108348a6092fSMaxime Coquelin 108434891872SAlexandre TORGUE ret = stm32_of_dma_rx_probe(stm32port, pdev); 108534891872SAlexandre TORGUE if (ret) 108634891872SAlexandre TORGUE dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 108734891872SAlexandre TORGUE 108834891872SAlexandre TORGUE ret = stm32_of_dma_tx_probe(stm32port, pdev); 108934891872SAlexandre TORGUE if (ret) 109034891872SAlexandre TORGUE dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 109134891872SAlexandre TORGUE 109248a6092fSMaxime Coquelin platform_set_drvdata(pdev, &stm32port->port); 109348a6092fSMaxime Coquelin 109448a6092fSMaxime Coquelin return 0; 1095ada80043SFabrice Gasnier 1096*5297f274SErwan Le Ray err_wirq: 1097*5297f274SErwan Le Ray if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) 1098*5297f274SErwan Le Ray dev_pm_clear_wake_irq(&pdev->dev); 1099*5297f274SErwan Le Ray 1100270e5a74SFabrice Gasnier err_nowup: 1101270e5a74SFabrice Gasnier if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) 1102270e5a74SFabrice Gasnier device_init_wakeup(&pdev->dev, false); 1103270e5a74SFabrice Gasnier 1104ada80043SFabrice Gasnier err_uninit: 1105ada80043SFabrice Gasnier clk_disable_unprepare(stm32port->clk); 1106ada80043SFabrice Gasnier 1107ada80043SFabrice Gasnier return ret; 110848a6092fSMaxime Coquelin } 110948a6092fSMaxime Coquelin 111048a6092fSMaxime Coquelin static int stm32_serial_remove(struct platform_device *pdev) 111148a6092fSMaxime Coquelin { 111248a6092fSMaxime Coquelin struct uart_port *port = platform_get_drvdata(pdev); 1113511c7b1bSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 111434891872SAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1115270e5a74SFabrice Gasnier struct stm32_usart_config *cfg = &stm32_port->info->cfg; 111634891872SAlexandre TORGUE 111734891872SAlexandre TORGUE stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 111834891872SAlexandre TORGUE 111934891872SAlexandre TORGUE if (stm32_port->rx_ch) 112034891872SAlexandre TORGUE dma_release_channel(stm32_port->rx_ch); 112134891872SAlexandre TORGUE 112234891872SAlexandre TORGUE if (stm32_port->rx_dma_buf) 112334891872SAlexandre TORGUE dma_free_coherent(&pdev->dev, 112434891872SAlexandre TORGUE RX_BUF_L, stm32_port->rx_buf, 112534891872SAlexandre TORGUE stm32_port->rx_dma_buf); 112634891872SAlexandre TORGUE 112734891872SAlexandre TORGUE stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 112834891872SAlexandre TORGUE 112934891872SAlexandre TORGUE if (stm32_port->tx_ch) 113034891872SAlexandre TORGUE dma_release_channel(stm32_port->tx_ch); 113134891872SAlexandre TORGUE 113234891872SAlexandre TORGUE if (stm32_port->tx_dma_buf) 113334891872SAlexandre TORGUE dma_free_coherent(&pdev->dev, 113434891872SAlexandre TORGUE TX_BUF_L, stm32_port->tx_buf, 113534891872SAlexandre TORGUE stm32_port->tx_dma_buf); 1136511c7b1bSAlexandre TORGUE 1137*5297f274SErwan Le Ray if (cfg->has_wakeup && stm32_port->wakeirq >= 0) { 1138*5297f274SErwan Le Ray dev_pm_clear_wake_irq(&pdev->dev); 1139270e5a74SFabrice Gasnier device_init_wakeup(&pdev->dev, false); 1140*5297f274SErwan Le Ray } 1141270e5a74SFabrice Gasnier 1142511c7b1bSAlexandre TORGUE clk_disable_unprepare(stm32_port->clk); 114348a6092fSMaxime Coquelin 114448a6092fSMaxime Coquelin return uart_remove_one_port(&stm32_usart_driver, port); 114548a6092fSMaxime Coquelin } 114648a6092fSMaxime Coquelin 114748a6092fSMaxime Coquelin 114848a6092fSMaxime Coquelin #ifdef CONFIG_SERIAL_STM32_CONSOLE 114948a6092fSMaxime Coquelin static void stm32_console_putchar(struct uart_port *port, int ch) 115048a6092fSMaxime Coquelin { 1151ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1152ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1153ada8618fSAlexandre TORGUE 1154ada8618fSAlexandre TORGUE while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 115548a6092fSMaxime Coquelin cpu_relax(); 115648a6092fSMaxime Coquelin 1157ada8618fSAlexandre TORGUE writel_relaxed(ch, port->membase + ofs->tdr); 115848a6092fSMaxime Coquelin } 115948a6092fSMaxime Coquelin 116048a6092fSMaxime Coquelin static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 116148a6092fSMaxime Coquelin { 116248a6092fSMaxime Coquelin struct uart_port *port = &stm32_ports[co->index].port; 1163ada8618fSAlexandre TORGUE struct stm32_port *stm32_port = to_stm32_port(port); 1164ada8618fSAlexandre TORGUE struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 116587f1f809SAlexandre TORGUE struct stm32_usart_config *cfg = &stm32_port->info->cfg; 116648a6092fSMaxime Coquelin unsigned long flags; 116748a6092fSMaxime Coquelin u32 old_cr1, new_cr1; 116848a6092fSMaxime Coquelin int locked = 1; 116948a6092fSMaxime Coquelin 117048a6092fSMaxime Coquelin local_irq_save(flags); 117148a6092fSMaxime Coquelin if (port->sysrq) 117248a6092fSMaxime Coquelin locked = 0; 117348a6092fSMaxime Coquelin else if (oops_in_progress) 117448a6092fSMaxime Coquelin locked = spin_trylock(&port->lock); 117548a6092fSMaxime Coquelin else 117648a6092fSMaxime Coquelin spin_lock(&port->lock); 117748a6092fSMaxime Coquelin 117887f1f809SAlexandre TORGUE /* Save and disable interrupts, enable the transmitter */ 1179ada8618fSAlexandre TORGUE old_cr1 = readl_relaxed(port->membase + ofs->cr1); 118048a6092fSMaxime Coquelin new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 118187f1f809SAlexandre TORGUE new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1182ada8618fSAlexandre TORGUE writel_relaxed(new_cr1, port->membase + ofs->cr1); 118348a6092fSMaxime Coquelin 118448a6092fSMaxime Coquelin uart_console_write(port, s, cnt, stm32_console_putchar); 118548a6092fSMaxime Coquelin 118648a6092fSMaxime Coquelin /* Restore interrupt state */ 1187ada8618fSAlexandre TORGUE writel_relaxed(old_cr1, port->membase + ofs->cr1); 118848a6092fSMaxime Coquelin 118948a6092fSMaxime Coquelin if (locked) 119048a6092fSMaxime Coquelin spin_unlock(&port->lock); 119148a6092fSMaxime Coquelin local_irq_restore(flags); 119248a6092fSMaxime Coquelin } 119348a6092fSMaxime Coquelin 119448a6092fSMaxime Coquelin static int stm32_console_setup(struct console *co, char *options) 119548a6092fSMaxime Coquelin { 119648a6092fSMaxime Coquelin struct stm32_port *stm32port; 119748a6092fSMaxime Coquelin int baud = 9600; 119848a6092fSMaxime Coquelin int bits = 8; 119948a6092fSMaxime Coquelin int parity = 'n'; 120048a6092fSMaxime Coquelin int flow = 'n'; 120148a6092fSMaxime Coquelin 120248a6092fSMaxime Coquelin if (co->index >= STM32_MAX_PORTS) 120348a6092fSMaxime Coquelin return -ENODEV; 120448a6092fSMaxime Coquelin 120548a6092fSMaxime Coquelin stm32port = &stm32_ports[co->index]; 120648a6092fSMaxime Coquelin 120748a6092fSMaxime Coquelin /* 120848a6092fSMaxime Coquelin * This driver does not support early console initialization 120948a6092fSMaxime Coquelin * (use ARM early printk support instead), so we only expect 121048a6092fSMaxime Coquelin * this to be called during the uart port registration when the 121148a6092fSMaxime Coquelin * driver gets probed and the port should be mapped at that point. 121248a6092fSMaxime Coquelin */ 121348a6092fSMaxime Coquelin if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 121448a6092fSMaxime Coquelin return -ENXIO; 121548a6092fSMaxime Coquelin 121648a6092fSMaxime Coquelin if (options) 121748a6092fSMaxime Coquelin uart_parse_options(options, &baud, &parity, &bits, &flow); 121848a6092fSMaxime Coquelin 121948a6092fSMaxime Coquelin return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 122048a6092fSMaxime Coquelin } 122148a6092fSMaxime Coquelin 122248a6092fSMaxime Coquelin static struct console stm32_console = { 122348a6092fSMaxime Coquelin .name = STM32_SERIAL_NAME, 122448a6092fSMaxime Coquelin .device = uart_console_device, 122548a6092fSMaxime Coquelin .write = stm32_console_write, 122648a6092fSMaxime Coquelin .setup = stm32_console_setup, 122748a6092fSMaxime Coquelin .flags = CON_PRINTBUFFER, 122848a6092fSMaxime Coquelin .index = -1, 122948a6092fSMaxime Coquelin .data = &stm32_usart_driver, 123048a6092fSMaxime Coquelin }; 123148a6092fSMaxime Coquelin 123248a6092fSMaxime Coquelin #define STM32_SERIAL_CONSOLE (&stm32_console) 123348a6092fSMaxime Coquelin 123448a6092fSMaxime Coquelin #else 123548a6092fSMaxime Coquelin #define STM32_SERIAL_CONSOLE NULL 123648a6092fSMaxime Coquelin #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 123748a6092fSMaxime Coquelin 123848a6092fSMaxime Coquelin static struct uart_driver stm32_usart_driver = { 123948a6092fSMaxime Coquelin .driver_name = DRIVER_NAME, 124048a6092fSMaxime Coquelin .dev_name = STM32_SERIAL_NAME, 124148a6092fSMaxime Coquelin .major = 0, 124248a6092fSMaxime Coquelin .minor = 0, 124348a6092fSMaxime Coquelin .nr = STM32_MAX_PORTS, 124448a6092fSMaxime Coquelin .cons = STM32_SERIAL_CONSOLE, 124548a6092fSMaxime Coquelin }; 124648a6092fSMaxime Coquelin 1247270e5a74SFabrice Gasnier #ifdef CONFIG_PM_SLEEP 1248270e5a74SFabrice Gasnier static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable) 1249270e5a74SFabrice Gasnier { 1250270e5a74SFabrice Gasnier struct stm32_port *stm32_port = to_stm32_port(port); 1251270e5a74SFabrice Gasnier struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1252270e5a74SFabrice Gasnier struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1253270e5a74SFabrice Gasnier u32 val; 1254270e5a74SFabrice Gasnier 1255270e5a74SFabrice Gasnier if (!cfg->has_wakeup || stm32_port->wakeirq < 0) 1256270e5a74SFabrice Gasnier return; 1257270e5a74SFabrice Gasnier 1258270e5a74SFabrice Gasnier if (enable) { 1259270e5a74SFabrice Gasnier stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1260270e5a74SFabrice Gasnier stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1261270e5a74SFabrice Gasnier val = readl_relaxed(port->membase + ofs->cr3); 1262270e5a74SFabrice Gasnier val &= ~USART_CR3_WUS_MASK; 1263270e5a74SFabrice Gasnier /* Enable Wake up interrupt from low power on start bit */ 1264270e5a74SFabrice Gasnier val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1265270e5a74SFabrice Gasnier writel_relaxed(val, port->membase + ofs->cr3); 1266270e5a74SFabrice Gasnier stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1267270e5a74SFabrice Gasnier } else { 1268270e5a74SFabrice Gasnier stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1269270e5a74SFabrice Gasnier } 1270270e5a74SFabrice Gasnier } 1271270e5a74SFabrice Gasnier 1272270e5a74SFabrice Gasnier static int stm32_serial_suspend(struct device *dev) 1273270e5a74SFabrice Gasnier { 1274270e5a74SFabrice Gasnier struct uart_port *port = dev_get_drvdata(dev); 1275270e5a74SFabrice Gasnier 1276270e5a74SFabrice Gasnier uart_suspend_port(&stm32_usart_driver, port); 1277270e5a74SFabrice Gasnier 1278270e5a74SFabrice Gasnier if (device_may_wakeup(dev)) 1279270e5a74SFabrice Gasnier stm32_serial_enable_wakeup(port, true); 1280270e5a74SFabrice Gasnier else 1281270e5a74SFabrice Gasnier stm32_serial_enable_wakeup(port, false); 1282270e5a74SFabrice Gasnier 1283270e5a74SFabrice Gasnier return 0; 1284270e5a74SFabrice Gasnier } 1285270e5a74SFabrice Gasnier 1286270e5a74SFabrice Gasnier static int stm32_serial_resume(struct device *dev) 1287270e5a74SFabrice Gasnier { 1288270e5a74SFabrice Gasnier struct uart_port *port = dev_get_drvdata(dev); 1289270e5a74SFabrice Gasnier 1290270e5a74SFabrice Gasnier if (device_may_wakeup(dev)) 1291270e5a74SFabrice Gasnier stm32_serial_enable_wakeup(port, false); 1292270e5a74SFabrice Gasnier 1293270e5a74SFabrice Gasnier return uart_resume_port(&stm32_usart_driver, port); 1294270e5a74SFabrice Gasnier } 1295270e5a74SFabrice Gasnier #endif /* CONFIG_PM_SLEEP */ 1296270e5a74SFabrice Gasnier 1297270e5a74SFabrice Gasnier static const struct dev_pm_ops stm32_serial_pm_ops = { 1298270e5a74SFabrice Gasnier SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1299270e5a74SFabrice Gasnier }; 1300270e5a74SFabrice Gasnier 130148a6092fSMaxime Coquelin static struct platform_driver stm32_serial_driver = { 130248a6092fSMaxime Coquelin .probe = stm32_serial_probe, 130348a6092fSMaxime Coquelin .remove = stm32_serial_remove, 130448a6092fSMaxime Coquelin .driver = { 130548a6092fSMaxime Coquelin .name = DRIVER_NAME, 1306270e5a74SFabrice Gasnier .pm = &stm32_serial_pm_ops, 130748a6092fSMaxime Coquelin .of_match_table = of_match_ptr(stm32_match), 130848a6092fSMaxime Coquelin }, 130948a6092fSMaxime Coquelin }; 131048a6092fSMaxime Coquelin 131148a6092fSMaxime Coquelin static int __init usart_init(void) 131248a6092fSMaxime Coquelin { 131348a6092fSMaxime Coquelin static char banner[] __initdata = "STM32 USART driver initialized"; 131448a6092fSMaxime Coquelin int ret; 131548a6092fSMaxime Coquelin 131648a6092fSMaxime Coquelin pr_info("%s\n", banner); 131748a6092fSMaxime Coquelin 131848a6092fSMaxime Coquelin ret = uart_register_driver(&stm32_usart_driver); 131948a6092fSMaxime Coquelin if (ret) 132048a6092fSMaxime Coquelin return ret; 132148a6092fSMaxime Coquelin 132248a6092fSMaxime Coquelin ret = platform_driver_register(&stm32_serial_driver); 132348a6092fSMaxime Coquelin if (ret) 132448a6092fSMaxime Coquelin uart_unregister_driver(&stm32_usart_driver); 132548a6092fSMaxime Coquelin 132648a6092fSMaxime Coquelin return ret; 132748a6092fSMaxime Coquelin } 132848a6092fSMaxime Coquelin 132948a6092fSMaxime Coquelin static void __exit usart_exit(void) 133048a6092fSMaxime Coquelin { 133148a6092fSMaxime Coquelin platform_driver_unregister(&stm32_serial_driver); 133248a6092fSMaxime Coquelin uart_unregister_driver(&stm32_usart_driver); 133348a6092fSMaxime Coquelin } 133448a6092fSMaxime Coquelin 133548a6092fSMaxime Coquelin module_init(usart_init); 133648a6092fSMaxime Coquelin module_exit(usart_exit); 133748a6092fSMaxime Coquelin 133848a6092fSMaxime Coquelin MODULE_ALIAS("platform:" DRIVER_NAME); 133948a6092fSMaxime Coquelin MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 134048a6092fSMaxime Coquelin MODULE_LICENSE("GPL v2"); 1341