1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2015 Spreadtrum Communications Inc. 4 */ 5 6 #if defined(CONFIG_SERIAL_SPRD_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 7 #define SUPPORT_SYSRQ 8 #endif 9 10 #include <linux/clk.h> 11 #include <linux/console.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dma/sprd-dma.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/slab.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 28 /* device name */ 29 #define UART_NR_MAX 8 30 #define SPRD_TTY_NAME "ttyS" 31 #define SPRD_FIFO_SIZE 128 32 #define SPRD_DEF_RATE 26000000 33 #define SPRD_BAUD_IO_LIMIT 3000000 34 #define SPRD_TIMEOUT 256000 35 36 /* the offset of serial registers and BITs for them */ 37 /* data registers */ 38 #define SPRD_TXD 0x0000 39 #define SPRD_RXD 0x0004 40 41 /* line status register and its BITs */ 42 #define SPRD_LSR 0x0008 43 #define SPRD_LSR_OE BIT(4) 44 #define SPRD_LSR_FE BIT(3) 45 #define SPRD_LSR_PE BIT(2) 46 #define SPRD_LSR_BI BIT(7) 47 #define SPRD_LSR_TX_OVER BIT(15) 48 49 /* data number in TX and RX fifo */ 50 #define SPRD_STS1 0x000C 51 #define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0) 52 #define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8) 53 54 /* interrupt enable register and its BITs */ 55 #define SPRD_IEN 0x0010 56 #define SPRD_IEN_RX_FULL BIT(0) 57 #define SPRD_IEN_TX_EMPTY BIT(1) 58 #define SPRD_IEN_BREAK_DETECT BIT(7) 59 #define SPRD_IEN_TIMEOUT BIT(13) 60 61 /* interrupt clear register */ 62 #define SPRD_ICLR 0x0014 63 #define SPRD_ICLR_TIMEOUT BIT(13) 64 65 /* line control register */ 66 #define SPRD_LCR 0x0018 67 #define SPRD_LCR_STOP_1BIT 0x10 68 #define SPRD_LCR_STOP_2BIT 0x30 69 #define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3)) 70 #define SPRD_LCR_DATA_LEN5 0x0 71 #define SPRD_LCR_DATA_LEN6 0x4 72 #define SPRD_LCR_DATA_LEN7 0x8 73 #define SPRD_LCR_DATA_LEN8 0xc 74 #define SPRD_LCR_PARITY (BIT(0) | BIT(1)) 75 #define SPRD_LCR_PARITY_EN 0x2 76 #define SPRD_LCR_EVEN_PAR 0x0 77 #define SPRD_LCR_ODD_PAR 0x1 78 79 /* control register 1 */ 80 #define SPRD_CTL1 0x001C 81 #define SPRD_DMA_EN BIT(15) 82 #define SPRD_LOOPBACK_EN BIT(14) 83 #define RX_HW_FLOW_CTL_THLD BIT(6) 84 #define RX_HW_FLOW_CTL_EN BIT(7) 85 #define TX_HW_FLOW_CTL_EN BIT(8) 86 #define RX_TOUT_THLD_DEF 0x3E00 87 #define RX_HFC_THLD_DEF 0x40 88 89 /* fifo threshold register */ 90 #define SPRD_CTL2 0x0020 91 #define THLD_TX_EMPTY 0x40 92 #define THLD_TX_EMPTY_SHIFT 8 93 #define THLD_RX_FULL 0x40 94 #define THLD_RX_FULL_MASK GENMASK(6, 0) 95 96 /* config baud rate register */ 97 #define SPRD_CLKD0 0x0024 98 #define SPRD_CLKD0_MASK GENMASK(15, 0) 99 #define SPRD_CLKD1 0x0028 100 #define SPRD_CLKD1_MASK GENMASK(20, 16) 101 #define SPRD_CLKD1_SHIFT 16 102 103 /* interrupt mask status register */ 104 #define SPRD_IMSR 0x002C 105 #define SPRD_IMSR_RX_FIFO_FULL BIT(0) 106 #define SPRD_IMSR_TX_FIFO_EMPTY BIT(1) 107 #define SPRD_IMSR_BREAK_DETECT BIT(7) 108 #define SPRD_IMSR_TIMEOUT BIT(13) 109 #define SPRD_DEFAULT_SOURCE_CLK 26000000 110 111 #define SPRD_RX_DMA_STEP 1 112 #define SPRD_RX_FIFO_FULL 1 113 #define SPRD_TX_FIFO_FULL 0x20 114 #define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4) 115 116 struct sprd_uart_dma { 117 struct dma_chan *chn; 118 unsigned char *virt; 119 dma_addr_t phys_addr; 120 dma_cookie_t cookie; 121 u32 trans_len; 122 bool enable; 123 }; 124 125 struct sprd_uart_port { 126 struct uart_port port; 127 char name[16]; 128 struct clk *clk; 129 struct sprd_uart_dma tx_dma; 130 struct sprd_uart_dma rx_dma; 131 dma_addr_t pos; 132 unsigned char *rx_buf_tail; 133 }; 134 135 static struct sprd_uart_port *sprd_port[UART_NR_MAX]; 136 static int sprd_ports_num; 137 138 static int sprd_start_dma_rx(struct uart_port *port); 139 static int sprd_tx_dma_config(struct uart_port *port); 140 141 static inline unsigned int serial_in(struct uart_port *port, 142 unsigned int offset) 143 { 144 return readl_relaxed(port->membase + offset); 145 } 146 147 static inline void serial_out(struct uart_port *port, unsigned int offset, 148 int value) 149 { 150 writel_relaxed(value, port->membase + offset); 151 } 152 153 static unsigned int sprd_tx_empty(struct uart_port *port) 154 { 155 if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK) 156 return 0; 157 else 158 return TIOCSER_TEMT; 159 } 160 161 static unsigned int sprd_get_mctrl(struct uart_port *port) 162 { 163 return TIOCM_DSR | TIOCM_CTS; 164 } 165 166 static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl) 167 { 168 u32 val = serial_in(port, SPRD_CTL1); 169 170 if (mctrl & TIOCM_LOOP) 171 val |= SPRD_LOOPBACK_EN; 172 else 173 val &= ~SPRD_LOOPBACK_EN; 174 175 serial_out(port, SPRD_CTL1, val); 176 } 177 178 static void sprd_stop_rx(struct uart_port *port) 179 { 180 struct sprd_uart_port *sp = 181 container_of(port, struct sprd_uart_port, port); 182 unsigned int ien, iclr; 183 184 if (sp->rx_dma.enable) 185 dmaengine_terminate_all(sp->rx_dma.chn); 186 187 iclr = serial_in(port, SPRD_ICLR); 188 ien = serial_in(port, SPRD_IEN); 189 190 ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT); 191 iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT; 192 193 serial_out(port, SPRD_IEN, ien); 194 serial_out(port, SPRD_ICLR, iclr); 195 } 196 197 static void sprd_uart_dma_enable(struct uart_port *port, bool enable) 198 { 199 u32 val = serial_in(port, SPRD_CTL1); 200 201 if (enable) 202 val |= SPRD_DMA_EN; 203 else 204 val &= ~SPRD_DMA_EN; 205 206 serial_out(port, SPRD_CTL1, val); 207 } 208 209 static void sprd_stop_tx_dma(struct uart_port *port) 210 { 211 struct sprd_uart_port *sp = 212 container_of(port, struct sprd_uart_port, port); 213 struct circ_buf *xmit = &port->state->xmit; 214 struct dma_tx_state state; 215 u32 trans_len; 216 217 dmaengine_pause(sp->tx_dma.chn); 218 219 dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state); 220 if (state.residue) { 221 trans_len = state.residue - sp->tx_dma.phys_addr; 222 xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1); 223 port->icount.tx += trans_len; 224 dma_unmap_single(port->dev, sp->tx_dma.phys_addr, 225 sp->tx_dma.trans_len, DMA_TO_DEVICE); 226 } 227 228 dmaengine_terminate_all(sp->tx_dma.chn); 229 sp->tx_dma.trans_len = 0; 230 } 231 232 static int sprd_tx_buf_remap(struct uart_port *port) 233 { 234 struct sprd_uart_port *sp = 235 container_of(port, struct sprd_uart_port, port); 236 struct circ_buf *xmit = &port->state->xmit; 237 238 sp->tx_dma.trans_len = 239 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 240 241 sp->tx_dma.phys_addr = dma_map_single(port->dev, 242 (void *)&(xmit->buf[xmit->tail]), 243 sp->tx_dma.trans_len, 244 DMA_TO_DEVICE); 245 return dma_mapping_error(port->dev, sp->tx_dma.phys_addr); 246 } 247 248 static void sprd_complete_tx_dma(void *data) 249 { 250 struct uart_port *port = (struct uart_port *)data; 251 struct sprd_uart_port *sp = 252 container_of(port, struct sprd_uart_port, port); 253 struct circ_buf *xmit = &port->state->xmit; 254 unsigned long flags; 255 256 spin_lock_irqsave(&port->lock, flags); 257 dma_unmap_single(port->dev, sp->tx_dma.phys_addr, 258 sp->tx_dma.trans_len, DMA_TO_DEVICE); 259 260 xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1); 261 port->icount.tx += sp->tx_dma.trans_len; 262 263 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 264 uart_write_wakeup(port); 265 266 if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) || 267 sprd_tx_dma_config(port)) 268 sp->tx_dma.trans_len = 0; 269 270 spin_unlock_irqrestore(&port->lock, flags); 271 } 272 273 static int sprd_uart_dma_submit(struct uart_port *port, 274 struct sprd_uart_dma *ud, u32 trans_len, 275 enum dma_transfer_direction direction, 276 dma_async_tx_callback callback) 277 { 278 struct dma_async_tx_descriptor *dma_des; 279 unsigned long flags; 280 281 flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE, 282 SPRD_DMA_NO_TRG, 283 SPRD_DMA_FRAG_REQ, 284 SPRD_DMA_TRANS_INT); 285 286 dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len, 287 direction, flags); 288 if (!dma_des) 289 return -ENODEV; 290 291 dma_des->callback = callback; 292 dma_des->callback_param = port; 293 294 ud->cookie = dmaengine_submit(dma_des); 295 if (dma_submit_error(ud->cookie)) 296 return dma_submit_error(ud->cookie); 297 298 dma_async_issue_pending(ud->chn); 299 300 return 0; 301 } 302 303 static int sprd_tx_dma_config(struct uart_port *port) 304 { 305 struct sprd_uart_port *sp = 306 container_of(port, struct sprd_uart_port, port); 307 u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ? 308 SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len; 309 int ret; 310 struct dma_slave_config cfg = { 311 .dst_addr = port->mapbase + SPRD_TXD, 312 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 313 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 314 .src_maxburst = burst, 315 }; 316 317 ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg); 318 if (ret < 0) 319 return ret; 320 321 return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len, 322 DMA_MEM_TO_DEV, sprd_complete_tx_dma); 323 } 324 325 static void sprd_start_tx_dma(struct uart_port *port) 326 { 327 struct sprd_uart_port *sp = 328 container_of(port, struct sprd_uart_port, port); 329 struct circ_buf *xmit = &port->state->xmit; 330 331 if (port->x_char) { 332 serial_out(port, SPRD_TXD, port->x_char); 333 port->icount.tx++; 334 port->x_char = 0; 335 return; 336 } 337 338 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 339 sprd_stop_tx_dma(port); 340 return; 341 } 342 343 if (sp->tx_dma.trans_len) 344 return; 345 346 if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port)) 347 sp->tx_dma.trans_len = 0; 348 } 349 350 static void sprd_rx_full_thld(struct uart_port *port, u32 thld) 351 { 352 u32 val = serial_in(port, SPRD_CTL2); 353 354 val &= ~THLD_RX_FULL_MASK; 355 val |= thld & THLD_RX_FULL_MASK; 356 serial_out(port, SPRD_CTL2, val); 357 } 358 359 static int sprd_rx_alloc_buf(struct sprd_uart_port *sp) 360 { 361 sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE, 362 &sp->rx_dma.phys_addr, GFP_KERNEL); 363 if (!sp->rx_dma.virt) 364 return -ENOMEM; 365 366 return 0; 367 } 368 369 static void sprd_rx_free_buf(struct sprd_uart_port *sp) 370 { 371 if (sp->rx_dma.virt) 372 dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE, 373 sp->rx_dma.virt, sp->rx_dma.phys_addr); 374 375 } 376 377 static int sprd_rx_dma_config(struct uart_port *port, u32 burst) 378 { 379 struct sprd_uart_port *sp = 380 container_of(port, struct sprd_uart_port, port); 381 struct dma_slave_config cfg = { 382 .src_addr = port->mapbase + SPRD_RXD, 383 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 384 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 385 .src_maxburst = burst, 386 }; 387 388 return dmaengine_slave_config(sp->rx_dma.chn, &cfg); 389 } 390 391 static void sprd_uart_dma_rx(struct uart_port *port) 392 { 393 struct sprd_uart_port *sp = 394 container_of(port, struct sprd_uart_port, port); 395 struct tty_port *tty = &port->state->port; 396 397 port->icount.rx += sp->rx_dma.trans_len; 398 tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len); 399 tty_flip_buffer_push(tty); 400 } 401 402 static void sprd_uart_dma_irq(struct uart_port *port) 403 { 404 struct sprd_uart_port *sp = 405 container_of(port, struct sprd_uart_port, port); 406 struct dma_tx_state state; 407 enum dma_status status; 408 409 status = dmaengine_tx_status(sp->rx_dma.chn, 410 sp->rx_dma.cookie, &state); 411 if (status == DMA_ERROR) 412 sprd_stop_rx(port); 413 414 if (!state.residue && sp->pos == sp->rx_dma.phys_addr) 415 return; 416 417 if (!state.residue) { 418 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE + 419 sp->rx_dma.phys_addr - sp->pos; 420 sp->pos = sp->rx_dma.phys_addr; 421 } else { 422 sp->rx_dma.trans_len = state.residue - sp->pos; 423 sp->pos = state.residue; 424 } 425 426 sprd_uart_dma_rx(port); 427 sp->rx_buf_tail += sp->rx_dma.trans_len; 428 } 429 430 static void sprd_complete_rx_dma(void *data) 431 { 432 struct uart_port *port = (struct uart_port *)data; 433 struct sprd_uart_port *sp = 434 container_of(port, struct sprd_uart_port, port); 435 struct dma_tx_state state; 436 enum dma_status status; 437 unsigned long flags; 438 439 spin_lock_irqsave(&port->lock, flags); 440 441 status = dmaengine_tx_status(sp->rx_dma.chn, 442 sp->rx_dma.cookie, &state); 443 if (status != DMA_COMPLETE) { 444 sprd_stop_rx(port); 445 spin_unlock_irqrestore(&port->lock, flags); 446 return; 447 } 448 449 if (sp->pos != sp->rx_dma.phys_addr) { 450 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE + 451 sp->rx_dma.phys_addr - sp->pos; 452 sprd_uart_dma_rx(port); 453 sp->rx_buf_tail += sp->rx_dma.trans_len; 454 } 455 456 if (sprd_start_dma_rx(port)) 457 sprd_stop_rx(port); 458 459 spin_unlock_irqrestore(&port->lock, flags); 460 } 461 462 static int sprd_start_dma_rx(struct uart_port *port) 463 { 464 struct sprd_uart_port *sp = 465 container_of(port, struct sprd_uart_port, port); 466 int ret; 467 468 if (!sp->rx_dma.enable) 469 return 0; 470 471 sp->pos = sp->rx_dma.phys_addr; 472 sp->rx_buf_tail = sp->rx_dma.virt; 473 sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL); 474 ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP); 475 if (ret) 476 return ret; 477 478 return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE, 479 DMA_DEV_TO_MEM, sprd_complete_rx_dma); 480 } 481 482 static void sprd_release_dma(struct uart_port *port) 483 { 484 struct sprd_uart_port *sp = 485 container_of(port, struct sprd_uart_port, port); 486 487 sprd_uart_dma_enable(port, false); 488 489 if (sp->rx_dma.enable) 490 dma_release_channel(sp->rx_dma.chn); 491 492 if (sp->tx_dma.enable) 493 dma_release_channel(sp->tx_dma.chn); 494 495 sp->tx_dma.enable = false; 496 sp->rx_dma.enable = false; 497 } 498 499 static void sprd_request_dma(struct uart_port *port) 500 { 501 struct sprd_uart_port *sp = 502 container_of(port, struct sprd_uart_port, port); 503 504 sp->tx_dma.enable = true; 505 sp->rx_dma.enable = true; 506 507 sp->tx_dma.chn = dma_request_chan(port->dev, "tx"); 508 if (IS_ERR(sp->tx_dma.chn)) { 509 dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n", 510 PTR_ERR(sp->tx_dma.chn)); 511 sp->tx_dma.enable = false; 512 } 513 514 sp->rx_dma.chn = dma_request_chan(port->dev, "rx"); 515 if (IS_ERR(sp->rx_dma.chn)) { 516 dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n", 517 PTR_ERR(sp->rx_dma.chn)); 518 sp->rx_dma.enable = false; 519 } 520 } 521 522 static void sprd_stop_tx(struct uart_port *port) 523 { 524 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port, 525 port); 526 unsigned int ien, iclr; 527 528 if (sp->tx_dma.enable) { 529 sprd_stop_tx_dma(port); 530 return; 531 } 532 533 iclr = serial_in(port, SPRD_ICLR); 534 ien = serial_in(port, SPRD_IEN); 535 536 iclr |= SPRD_IEN_TX_EMPTY; 537 ien &= ~SPRD_IEN_TX_EMPTY; 538 539 serial_out(port, SPRD_IEN, ien); 540 serial_out(port, SPRD_ICLR, iclr); 541 } 542 543 static void sprd_start_tx(struct uart_port *port) 544 { 545 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port, 546 port); 547 unsigned int ien; 548 549 if (sp->tx_dma.enable) { 550 sprd_start_tx_dma(port); 551 return; 552 } 553 554 ien = serial_in(port, SPRD_IEN); 555 if (!(ien & SPRD_IEN_TX_EMPTY)) { 556 ien |= SPRD_IEN_TX_EMPTY; 557 serial_out(port, SPRD_IEN, ien); 558 } 559 } 560 561 /* The Sprd serial does not support this function. */ 562 static void sprd_break_ctl(struct uart_port *port, int break_state) 563 { 564 /* nothing to do */ 565 } 566 567 static int handle_lsr_errors(struct uart_port *port, 568 unsigned int *flag, 569 unsigned int *lsr) 570 { 571 int ret = 0; 572 573 /* statistics */ 574 if (*lsr & SPRD_LSR_BI) { 575 *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE); 576 port->icount.brk++; 577 ret = uart_handle_break(port); 578 if (ret) 579 return ret; 580 } else if (*lsr & SPRD_LSR_PE) 581 port->icount.parity++; 582 else if (*lsr & SPRD_LSR_FE) 583 port->icount.frame++; 584 if (*lsr & SPRD_LSR_OE) 585 port->icount.overrun++; 586 587 /* mask off conditions which should be ignored */ 588 *lsr &= port->read_status_mask; 589 if (*lsr & SPRD_LSR_BI) 590 *flag = TTY_BREAK; 591 else if (*lsr & SPRD_LSR_PE) 592 *flag = TTY_PARITY; 593 else if (*lsr & SPRD_LSR_FE) 594 *flag = TTY_FRAME; 595 596 return ret; 597 } 598 599 static inline void sprd_rx(struct uart_port *port) 600 { 601 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port, 602 port); 603 struct tty_port *tty = &port->state->port; 604 unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT; 605 606 if (sp->rx_dma.enable) { 607 sprd_uart_dma_irq(port); 608 return; 609 } 610 611 while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) && 612 max_count--) { 613 lsr = serial_in(port, SPRD_LSR); 614 ch = serial_in(port, SPRD_RXD); 615 flag = TTY_NORMAL; 616 port->icount.rx++; 617 618 if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE | 619 SPRD_LSR_FE | SPRD_LSR_OE)) 620 if (handle_lsr_errors(port, &flag, &lsr)) 621 continue; 622 if (uart_handle_sysrq_char(port, ch)) 623 continue; 624 625 uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag); 626 } 627 628 tty_flip_buffer_push(tty); 629 } 630 631 static inline void sprd_tx(struct uart_port *port) 632 { 633 struct circ_buf *xmit = &port->state->xmit; 634 int count; 635 636 if (port->x_char) { 637 serial_out(port, SPRD_TXD, port->x_char); 638 port->icount.tx++; 639 port->x_char = 0; 640 return; 641 } 642 643 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 644 sprd_stop_tx(port); 645 return; 646 } 647 648 count = THLD_TX_EMPTY; 649 do { 650 serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]); 651 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 652 port->icount.tx++; 653 if (uart_circ_empty(xmit)) 654 break; 655 } while (--count > 0); 656 657 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 658 uart_write_wakeup(port); 659 660 if (uart_circ_empty(xmit)) 661 sprd_stop_tx(port); 662 } 663 664 /* this handles the interrupt from one port */ 665 static irqreturn_t sprd_handle_irq(int irq, void *dev_id) 666 { 667 struct uart_port *port = dev_id; 668 unsigned int ims; 669 670 spin_lock(&port->lock); 671 672 ims = serial_in(port, SPRD_IMSR); 673 674 if (!ims) { 675 spin_unlock(&port->lock); 676 return IRQ_NONE; 677 } 678 679 if (ims & SPRD_IMSR_TIMEOUT) 680 serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT); 681 682 if (ims & SPRD_IMSR_BREAK_DETECT) 683 serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT); 684 685 if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT | 686 SPRD_IMSR_TIMEOUT)) 687 sprd_rx(port); 688 689 if (ims & SPRD_IMSR_TX_FIFO_EMPTY) 690 sprd_tx(port); 691 692 spin_unlock(&port->lock); 693 694 return IRQ_HANDLED; 695 } 696 697 static void sprd_uart_dma_startup(struct uart_port *port, 698 struct sprd_uart_port *sp) 699 { 700 int ret; 701 702 sprd_request_dma(port); 703 if (!(sp->rx_dma.enable || sp->tx_dma.enable)) 704 return; 705 706 ret = sprd_start_dma_rx(port); 707 if (ret) { 708 sp->rx_dma.enable = false; 709 dma_release_channel(sp->rx_dma.chn); 710 dev_warn(port->dev, "fail to start RX dma mode\n"); 711 } 712 713 sprd_uart_dma_enable(port, true); 714 } 715 716 static int sprd_startup(struct uart_port *port) 717 { 718 int ret = 0; 719 unsigned int ien, fc; 720 unsigned int timeout; 721 struct sprd_uart_port *sp; 722 unsigned long flags; 723 724 serial_out(port, SPRD_CTL2, 725 THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL); 726 727 /* clear rx fifo */ 728 timeout = SPRD_TIMEOUT; 729 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) 730 serial_in(port, SPRD_RXD); 731 732 /* clear tx fifo */ 733 timeout = SPRD_TIMEOUT; 734 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK) 735 cpu_relax(); 736 737 /* clear interrupt */ 738 serial_out(port, SPRD_IEN, 0); 739 serial_out(port, SPRD_ICLR, ~0); 740 741 /* allocate irq */ 742 sp = container_of(port, struct sprd_uart_port, port); 743 snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line); 744 745 sprd_uart_dma_startup(port, sp); 746 747 ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq, 748 IRQF_SHARED, sp->name, port); 749 if (ret) { 750 dev_err(port->dev, "fail to request serial irq %d, ret=%d\n", 751 port->irq, ret); 752 return ret; 753 } 754 fc = serial_in(port, SPRD_CTL1); 755 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF; 756 serial_out(port, SPRD_CTL1, fc); 757 758 /* enable interrupt */ 759 spin_lock_irqsave(&port->lock, flags); 760 ien = serial_in(port, SPRD_IEN); 761 ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT; 762 if (!sp->rx_dma.enable) 763 ien |= SPRD_IEN_RX_FULL; 764 serial_out(port, SPRD_IEN, ien); 765 spin_unlock_irqrestore(&port->lock, flags); 766 767 return 0; 768 } 769 770 static void sprd_shutdown(struct uart_port *port) 771 { 772 sprd_release_dma(port); 773 serial_out(port, SPRD_IEN, 0); 774 serial_out(port, SPRD_ICLR, ~0); 775 devm_free_irq(port->dev, port->irq, port); 776 } 777 778 static void sprd_set_termios(struct uart_port *port, 779 struct ktermios *termios, 780 struct ktermios *old) 781 { 782 unsigned int baud, quot; 783 unsigned int lcr = 0, fc; 784 unsigned long flags; 785 786 /* ask the core to calculate the divisor for us */ 787 baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT); 788 789 quot = port->uartclk / baud; 790 791 /* set data length */ 792 switch (termios->c_cflag & CSIZE) { 793 case CS5: 794 lcr |= SPRD_LCR_DATA_LEN5; 795 break; 796 case CS6: 797 lcr |= SPRD_LCR_DATA_LEN6; 798 break; 799 case CS7: 800 lcr |= SPRD_LCR_DATA_LEN7; 801 break; 802 case CS8: 803 default: 804 lcr |= SPRD_LCR_DATA_LEN8; 805 break; 806 } 807 808 /* calculate stop bits */ 809 lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT); 810 if (termios->c_cflag & CSTOPB) 811 lcr |= SPRD_LCR_STOP_2BIT; 812 else 813 lcr |= SPRD_LCR_STOP_1BIT; 814 815 /* calculate parity */ 816 lcr &= ~SPRD_LCR_PARITY; 817 termios->c_cflag &= ~CMSPAR; /* no support mark/space */ 818 if (termios->c_cflag & PARENB) { 819 lcr |= SPRD_LCR_PARITY_EN; 820 if (termios->c_cflag & PARODD) 821 lcr |= SPRD_LCR_ODD_PAR; 822 else 823 lcr |= SPRD_LCR_EVEN_PAR; 824 } 825 826 spin_lock_irqsave(&port->lock, flags); 827 828 /* update the per-port timeout */ 829 uart_update_timeout(port, termios->c_cflag, baud); 830 831 port->read_status_mask = SPRD_LSR_OE; 832 if (termios->c_iflag & INPCK) 833 port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE; 834 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 835 port->read_status_mask |= SPRD_LSR_BI; 836 837 /* characters to ignore */ 838 port->ignore_status_mask = 0; 839 if (termios->c_iflag & IGNPAR) 840 port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE; 841 if (termios->c_iflag & IGNBRK) { 842 port->ignore_status_mask |= SPRD_LSR_BI; 843 /* 844 * If we're ignoring parity and break indicators, 845 * ignore overruns too (for real raw support). 846 */ 847 if (termios->c_iflag & IGNPAR) 848 port->ignore_status_mask |= SPRD_LSR_OE; 849 } 850 851 /* flow control */ 852 fc = serial_in(port, SPRD_CTL1); 853 fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN); 854 if (termios->c_cflag & CRTSCTS) { 855 fc |= RX_HW_FLOW_CTL_THLD; 856 fc |= RX_HW_FLOW_CTL_EN; 857 fc |= TX_HW_FLOW_CTL_EN; 858 } 859 860 /* clock divider bit0~bit15 */ 861 serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK); 862 863 /* clock divider bit16~bit20 */ 864 serial_out(port, SPRD_CLKD1, 865 (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT); 866 serial_out(port, SPRD_LCR, lcr); 867 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF; 868 serial_out(port, SPRD_CTL1, fc); 869 870 spin_unlock_irqrestore(&port->lock, flags); 871 872 /* Don't rewrite B0 */ 873 if (tty_termios_baud_rate(termios)) 874 tty_termios_encode_baud_rate(termios, baud, baud); 875 } 876 877 static const char *sprd_type(struct uart_port *port) 878 { 879 return "SPX"; 880 } 881 882 static void sprd_release_port(struct uart_port *port) 883 { 884 /* nothing to do */ 885 } 886 887 static int sprd_request_port(struct uart_port *port) 888 { 889 return 0; 890 } 891 892 static void sprd_config_port(struct uart_port *port, int flags) 893 { 894 if (flags & UART_CONFIG_TYPE) 895 port->type = PORT_SPRD; 896 } 897 898 static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser) 899 { 900 if (ser->type != PORT_SPRD) 901 return -EINVAL; 902 if (port->irq != ser->irq) 903 return -EINVAL; 904 if (port->iotype != ser->io_type) 905 return -EINVAL; 906 return 0; 907 } 908 909 static void sprd_pm(struct uart_port *port, unsigned int state, 910 unsigned int oldstate) 911 { 912 struct sprd_uart_port *sup = 913 container_of(port, struct sprd_uart_port, port); 914 915 switch (state) { 916 case UART_PM_STATE_ON: 917 clk_prepare_enable(sup->clk); 918 break; 919 case UART_PM_STATE_OFF: 920 clk_disable_unprepare(sup->clk); 921 break; 922 } 923 } 924 925 #ifdef CONFIG_CONSOLE_POLL 926 static int sprd_poll_init(struct uart_port *port) 927 { 928 if (port->state->pm_state != UART_PM_STATE_ON) { 929 sprd_pm(port, UART_PM_STATE_ON, 0); 930 port->state->pm_state = UART_PM_STATE_ON; 931 } 932 933 return 0; 934 } 935 936 static int sprd_poll_get_char(struct uart_port *port) 937 { 938 while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)) 939 cpu_relax(); 940 941 return serial_in(port, SPRD_RXD); 942 } 943 944 static void sprd_poll_put_char(struct uart_port *port, unsigned char ch) 945 { 946 while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK) 947 cpu_relax(); 948 949 serial_out(port, SPRD_TXD, ch); 950 } 951 #endif 952 953 static const struct uart_ops serial_sprd_ops = { 954 .tx_empty = sprd_tx_empty, 955 .get_mctrl = sprd_get_mctrl, 956 .set_mctrl = sprd_set_mctrl, 957 .stop_tx = sprd_stop_tx, 958 .start_tx = sprd_start_tx, 959 .stop_rx = sprd_stop_rx, 960 .break_ctl = sprd_break_ctl, 961 .startup = sprd_startup, 962 .shutdown = sprd_shutdown, 963 .set_termios = sprd_set_termios, 964 .type = sprd_type, 965 .release_port = sprd_release_port, 966 .request_port = sprd_request_port, 967 .config_port = sprd_config_port, 968 .verify_port = sprd_verify_port, 969 .pm = sprd_pm, 970 #ifdef CONFIG_CONSOLE_POLL 971 .poll_init = sprd_poll_init, 972 .poll_get_char = sprd_poll_get_char, 973 .poll_put_char = sprd_poll_put_char, 974 #endif 975 }; 976 977 #ifdef CONFIG_SERIAL_SPRD_CONSOLE 978 static void wait_for_xmitr(struct uart_port *port) 979 { 980 unsigned int status, tmout = 10000; 981 982 /* wait up to 10ms for the character(s) to be sent */ 983 do { 984 status = serial_in(port, SPRD_STS1); 985 if (--tmout == 0) 986 break; 987 udelay(1); 988 } while (status & SPRD_TX_FIFO_CNT_MASK); 989 } 990 991 static void sprd_console_putchar(struct uart_port *port, int ch) 992 { 993 wait_for_xmitr(port); 994 serial_out(port, SPRD_TXD, ch); 995 } 996 997 static void sprd_console_write(struct console *co, const char *s, 998 unsigned int count) 999 { 1000 struct uart_port *port = &sprd_port[co->index]->port; 1001 int locked = 1; 1002 unsigned long flags; 1003 1004 if (port->sysrq) 1005 locked = 0; 1006 else if (oops_in_progress) 1007 locked = spin_trylock_irqsave(&port->lock, flags); 1008 else 1009 spin_lock_irqsave(&port->lock, flags); 1010 1011 uart_console_write(port, s, count, sprd_console_putchar); 1012 1013 /* wait for transmitter to become empty */ 1014 wait_for_xmitr(port); 1015 1016 if (locked) 1017 spin_unlock_irqrestore(&port->lock, flags); 1018 } 1019 1020 static int __init sprd_console_setup(struct console *co, char *options) 1021 { 1022 struct sprd_uart_port *sprd_uart_port; 1023 int baud = 115200; 1024 int bits = 8; 1025 int parity = 'n'; 1026 int flow = 'n'; 1027 1028 if (co->index >= UART_NR_MAX || co->index < 0) 1029 co->index = 0; 1030 1031 sprd_uart_port = sprd_port[co->index]; 1032 if (!sprd_uart_port || !sprd_uart_port->port.membase) { 1033 pr_info("serial port %d not yet initialized\n", co->index); 1034 return -ENODEV; 1035 } 1036 1037 if (options) 1038 uart_parse_options(options, &baud, &parity, &bits, &flow); 1039 1040 return uart_set_options(&sprd_uart_port->port, co, baud, 1041 parity, bits, flow); 1042 } 1043 1044 static struct uart_driver sprd_uart_driver; 1045 static struct console sprd_console = { 1046 .name = SPRD_TTY_NAME, 1047 .write = sprd_console_write, 1048 .device = uart_console_device, 1049 .setup = sprd_console_setup, 1050 .flags = CON_PRINTBUFFER, 1051 .index = -1, 1052 .data = &sprd_uart_driver, 1053 }; 1054 1055 static int __init sprd_serial_console_init(void) 1056 { 1057 register_console(&sprd_console); 1058 return 0; 1059 } 1060 console_initcall(sprd_serial_console_init); 1061 1062 #define SPRD_CONSOLE (&sprd_console) 1063 1064 /* Support for earlycon */ 1065 static void sprd_putc(struct uart_port *port, int c) 1066 { 1067 unsigned int timeout = SPRD_TIMEOUT; 1068 1069 while (timeout-- && 1070 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER)) 1071 cpu_relax(); 1072 1073 writeb(c, port->membase + SPRD_TXD); 1074 } 1075 1076 static void sprd_early_write(struct console *con, const char *s, unsigned int n) 1077 { 1078 struct earlycon_device *dev = con->data; 1079 1080 uart_console_write(&dev->port, s, n, sprd_putc); 1081 } 1082 1083 static int __init sprd_early_console_setup(struct earlycon_device *device, 1084 const char *opt) 1085 { 1086 if (!device->port.membase) 1087 return -ENODEV; 1088 1089 device->con->write = sprd_early_write; 1090 return 0; 1091 } 1092 OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart", 1093 sprd_early_console_setup); 1094 1095 #else /* !CONFIG_SERIAL_SPRD_CONSOLE */ 1096 #define SPRD_CONSOLE NULL 1097 #endif 1098 1099 static struct uart_driver sprd_uart_driver = { 1100 .owner = THIS_MODULE, 1101 .driver_name = "sprd_serial", 1102 .dev_name = SPRD_TTY_NAME, 1103 .major = 0, 1104 .minor = 0, 1105 .nr = UART_NR_MAX, 1106 .cons = SPRD_CONSOLE, 1107 }; 1108 1109 static int sprd_probe_dt_alias(int index, struct device *dev) 1110 { 1111 struct device_node *np; 1112 int ret = index; 1113 1114 if (!IS_ENABLED(CONFIG_OF)) 1115 return ret; 1116 1117 np = dev->of_node; 1118 if (!np) 1119 return ret; 1120 1121 ret = of_alias_get_id(np, "serial"); 1122 if (ret < 0) 1123 ret = index; 1124 else if (ret >= ARRAY_SIZE(sprd_port) || sprd_port[ret] != NULL) { 1125 dev_warn(dev, "requested serial port %d not available.\n", ret); 1126 ret = index; 1127 } 1128 1129 return ret; 1130 } 1131 1132 static int sprd_remove(struct platform_device *dev) 1133 { 1134 struct sprd_uart_port *sup = platform_get_drvdata(dev); 1135 1136 if (sup) { 1137 uart_remove_one_port(&sprd_uart_driver, &sup->port); 1138 sprd_port[sup->port.line] = NULL; 1139 sprd_ports_num--; 1140 } 1141 1142 if (!sprd_ports_num) 1143 uart_unregister_driver(&sprd_uart_driver); 1144 1145 sprd_rx_free_buf(sup); 1146 1147 return 0; 1148 } 1149 1150 static bool sprd_uart_is_console(struct uart_port *uport) 1151 { 1152 struct console *cons = sprd_uart_driver.cons; 1153 1154 if (cons && cons->index >= 0 && cons->index == uport->line) 1155 return true; 1156 1157 return false; 1158 } 1159 1160 static int sprd_clk_init(struct uart_port *uport) 1161 { 1162 struct clk *clk_uart, *clk_parent; 1163 struct sprd_uart_port *u = sprd_port[uport->line]; 1164 1165 clk_uart = devm_clk_get(uport->dev, "uart"); 1166 if (IS_ERR(clk_uart)) { 1167 dev_warn(uport->dev, "uart%d can't get uart clock\n", 1168 uport->line); 1169 clk_uart = NULL; 1170 } 1171 1172 clk_parent = devm_clk_get(uport->dev, "source"); 1173 if (IS_ERR(clk_parent)) { 1174 dev_warn(uport->dev, "uart%d can't get source clock\n", 1175 uport->line); 1176 clk_parent = NULL; 1177 } 1178 1179 if (!clk_uart || clk_set_parent(clk_uart, clk_parent)) 1180 uport->uartclk = SPRD_DEFAULT_SOURCE_CLK; 1181 else 1182 uport->uartclk = clk_get_rate(clk_uart); 1183 1184 u->clk = devm_clk_get(uport->dev, "enable"); 1185 if (IS_ERR(u->clk)) { 1186 if (PTR_ERR(u->clk) == -EPROBE_DEFER) 1187 return -EPROBE_DEFER; 1188 1189 dev_warn(uport->dev, "uart%d can't get enable clock\n", 1190 uport->line); 1191 1192 /* To keep console alive even if the error occurred */ 1193 if (!sprd_uart_is_console(uport)) 1194 return PTR_ERR(u->clk); 1195 1196 u->clk = NULL; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int sprd_probe(struct platform_device *pdev) 1203 { 1204 struct resource *res; 1205 struct uart_port *up; 1206 int irq; 1207 int index; 1208 int ret; 1209 1210 for (index = 0; index < ARRAY_SIZE(sprd_port); index++) 1211 if (sprd_port[index] == NULL) 1212 break; 1213 1214 if (index == ARRAY_SIZE(sprd_port)) 1215 return -EBUSY; 1216 1217 index = sprd_probe_dt_alias(index, &pdev->dev); 1218 1219 sprd_port[index] = devm_kzalloc(&pdev->dev, sizeof(*sprd_port[index]), 1220 GFP_KERNEL); 1221 if (!sprd_port[index]) 1222 return -ENOMEM; 1223 1224 up = &sprd_port[index]->port; 1225 up->dev = &pdev->dev; 1226 up->line = index; 1227 up->type = PORT_SPRD; 1228 up->iotype = UPIO_MEM; 1229 up->uartclk = SPRD_DEF_RATE; 1230 up->fifosize = SPRD_FIFO_SIZE; 1231 up->ops = &serial_sprd_ops; 1232 up->flags = UPF_BOOT_AUTOCONF; 1233 1234 ret = sprd_clk_init(up); 1235 if (ret) 1236 return ret; 1237 1238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1239 up->membase = devm_ioremap_resource(&pdev->dev, res); 1240 if (IS_ERR(up->membase)) 1241 return PTR_ERR(up->membase); 1242 1243 up->mapbase = res->start; 1244 1245 irq = platform_get_irq(pdev, 0); 1246 if (irq < 0) 1247 return irq; 1248 up->irq = irq; 1249 1250 /* 1251 * Allocate one dma buffer to prepare for receive transfer, in case 1252 * memory allocation failure at runtime. 1253 */ 1254 ret = sprd_rx_alloc_buf(sprd_port[index]); 1255 if (ret) 1256 return ret; 1257 1258 if (!sprd_ports_num) { 1259 ret = uart_register_driver(&sprd_uart_driver); 1260 if (ret < 0) { 1261 pr_err("Failed to register SPRD-UART driver\n"); 1262 return ret; 1263 } 1264 } 1265 sprd_ports_num++; 1266 1267 ret = uart_add_one_port(&sprd_uart_driver, up); 1268 if (ret) { 1269 sprd_port[index] = NULL; 1270 sprd_remove(pdev); 1271 } 1272 1273 platform_set_drvdata(pdev, up); 1274 1275 return ret; 1276 } 1277 1278 #ifdef CONFIG_PM_SLEEP 1279 static int sprd_suspend(struct device *dev) 1280 { 1281 struct sprd_uart_port *sup = dev_get_drvdata(dev); 1282 1283 uart_suspend_port(&sprd_uart_driver, &sup->port); 1284 1285 return 0; 1286 } 1287 1288 static int sprd_resume(struct device *dev) 1289 { 1290 struct sprd_uart_port *sup = dev_get_drvdata(dev); 1291 1292 uart_resume_port(&sprd_uart_driver, &sup->port); 1293 1294 return 0; 1295 } 1296 #endif 1297 1298 static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume); 1299 1300 static const struct of_device_id serial_ids[] = { 1301 {.compatible = "sprd,sc9836-uart",}, 1302 {} 1303 }; 1304 MODULE_DEVICE_TABLE(of, serial_ids); 1305 1306 static struct platform_driver sprd_platform_driver = { 1307 .probe = sprd_probe, 1308 .remove = sprd_remove, 1309 .driver = { 1310 .name = "sprd_serial", 1311 .of_match_table = of_match_ptr(serial_ids), 1312 .pm = &sprd_pm_ops, 1313 }, 1314 }; 1315 1316 module_platform_driver(sprd_platform_driver); 1317 1318 MODULE_LICENSE("GPL v2"); 1319 MODULE_DESCRIPTION("Spreadtrum SoC serial driver series"); 1320