1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/module.h> 35 #include <linux/mm.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 }; 161 162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164 static struct sci_port sci_ports[SCI_NPORTS]; 165 static unsigned long sci_ports_in_use; 166 static struct uart_driver sci_uart_driver; 167 168 static inline struct sci_port * 169 to_sci_port(struct uart_port *uart) 170 { 171 return container_of(uart, struct sci_port, port); 172 } 173 174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * Common SH-3 SCIF definitions. 322 */ 323 [SCIx_SH3_SCIF_REGTYPE] = { 324 .regs = { 325 [SCSMR] = { 0x00, 8 }, 326 [SCBRR] = { 0x02, 8 }, 327 [SCSCR] = { 0x04, 8 }, 328 [SCxTDR] = { 0x06, 8 }, 329 [SCxSR] = { 0x08, 16 }, 330 [SCxRDR] = { 0x0a, 8 }, 331 [SCFCR] = { 0x0c, 8 }, 332 [SCFDR] = { 0x0e, 16 }, 333 }, 334 .fifosize = 16, 335 .overrun_reg = SCLSR, 336 .overrun_mask = SCLSR_ORER, 337 .sampling_rate_mask = SCI_SR(32), 338 .error_mask = SCIF_DEFAULT_ERROR_MASK, 339 .error_clear = SCIF_ERROR_CLEAR, 340 }, 341 342 /* 343 * Common SH-4(A) SCIF(B) definitions. 344 */ 345 [SCIx_SH4_SCIF_REGTYPE] = { 346 .regs = { 347 [SCSMR] = { 0x00, 16 }, 348 [SCBRR] = { 0x04, 8 }, 349 [SCSCR] = { 0x08, 16 }, 350 [SCxTDR] = { 0x0c, 8 }, 351 [SCxSR] = { 0x10, 16 }, 352 [SCxRDR] = { 0x14, 8 }, 353 [SCFCR] = { 0x18, 16 }, 354 [SCFDR] = { 0x1c, 16 }, 355 [SCSPTR] = { 0x20, 16 }, 356 [SCLSR] = { 0x24, 16 }, 357 }, 358 .fifosize = 16, 359 .overrun_reg = SCLSR, 360 .overrun_mask = SCLSR_ORER, 361 .sampling_rate_mask = SCI_SR(32), 362 .error_mask = SCIF_DEFAULT_ERROR_MASK, 363 .error_clear = SCIF_ERROR_CLEAR, 364 }, 365 366 /* 367 * Common SCIF definitions for ports with a Baud Rate Generator for 368 * External Clock (BRG). 369 */ 370 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 371 .regs = { 372 [SCSMR] = { 0x00, 16 }, 373 [SCBRR] = { 0x04, 8 }, 374 [SCSCR] = { 0x08, 16 }, 375 [SCxTDR] = { 0x0c, 8 }, 376 [SCxSR] = { 0x10, 16 }, 377 [SCxRDR] = { 0x14, 8 }, 378 [SCFCR] = { 0x18, 16 }, 379 [SCFDR] = { 0x1c, 16 }, 380 [SCSPTR] = { 0x20, 16 }, 381 [SCLSR] = { 0x24, 16 }, 382 [SCDL] = { 0x30, 16 }, 383 [SCCKS] = { 0x34, 16 }, 384 }, 385 .fifosize = 16, 386 .overrun_reg = SCLSR, 387 .overrun_mask = SCLSR_ORER, 388 .sampling_rate_mask = SCI_SR(32), 389 .error_mask = SCIF_DEFAULT_ERROR_MASK, 390 .error_clear = SCIF_ERROR_CLEAR, 391 }, 392 393 /* 394 * Common HSCIF definitions. 395 */ 396 [SCIx_HSCIF_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCSPTR] = { 0x20, 16 }, 407 [SCLSR] = { 0x24, 16 }, 408 [HSSRR] = { 0x40, 16 }, 409 [SCDL] = { 0x30, 16 }, 410 [SCCKS] = { 0x34, 16 }, 411 [HSRTRGR] = { 0x54, 16 }, 412 [HSTTRGR] = { 0x58, 16 }, 413 }, 414 .fifosize = 128, 415 .overrun_reg = SCLSR, 416 .overrun_mask = SCLSR_ORER, 417 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 418 .error_mask = SCIF_DEFAULT_ERROR_MASK, 419 .error_clear = SCIF_ERROR_CLEAR, 420 }, 421 422 /* 423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 424 * register. 425 */ 426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 427 .regs = { 428 [SCSMR] = { 0x00, 16 }, 429 [SCBRR] = { 0x04, 8 }, 430 [SCSCR] = { 0x08, 16 }, 431 [SCxTDR] = { 0x0c, 8 }, 432 [SCxSR] = { 0x10, 16 }, 433 [SCxRDR] = { 0x14, 8 }, 434 [SCFCR] = { 0x18, 16 }, 435 [SCFDR] = { 0x1c, 16 }, 436 [SCLSR] = { 0x24, 16 }, 437 }, 438 .fifosize = 16, 439 .overrun_reg = SCLSR, 440 .overrun_mask = SCLSR_ORER, 441 .sampling_rate_mask = SCI_SR(32), 442 .error_mask = SCIF_DEFAULT_ERROR_MASK, 443 .error_clear = SCIF_ERROR_CLEAR, 444 }, 445 446 /* 447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 448 * count registers. 449 */ 450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 451 .regs = { 452 [SCSMR] = { 0x00, 16 }, 453 [SCBRR] = { 0x04, 8 }, 454 [SCSCR] = { 0x08, 16 }, 455 [SCxTDR] = { 0x0c, 8 }, 456 [SCxSR] = { 0x10, 16 }, 457 [SCxRDR] = { 0x14, 8 }, 458 [SCFCR] = { 0x18, 16 }, 459 [SCFDR] = { 0x1c, 16 }, 460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 461 [SCRFDR] = { 0x20, 16 }, 462 [SCSPTR] = { 0x24, 16 }, 463 [SCLSR] = { 0x28, 16 }, 464 }, 465 .fifosize = 16, 466 .overrun_reg = SCLSR, 467 .overrun_mask = SCLSR_ORER, 468 .sampling_rate_mask = SCI_SR(32), 469 .error_mask = SCIF_DEFAULT_ERROR_MASK, 470 .error_clear = SCIF_ERROR_CLEAR, 471 }, 472 473 /* 474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 475 * registers. 476 */ 477 [SCIx_SH7705_SCIF_REGTYPE] = { 478 .regs = { 479 [SCSMR] = { 0x00, 16 }, 480 [SCBRR] = { 0x04, 8 }, 481 [SCSCR] = { 0x08, 16 }, 482 [SCxTDR] = { 0x20, 8 }, 483 [SCxSR] = { 0x14, 16 }, 484 [SCxRDR] = { 0x24, 8 }, 485 [SCFCR] = { 0x18, 16 }, 486 [SCFDR] = { 0x1c, 16 }, 487 }, 488 .fifosize = 64, 489 .overrun_reg = SCxSR, 490 .overrun_mask = SCIFA_ORER, 491 .sampling_rate_mask = SCI_SR(16), 492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 494 }, 495 }; 496 497 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 498 499 /* 500 * The "offset" here is rather misleading, in that it refers to an enum 501 * value relative to the port mapping rather than the fixed offset 502 * itself, which needs to be manually retrieved from the platform's 503 * register map for the given port. 504 */ 505 static unsigned int sci_serial_in(struct uart_port *p, int offset) 506 { 507 const struct plat_sci_reg *reg = sci_getreg(p, offset); 508 509 if (reg->size == 8) 510 return ioread8(p->membase + (reg->offset << p->regshift)); 511 else if (reg->size == 16) 512 return ioread16(p->membase + (reg->offset << p->regshift)); 513 else 514 WARN(1, "Invalid register access\n"); 515 516 return 0; 517 } 518 519 static void sci_serial_out(struct uart_port *p, int offset, int value) 520 { 521 const struct plat_sci_reg *reg = sci_getreg(p, offset); 522 523 if (reg->size == 8) 524 iowrite8(value, p->membase + (reg->offset << p->regshift)); 525 else if (reg->size == 16) 526 iowrite16(value, p->membase + (reg->offset << p->regshift)); 527 else 528 WARN(1, "Invalid register access\n"); 529 } 530 531 static void sci_port_enable(struct sci_port *sci_port) 532 { 533 unsigned int i; 534 535 if (!sci_port->port.dev) 536 return; 537 538 pm_runtime_get_sync(sci_port->port.dev); 539 540 for (i = 0; i < SCI_NUM_CLKS; i++) { 541 clk_prepare_enable(sci_port->clks[i]); 542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 543 } 544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 545 } 546 547 static void sci_port_disable(struct sci_port *sci_port) 548 { 549 unsigned int i; 550 551 if (!sci_port->port.dev) 552 return; 553 554 for (i = SCI_NUM_CLKS; i-- > 0; ) 555 clk_disable_unprepare(sci_port->clks[i]); 556 557 pm_runtime_put_sync(sci_port->port.dev); 558 } 559 560 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 561 { 562 /* 563 * Not all ports (such as SCIFA) will support REIE. Rather than 564 * special-casing the port type, we check the port initialization 565 * IRQ enable mask to see whether the IRQ is desired at all. If 566 * it's unset, it's logically inferred that there's no point in 567 * testing for it. 568 */ 569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 570 } 571 572 static void sci_start_tx(struct uart_port *port) 573 { 574 struct sci_port *s = to_sci_port(port); 575 unsigned short ctrl; 576 577 #ifdef CONFIG_SERIAL_SH_SCI_DMA 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 579 u16 new, scr = serial_port_in(port, SCSCR); 580 if (s->chan_tx) 581 new = scr | SCSCR_TDRQE; 582 else 583 new = scr & ~SCSCR_TDRQE; 584 if (new != scr) 585 serial_port_out(port, SCSCR, new); 586 } 587 588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 589 dma_submit_error(s->cookie_tx)) { 590 s->cookie_tx = 0; 591 schedule_work(&s->work_tx); 592 } 593 #endif 594 595 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 596 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 597 ctrl = serial_port_in(port, SCSCR); 598 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 599 } 600 } 601 602 static void sci_stop_tx(struct uart_port *port) 603 { 604 unsigned short ctrl; 605 606 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 607 ctrl = serial_port_in(port, SCSCR); 608 609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 610 ctrl &= ~SCSCR_TDRQE; 611 612 ctrl &= ~SCSCR_TIE; 613 614 serial_port_out(port, SCSCR, ctrl); 615 616 #ifdef CONFIG_SERIAL_SH_SCI_DMA 617 if (to_sci_port(port)->chan_tx && 618 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 619 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 620 to_sci_port(port)->cookie_tx = -EINVAL; 621 } 622 #endif 623 } 624 625 static void sci_start_rx(struct uart_port *port) 626 { 627 unsigned short ctrl; 628 629 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 630 631 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 632 ctrl &= ~SCSCR_RDRQE; 633 634 serial_port_out(port, SCSCR, ctrl); 635 } 636 637 static void sci_stop_rx(struct uart_port *port) 638 { 639 unsigned short ctrl; 640 641 ctrl = serial_port_in(port, SCSCR); 642 643 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 644 ctrl &= ~SCSCR_RDRQE; 645 646 ctrl &= ~port_rx_irq_mask(port); 647 648 serial_port_out(port, SCSCR, ctrl); 649 } 650 651 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 652 { 653 if (port->type == PORT_SCI) { 654 /* Just store the mask */ 655 serial_port_out(port, SCxSR, mask); 656 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 657 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 658 /* Only clear the status bits we want to clear */ 659 serial_port_out(port, SCxSR, 660 serial_port_in(port, SCxSR) & mask); 661 } else { 662 /* Store the mask, clear parity/framing errors */ 663 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 664 } 665 } 666 667 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 668 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 669 670 #ifdef CONFIG_CONSOLE_POLL 671 static int sci_poll_get_char(struct uart_port *port) 672 { 673 unsigned short status; 674 int c; 675 676 do { 677 status = serial_port_in(port, SCxSR); 678 if (status & SCxSR_ERRORS(port)) { 679 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 680 continue; 681 } 682 break; 683 } while (1); 684 685 if (!(status & SCxSR_RDxF(port))) 686 return NO_POLL_CHAR; 687 688 c = serial_port_in(port, SCxRDR); 689 690 /* Dummy read */ 691 serial_port_in(port, SCxSR); 692 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 693 694 return c; 695 } 696 #endif 697 698 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 699 { 700 unsigned short status; 701 702 do { 703 status = serial_port_in(port, SCxSR); 704 } while (!(status & SCxSR_TDxE(port))); 705 706 serial_port_out(port, SCxTDR, c); 707 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 708 } 709 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 710 CONFIG_SERIAL_SH_SCI_EARLYCON */ 711 712 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 713 { 714 struct sci_port *s = to_sci_port(port); 715 716 /* 717 * Use port-specific handler if provided. 718 */ 719 if (s->cfg->ops && s->cfg->ops->init_pins) { 720 s->cfg->ops->init_pins(port, cflag); 721 return; 722 } 723 724 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 725 u16 data = serial_port_in(port, SCPDR); 726 u16 ctrl = serial_port_in(port, SCPCR); 727 728 /* Enable RXD and TXD pin functions */ 729 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 730 if (to_sci_port(port)->has_rtscts) { 731 /* RTS# is output, active low, unless autorts */ 732 if (!(port->mctrl & TIOCM_RTS)) { 733 ctrl |= SCPCR_RTSC; 734 data |= SCPDR_RTSD; 735 } else if (!s->autorts) { 736 ctrl |= SCPCR_RTSC; 737 data &= ~SCPDR_RTSD; 738 } else { 739 /* Enable RTS# pin function */ 740 ctrl &= ~SCPCR_RTSC; 741 } 742 /* Enable CTS# pin function */ 743 ctrl &= ~SCPCR_CTSC; 744 } 745 serial_port_out(port, SCPDR, data); 746 serial_port_out(port, SCPCR, ctrl); 747 } else if (sci_getreg(port, SCSPTR)->size) { 748 u16 status = serial_port_in(port, SCSPTR); 749 750 /* RTS# is always output; and active low, unless autorts */ 751 status |= SCSPTR_RTSIO; 752 if (!(port->mctrl & TIOCM_RTS)) 753 status |= SCSPTR_RTSDT; 754 else if (!s->autorts) 755 status &= ~SCSPTR_RTSDT; 756 /* CTS# and SCK are inputs */ 757 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 758 serial_port_out(port, SCSPTR, status); 759 } 760 } 761 762 static int sci_txfill(struct uart_port *port) 763 { 764 struct sci_port *s = to_sci_port(port); 765 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 766 const struct plat_sci_reg *reg; 767 768 reg = sci_getreg(port, SCTFDR); 769 if (reg->size) 770 return serial_port_in(port, SCTFDR) & fifo_mask; 771 772 reg = sci_getreg(port, SCFDR); 773 if (reg->size) 774 return serial_port_in(port, SCFDR) >> 8; 775 776 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 777 } 778 779 static int sci_txroom(struct uart_port *port) 780 { 781 return port->fifosize - sci_txfill(port); 782 } 783 784 static int sci_rxfill(struct uart_port *port) 785 { 786 struct sci_port *s = to_sci_port(port); 787 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 788 const struct plat_sci_reg *reg; 789 790 reg = sci_getreg(port, SCRFDR); 791 if (reg->size) 792 return serial_port_in(port, SCRFDR) & fifo_mask; 793 794 reg = sci_getreg(port, SCFDR); 795 if (reg->size) 796 return serial_port_in(port, SCFDR) & fifo_mask; 797 798 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 799 } 800 801 /* ********************************************************************** * 802 * the interrupt related routines * 803 * ********************************************************************** */ 804 805 static void sci_transmit_chars(struct uart_port *port) 806 { 807 struct circ_buf *xmit = &port->state->xmit; 808 unsigned int stopped = uart_tx_stopped(port); 809 unsigned short status; 810 unsigned short ctrl; 811 int count; 812 813 status = serial_port_in(port, SCxSR); 814 if (!(status & SCxSR_TDxE(port))) { 815 ctrl = serial_port_in(port, SCSCR); 816 if (uart_circ_empty(xmit)) 817 ctrl &= ~SCSCR_TIE; 818 else 819 ctrl |= SCSCR_TIE; 820 serial_port_out(port, SCSCR, ctrl); 821 return; 822 } 823 824 count = sci_txroom(port); 825 826 do { 827 unsigned char c; 828 829 if (port->x_char) { 830 c = port->x_char; 831 port->x_char = 0; 832 } else if (!uart_circ_empty(xmit) && !stopped) { 833 c = xmit->buf[xmit->tail]; 834 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 835 } else { 836 break; 837 } 838 839 serial_port_out(port, SCxTDR, c); 840 841 port->icount.tx++; 842 } while (--count > 0); 843 844 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 845 846 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 847 uart_write_wakeup(port); 848 if (uart_circ_empty(xmit)) 849 sci_stop_tx(port); 850 851 } 852 853 static void sci_receive_chars(struct uart_port *port) 854 { 855 struct tty_port *tport = &port->state->port; 856 int i, count, copied = 0; 857 unsigned short status; 858 unsigned char flag; 859 860 status = serial_port_in(port, SCxSR); 861 if (!(status & SCxSR_RDxF(port))) 862 return; 863 864 while (1) { 865 /* Don't copy more bytes than there is room for in the buffer */ 866 count = tty_buffer_request_room(tport, sci_rxfill(port)); 867 868 /* If for any reason we can't copy more data, we're done! */ 869 if (count == 0) 870 break; 871 872 if (port->type == PORT_SCI) { 873 char c = serial_port_in(port, SCxRDR); 874 if (uart_handle_sysrq_char(port, c)) 875 count = 0; 876 else 877 tty_insert_flip_char(tport, c, TTY_NORMAL); 878 } else { 879 for (i = 0; i < count; i++) { 880 char c; 881 882 if (port->type == PORT_SCIF || 883 port->type == PORT_HSCIF) { 884 status = serial_port_in(port, SCxSR); 885 c = serial_port_in(port, SCxRDR); 886 } else { 887 c = serial_port_in(port, SCxRDR); 888 status = serial_port_in(port, SCxSR); 889 } 890 if (uart_handle_sysrq_char(port, c)) { 891 count--; i--; 892 continue; 893 } 894 895 /* Store data and status */ 896 if (status & SCxSR_FER(port)) { 897 flag = TTY_FRAME; 898 port->icount.frame++; 899 dev_notice(port->dev, "frame error\n"); 900 } else if (status & SCxSR_PER(port)) { 901 flag = TTY_PARITY; 902 port->icount.parity++; 903 dev_notice(port->dev, "parity error\n"); 904 } else 905 flag = TTY_NORMAL; 906 907 tty_insert_flip_char(tport, c, flag); 908 } 909 } 910 911 serial_port_in(port, SCxSR); /* dummy read */ 912 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 913 914 copied += count; 915 port->icount.rx += count; 916 } 917 918 if (copied) { 919 /* Tell the rest of the system the news. New characters! */ 920 tty_flip_buffer_push(tport); 921 } else { 922 /* TTY buffers full; read from RX reg to prevent lockup */ 923 serial_port_in(port, SCxRDR); 924 serial_port_in(port, SCxSR); /* dummy read */ 925 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 926 } 927 } 928 929 static int sci_handle_errors(struct uart_port *port) 930 { 931 int copied = 0; 932 unsigned short status = serial_port_in(port, SCxSR); 933 struct tty_port *tport = &port->state->port; 934 struct sci_port *s = to_sci_port(port); 935 936 /* Handle overruns */ 937 if (status & s->params->overrun_mask) { 938 port->icount.overrun++; 939 940 /* overrun error */ 941 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 942 copied++; 943 944 dev_notice(port->dev, "overrun error\n"); 945 } 946 947 if (status & SCxSR_FER(port)) { 948 /* frame error */ 949 port->icount.frame++; 950 951 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 952 copied++; 953 954 dev_notice(port->dev, "frame error\n"); 955 } 956 957 if (status & SCxSR_PER(port)) { 958 /* parity error */ 959 port->icount.parity++; 960 961 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 962 copied++; 963 964 dev_notice(port->dev, "parity error\n"); 965 } 966 967 if (copied) 968 tty_flip_buffer_push(tport); 969 970 return copied; 971 } 972 973 static int sci_handle_fifo_overrun(struct uart_port *port) 974 { 975 struct tty_port *tport = &port->state->port; 976 struct sci_port *s = to_sci_port(port); 977 const struct plat_sci_reg *reg; 978 int copied = 0; 979 u16 status; 980 981 reg = sci_getreg(port, s->params->overrun_reg); 982 if (!reg->size) 983 return 0; 984 985 status = serial_port_in(port, s->params->overrun_reg); 986 if (status & s->params->overrun_mask) { 987 status &= ~s->params->overrun_mask; 988 serial_port_out(port, s->params->overrun_reg, status); 989 990 port->icount.overrun++; 991 992 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 993 tty_flip_buffer_push(tport); 994 995 dev_dbg(port->dev, "overrun error\n"); 996 copied++; 997 } 998 999 return copied; 1000 } 1001 1002 static int sci_handle_breaks(struct uart_port *port) 1003 { 1004 int copied = 0; 1005 unsigned short status = serial_port_in(port, SCxSR); 1006 struct tty_port *tport = &port->state->port; 1007 1008 if (uart_handle_break(port)) 1009 return 0; 1010 1011 if (status & SCxSR_BRK(port)) { 1012 port->icount.brk++; 1013 1014 /* Notify of BREAK */ 1015 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1016 copied++; 1017 1018 dev_dbg(port->dev, "BREAK detected\n"); 1019 } 1020 1021 if (copied) 1022 tty_flip_buffer_push(tport); 1023 1024 copied += sci_handle_fifo_overrun(port); 1025 1026 return copied; 1027 } 1028 1029 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1030 { 1031 unsigned int bits; 1032 1033 if (rx_trig >= port->fifosize) 1034 rx_trig = port->fifosize - 1; 1035 if (rx_trig < 1) 1036 rx_trig = 1; 1037 1038 /* HSCIF can be set to an arbitrary level. */ 1039 if (sci_getreg(port, HSRTRGR)->size) { 1040 serial_port_out(port, HSRTRGR, rx_trig); 1041 return rx_trig; 1042 } 1043 1044 switch (port->type) { 1045 case PORT_SCIF: 1046 if (rx_trig < 4) { 1047 bits = 0; 1048 rx_trig = 1; 1049 } else if (rx_trig < 8) { 1050 bits = SCFCR_RTRG0; 1051 rx_trig = 4; 1052 } else if (rx_trig < 14) { 1053 bits = SCFCR_RTRG1; 1054 rx_trig = 8; 1055 } else { 1056 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1057 rx_trig = 14; 1058 } 1059 break; 1060 case PORT_SCIFA: 1061 case PORT_SCIFB: 1062 if (rx_trig < 16) { 1063 bits = 0; 1064 rx_trig = 1; 1065 } else if (rx_trig < 32) { 1066 bits = SCFCR_RTRG0; 1067 rx_trig = 16; 1068 } else if (rx_trig < 48) { 1069 bits = SCFCR_RTRG1; 1070 rx_trig = 32; 1071 } else { 1072 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1073 rx_trig = 48; 1074 } 1075 break; 1076 default: 1077 WARN(1, "unknown FIFO configuration"); 1078 return 1; 1079 } 1080 1081 serial_port_out(port, SCFCR, 1082 (serial_port_in(port, SCFCR) & 1083 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1084 1085 return rx_trig; 1086 } 1087 1088 static int scif_rtrg_enabled(struct uart_port *port) 1089 { 1090 if (sci_getreg(port, HSRTRGR)->size) 1091 return serial_port_in(port, HSRTRGR) != 0; 1092 else 1093 return (serial_port_in(port, SCFCR) & 1094 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1095 } 1096 1097 static void rx_fifo_timer_fn(struct timer_list *t) 1098 { 1099 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1100 struct uart_port *port = &s->port; 1101 1102 dev_dbg(port->dev, "Rx timed out\n"); 1103 scif_set_rtrg(port, 1); 1104 } 1105 1106 static ssize_t rx_fifo_trigger_show(struct device *dev, 1107 struct device_attribute *attr, char *buf) 1108 { 1109 struct uart_port *port = dev_get_drvdata(dev); 1110 struct sci_port *sci = to_sci_port(port); 1111 1112 return sprintf(buf, "%d\n", sci->rx_trigger); 1113 } 1114 1115 static ssize_t rx_fifo_trigger_store(struct device *dev, 1116 struct device_attribute *attr, 1117 const char *buf, size_t count) 1118 { 1119 struct uart_port *port = dev_get_drvdata(dev); 1120 struct sci_port *sci = to_sci_port(port); 1121 int ret; 1122 long r; 1123 1124 ret = kstrtol(buf, 0, &r); 1125 if (ret) 1126 return ret; 1127 1128 sci->rx_trigger = scif_set_rtrg(port, r); 1129 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1130 scif_set_rtrg(port, 1); 1131 1132 return count; 1133 } 1134 1135 static DEVICE_ATTR_RW(rx_fifo_trigger); 1136 1137 static ssize_t rx_fifo_timeout_show(struct device *dev, 1138 struct device_attribute *attr, 1139 char *buf) 1140 { 1141 struct uart_port *port = dev_get_drvdata(dev); 1142 struct sci_port *sci = to_sci_port(port); 1143 int v; 1144 1145 if (port->type == PORT_HSCIF) 1146 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1147 else 1148 v = sci->rx_fifo_timeout; 1149 1150 return sprintf(buf, "%d\n", v); 1151 } 1152 1153 static ssize_t rx_fifo_timeout_store(struct device *dev, 1154 struct device_attribute *attr, 1155 const char *buf, 1156 size_t count) 1157 { 1158 struct uart_port *port = dev_get_drvdata(dev); 1159 struct sci_port *sci = to_sci_port(port); 1160 int ret; 1161 long r; 1162 1163 ret = kstrtol(buf, 0, &r); 1164 if (ret) 1165 return ret; 1166 1167 if (port->type == PORT_HSCIF) { 1168 if (r < 0 || r > 3) 1169 return -EINVAL; 1170 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1171 } else { 1172 sci->rx_fifo_timeout = r; 1173 scif_set_rtrg(port, 1); 1174 if (r > 0) 1175 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1176 } 1177 1178 return count; 1179 } 1180 1181 static DEVICE_ATTR_RW(rx_fifo_timeout); 1182 1183 1184 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1185 static void sci_dma_tx_complete(void *arg) 1186 { 1187 struct sci_port *s = arg; 1188 struct uart_port *port = &s->port; 1189 struct circ_buf *xmit = &port->state->xmit; 1190 unsigned long flags; 1191 1192 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1193 1194 spin_lock_irqsave(&port->lock, flags); 1195 1196 xmit->tail += s->tx_dma_len; 1197 xmit->tail &= UART_XMIT_SIZE - 1; 1198 1199 port->icount.tx += s->tx_dma_len; 1200 1201 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1202 uart_write_wakeup(port); 1203 1204 if (!uart_circ_empty(xmit)) { 1205 s->cookie_tx = 0; 1206 schedule_work(&s->work_tx); 1207 } else { 1208 s->cookie_tx = -EINVAL; 1209 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1210 u16 ctrl = serial_port_in(port, SCSCR); 1211 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1212 } 1213 } 1214 1215 spin_unlock_irqrestore(&port->lock, flags); 1216 } 1217 1218 /* Locking: called with port lock held */ 1219 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1220 { 1221 struct uart_port *port = &s->port; 1222 struct tty_port *tport = &port->state->port; 1223 int copied; 1224 1225 copied = tty_insert_flip_string(tport, buf, count); 1226 if (copied < count) 1227 port->icount.buf_overrun++; 1228 1229 port->icount.rx += copied; 1230 1231 return copied; 1232 } 1233 1234 static int sci_dma_rx_find_active(struct sci_port *s) 1235 { 1236 unsigned int i; 1237 1238 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1239 if (s->active_rx == s->cookie_rx[i]) 1240 return i; 1241 1242 return -1; 1243 } 1244 1245 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1246 { 1247 unsigned int i; 1248 1249 s->chan_rx = NULL; 1250 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1251 s->cookie_rx[i] = -EINVAL; 1252 s->active_rx = 0; 1253 } 1254 1255 static void sci_dma_rx_release(struct sci_port *s) 1256 { 1257 struct dma_chan *chan = s->chan_rx_saved; 1258 1259 s->chan_rx_saved = NULL; 1260 sci_dma_rx_chan_invalidate(s); 1261 dmaengine_terminate_sync(chan); 1262 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1263 sg_dma_address(&s->sg_rx[0])); 1264 dma_release_channel(chan); 1265 } 1266 1267 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1268 { 1269 long sec = usec / 1000000; 1270 long nsec = (usec % 1000000) * 1000; 1271 ktime_t t = ktime_set(sec, nsec); 1272 1273 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1274 } 1275 1276 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1277 { 1278 struct uart_port *port = &s->port; 1279 u16 scr; 1280 1281 /* Direct new serial port interrupts back to CPU */ 1282 scr = serial_port_in(port, SCSCR); 1283 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1284 scr &= ~SCSCR_RDRQE; 1285 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1286 } 1287 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1288 } 1289 1290 static void sci_dma_rx_complete(void *arg) 1291 { 1292 struct sci_port *s = arg; 1293 struct dma_chan *chan = s->chan_rx; 1294 struct uart_port *port = &s->port; 1295 struct dma_async_tx_descriptor *desc; 1296 unsigned long flags; 1297 int active, count = 0; 1298 1299 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1300 s->active_rx); 1301 1302 spin_lock_irqsave(&port->lock, flags); 1303 1304 active = sci_dma_rx_find_active(s); 1305 if (active >= 0) 1306 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1307 1308 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1309 1310 if (count) 1311 tty_flip_buffer_push(&port->state->port); 1312 1313 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1314 DMA_DEV_TO_MEM, 1315 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1316 if (!desc) 1317 goto fail; 1318 1319 desc->callback = sci_dma_rx_complete; 1320 desc->callback_param = s; 1321 s->cookie_rx[active] = dmaengine_submit(desc); 1322 if (dma_submit_error(s->cookie_rx[active])) 1323 goto fail; 1324 1325 s->active_rx = s->cookie_rx[!active]; 1326 1327 dma_async_issue_pending(chan); 1328 1329 spin_unlock_irqrestore(&port->lock, flags); 1330 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1331 __func__, s->cookie_rx[active], active, s->active_rx); 1332 return; 1333 1334 fail: 1335 spin_unlock_irqrestore(&port->lock, flags); 1336 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1337 /* Switch to PIO */ 1338 spin_lock_irqsave(&port->lock, flags); 1339 dmaengine_terminate_async(chan); 1340 sci_dma_rx_chan_invalidate(s); 1341 sci_dma_rx_reenable_irq(s); 1342 spin_unlock_irqrestore(&port->lock, flags); 1343 } 1344 1345 static void sci_dma_tx_release(struct sci_port *s) 1346 { 1347 struct dma_chan *chan = s->chan_tx_saved; 1348 1349 cancel_work_sync(&s->work_tx); 1350 s->chan_tx_saved = s->chan_tx = NULL; 1351 s->cookie_tx = -EINVAL; 1352 dmaengine_terminate_sync(chan); 1353 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1354 DMA_TO_DEVICE); 1355 dma_release_channel(chan); 1356 } 1357 1358 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1359 { 1360 struct dma_chan *chan = s->chan_rx; 1361 struct uart_port *port = &s->port; 1362 unsigned long flags; 1363 int i; 1364 1365 for (i = 0; i < 2; i++) { 1366 struct scatterlist *sg = &s->sg_rx[i]; 1367 struct dma_async_tx_descriptor *desc; 1368 1369 desc = dmaengine_prep_slave_sg(chan, 1370 sg, 1, DMA_DEV_TO_MEM, 1371 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1372 if (!desc) 1373 goto fail; 1374 1375 desc->callback = sci_dma_rx_complete; 1376 desc->callback_param = s; 1377 s->cookie_rx[i] = dmaengine_submit(desc); 1378 if (dma_submit_error(s->cookie_rx[i])) 1379 goto fail; 1380 1381 } 1382 1383 s->active_rx = s->cookie_rx[0]; 1384 1385 dma_async_issue_pending(chan); 1386 return 0; 1387 1388 fail: 1389 /* Switch to PIO */ 1390 if (!port_lock_held) 1391 spin_lock_irqsave(&port->lock, flags); 1392 if (i) 1393 dmaengine_terminate_async(chan); 1394 sci_dma_rx_chan_invalidate(s); 1395 sci_start_rx(port); 1396 if (!port_lock_held) 1397 spin_unlock_irqrestore(&port->lock, flags); 1398 return -EAGAIN; 1399 } 1400 1401 static void sci_dma_tx_work_fn(struct work_struct *work) 1402 { 1403 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1404 struct dma_async_tx_descriptor *desc; 1405 struct dma_chan *chan = s->chan_tx; 1406 struct uart_port *port = &s->port; 1407 struct circ_buf *xmit = &port->state->xmit; 1408 unsigned long flags; 1409 dma_addr_t buf; 1410 int head, tail; 1411 1412 /* 1413 * DMA is idle now. 1414 * Port xmit buffer is already mapped, and it is one page... Just adjust 1415 * offsets and lengths. Since it is a circular buffer, we have to 1416 * transmit till the end, and then the rest. Take the port lock to get a 1417 * consistent xmit buffer state. 1418 */ 1419 spin_lock_irq(&port->lock); 1420 head = xmit->head; 1421 tail = xmit->tail; 1422 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1423 s->tx_dma_len = min_t(unsigned int, 1424 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1425 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1426 if (!s->tx_dma_len) { 1427 /* Transmit buffer has been flushed */ 1428 spin_unlock_irq(&port->lock); 1429 return; 1430 } 1431 1432 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1433 DMA_MEM_TO_DEV, 1434 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1435 if (!desc) { 1436 spin_unlock_irq(&port->lock); 1437 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1438 goto switch_to_pio; 1439 } 1440 1441 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1442 DMA_TO_DEVICE); 1443 1444 desc->callback = sci_dma_tx_complete; 1445 desc->callback_param = s; 1446 s->cookie_tx = dmaengine_submit(desc); 1447 if (dma_submit_error(s->cookie_tx)) { 1448 spin_unlock_irq(&port->lock); 1449 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1450 goto switch_to_pio; 1451 } 1452 1453 spin_unlock_irq(&port->lock); 1454 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1455 __func__, xmit->buf, tail, head, s->cookie_tx); 1456 1457 dma_async_issue_pending(chan); 1458 return; 1459 1460 switch_to_pio: 1461 spin_lock_irqsave(&port->lock, flags); 1462 s->chan_tx = NULL; 1463 sci_start_tx(port); 1464 spin_unlock_irqrestore(&port->lock, flags); 1465 return; 1466 } 1467 1468 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1469 { 1470 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1471 struct dma_chan *chan = s->chan_rx; 1472 struct uart_port *port = &s->port; 1473 struct dma_tx_state state; 1474 enum dma_status status; 1475 unsigned long flags; 1476 unsigned int read; 1477 int active, count; 1478 1479 dev_dbg(port->dev, "DMA Rx timed out\n"); 1480 1481 spin_lock_irqsave(&port->lock, flags); 1482 1483 active = sci_dma_rx_find_active(s); 1484 if (active < 0) { 1485 spin_unlock_irqrestore(&port->lock, flags); 1486 return HRTIMER_NORESTART; 1487 } 1488 1489 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1490 if (status == DMA_COMPLETE) { 1491 spin_unlock_irqrestore(&port->lock, flags); 1492 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1493 s->active_rx, active); 1494 1495 /* Let packet complete handler take care of the packet */ 1496 return HRTIMER_NORESTART; 1497 } 1498 1499 dmaengine_pause(chan); 1500 1501 /* 1502 * sometimes DMA transfer doesn't stop even if it is stopped and 1503 * data keeps on coming until transaction is complete so check 1504 * for DMA_COMPLETE again 1505 * Let packet complete handler take care of the packet 1506 */ 1507 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1508 if (status == DMA_COMPLETE) { 1509 spin_unlock_irqrestore(&port->lock, flags); 1510 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1511 return HRTIMER_NORESTART; 1512 } 1513 1514 /* Handle incomplete DMA receive */ 1515 dmaengine_terminate_async(s->chan_rx); 1516 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1517 1518 if (read) { 1519 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1520 if (count) 1521 tty_flip_buffer_push(&port->state->port); 1522 } 1523 1524 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1525 sci_dma_rx_submit(s, true); 1526 1527 sci_dma_rx_reenable_irq(s); 1528 1529 spin_unlock_irqrestore(&port->lock, flags); 1530 1531 return HRTIMER_NORESTART; 1532 } 1533 1534 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1535 enum dma_transfer_direction dir) 1536 { 1537 struct dma_chan *chan; 1538 struct dma_slave_config cfg; 1539 int ret; 1540 1541 chan = dma_request_slave_channel(port->dev, 1542 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1543 if (!chan) { 1544 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1545 return NULL; 1546 } 1547 1548 memset(&cfg, 0, sizeof(cfg)); 1549 cfg.direction = dir; 1550 if (dir == DMA_MEM_TO_DEV) { 1551 cfg.dst_addr = port->mapbase + 1552 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1553 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1554 } else { 1555 cfg.src_addr = port->mapbase + 1556 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1557 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1558 } 1559 1560 ret = dmaengine_slave_config(chan, &cfg); 1561 if (ret) { 1562 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1563 dma_release_channel(chan); 1564 return NULL; 1565 } 1566 1567 return chan; 1568 } 1569 1570 static void sci_request_dma(struct uart_port *port) 1571 { 1572 struct sci_port *s = to_sci_port(port); 1573 struct dma_chan *chan; 1574 1575 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1576 1577 /* 1578 * DMA on console may interfere with Kernel log messages which use 1579 * plain putchar(). So, simply don't use it with a console. 1580 */ 1581 if (uart_console(port)) 1582 return; 1583 1584 if (!port->dev->of_node) 1585 return; 1586 1587 s->cookie_tx = -EINVAL; 1588 1589 /* 1590 * Don't request a dma channel if no channel was specified 1591 * in the device tree. 1592 */ 1593 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1594 return; 1595 1596 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1597 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1598 if (chan) { 1599 /* UART circular tx buffer is an aligned page. */ 1600 s->tx_dma_addr = dma_map_single(chan->device->dev, 1601 port->state->xmit.buf, 1602 UART_XMIT_SIZE, 1603 DMA_TO_DEVICE); 1604 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1605 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1606 dma_release_channel(chan); 1607 } else { 1608 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1609 __func__, UART_XMIT_SIZE, 1610 port->state->xmit.buf, &s->tx_dma_addr); 1611 1612 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1613 s->chan_tx_saved = s->chan_tx = chan; 1614 } 1615 } 1616 1617 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1618 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1619 if (chan) { 1620 unsigned int i; 1621 dma_addr_t dma; 1622 void *buf; 1623 1624 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1625 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1626 &dma, GFP_KERNEL); 1627 if (!buf) { 1628 dev_warn(port->dev, 1629 "Failed to allocate Rx dma buffer, using PIO\n"); 1630 dma_release_channel(chan); 1631 return; 1632 } 1633 1634 for (i = 0; i < 2; i++) { 1635 struct scatterlist *sg = &s->sg_rx[i]; 1636 1637 sg_init_table(sg, 1); 1638 s->rx_buf[i] = buf; 1639 sg_dma_address(sg) = dma; 1640 sg_dma_len(sg) = s->buf_len_rx; 1641 1642 buf += s->buf_len_rx; 1643 dma += s->buf_len_rx; 1644 } 1645 1646 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1647 s->rx_timer.function = sci_dma_rx_timer_fn; 1648 1649 s->chan_rx_saved = s->chan_rx = chan; 1650 1651 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1652 sci_dma_rx_submit(s, false); 1653 } 1654 } 1655 1656 static void sci_free_dma(struct uart_port *port) 1657 { 1658 struct sci_port *s = to_sci_port(port); 1659 1660 if (s->chan_tx_saved) 1661 sci_dma_tx_release(s); 1662 if (s->chan_rx_saved) 1663 sci_dma_rx_release(s); 1664 } 1665 1666 static void sci_flush_buffer(struct uart_port *port) 1667 { 1668 struct sci_port *s = to_sci_port(port); 1669 1670 /* 1671 * In uart_flush_buffer(), the xmit circular buffer has just been 1672 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1673 * pending transfers 1674 */ 1675 s->tx_dma_len = 0; 1676 if (s->chan_tx) { 1677 dmaengine_terminate_async(s->chan_tx); 1678 s->cookie_tx = -EINVAL; 1679 } 1680 } 1681 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1682 static inline void sci_request_dma(struct uart_port *port) 1683 { 1684 } 1685 1686 static inline void sci_free_dma(struct uart_port *port) 1687 { 1688 } 1689 1690 #define sci_flush_buffer NULL 1691 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1692 1693 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1694 { 1695 struct uart_port *port = ptr; 1696 struct sci_port *s = to_sci_port(port); 1697 1698 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1699 if (s->chan_rx) { 1700 u16 scr = serial_port_in(port, SCSCR); 1701 u16 ssr = serial_port_in(port, SCxSR); 1702 1703 /* Disable future Rx interrupts */ 1704 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1705 disable_irq_nosync(irq); 1706 scr |= SCSCR_RDRQE; 1707 } else { 1708 if (sci_dma_rx_submit(s, false) < 0) 1709 goto handle_pio; 1710 1711 scr &= ~SCSCR_RIE; 1712 } 1713 serial_port_out(port, SCSCR, scr); 1714 /* Clear current interrupt */ 1715 serial_port_out(port, SCxSR, 1716 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1717 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1718 jiffies, s->rx_timeout); 1719 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1720 1721 return IRQ_HANDLED; 1722 } 1723 1724 handle_pio: 1725 #endif 1726 1727 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1728 if (!scif_rtrg_enabled(port)) 1729 scif_set_rtrg(port, s->rx_trigger); 1730 1731 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1732 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1733 } 1734 1735 /* I think sci_receive_chars has to be called irrespective 1736 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1737 * to be disabled? 1738 */ 1739 sci_receive_chars(port); 1740 1741 return IRQ_HANDLED; 1742 } 1743 1744 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1745 { 1746 struct uart_port *port = ptr; 1747 unsigned long flags; 1748 1749 spin_lock_irqsave(&port->lock, flags); 1750 sci_transmit_chars(port); 1751 spin_unlock_irqrestore(&port->lock, flags); 1752 1753 return IRQ_HANDLED; 1754 } 1755 1756 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1757 { 1758 struct uart_port *port = ptr; 1759 1760 /* Handle BREAKs */ 1761 sci_handle_breaks(port); 1762 1763 /* drop invalid character received before break was detected */ 1764 serial_port_in(port, SCxRDR); 1765 1766 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1767 1768 return IRQ_HANDLED; 1769 } 1770 1771 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1772 { 1773 struct uart_port *port = ptr; 1774 struct sci_port *s = to_sci_port(port); 1775 1776 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1777 /* Break and Error interrupts are muxed */ 1778 unsigned short ssr_status = serial_port_in(port, SCxSR); 1779 1780 /* Break Interrupt */ 1781 if (ssr_status & SCxSR_BRK(port)) 1782 sci_br_interrupt(irq, ptr); 1783 1784 /* Break only? */ 1785 if (!(ssr_status & SCxSR_ERRORS(port))) 1786 return IRQ_HANDLED; 1787 } 1788 1789 /* Handle errors */ 1790 if (port->type == PORT_SCI) { 1791 if (sci_handle_errors(port)) { 1792 /* discard character in rx buffer */ 1793 serial_port_in(port, SCxSR); 1794 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1795 } 1796 } else { 1797 sci_handle_fifo_overrun(port); 1798 if (!s->chan_rx) 1799 sci_receive_chars(port); 1800 } 1801 1802 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1803 1804 /* Kick the transmission */ 1805 if (!s->chan_tx) 1806 sci_tx_interrupt(irq, ptr); 1807 1808 return IRQ_HANDLED; 1809 } 1810 1811 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1812 { 1813 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1814 struct uart_port *port = ptr; 1815 struct sci_port *s = to_sci_port(port); 1816 irqreturn_t ret = IRQ_NONE; 1817 1818 ssr_status = serial_port_in(port, SCxSR); 1819 scr_status = serial_port_in(port, SCSCR); 1820 if (s->params->overrun_reg == SCxSR) 1821 orer_status = ssr_status; 1822 else if (sci_getreg(port, s->params->overrun_reg)->size) 1823 orer_status = serial_port_in(port, s->params->overrun_reg); 1824 1825 err_enabled = scr_status & port_rx_irq_mask(port); 1826 1827 /* Tx Interrupt */ 1828 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1829 !s->chan_tx) 1830 ret = sci_tx_interrupt(irq, ptr); 1831 1832 /* 1833 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1834 * DR flags 1835 */ 1836 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1837 (scr_status & SCSCR_RIE)) 1838 ret = sci_rx_interrupt(irq, ptr); 1839 1840 /* Error Interrupt */ 1841 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1842 ret = sci_er_interrupt(irq, ptr); 1843 1844 /* Break Interrupt */ 1845 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1846 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1847 ret = sci_br_interrupt(irq, ptr); 1848 1849 /* Overrun Interrupt */ 1850 if (orer_status & s->params->overrun_mask) { 1851 sci_handle_fifo_overrun(port); 1852 ret = IRQ_HANDLED; 1853 } 1854 1855 return ret; 1856 } 1857 1858 static const struct sci_irq_desc { 1859 const char *desc; 1860 irq_handler_t handler; 1861 } sci_irq_desc[] = { 1862 /* 1863 * Split out handlers, the default case. 1864 */ 1865 [SCIx_ERI_IRQ] = { 1866 .desc = "rx err", 1867 .handler = sci_er_interrupt, 1868 }, 1869 1870 [SCIx_RXI_IRQ] = { 1871 .desc = "rx full", 1872 .handler = sci_rx_interrupt, 1873 }, 1874 1875 [SCIx_TXI_IRQ] = { 1876 .desc = "tx empty", 1877 .handler = sci_tx_interrupt, 1878 }, 1879 1880 [SCIx_BRI_IRQ] = { 1881 .desc = "break", 1882 .handler = sci_br_interrupt, 1883 }, 1884 1885 [SCIx_DRI_IRQ] = { 1886 .desc = "rx ready", 1887 .handler = sci_rx_interrupt, 1888 }, 1889 1890 [SCIx_TEI_IRQ] = { 1891 .desc = "tx end", 1892 .handler = sci_tx_interrupt, 1893 }, 1894 1895 /* 1896 * Special muxed handler. 1897 */ 1898 [SCIx_MUX_IRQ] = { 1899 .desc = "mux", 1900 .handler = sci_mpxed_interrupt, 1901 }, 1902 }; 1903 1904 static int sci_request_irq(struct sci_port *port) 1905 { 1906 struct uart_port *up = &port->port; 1907 int i, j, w, ret = 0; 1908 1909 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1910 const struct sci_irq_desc *desc; 1911 int irq; 1912 1913 /* Check if already registered (muxed) */ 1914 for (w = 0; w < i; w++) 1915 if (port->irqs[w] == port->irqs[i]) 1916 w = i + 1; 1917 if (w > i) 1918 continue; 1919 1920 if (SCIx_IRQ_IS_MUXED(port)) { 1921 i = SCIx_MUX_IRQ; 1922 irq = up->irq; 1923 } else { 1924 irq = port->irqs[i]; 1925 1926 /* 1927 * Certain port types won't support all of the 1928 * available interrupt sources. 1929 */ 1930 if (unlikely(irq < 0)) 1931 continue; 1932 } 1933 1934 desc = sci_irq_desc + i; 1935 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1936 dev_name(up->dev), desc->desc); 1937 if (!port->irqstr[j]) { 1938 ret = -ENOMEM; 1939 goto out_nomem; 1940 } 1941 1942 ret = request_irq(irq, desc->handler, up->irqflags, 1943 port->irqstr[j], port); 1944 if (unlikely(ret)) { 1945 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1946 goto out_noirq; 1947 } 1948 } 1949 1950 return 0; 1951 1952 out_noirq: 1953 while (--i >= 0) 1954 free_irq(port->irqs[i], port); 1955 1956 out_nomem: 1957 while (--j >= 0) 1958 kfree(port->irqstr[j]); 1959 1960 return ret; 1961 } 1962 1963 static void sci_free_irq(struct sci_port *port) 1964 { 1965 int i, j; 1966 1967 /* 1968 * Intentionally in reverse order so we iterate over the muxed 1969 * IRQ first. 1970 */ 1971 for (i = 0; i < SCIx_NR_IRQS; i++) { 1972 int irq = port->irqs[i]; 1973 1974 /* 1975 * Certain port types won't support all of the available 1976 * interrupt sources. 1977 */ 1978 if (unlikely(irq < 0)) 1979 continue; 1980 1981 /* Check if already freed (irq was muxed) */ 1982 for (j = 0; j < i; j++) 1983 if (port->irqs[j] == irq) 1984 j = i + 1; 1985 if (j > i) 1986 continue; 1987 1988 free_irq(port->irqs[i], port); 1989 kfree(port->irqstr[i]); 1990 1991 if (SCIx_IRQ_IS_MUXED(port)) { 1992 /* If there's only one IRQ, we're done. */ 1993 return; 1994 } 1995 } 1996 } 1997 1998 static unsigned int sci_tx_empty(struct uart_port *port) 1999 { 2000 unsigned short status = serial_port_in(port, SCxSR); 2001 unsigned short in_tx_fifo = sci_txfill(port); 2002 2003 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2004 } 2005 2006 static void sci_set_rts(struct uart_port *port, bool state) 2007 { 2008 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2009 u16 data = serial_port_in(port, SCPDR); 2010 2011 /* Active low */ 2012 if (state) 2013 data &= ~SCPDR_RTSD; 2014 else 2015 data |= SCPDR_RTSD; 2016 serial_port_out(port, SCPDR, data); 2017 2018 /* RTS# is output */ 2019 serial_port_out(port, SCPCR, 2020 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2021 } else if (sci_getreg(port, SCSPTR)->size) { 2022 u16 ctrl = serial_port_in(port, SCSPTR); 2023 2024 /* Active low */ 2025 if (state) 2026 ctrl &= ~SCSPTR_RTSDT; 2027 else 2028 ctrl |= SCSPTR_RTSDT; 2029 serial_port_out(port, SCSPTR, ctrl); 2030 } 2031 } 2032 2033 static bool sci_get_cts(struct uart_port *port) 2034 { 2035 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2036 /* Active low */ 2037 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2038 } else if (sci_getreg(port, SCSPTR)->size) { 2039 /* Active low */ 2040 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2041 } 2042 2043 return true; 2044 } 2045 2046 /* 2047 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2048 * CTS/RTS is supported in hardware by at least one port and controlled 2049 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2050 * handled via the ->init_pins() op, which is a bit of a one-way street, 2051 * lacking any ability to defer pin control -- this will later be 2052 * converted over to the GPIO framework). 2053 * 2054 * Other modes (such as loopback) are supported generically on certain 2055 * port types, but not others. For these it's sufficient to test for the 2056 * existence of the support register and simply ignore the port type. 2057 */ 2058 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2059 { 2060 struct sci_port *s = to_sci_port(port); 2061 2062 if (mctrl & TIOCM_LOOP) { 2063 const struct plat_sci_reg *reg; 2064 2065 /* 2066 * Standard loopback mode for SCFCR ports. 2067 */ 2068 reg = sci_getreg(port, SCFCR); 2069 if (reg->size) 2070 serial_port_out(port, SCFCR, 2071 serial_port_in(port, SCFCR) | 2072 SCFCR_LOOP); 2073 } 2074 2075 mctrl_gpio_set(s->gpios, mctrl); 2076 2077 if (!s->has_rtscts) 2078 return; 2079 2080 if (!(mctrl & TIOCM_RTS)) { 2081 /* Disable Auto RTS */ 2082 serial_port_out(port, SCFCR, 2083 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2084 2085 /* Clear RTS */ 2086 sci_set_rts(port, 0); 2087 } else if (s->autorts) { 2088 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2089 /* Enable RTS# pin function */ 2090 serial_port_out(port, SCPCR, 2091 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2092 } 2093 2094 /* Enable Auto RTS */ 2095 serial_port_out(port, SCFCR, 2096 serial_port_in(port, SCFCR) | SCFCR_MCE); 2097 } else { 2098 /* Set RTS */ 2099 sci_set_rts(port, 1); 2100 } 2101 } 2102 2103 static unsigned int sci_get_mctrl(struct uart_port *port) 2104 { 2105 struct sci_port *s = to_sci_port(port); 2106 struct mctrl_gpios *gpios = s->gpios; 2107 unsigned int mctrl = 0; 2108 2109 mctrl_gpio_get(gpios, &mctrl); 2110 2111 /* 2112 * CTS/RTS is handled in hardware when supported, while nothing 2113 * else is wired up. 2114 */ 2115 if (s->autorts) { 2116 if (sci_get_cts(port)) 2117 mctrl |= TIOCM_CTS; 2118 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2119 mctrl |= TIOCM_CTS; 2120 } 2121 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2122 mctrl |= TIOCM_DSR; 2123 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2124 mctrl |= TIOCM_CAR; 2125 2126 return mctrl; 2127 } 2128 2129 static void sci_enable_ms(struct uart_port *port) 2130 { 2131 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2132 } 2133 2134 static void sci_break_ctl(struct uart_port *port, int break_state) 2135 { 2136 unsigned short scscr, scsptr; 2137 unsigned long flags; 2138 2139 /* check whether the port has SCSPTR */ 2140 if (!sci_getreg(port, SCSPTR)->size) { 2141 /* 2142 * Not supported by hardware. Most parts couple break and rx 2143 * interrupts together, with break detection always enabled. 2144 */ 2145 return; 2146 } 2147 2148 spin_lock_irqsave(&port->lock, flags); 2149 scsptr = serial_port_in(port, SCSPTR); 2150 scscr = serial_port_in(port, SCSCR); 2151 2152 if (break_state == -1) { 2153 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2154 scscr &= ~SCSCR_TE; 2155 } else { 2156 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2157 scscr |= SCSCR_TE; 2158 } 2159 2160 serial_port_out(port, SCSPTR, scsptr); 2161 serial_port_out(port, SCSCR, scscr); 2162 spin_unlock_irqrestore(&port->lock, flags); 2163 } 2164 2165 static int sci_startup(struct uart_port *port) 2166 { 2167 struct sci_port *s = to_sci_port(port); 2168 int ret; 2169 2170 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2171 2172 sci_request_dma(port); 2173 2174 ret = sci_request_irq(s); 2175 if (unlikely(ret < 0)) { 2176 sci_free_dma(port); 2177 return ret; 2178 } 2179 2180 return 0; 2181 } 2182 2183 static void sci_shutdown(struct uart_port *port) 2184 { 2185 struct sci_port *s = to_sci_port(port); 2186 unsigned long flags; 2187 u16 scr; 2188 2189 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2190 2191 s->autorts = false; 2192 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2193 2194 spin_lock_irqsave(&port->lock, flags); 2195 sci_stop_rx(port); 2196 sci_stop_tx(port); 2197 /* 2198 * Stop RX and TX, disable related interrupts, keep clock source 2199 * and HSCIF TOT bits 2200 */ 2201 scr = serial_port_in(port, SCSCR); 2202 serial_port_out(port, SCSCR, scr & 2203 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2204 spin_unlock_irqrestore(&port->lock, flags); 2205 2206 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2207 if (s->chan_rx_saved) { 2208 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2209 port->line); 2210 hrtimer_cancel(&s->rx_timer); 2211 } 2212 #endif 2213 2214 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2215 del_timer_sync(&s->rx_fifo_timer); 2216 sci_free_irq(s); 2217 sci_free_dma(port); 2218 } 2219 2220 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2221 unsigned int *srr) 2222 { 2223 unsigned long freq = s->clk_rates[SCI_SCK]; 2224 int err, min_err = INT_MAX; 2225 unsigned int sr; 2226 2227 if (s->port.type != PORT_HSCIF) 2228 freq *= 2; 2229 2230 for_each_sr(sr, s) { 2231 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2232 if (abs(err) >= abs(min_err)) 2233 continue; 2234 2235 min_err = err; 2236 *srr = sr - 1; 2237 2238 if (!err) 2239 break; 2240 } 2241 2242 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2243 *srr + 1); 2244 return min_err; 2245 } 2246 2247 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2248 unsigned long freq, unsigned int *dlr, 2249 unsigned int *srr) 2250 { 2251 int err, min_err = INT_MAX; 2252 unsigned int sr, dl; 2253 2254 if (s->port.type != PORT_HSCIF) 2255 freq *= 2; 2256 2257 for_each_sr(sr, s) { 2258 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2259 dl = clamp(dl, 1U, 65535U); 2260 2261 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2262 if (abs(err) >= abs(min_err)) 2263 continue; 2264 2265 min_err = err; 2266 *dlr = dl; 2267 *srr = sr - 1; 2268 2269 if (!err) 2270 break; 2271 } 2272 2273 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2274 min_err, *dlr, *srr + 1); 2275 return min_err; 2276 } 2277 2278 /* calculate sample rate, BRR, and clock select */ 2279 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2280 unsigned int *brr, unsigned int *srr, 2281 unsigned int *cks) 2282 { 2283 unsigned long freq = s->clk_rates[SCI_FCK]; 2284 unsigned int sr, br, prediv, scrate, c; 2285 int err, min_err = INT_MAX; 2286 2287 if (s->port.type != PORT_HSCIF) 2288 freq *= 2; 2289 2290 /* 2291 * Find the combination of sample rate and clock select with the 2292 * smallest deviation from the desired baud rate. 2293 * Prefer high sample rates to maximise the receive margin. 2294 * 2295 * M: Receive margin (%) 2296 * N: Ratio of bit rate to clock (N = sampling rate) 2297 * D: Clock duty (D = 0 to 1.0) 2298 * L: Frame length (L = 9 to 12) 2299 * F: Absolute value of clock frequency deviation 2300 * 2301 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2302 * (|D - 0.5| / N * (1 + F))| 2303 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2304 */ 2305 for_each_sr(sr, s) { 2306 for (c = 0; c <= 3; c++) { 2307 /* integerized formulas from HSCIF documentation */ 2308 prediv = sr * (1 << (2 * c + 1)); 2309 2310 /* 2311 * We need to calculate: 2312 * 2313 * br = freq / (prediv * bps) clamped to [1..256] 2314 * err = freq / (br * prediv) - bps 2315 * 2316 * Watch out for overflow when calculating the desired 2317 * sampling clock rate! 2318 */ 2319 if (bps > UINT_MAX / prediv) 2320 break; 2321 2322 scrate = prediv * bps; 2323 br = DIV_ROUND_CLOSEST(freq, scrate); 2324 br = clamp(br, 1U, 256U); 2325 2326 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2327 if (abs(err) >= abs(min_err)) 2328 continue; 2329 2330 min_err = err; 2331 *brr = br - 1; 2332 *srr = sr - 1; 2333 *cks = c; 2334 2335 if (!err) 2336 goto found; 2337 } 2338 } 2339 2340 found: 2341 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2342 min_err, *brr, *srr + 1, *cks); 2343 return min_err; 2344 } 2345 2346 static void sci_reset(struct uart_port *port) 2347 { 2348 const struct plat_sci_reg *reg; 2349 unsigned int status; 2350 struct sci_port *s = to_sci_port(port); 2351 2352 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2353 2354 reg = sci_getreg(port, SCFCR); 2355 if (reg->size) 2356 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2357 2358 sci_clear_SCxSR(port, 2359 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2360 SCxSR_BREAK_CLEAR(port)); 2361 if (sci_getreg(port, SCLSR)->size) { 2362 status = serial_port_in(port, SCLSR); 2363 status &= ~(SCLSR_TO | SCLSR_ORER); 2364 serial_port_out(port, SCLSR, status); 2365 } 2366 2367 if (s->rx_trigger > 1) { 2368 if (s->rx_fifo_timeout) { 2369 scif_set_rtrg(port, 1); 2370 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2371 } else { 2372 if (port->type == PORT_SCIFA || 2373 port->type == PORT_SCIFB) 2374 scif_set_rtrg(port, 1); 2375 else 2376 scif_set_rtrg(port, s->rx_trigger); 2377 } 2378 } 2379 } 2380 2381 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2382 struct ktermios *old) 2383 { 2384 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2385 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2386 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2387 struct sci_port *s = to_sci_port(port); 2388 const struct plat_sci_reg *reg; 2389 int min_err = INT_MAX, err; 2390 unsigned long max_freq = 0; 2391 int best_clk = -1; 2392 unsigned long flags; 2393 2394 if ((termios->c_cflag & CSIZE) == CS7) 2395 smr_val |= SCSMR_CHR; 2396 if (termios->c_cflag & PARENB) 2397 smr_val |= SCSMR_PE; 2398 if (termios->c_cflag & PARODD) 2399 smr_val |= SCSMR_PE | SCSMR_ODD; 2400 if (termios->c_cflag & CSTOPB) 2401 smr_val |= SCSMR_STOP; 2402 2403 /* 2404 * earlyprintk comes here early on with port->uartclk set to zero. 2405 * the clock framework is not up and running at this point so here 2406 * we assume that 115200 is the maximum baud rate. please note that 2407 * the baud rate is not programmed during earlyprintk - it is assumed 2408 * that the previous boot loader has enabled required clocks and 2409 * setup the baud rate generator hardware for us already. 2410 */ 2411 if (!port->uartclk) { 2412 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2413 goto done; 2414 } 2415 2416 for (i = 0; i < SCI_NUM_CLKS; i++) 2417 max_freq = max(max_freq, s->clk_rates[i]); 2418 2419 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2420 if (!baud) 2421 goto done; 2422 2423 /* 2424 * There can be multiple sources for the sampling clock. Find the one 2425 * that gives us the smallest deviation from the desired baud rate. 2426 */ 2427 2428 /* Optional Undivided External Clock */ 2429 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2430 port->type != PORT_SCIFB) { 2431 err = sci_sck_calc(s, baud, &srr1); 2432 if (abs(err) < abs(min_err)) { 2433 best_clk = SCI_SCK; 2434 scr_val = SCSCR_CKE1; 2435 sccks = SCCKS_CKS; 2436 min_err = err; 2437 srr = srr1; 2438 if (!err) 2439 goto done; 2440 } 2441 } 2442 2443 /* Optional BRG Frequency Divided External Clock */ 2444 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2445 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2446 &srr1); 2447 if (abs(err) < abs(min_err)) { 2448 best_clk = SCI_SCIF_CLK; 2449 scr_val = SCSCR_CKE1; 2450 sccks = 0; 2451 min_err = err; 2452 dl = dl1; 2453 srr = srr1; 2454 if (!err) 2455 goto done; 2456 } 2457 } 2458 2459 /* Optional BRG Frequency Divided Internal Clock */ 2460 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2461 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2462 &srr1); 2463 if (abs(err) < abs(min_err)) { 2464 best_clk = SCI_BRG_INT; 2465 scr_val = SCSCR_CKE1; 2466 sccks = SCCKS_XIN; 2467 min_err = err; 2468 dl = dl1; 2469 srr = srr1; 2470 if (!min_err) 2471 goto done; 2472 } 2473 } 2474 2475 /* Divided Functional Clock using standard Bit Rate Register */ 2476 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2477 if (abs(err) < abs(min_err)) { 2478 best_clk = SCI_FCK; 2479 scr_val = 0; 2480 min_err = err; 2481 brr = brr1; 2482 srr = srr1; 2483 cks = cks1; 2484 } 2485 2486 done: 2487 if (best_clk >= 0) 2488 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2489 s->clks[best_clk], baud, min_err); 2490 2491 sci_port_enable(s); 2492 2493 /* 2494 * Program the optional External Baud Rate Generator (BRG) first. 2495 * It controls the mux to select (H)SCK or frequency divided clock. 2496 */ 2497 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2498 serial_port_out(port, SCDL, dl); 2499 serial_port_out(port, SCCKS, sccks); 2500 } 2501 2502 spin_lock_irqsave(&port->lock, flags); 2503 2504 sci_reset(port); 2505 2506 uart_update_timeout(port, termios->c_cflag, baud); 2507 2508 /* byte size and parity */ 2509 bits = tty_get_frame_size(termios->c_cflag); 2510 2511 if (sci_getreg(port, SEMR)->size) 2512 serial_port_out(port, SEMR, 0); 2513 2514 if (best_clk >= 0) { 2515 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2516 switch (srr + 1) { 2517 case 5: smr_val |= SCSMR_SRC_5; break; 2518 case 7: smr_val |= SCSMR_SRC_7; break; 2519 case 11: smr_val |= SCSMR_SRC_11; break; 2520 case 13: smr_val |= SCSMR_SRC_13; break; 2521 case 16: smr_val |= SCSMR_SRC_16; break; 2522 case 17: smr_val |= SCSMR_SRC_17; break; 2523 case 19: smr_val |= SCSMR_SRC_19; break; 2524 case 27: smr_val |= SCSMR_SRC_27; break; 2525 } 2526 smr_val |= cks; 2527 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2528 serial_port_out(port, SCSMR, smr_val); 2529 serial_port_out(port, SCBRR, brr); 2530 if (sci_getreg(port, HSSRR)->size) { 2531 unsigned int hssrr = srr | HSCIF_SRE; 2532 /* Calculate deviation from intended rate at the 2533 * center of the last stop bit in sampling clocks. 2534 */ 2535 int last_stop = bits * 2 - 1; 2536 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2537 (int)(srr + 1), 2538 2 * (int)baud); 2539 2540 if (abs(deviation) >= 2) { 2541 /* At least two sampling clocks off at the 2542 * last stop bit; we can increase the error 2543 * margin by shifting the sampling point. 2544 */ 2545 int shift = clamp(deviation / 2, -8, 7); 2546 2547 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2548 HSCIF_SRHP_MASK; 2549 hssrr |= HSCIF_SRDE; 2550 } 2551 serial_port_out(port, HSSRR, hssrr); 2552 } 2553 2554 /* Wait one bit interval */ 2555 udelay((1000000 + (baud - 1)) / baud); 2556 } else { 2557 /* Don't touch the bit rate configuration */ 2558 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2559 smr_val |= serial_port_in(port, SCSMR) & 2560 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2561 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2562 serial_port_out(port, SCSMR, smr_val); 2563 } 2564 2565 sci_init_pins(port, termios->c_cflag); 2566 2567 port->status &= ~UPSTAT_AUTOCTS; 2568 s->autorts = false; 2569 reg = sci_getreg(port, SCFCR); 2570 if (reg->size) { 2571 unsigned short ctrl = serial_port_in(port, SCFCR); 2572 2573 if ((port->flags & UPF_HARD_FLOW) && 2574 (termios->c_cflag & CRTSCTS)) { 2575 /* There is no CTS interrupt to restart the hardware */ 2576 port->status |= UPSTAT_AUTOCTS; 2577 /* MCE is enabled when RTS is raised */ 2578 s->autorts = true; 2579 } 2580 2581 /* 2582 * As we've done a sci_reset() above, ensure we don't 2583 * interfere with the FIFOs while toggling MCE. As the 2584 * reset values could still be set, simply mask them out. 2585 */ 2586 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2587 2588 serial_port_out(port, SCFCR, ctrl); 2589 } 2590 if (port->flags & UPF_HARD_FLOW) { 2591 /* Refresh (Auto) RTS */ 2592 sci_set_mctrl(port, port->mctrl); 2593 } 2594 2595 scr_val |= SCSCR_RE | SCSCR_TE | 2596 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2597 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2598 if ((srr + 1 == 5) && 2599 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2600 /* 2601 * In asynchronous mode, when the sampling rate is 1/5, first 2602 * received data may become invalid on some SCIFA and SCIFB. 2603 * To avoid this problem wait more than 1 serial data time (1 2604 * bit time x serial data number) after setting SCSCR.RE = 1. 2605 */ 2606 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2607 } 2608 2609 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2610 s->rx_frame = (10000 * bits) / (baud / 100); 2611 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2612 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2613 #endif 2614 2615 if ((termios->c_cflag & CREAD) != 0) 2616 sci_start_rx(port); 2617 2618 spin_unlock_irqrestore(&port->lock, flags); 2619 2620 sci_port_disable(s); 2621 2622 if (UART_ENABLE_MS(port, termios->c_cflag)) 2623 sci_enable_ms(port); 2624 } 2625 2626 static void sci_pm(struct uart_port *port, unsigned int state, 2627 unsigned int oldstate) 2628 { 2629 struct sci_port *sci_port = to_sci_port(port); 2630 2631 switch (state) { 2632 case UART_PM_STATE_OFF: 2633 sci_port_disable(sci_port); 2634 break; 2635 default: 2636 sci_port_enable(sci_port); 2637 break; 2638 } 2639 } 2640 2641 static const char *sci_type(struct uart_port *port) 2642 { 2643 switch (port->type) { 2644 case PORT_IRDA: 2645 return "irda"; 2646 case PORT_SCI: 2647 return "sci"; 2648 case PORT_SCIF: 2649 return "scif"; 2650 case PORT_SCIFA: 2651 return "scifa"; 2652 case PORT_SCIFB: 2653 return "scifb"; 2654 case PORT_HSCIF: 2655 return "hscif"; 2656 } 2657 2658 return NULL; 2659 } 2660 2661 static int sci_remap_port(struct uart_port *port) 2662 { 2663 struct sci_port *sport = to_sci_port(port); 2664 2665 /* 2666 * Nothing to do if there's already an established membase. 2667 */ 2668 if (port->membase) 2669 return 0; 2670 2671 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2672 port->membase = ioremap(port->mapbase, sport->reg_size); 2673 if (unlikely(!port->membase)) { 2674 dev_err(port->dev, "can't remap port#%d\n", port->line); 2675 return -ENXIO; 2676 } 2677 } else { 2678 /* 2679 * For the simple (and majority of) cases where we don't 2680 * need to do any remapping, just cast the cookie 2681 * directly. 2682 */ 2683 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2684 } 2685 2686 return 0; 2687 } 2688 2689 static void sci_release_port(struct uart_port *port) 2690 { 2691 struct sci_port *sport = to_sci_port(port); 2692 2693 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2694 iounmap(port->membase); 2695 port->membase = NULL; 2696 } 2697 2698 release_mem_region(port->mapbase, sport->reg_size); 2699 } 2700 2701 static int sci_request_port(struct uart_port *port) 2702 { 2703 struct resource *res; 2704 struct sci_port *sport = to_sci_port(port); 2705 int ret; 2706 2707 res = request_mem_region(port->mapbase, sport->reg_size, 2708 dev_name(port->dev)); 2709 if (unlikely(res == NULL)) { 2710 dev_err(port->dev, "request_mem_region failed."); 2711 return -EBUSY; 2712 } 2713 2714 ret = sci_remap_port(port); 2715 if (unlikely(ret != 0)) { 2716 release_resource(res); 2717 return ret; 2718 } 2719 2720 return 0; 2721 } 2722 2723 static void sci_config_port(struct uart_port *port, int flags) 2724 { 2725 if (flags & UART_CONFIG_TYPE) { 2726 struct sci_port *sport = to_sci_port(port); 2727 2728 port->type = sport->cfg->type; 2729 sci_request_port(port); 2730 } 2731 } 2732 2733 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2734 { 2735 if (ser->baud_base < 2400) 2736 /* No paper tape reader for Mitch.. */ 2737 return -EINVAL; 2738 2739 return 0; 2740 } 2741 2742 static const struct uart_ops sci_uart_ops = { 2743 .tx_empty = sci_tx_empty, 2744 .set_mctrl = sci_set_mctrl, 2745 .get_mctrl = sci_get_mctrl, 2746 .start_tx = sci_start_tx, 2747 .stop_tx = sci_stop_tx, 2748 .stop_rx = sci_stop_rx, 2749 .enable_ms = sci_enable_ms, 2750 .break_ctl = sci_break_ctl, 2751 .startup = sci_startup, 2752 .shutdown = sci_shutdown, 2753 .flush_buffer = sci_flush_buffer, 2754 .set_termios = sci_set_termios, 2755 .pm = sci_pm, 2756 .type = sci_type, 2757 .release_port = sci_release_port, 2758 .request_port = sci_request_port, 2759 .config_port = sci_config_port, 2760 .verify_port = sci_verify_port, 2761 #ifdef CONFIG_CONSOLE_POLL 2762 .poll_get_char = sci_poll_get_char, 2763 .poll_put_char = sci_poll_put_char, 2764 #endif 2765 }; 2766 2767 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2768 { 2769 const char *clk_names[] = { 2770 [SCI_FCK] = "fck", 2771 [SCI_SCK] = "sck", 2772 [SCI_BRG_INT] = "brg_int", 2773 [SCI_SCIF_CLK] = "scif_clk", 2774 }; 2775 struct clk *clk; 2776 unsigned int i; 2777 2778 if (sci_port->cfg->type == PORT_HSCIF) 2779 clk_names[SCI_SCK] = "hsck"; 2780 2781 for (i = 0; i < SCI_NUM_CLKS; i++) { 2782 clk = devm_clk_get(dev, clk_names[i]); 2783 if (PTR_ERR(clk) == -EPROBE_DEFER) 2784 return -EPROBE_DEFER; 2785 2786 if (IS_ERR(clk) && i == SCI_FCK) { 2787 /* 2788 * Not all SH platforms declare a clock lookup entry 2789 * for SCI devices, in which case we need to get the 2790 * global "peripheral_clk" clock. 2791 */ 2792 clk = devm_clk_get(dev, "peripheral_clk"); 2793 if (!IS_ERR(clk)) 2794 goto found; 2795 2796 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2797 PTR_ERR(clk)); 2798 return PTR_ERR(clk); 2799 } 2800 2801 found: 2802 if (IS_ERR(clk)) 2803 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2804 PTR_ERR(clk)); 2805 else 2806 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2807 clk, clk_get_rate(clk)); 2808 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2809 } 2810 return 0; 2811 } 2812 2813 static const struct sci_port_params * 2814 sci_probe_regmap(const struct plat_sci_port *cfg) 2815 { 2816 unsigned int regtype; 2817 2818 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2819 return &sci_port_params[cfg->regtype]; 2820 2821 switch (cfg->type) { 2822 case PORT_SCI: 2823 regtype = SCIx_SCI_REGTYPE; 2824 break; 2825 case PORT_IRDA: 2826 regtype = SCIx_IRDA_REGTYPE; 2827 break; 2828 case PORT_SCIFA: 2829 regtype = SCIx_SCIFA_REGTYPE; 2830 break; 2831 case PORT_SCIFB: 2832 regtype = SCIx_SCIFB_REGTYPE; 2833 break; 2834 case PORT_SCIF: 2835 /* 2836 * The SH-4 is a bit of a misnomer here, although that's 2837 * where this particular port layout originated. This 2838 * configuration (or some slight variation thereof) 2839 * remains the dominant model for all SCIFs. 2840 */ 2841 regtype = SCIx_SH4_SCIF_REGTYPE; 2842 break; 2843 case PORT_HSCIF: 2844 regtype = SCIx_HSCIF_REGTYPE; 2845 break; 2846 default: 2847 pr_err("Can't probe register map for given port\n"); 2848 return NULL; 2849 } 2850 2851 return &sci_port_params[regtype]; 2852 } 2853 2854 static int sci_init_single(struct platform_device *dev, 2855 struct sci_port *sci_port, unsigned int index, 2856 const struct plat_sci_port *p, bool early) 2857 { 2858 struct uart_port *port = &sci_port->port; 2859 const struct resource *res; 2860 unsigned int i; 2861 int ret; 2862 2863 sci_port->cfg = p; 2864 2865 port->ops = &sci_uart_ops; 2866 port->iotype = UPIO_MEM; 2867 port->line = index; 2868 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2869 2870 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2871 if (res == NULL) 2872 return -ENOMEM; 2873 2874 port->mapbase = res->start; 2875 sci_port->reg_size = resource_size(res); 2876 2877 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2878 if (i) 2879 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2880 else 2881 sci_port->irqs[i] = platform_get_irq(dev, i); 2882 } 2883 2884 /* The SCI generates several interrupts. They can be muxed together or 2885 * connected to different interrupt lines. In the muxed case only one 2886 * interrupt resource is specified as there is only one interrupt ID. 2887 * In the non-muxed case, up to 6 interrupt signals might be generated 2888 * from the SCI, however those signals might have their own individual 2889 * interrupt ID numbers, or muxed together with another interrupt. 2890 */ 2891 if (sci_port->irqs[0] < 0) 2892 return -ENXIO; 2893 2894 if (sci_port->irqs[1] < 0) 2895 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2896 sci_port->irqs[i] = sci_port->irqs[0]; 2897 2898 sci_port->params = sci_probe_regmap(p); 2899 if (unlikely(sci_port->params == NULL)) 2900 return -EINVAL; 2901 2902 switch (p->type) { 2903 case PORT_SCIFB: 2904 sci_port->rx_trigger = 48; 2905 break; 2906 case PORT_HSCIF: 2907 sci_port->rx_trigger = 64; 2908 break; 2909 case PORT_SCIFA: 2910 sci_port->rx_trigger = 32; 2911 break; 2912 case PORT_SCIF: 2913 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2914 /* RX triggering not implemented for this IP */ 2915 sci_port->rx_trigger = 1; 2916 else 2917 sci_port->rx_trigger = 8; 2918 break; 2919 default: 2920 sci_port->rx_trigger = 1; 2921 break; 2922 } 2923 2924 sci_port->rx_fifo_timeout = 0; 2925 sci_port->hscif_tot = 0; 2926 2927 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2928 * match the SoC datasheet, this should be investigated. Let platform 2929 * data override the sampling rate for now. 2930 */ 2931 sci_port->sampling_rate_mask = p->sampling_rate 2932 ? SCI_SR(p->sampling_rate) 2933 : sci_port->params->sampling_rate_mask; 2934 2935 if (!early) { 2936 ret = sci_init_clocks(sci_port, &dev->dev); 2937 if (ret < 0) 2938 return ret; 2939 2940 port->dev = &dev->dev; 2941 2942 pm_runtime_enable(&dev->dev); 2943 } 2944 2945 port->type = p->type; 2946 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2947 port->fifosize = sci_port->params->fifosize; 2948 2949 if (port->type == PORT_SCI) { 2950 if (sci_port->reg_size >= 0x20) 2951 port->regshift = 2; 2952 else 2953 port->regshift = 1; 2954 } 2955 2956 /* 2957 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2958 * for the multi-IRQ ports, which is where we are primarily 2959 * concerned with the shutdown path synchronization. 2960 * 2961 * For the muxed case there's nothing more to do. 2962 */ 2963 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2964 port->irqflags = 0; 2965 2966 port->serial_in = sci_serial_in; 2967 port->serial_out = sci_serial_out; 2968 2969 return 0; 2970 } 2971 2972 static void sci_cleanup_single(struct sci_port *port) 2973 { 2974 pm_runtime_disable(port->port.dev); 2975 } 2976 2977 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2978 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2979 static void serial_console_putchar(struct uart_port *port, int ch) 2980 { 2981 sci_poll_put_char(port, ch); 2982 } 2983 2984 /* 2985 * Print a string to the serial port trying not to disturb 2986 * any possible real use of the port... 2987 */ 2988 static void serial_console_write(struct console *co, const char *s, 2989 unsigned count) 2990 { 2991 struct sci_port *sci_port = &sci_ports[co->index]; 2992 struct uart_port *port = &sci_port->port; 2993 unsigned short bits, ctrl, ctrl_temp; 2994 unsigned long flags; 2995 int locked = 1; 2996 2997 if (port->sysrq) 2998 locked = 0; 2999 else if (oops_in_progress) 3000 locked = spin_trylock_irqsave(&port->lock, flags); 3001 else 3002 spin_lock_irqsave(&port->lock, flags); 3003 3004 /* first save SCSCR then disable interrupts, keep clock source */ 3005 ctrl = serial_port_in(port, SCSCR); 3006 ctrl_temp = SCSCR_RE | SCSCR_TE | 3007 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3008 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3009 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3010 3011 uart_console_write(port, s, count, serial_console_putchar); 3012 3013 /* wait until fifo is empty and last bit has been transmitted */ 3014 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3015 while ((serial_port_in(port, SCxSR) & bits) != bits) 3016 cpu_relax(); 3017 3018 /* restore the SCSCR */ 3019 serial_port_out(port, SCSCR, ctrl); 3020 3021 if (locked) 3022 spin_unlock_irqrestore(&port->lock, flags); 3023 } 3024 3025 static int serial_console_setup(struct console *co, char *options) 3026 { 3027 struct sci_port *sci_port; 3028 struct uart_port *port; 3029 int baud = 115200; 3030 int bits = 8; 3031 int parity = 'n'; 3032 int flow = 'n'; 3033 int ret; 3034 3035 /* 3036 * Refuse to handle any bogus ports. 3037 */ 3038 if (co->index < 0 || co->index >= SCI_NPORTS) 3039 return -ENODEV; 3040 3041 sci_port = &sci_ports[co->index]; 3042 port = &sci_port->port; 3043 3044 /* 3045 * Refuse to handle uninitialized ports. 3046 */ 3047 if (!port->ops) 3048 return -ENODEV; 3049 3050 ret = sci_remap_port(port); 3051 if (unlikely(ret != 0)) 3052 return ret; 3053 3054 if (options) 3055 uart_parse_options(options, &baud, &parity, &bits, &flow); 3056 3057 return uart_set_options(port, co, baud, parity, bits, flow); 3058 } 3059 3060 static struct console serial_console = { 3061 .name = "ttySC", 3062 .device = uart_console_device, 3063 .write = serial_console_write, 3064 .setup = serial_console_setup, 3065 .flags = CON_PRINTBUFFER, 3066 .index = -1, 3067 .data = &sci_uart_driver, 3068 }; 3069 3070 #ifdef CONFIG_SUPERH 3071 static struct console early_serial_console = { 3072 .name = "early_ttySC", 3073 .write = serial_console_write, 3074 .flags = CON_PRINTBUFFER, 3075 .index = -1, 3076 }; 3077 3078 static char early_serial_buf[32]; 3079 3080 static int sci_probe_earlyprintk(struct platform_device *pdev) 3081 { 3082 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3083 3084 if (early_serial_console.data) 3085 return -EEXIST; 3086 3087 early_serial_console.index = pdev->id; 3088 3089 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3090 3091 serial_console_setup(&early_serial_console, early_serial_buf); 3092 3093 if (!strstr(early_serial_buf, "keep")) 3094 early_serial_console.flags |= CON_BOOT; 3095 3096 register_console(&early_serial_console); 3097 return 0; 3098 } 3099 #endif 3100 3101 #define SCI_CONSOLE (&serial_console) 3102 3103 #else 3104 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3105 { 3106 return -EINVAL; 3107 } 3108 3109 #define SCI_CONSOLE NULL 3110 3111 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3112 3113 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3114 3115 static DEFINE_MUTEX(sci_uart_registration_lock); 3116 static struct uart_driver sci_uart_driver = { 3117 .owner = THIS_MODULE, 3118 .driver_name = "sci", 3119 .dev_name = "ttySC", 3120 .major = SCI_MAJOR, 3121 .minor = SCI_MINOR_START, 3122 .nr = SCI_NPORTS, 3123 .cons = SCI_CONSOLE, 3124 }; 3125 3126 static int sci_remove(struct platform_device *dev) 3127 { 3128 struct sci_port *port = platform_get_drvdata(dev); 3129 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3130 3131 sci_ports_in_use &= ~BIT(port->port.line); 3132 uart_remove_one_port(&sci_uart_driver, &port->port); 3133 3134 sci_cleanup_single(port); 3135 3136 if (port->port.fifosize > 1) 3137 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3138 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3139 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3140 3141 return 0; 3142 } 3143 3144 3145 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3146 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3147 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3148 3149 static const struct of_device_id of_sci_match[] = { 3150 /* SoC-specific types */ 3151 { 3152 .compatible = "renesas,scif-r7s72100", 3153 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3154 }, 3155 { 3156 .compatible = "renesas,scif-r7s9210", 3157 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3158 }, 3159 { 3160 .compatible = "renesas,scif-r9a07g044", 3161 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3162 }, 3163 /* Family-specific types */ 3164 { 3165 .compatible = "renesas,rcar-gen1-scif", 3166 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3167 }, { 3168 .compatible = "renesas,rcar-gen2-scif", 3169 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3170 }, { 3171 .compatible = "renesas,rcar-gen3-scif", 3172 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3173 }, { 3174 .compatible = "renesas,rcar-gen4-scif", 3175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3176 }, 3177 /* Generic types */ 3178 { 3179 .compatible = "renesas,scif", 3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3181 }, { 3182 .compatible = "renesas,scifa", 3183 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3184 }, { 3185 .compatible = "renesas,scifb", 3186 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3187 }, { 3188 .compatible = "renesas,hscif", 3189 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3190 }, { 3191 .compatible = "renesas,sci", 3192 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3193 }, { 3194 /* Terminator */ 3195 }, 3196 }; 3197 MODULE_DEVICE_TABLE(of, of_sci_match); 3198 3199 static void sci_reset_control_assert(void *data) 3200 { 3201 reset_control_assert(data); 3202 } 3203 3204 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3205 unsigned int *dev_id) 3206 { 3207 struct device_node *np = pdev->dev.of_node; 3208 struct reset_control *rstc; 3209 struct plat_sci_port *p; 3210 struct sci_port *sp; 3211 const void *data; 3212 int id, ret; 3213 3214 if (!IS_ENABLED(CONFIG_OF) || !np) 3215 return ERR_PTR(-EINVAL); 3216 3217 data = of_device_get_match_data(&pdev->dev); 3218 3219 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3220 if (IS_ERR(rstc)) 3221 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3222 "failed to get reset ctrl\n")); 3223 3224 ret = reset_control_deassert(rstc); 3225 if (ret) { 3226 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3227 return ERR_PTR(ret); 3228 } 3229 3230 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3231 if (ret) { 3232 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3233 ret); 3234 return ERR_PTR(ret); 3235 } 3236 3237 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3238 if (!p) 3239 return ERR_PTR(-ENOMEM); 3240 3241 /* Get the line number from the aliases node. */ 3242 id = of_alias_get_id(np, "serial"); 3243 if (id < 0 && ~sci_ports_in_use) 3244 id = ffz(sci_ports_in_use); 3245 if (id < 0) { 3246 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3247 return ERR_PTR(-EINVAL); 3248 } 3249 if (id >= ARRAY_SIZE(sci_ports)) { 3250 dev_err(&pdev->dev, "serial%d out of range\n", id); 3251 return ERR_PTR(-EINVAL); 3252 } 3253 3254 sp = &sci_ports[id]; 3255 *dev_id = id; 3256 3257 p->type = SCI_OF_TYPE(data); 3258 p->regtype = SCI_OF_REGTYPE(data); 3259 3260 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3261 3262 return p; 3263 } 3264 3265 static int sci_probe_single(struct platform_device *dev, 3266 unsigned int index, 3267 struct plat_sci_port *p, 3268 struct sci_port *sciport) 3269 { 3270 int ret; 3271 3272 /* Sanity check */ 3273 if (unlikely(index >= SCI_NPORTS)) { 3274 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3275 index+1, SCI_NPORTS); 3276 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3277 return -EINVAL; 3278 } 3279 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3280 if (sci_ports_in_use & BIT(index)) 3281 return -EBUSY; 3282 3283 mutex_lock(&sci_uart_registration_lock); 3284 if (!sci_uart_driver.state) { 3285 ret = uart_register_driver(&sci_uart_driver); 3286 if (ret) { 3287 mutex_unlock(&sci_uart_registration_lock); 3288 return ret; 3289 } 3290 } 3291 mutex_unlock(&sci_uart_registration_lock); 3292 3293 ret = sci_init_single(dev, sciport, index, p, false); 3294 if (ret) 3295 return ret; 3296 3297 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3298 if (IS_ERR(sciport->gpios)) 3299 return PTR_ERR(sciport->gpios); 3300 3301 if (sciport->has_rtscts) { 3302 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3303 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3304 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3305 return -EINVAL; 3306 } 3307 sciport->port.flags |= UPF_HARD_FLOW; 3308 } 3309 3310 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3311 if (ret) { 3312 sci_cleanup_single(sciport); 3313 return ret; 3314 } 3315 3316 return 0; 3317 } 3318 3319 static int sci_probe(struct platform_device *dev) 3320 { 3321 struct plat_sci_port *p; 3322 struct sci_port *sp; 3323 unsigned int dev_id; 3324 int ret; 3325 3326 /* 3327 * If we've come here via earlyprintk initialization, head off to 3328 * the special early probe. We don't have sufficient device state 3329 * to make it beyond this yet. 3330 */ 3331 #ifdef CONFIG_SUPERH 3332 if (is_sh_early_platform_device(dev)) 3333 return sci_probe_earlyprintk(dev); 3334 #endif 3335 3336 if (dev->dev.of_node) { 3337 p = sci_parse_dt(dev, &dev_id); 3338 if (IS_ERR(p)) 3339 return PTR_ERR(p); 3340 } else { 3341 p = dev->dev.platform_data; 3342 if (p == NULL) { 3343 dev_err(&dev->dev, "no platform data supplied\n"); 3344 return -EINVAL; 3345 } 3346 3347 dev_id = dev->id; 3348 } 3349 3350 sp = &sci_ports[dev_id]; 3351 platform_set_drvdata(dev, sp); 3352 3353 ret = sci_probe_single(dev, dev_id, p, sp); 3354 if (ret) 3355 return ret; 3356 3357 if (sp->port.fifosize > 1) { 3358 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3359 if (ret) 3360 return ret; 3361 } 3362 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3363 sp->port.type == PORT_HSCIF) { 3364 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3365 if (ret) { 3366 if (sp->port.fifosize > 1) { 3367 device_remove_file(&dev->dev, 3368 &dev_attr_rx_fifo_trigger); 3369 } 3370 return ret; 3371 } 3372 } 3373 3374 #ifdef CONFIG_SH_STANDARD_BIOS 3375 sh_bios_gdb_detach(); 3376 #endif 3377 3378 sci_ports_in_use |= BIT(dev_id); 3379 return 0; 3380 } 3381 3382 static __maybe_unused int sci_suspend(struct device *dev) 3383 { 3384 struct sci_port *sport = dev_get_drvdata(dev); 3385 3386 if (sport) 3387 uart_suspend_port(&sci_uart_driver, &sport->port); 3388 3389 return 0; 3390 } 3391 3392 static __maybe_unused int sci_resume(struct device *dev) 3393 { 3394 struct sci_port *sport = dev_get_drvdata(dev); 3395 3396 if (sport) 3397 uart_resume_port(&sci_uart_driver, &sport->port); 3398 3399 return 0; 3400 } 3401 3402 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3403 3404 static struct platform_driver sci_driver = { 3405 .probe = sci_probe, 3406 .remove = sci_remove, 3407 .driver = { 3408 .name = "sh-sci", 3409 .pm = &sci_dev_pm_ops, 3410 .of_match_table = of_match_ptr(of_sci_match), 3411 }, 3412 }; 3413 3414 static int __init sci_init(void) 3415 { 3416 pr_info("%s\n", banner); 3417 3418 return platform_driver_register(&sci_driver); 3419 } 3420 3421 static void __exit sci_exit(void) 3422 { 3423 platform_driver_unregister(&sci_driver); 3424 3425 if (sci_uart_driver.state) 3426 uart_unregister_driver(&sci_uart_driver); 3427 } 3428 3429 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3430 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3431 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3432 #endif 3433 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3434 static struct plat_sci_port port_cfg __initdata; 3435 3436 static int __init early_console_setup(struct earlycon_device *device, 3437 int type) 3438 { 3439 if (!device->port.membase) 3440 return -ENODEV; 3441 3442 device->port.serial_in = sci_serial_in; 3443 device->port.serial_out = sci_serial_out; 3444 device->port.type = type; 3445 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3446 port_cfg.type = type; 3447 sci_ports[0].cfg = &port_cfg; 3448 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3449 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3450 sci_serial_out(&sci_ports[0].port, SCSCR, 3451 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3452 3453 device->con->write = serial_console_write; 3454 return 0; 3455 } 3456 static int __init sci_early_console_setup(struct earlycon_device *device, 3457 const char *opt) 3458 { 3459 return early_console_setup(device, PORT_SCI); 3460 } 3461 static int __init scif_early_console_setup(struct earlycon_device *device, 3462 const char *opt) 3463 { 3464 return early_console_setup(device, PORT_SCIF); 3465 } 3466 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3467 const char *opt) 3468 { 3469 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3470 return early_console_setup(device, PORT_SCIF); 3471 } 3472 3473 static int __init scifa_early_console_setup(struct earlycon_device *device, 3474 const char *opt) 3475 { 3476 return early_console_setup(device, PORT_SCIFA); 3477 } 3478 static int __init scifb_early_console_setup(struct earlycon_device *device, 3479 const char *opt) 3480 { 3481 return early_console_setup(device, PORT_SCIFB); 3482 } 3483 static int __init hscif_early_console_setup(struct earlycon_device *device, 3484 const char *opt) 3485 { 3486 return early_console_setup(device, PORT_HSCIF); 3487 } 3488 3489 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3490 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3491 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3492 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3493 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3494 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3495 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3496 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3497 3498 module_init(sci_init); 3499 module_exit(sci_exit); 3500 3501 MODULE_LICENSE("GPL"); 3502 MODULE_ALIAS("platform:sh-sci"); 3503 MODULE_AUTHOR("Paul Mundt"); 3504 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3505