1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 29 #define MAX310X_NAME "max310x" 30 #define MAX310X_MAJOR 204 31 #define MAX310X_MINOR 209 32 #define MAX310X_UART_NRMAX 16 33 34 /* MAX310X register definitions */ 35 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 36 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 37 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 38 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 39 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 40 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 41 #define MAX310X_REG_05 (0x05) 42 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 43 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 44 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 45 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 46 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 47 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 48 #define MAX310X_LCR_REG (0x0b) /* LCR */ 49 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 51 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 52 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 53 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 56 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 57 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 58 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 59 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 60 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 63 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 67 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 68 #define MAX310X_REG_1F (0x1f) 69 70 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 71 72 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 74 75 /* Extended registers */ 76 #define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 77 #define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */ 78 79 /* IRQ register bits */ 80 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 81 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 82 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 83 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 84 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 85 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 86 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 87 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 88 89 /* LSR register bits */ 90 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 91 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 92 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 93 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 94 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 95 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 97 98 /* Special character register bits */ 99 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 100 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 101 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 102 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 103 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 105 106 /* Status register bits */ 107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 111 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 112 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 113 114 /* MODE1 register bits */ 115 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 116 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 119 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 120 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 122 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 123 124 /* MODE2 register bits */ 125 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 126 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 129 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 130 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 132 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 133 134 /* LCR register bits */ 135 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 136 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 137 * 138 * Word length bits table: 139 * 00 -> 5 bit words 140 * 01 -> 6 bit words 141 * 10 -> 7 bit words 142 * 11 -> 8 bit words 143 */ 144 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 145 * 146 * STOP length bit table: 147 * 0 -> 1 stop bit 148 * 1 -> 1-1.5 stop bits if 149 * word length is 5, 150 * 2 stop bits otherwise 151 */ 152 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 153 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 155 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 156 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 157 158 /* IRDA register bits */ 159 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 160 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 161 162 /* Flow control trigger level register masks */ 163 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 164 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 165 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 166 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 167 168 /* FIFO interrupt trigger level register masks */ 169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 171 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 172 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 173 174 /* Flow control register bits */ 175 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 176 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 177 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 178 * are used in conjunction with 179 * XOFF2 for definition of 180 * special character */ 181 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 182 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 183 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 184 * 185 * SWFLOW bits 1 & 0 table: 186 * 00 -> no transmitter flow 187 * control 188 * 01 -> receiver compares 189 * XON2 and XOFF2 190 * and controls 191 * transmitter 192 * 10 -> receiver compares 193 * XON1 and XOFF1 194 * and controls 195 * transmitter 196 * 11 -> receiver compares 197 * XON1, XON2, XOFF1 and 198 * XOFF2 and controls 199 * transmitter 200 */ 201 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 202 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 203 * 204 * SWFLOW bits 3 & 2 table: 205 * 00 -> no received flow 206 * control 207 * 01 -> transmitter generates 208 * XON2 and XOFF2 209 * 10 -> transmitter generates 210 * XON1 and XOFF1 211 * 11 -> transmitter generates 212 * XON1, XON2, XOFF1 and 213 * XOFF2 214 */ 215 216 /* PLL configuration register masks */ 217 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 218 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 219 220 /* Baud rate generator configuration register bits */ 221 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 222 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 223 224 /* Clock source register bits */ 225 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 226 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 227 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 228 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 229 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 230 231 /* Global commands */ 232 #define MAX310X_EXTREG_ENBL (0xce) 233 #define MAX310X_EXTREG_DSBL (0xcd) 234 235 /* Misc definitions */ 236 #define MAX310X_FIFO_SIZE (128) 237 #define MAX310x_REV_MASK (0xf8) 238 #define MAX310X_WRITE_BIT 0x80 239 240 /* Crystal-related definitions */ 241 #define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */ 242 #define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */ 243 244 /* MAX3107 specific */ 245 #define MAX3107_REV_ID (0xa0) 246 247 /* MAX3109 specific */ 248 #define MAX3109_REV_ID (0xc0) 249 250 /* MAX14830 specific */ 251 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 252 #define MAX14830_REV_ID (0xb0) 253 254 struct max310x_if_cfg { 255 int (*extended_reg_enable)(struct device *dev, bool enable); 256 257 unsigned int rev_id_reg; 258 }; 259 260 struct max310x_devtype { 261 struct { 262 unsigned short min; 263 unsigned short max; 264 } slave_addr; 265 char name[9]; 266 int nr; 267 u8 mode1; 268 int (*detect)(struct device *); 269 void (*power)(struct uart_port *, int); 270 }; 271 272 struct max310x_one { 273 struct uart_port port; 274 struct work_struct tx_work; 275 struct work_struct md_work; 276 struct work_struct rs_work; 277 struct regmap *regmap; 278 279 u8 rx_buf[MAX310X_FIFO_SIZE]; 280 }; 281 #define to_max310x_port(_port) \ 282 container_of(_port, struct max310x_one, port) 283 284 struct max310x_port { 285 const struct max310x_devtype *devtype; 286 const struct max310x_if_cfg *if_cfg; 287 struct regmap *regmap; 288 struct clk *clk; 289 #ifdef CONFIG_GPIOLIB 290 struct gpio_chip gpio; 291 #endif 292 struct max310x_one p[]; 293 }; 294 295 static struct uart_driver max310x_uart = { 296 .owner = THIS_MODULE, 297 .driver_name = MAX310X_NAME, 298 .dev_name = "ttyMAX", 299 .major = MAX310X_MAJOR, 300 .minor = MAX310X_MINOR, 301 .nr = MAX310X_UART_NRMAX, 302 }; 303 304 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 305 306 static u8 max310x_port_read(struct uart_port *port, u8 reg) 307 { 308 struct max310x_one *one = to_max310x_port(port); 309 unsigned int val = 0; 310 311 regmap_read(one->regmap, reg, &val); 312 313 return val; 314 } 315 316 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 317 { 318 struct max310x_one *one = to_max310x_port(port); 319 320 regmap_write(one->regmap, reg, val); 321 } 322 323 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 324 { 325 struct max310x_one *one = to_max310x_port(port); 326 327 regmap_update_bits(one->regmap, reg, mask, val); 328 } 329 330 static int max3107_detect(struct device *dev) 331 { 332 struct max310x_port *s = dev_get_drvdata(dev); 333 unsigned int val = 0; 334 int ret; 335 336 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 337 if (ret) 338 return ret; 339 340 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 341 dev_err(dev, 342 "%s ID 0x%02x does not match\n", s->devtype->name, val); 343 return -ENODEV; 344 } 345 346 return 0; 347 } 348 349 static int max3108_detect(struct device *dev) 350 { 351 struct max310x_port *s = dev_get_drvdata(dev); 352 unsigned int val = 0; 353 int ret; 354 355 /* MAX3108 have not REV ID register, we just check default value 356 * from clocksource register to make sure everything works. 357 */ 358 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 359 if (ret) 360 return ret; 361 362 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 363 dev_err(dev, "%s not present\n", s->devtype->name); 364 return -ENODEV; 365 } 366 367 return 0; 368 } 369 370 static int max3109_detect(struct device *dev) 371 { 372 struct max310x_port *s = dev_get_drvdata(dev); 373 unsigned int val = 0; 374 int ret; 375 376 ret = s->if_cfg->extended_reg_enable(dev, true); 377 if (ret) 378 return ret; 379 380 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 381 s->if_cfg->extended_reg_enable(dev, false); 382 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 383 dev_err(dev, 384 "%s ID 0x%02x does not match\n", s->devtype->name, val); 385 return -ENODEV; 386 } 387 388 return 0; 389 } 390 391 static void max310x_power(struct uart_port *port, int on) 392 { 393 max310x_port_update(port, MAX310X_MODE1_REG, 394 MAX310X_MODE1_FORCESLEEP_BIT, 395 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 396 if (on) 397 msleep(50); 398 } 399 400 static int max14830_detect(struct device *dev) 401 { 402 struct max310x_port *s = dev_get_drvdata(dev); 403 unsigned int val = 0; 404 int ret; 405 406 ret = s->if_cfg->extended_reg_enable(dev, true); 407 if (ret) 408 return ret; 409 410 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 411 s->if_cfg->extended_reg_enable(dev, false); 412 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 413 dev_err(dev, 414 "%s ID 0x%02x does not match\n", s->devtype->name, val); 415 return -ENODEV; 416 } 417 418 return 0; 419 } 420 421 static void max14830_power(struct uart_port *port, int on) 422 { 423 max310x_port_update(port, MAX310X_BRGCFG_REG, 424 MAX14830_BRGCFG_CLKDIS_BIT, 425 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 426 if (on) 427 msleep(50); 428 } 429 430 static const struct max310x_devtype max3107_devtype = { 431 .name = "MAX3107", 432 .nr = 1, 433 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 434 .detect = max3107_detect, 435 .power = max310x_power, 436 .slave_addr = { 437 .min = 0x2c, 438 .max = 0x2f, 439 }, 440 }; 441 442 static const struct max310x_devtype max3108_devtype = { 443 .name = "MAX3108", 444 .nr = 1, 445 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 446 .detect = max3108_detect, 447 .power = max310x_power, 448 .slave_addr = { 449 .min = 0x60, 450 .max = 0x6f, 451 }, 452 }; 453 454 static const struct max310x_devtype max3109_devtype = { 455 .name = "MAX3109", 456 .nr = 2, 457 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 458 .detect = max3109_detect, 459 .power = max310x_power, 460 .slave_addr = { 461 .min = 0x60, 462 .max = 0x6f, 463 }, 464 }; 465 466 static const struct max310x_devtype max14830_devtype = { 467 .name = "MAX14830", 468 .nr = 4, 469 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 470 .detect = max14830_detect, 471 .power = max14830_power, 472 .slave_addr = { 473 .min = 0x60, 474 .max = 0x6f, 475 }, 476 }; 477 478 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 479 { 480 switch (reg) { 481 case MAX310X_IRQSTS_REG: 482 case MAX310X_LSR_IRQSTS_REG: 483 case MAX310X_SPCHR_IRQSTS_REG: 484 case MAX310X_STS_IRQSTS_REG: 485 case MAX310X_TXFIFOLVL_REG: 486 case MAX310X_RXFIFOLVL_REG: 487 return false; 488 default: 489 break; 490 } 491 492 return true; 493 } 494 495 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 496 { 497 switch (reg) { 498 case MAX310X_RHR_REG: 499 case MAX310X_IRQSTS_REG: 500 case MAX310X_LSR_IRQSTS_REG: 501 case MAX310X_SPCHR_IRQSTS_REG: 502 case MAX310X_STS_IRQSTS_REG: 503 case MAX310X_TXFIFOLVL_REG: 504 case MAX310X_RXFIFOLVL_REG: 505 case MAX310X_GPIODATA_REG: 506 case MAX310X_BRGDIVLSB_REG: 507 case MAX310X_REG_05: 508 case MAX310X_REG_1F: 509 return true; 510 default: 511 break; 512 } 513 514 return false; 515 } 516 517 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 518 { 519 switch (reg) { 520 case MAX310X_RHR_REG: 521 case MAX310X_IRQSTS_REG: 522 case MAX310X_SPCHR_IRQSTS_REG: 523 case MAX310X_STS_IRQSTS_REG: 524 return true; 525 default: 526 break; 527 } 528 529 return false; 530 } 531 532 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 533 { 534 return reg == MAX310X_RHR_REG; 535 } 536 537 static int max310x_set_baud(struct uart_port *port, int baud) 538 { 539 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 540 541 /* 542 * Calculate the integer divisor first. Select a proper mode 543 * in case if the requested baud is too high for the pre-defined 544 * clocks frequency. 545 */ 546 div = port->uartclk / baud; 547 if (div < 8) { 548 /* Mode x4 */ 549 c = 4; 550 mode = MAX310X_BRGCFG_4XMODE_BIT; 551 } else if (div < 16) { 552 /* Mode x2 */ 553 c = 8; 554 mode = MAX310X_BRGCFG_2XMODE_BIT; 555 } else { 556 c = 16; 557 } 558 559 /* Calculate the divisor in accordance with the fraction coefficient */ 560 div /= c; 561 F = c*baud; 562 563 /* Calculate the baud rate fraction */ 564 if (div > 0) 565 frac = (16*(port->uartclk % F)) / F; 566 else 567 div = 1; 568 569 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 570 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 571 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 572 573 /* Return the actual baud rate we just programmed */ 574 return (16*port->uartclk) / (c*(16*div + frac)); 575 } 576 577 static int max310x_update_best_err(unsigned long f, long *besterr) 578 { 579 /* Use baudrate 115200 for calculate error */ 580 long err = f % (460800 * 16); 581 582 if ((*besterr < 0) || (*besterr > err)) { 583 *besterr = err; 584 return 0; 585 } 586 587 return 1; 588 } 589 590 static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 591 unsigned long freq, bool xtal) 592 { 593 unsigned int div, clksrc, pllcfg = 0; 594 long besterr = -1; 595 unsigned long fdiv, fmul, bestfreq = freq; 596 597 /* First, update error without PLL */ 598 max310x_update_best_err(freq, &besterr); 599 600 /* Try all possible PLL dividers */ 601 for (div = 1; (div <= 63) && besterr; div++) { 602 fdiv = DIV_ROUND_CLOSEST(freq, div); 603 604 /* Try multiplier 6 */ 605 fmul = fdiv * 6; 606 if ((fdiv >= 500000) && (fdiv <= 800000)) 607 if (!max310x_update_best_err(fmul, &besterr)) { 608 pllcfg = (0 << 6) | div; 609 bestfreq = fmul; 610 } 611 /* Try multiplier 48 */ 612 fmul = fdiv * 48; 613 if ((fdiv >= 850000) && (fdiv <= 1200000)) 614 if (!max310x_update_best_err(fmul, &besterr)) { 615 pllcfg = (1 << 6) | div; 616 bestfreq = fmul; 617 } 618 /* Try multiplier 96 */ 619 fmul = fdiv * 96; 620 if ((fdiv >= 425000) && (fdiv <= 1000000)) 621 if (!max310x_update_best_err(fmul, &besterr)) { 622 pllcfg = (2 << 6) | div; 623 bestfreq = fmul; 624 } 625 /* Try multiplier 144 */ 626 fmul = fdiv * 144; 627 if ((fdiv >= 390000) && (fdiv <= 667000)) 628 if (!max310x_update_best_err(fmul, &besterr)) { 629 pllcfg = (3 << 6) | div; 630 bestfreq = fmul; 631 } 632 } 633 634 /* Configure clock source */ 635 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 636 637 /* Configure PLL */ 638 if (pllcfg) { 639 clksrc |= MAX310X_CLKSRC_PLL_BIT; 640 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 641 } else 642 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 643 644 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 645 646 /* Wait for crystal */ 647 if (xtal) { 648 bool stable = false; 649 unsigned int try = 0, val = 0; 650 651 do { 652 msleep(MAX310X_XTAL_WAIT_DELAY_MS); 653 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 654 655 if (val & MAX310X_STS_CLKREADY_BIT) 656 stable = true; 657 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES)); 658 659 if (!stable) 660 return dev_err_probe(dev, -EAGAIN, 661 "clock is not stable\n"); 662 } 663 664 return bestfreq; 665 } 666 667 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 668 { 669 struct max310x_one *one = to_max310x_port(port); 670 671 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 672 } 673 674 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 675 { 676 struct max310x_one *one = to_max310x_port(port); 677 678 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 679 } 680 681 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 682 { 683 struct max310x_one *one = to_max310x_port(port); 684 unsigned int sts, i; 685 u8 ch, flag; 686 687 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 688 /* We are just reading, happily ignoring any error conditions. 689 * Break condition, parity checking, framing errors -- they 690 * are all ignored. That means that we can do a batch-read. 691 * 692 * There is a small opportunity for race if the RX FIFO 693 * overruns while we're reading the buffer; the datasheets says 694 * that the LSR register applies to the "current" character. 695 * That's also the reason why we cannot do batched reads when 696 * asked to check the individual statuses. 697 * */ 698 699 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 700 max310x_batch_read(port, one->rx_buf, rxlen); 701 702 port->icount.rx += rxlen; 703 flag = TTY_NORMAL; 704 sts &= port->read_status_mask; 705 706 if (sts & MAX310X_LSR_RXOVR_BIT) { 707 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 708 port->icount.overrun++; 709 } 710 711 for (i = 0; i < (rxlen - 1); ++i) 712 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 713 714 /* 715 * Handle the overrun case for the last character only, since 716 * the RxFIFO overflow happens after it is pushed to the FIFO 717 * tail. 718 */ 719 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 720 one->rx_buf[rxlen-1], flag); 721 722 } else { 723 if (unlikely(rxlen >= port->fifosize)) { 724 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 725 port->icount.buf_overrun++; 726 /* Ensure sanity of RX level */ 727 rxlen = port->fifosize; 728 } 729 730 while (rxlen--) { 731 ch = max310x_port_read(port, MAX310X_RHR_REG); 732 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 733 734 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 735 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 736 737 port->icount.rx++; 738 flag = TTY_NORMAL; 739 740 if (unlikely(sts)) { 741 if (sts & MAX310X_LSR_RXBRK_BIT) { 742 port->icount.brk++; 743 if (uart_handle_break(port)) 744 continue; 745 } else if (sts & MAX310X_LSR_RXPAR_BIT) 746 port->icount.parity++; 747 else if (sts & MAX310X_LSR_FRERR_BIT) 748 port->icount.frame++; 749 else if (sts & MAX310X_LSR_RXOVR_BIT) 750 port->icount.overrun++; 751 752 sts &= port->read_status_mask; 753 if (sts & MAX310X_LSR_RXBRK_BIT) 754 flag = TTY_BREAK; 755 else if (sts & MAX310X_LSR_RXPAR_BIT) 756 flag = TTY_PARITY; 757 else if (sts & MAX310X_LSR_FRERR_BIT) 758 flag = TTY_FRAME; 759 else if (sts & MAX310X_LSR_RXOVR_BIT) 760 flag = TTY_OVERRUN; 761 } 762 763 if (uart_handle_sysrq_char(port, ch)) 764 continue; 765 766 if (sts & port->ignore_status_mask) 767 continue; 768 769 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 770 } 771 } 772 773 tty_flip_buffer_push(&port->state->port); 774 } 775 776 static void max310x_handle_tx(struct uart_port *port) 777 { 778 struct circ_buf *xmit = &port->state->xmit; 779 unsigned int txlen, to_send, until_end; 780 781 if (unlikely(port->x_char)) { 782 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 783 port->icount.tx++; 784 port->x_char = 0; 785 return; 786 } 787 788 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 789 return; 790 791 /* Get length of data pending in circular buffer */ 792 to_send = uart_circ_chars_pending(xmit); 793 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 794 if (likely(to_send)) { 795 /* Limit to size of TX FIFO */ 796 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 797 txlen = port->fifosize - txlen; 798 to_send = (to_send > txlen) ? txlen : to_send; 799 800 if (until_end < to_send) { 801 /* It's a circ buffer -- wrap around. 802 * We could do that in one SPI transaction, but meh. */ 803 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 804 max310x_batch_write(port, xmit->buf, to_send - until_end); 805 } else { 806 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 807 } 808 uart_xmit_advance(port, to_send); 809 } 810 811 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 812 uart_write_wakeup(port); 813 } 814 815 static void max310x_start_tx(struct uart_port *port) 816 { 817 struct max310x_one *one = to_max310x_port(port); 818 819 schedule_work(&one->tx_work); 820 } 821 822 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 823 { 824 struct uart_port *port = &s->p[portno].port; 825 irqreturn_t res = IRQ_NONE; 826 827 do { 828 unsigned int ists, lsr, rxlen; 829 830 /* Read IRQ status & RX FIFO level */ 831 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 832 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 833 if (!ists && !rxlen) 834 break; 835 836 res = IRQ_HANDLED; 837 838 if (ists & MAX310X_IRQ_CTS_BIT) { 839 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 840 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 841 } 842 if (rxlen) 843 max310x_handle_rx(port, rxlen); 844 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 845 max310x_start_tx(port); 846 } while (1); 847 return res; 848 } 849 850 static irqreturn_t max310x_ist(int irq, void *dev_id) 851 { 852 struct max310x_port *s = (struct max310x_port *)dev_id; 853 bool handled = false; 854 855 if (s->devtype->nr > 1) { 856 do { 857 unsigned int val = ~0; 858 859 WARN_ON_ONCE(regmap_read(s->regmap, 860 MAX310X_GLOBALIRQ_REG, &val)); 861 val = ((1 << s->devtype->nr) - 1) & ~val; 862 if (!val) 863 break; 864 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 865 handled = true; 866 } while (1); 867 } else { 868 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 869 handled = true; 870 } 871 872 return IRQ_RETVAL(handled); 873 } 874 875 static void max310x_tx_proc(struct work_struct *ws) 876 { 877 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 878 879 max310x_handle_tx(&one->port); 880 } 881 882 static unsigned int max310x_tx_empty(struct uart_port *port) 883 { 884 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 885 886 return lvl ? 0 : TIOCSER_TEMT; 887 } 888 889 static unsigned int max310x_get_mctrl(struct uart_port *port) 890 { 891 /* DCD and DSR are not wired and CTS/RTS is handled automatically 892 * so just indicate DSR and CAR asserted 893 */ 894 return TIOCM_DSR | TIOCM_CAR; 895 } 896 897 static void max310x_md_proc(struct work_struct *ws) 898 { 899 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 900 901 max310x_port_update(&one->port, MAX310X_MODE2_REG, 902 MAX310X_MODE2_LOOPBACK_BIT, 903 (one->port.mctrl & TIOCM_LOOP) ? 904 MAX310X_MODE2_LOOPBACK_BIT : 0); 905 } 906 907 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 908 { 909 struct max310x_one *one = to_max310x_port(port); 910 911 schedule_work(&one->md_work); 912 } 913 914 static void max310x_break_ctl(struct uart_port *port, int break_state) 915 { 916 max310x_port_update(port, MAX310X_LCR_REG, 917 MAX310X_LCR_TXBREAK_BIT, 918 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 919 } 920 921 static void max310x_set_termios(struct uart_port *port, 922 struct ktermios *termios, 923 const struct ktermios *old) 924 { 925 unsigned int lcr = 0, flow = 0; 926 int baud; 927 928 /* Mask termios capabilities we don't support */ 929 termios->c_cflag &= ~CMSPAR; 930 931 /* Word size */ 932 switch (termios->c_cflag & CSIZE) { 933 case CS5: 934 break; 935 case CS6: 936 lcr = MAX310X_LCR_LENGTH0_BIT; 937 break; 938 case CS7: 939 lcr = MAX310X_LCR_LENGTH1_BIT; 940 break; 941 case CS8: 942 default: 943 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 944 break; 945 } 946 947 /* Parity */ 948 if (termios->c_cflag & PARENB) { 949 lcr |= MAX310X_LCR_PARITY_BIT; 950 if (!(termios->c_cflag & PARODD)) 951 lcr |= MAX310X_LCR_EVENPARITY_BIT; 952 } 953 954 /* Stop bits */ 955 if (termios->c_cflag & CSTOPB) 956 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 957 958 /* Update LCR register */ 959 max310x_port_write(port, MAX310X_LCR_REG, lcr); 960 961 /* Set read status mask */ 962 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 963 if (termios->c_iflag & INPCK) 964 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 965 MAX310X_LSR_FRERR_BIT; 966 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 967 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 968 969 /* Set status ignore mask */ 970 port->ignore_status_mask = 0; 971 if (termios->c_iflag & IGNBRK) 972 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 973 if (!(termios->c_cflag & CREAD)) 974 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 975 MAX310X_LSR_RXOVR_BIT | 976 MAX310X_LSR_FRERR_BIT | 977 MAX310X_LSR_RXBRK_BIT; 978 979 /* Configure flow control */ 980 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 981 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 982 983 /* Disable transmitter before enabling AutoCTS or auto transmitter 984 * flow control 985 */ 986 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 987 max310x_port_update(port, MAX310X_MODE1_REG, 988 MAX310X_MODE1_TXDIS_BIT, 989 MAX310X_MODE1_TXDIS_BIT); 990 } 991 992 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 993 994 if (termios->c_cflag & CRTSCTS) { 995 /* Enable AUTORTS and AUTOCTS */ 996 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 997 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 998 MAX310X_FLOWCTRL_AUTORTS_BIT; 999 } 1000 if (termios->c_iflag & IXON) 1001 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 1002 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1003 if (termios->c_iflag & IXOFF) { 1004 port->status |= UPSTAT_AUTOXOFF; 1005 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 1006 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1007 } 1008 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 1009 1010 /* Enable transmitter after disabling AutoCTS and auto transmitter 1011 * flow control 1012 */ 1013 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1014 max310x_port_update(port, MAX310X_MODE1_REG, 1015 MAX310X_MODE1_TXDIS_BIT, 1016 0); 1017 } 1018 1019 /* Get baud rate generator configuration */ 1020 baud = uart_get_baud_rate(port, termios, old, 1021 port->uartclk / 16 / 0xffff, 1022 port->uartclk / 4); 1023 1024 /* Setup baudrate generator */ 1025 baud = max310x_set_baud(port, baud); 1026 1027 /* Update timeout according to new baud rate */ 1028 uart_update_timeout(port, termios->c_cflag, baud); 1029 } 1030 1031 static void max310x_rs_proc(struct work_struct *ws) 1032 { 1033 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1034 unsigned int delay, mode1 = 0, mode2 = 0; 1035 1036 delay = (one->port.rs485.delay_rts_before_send << 4) | 1037 one->port.rs485.delay_rts_after_send; 1038 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1039 1040 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1041 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1042 1043 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1044 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1045 } 1046 1047 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1048 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1049 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1050 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1051 } 1052 1053 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1054 struct serial_rs485 *rs485) 1055 { 1056 struct max310x_one *one = to_max310x_port(port); 1057 1058 if ((rs485->delay_rts_before_send > 0x0f) || 1059 (rs485->delay_rts_after_send > 0x0f)) 1060 return -ERANGE; 1061 1062 port->rs485 = *rs485; 1063 1064 schedule_work(&one->rs_work); 1065 1066 return 0; 1067 } 1068 1069 static int max310x_startup(struct uart_port *port) 1070 { 1071 struct max310x_port *s = dev_get_drvdata(port->dev); 1072 unsigned int val; 1073 1074 s->devtype->power(port, 1); 1075 1076 /* Configure MODE1 register */ 1077 max310x_port_update(port, MAX310X_MODE1_REG, 1078 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1079 1080 /* Configure MODE2 register & Reset FIFOs*/ 1081 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1082 max310x_port_write(port, MAX310X_MODE2_REG, val); 1083 max310x_port_update(port, MAX310X_MODE2_REG, 1084 MAX310X_MODE2_FIFORST_BIT, 0); 1085 1086 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1087 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1088 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1089 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1090 1091 if (port->rs485.flags & SER_RS485_ENABLED) { 1092 max310x_port_update(port, MAX310X_MODE1_REG, 1093 MAX310X_MODE1_TRNSCVCTRL_BIT, 1094 MAX310X_MODE1_TRNSCVCTRL_BIT); 1095 1096 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1097 max310x_port_update(port, MAX310X_MODE2_REG, 1098 MAX310X_MODE2_ECHOSUPR_BIT, 1099 MAX310X_MODE2_ECHOSUPR_BIT); 1100 } 1101 1102 /* Configure flow control levels */ 1103 /* Flow control halt level 96, resume level 48 */ 1104 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1105 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1106 1107 /* Clear IRQ status register */ 1108 max310x_port_read(port, MAX310X_IRQSTS_REG); 1109 1110 /* Enable RX, TX, CTS change interrupts */ 1111 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1112 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1113 1114 return 0; 1115 } 1116 1117 static void max310x_shutdown(struct uart_port *port) 1118 { 1119 struct max310x_port *s = dev_get_drvdata(port->dev); 1120 1121 /* Disable all interrupts */ 1122 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1123 1124 s->devtype->power(port, 0); 1125 } 1126 1127 static const char *max310x_type(struct uart_port *port) 1128 { 1129 struct max310x_port *s = dev_get_drvdata(port->dev); 1130 1131 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1132 } 1133 1134 static int max310x_request_port(struct uart_port *port) 1135 { 1136 /* Do nothing */ 1137 return 0; 1138 } 1139 1140 static void max310x_config_port(struct uart_port *port, int flags) 1141 { 1142 if (flags & UART_CONFIG_TYPE) 1143 port->type = PORT_MAX310X; 1144 } 1145 1146 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1147 { 1148 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1149 return -EINVAL; 1150 if (s->irq != port->irq) 1151 return -EINVAL; 1152 1153 return 0; 1154 } 1155 1156 static void max310x_null_void(struct uart_port *port) 1157 { 1158 /* Do nothing */ 1159 } 1160 1161 static const struct uart_ops max310x_ops = { 1162 .tx_empty = max310x_tx_empty, 1163 .set_mctrl = max310x_set_mctrl, 1164 .get_mctrl = max310x_get_mctrl, 1165 .stop_tx = max310x_null_void, 1166 .start_tx = max310x_start_tx, 1167 .stop_rx = max310x_null_void, 1168 .break_ctl = max310x_break_ctl, 1169 .startup = max310x_startup, 1170 .shutdown = max310x_shutdown, 1171 .set_termios = max310x_set_termios, 1172 .type = max310x_type, 1173 .request_port = max310x_request_port, 1174 .release_port = max310x_null_void, 1175 .config_port = max310x_config_port, 1176 .verify_port = max310x_verify_port, 1177 }; 1178 1179 static int __maybe_unused max310x_suspend(struct device *dev) 1180 { 1181 struct max310x_port *s = dev_get_drvdata(dev); 1182 int i; 1183 1184 for (i = 0; i < s->devtype->nr; i++) { 1185 uart_suspend_port(&max310x_uart, &s->p[i].port); 1186 s->devtype->power(&s->p[i].port, 0); 1187 } 1188 1189 return 0; 1190 } 1191 1192 static int __maybe_unused max310x_resume(struct device *dev) 1193 { 1194 struct max310x_port *s = dev_get_drvdata(dev); 1195 int i; 1196 1197 for (i = 0; i < s->devtype->nr; i++) { 1198 s->devtype->power(&s->p[i].port, 1); 1199 uart_resume_port(&max310x_uart, &s->p[i].port); 1200 } 1201 1202 return 0; 1203 } 1204 1205 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1206 1207 #ifdef CONFIG_GPIOLIB 1208 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1209 { 1210 unsigned int val; 1211 struct max310x_port *s = gpiochip_get_data(chip); 1212 struct uart_port *port = &s->p[offset / 4].port; 1213 1214 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1215 1216 return !!((val >> 4) & (1 << (offset % 4))); 1217 } 1218 1219 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1220 { 1221 struct max310x_port *s = gpiochip_get_data(chip); 1222 struct uart_port *port = &s->p[offset / 4].port; 1223 1224 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1225 value ? 1 << (offset % 4) : 0); 1226 } 1227 1228 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1229 { 1230 struct max310x_port *s = gpiochip_get_data(chip); 1231 struct uart_port *port = &s->p[offset / 4].port; 1232 1233 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1234 1235 return 0; 1236 } 1237 1238 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1239 unsigned offset, int value) 1240 { 1241 struct max310x_port *s = gpiochip_get_data(chip); 1242 struct uart_port *port = &s->p[offset / 4].port; 1243 1244 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1245 value ? 1 << (offset % 4) : 0); 1246 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1247 1 << (offset % 4)); 1248 1249 return 0; 1250 } 1251 1252 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1253 unsigned long config) 1254 { 1255 struct max310x_port *s = gpiochip_get_data(chip); 1256 struct uart_port *port = &s->p[offset / 4].port; 1257 1258 switch (pinconf_to_config_param(config)) { 1259 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1260 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1261 1 << ((offset % 4) + 4), 1262 1 << ((offset % 4) + 4)); 1263 return 0; 1264 case PIN_CONFIG_DRIVE_PUSH_PULL: 1265 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1266 1 << ((offset % 4) + 4), 0); 1267 return 0; 1268 default: 1269 return -ENOTSUPP; 1270 } 1271 } 1272 #endif 1273 1274 static const struct serial_rs485 max310x_rs485_supported = { 1275 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1276 .delay_rts_before_send = 1, 1277 .delay_rts_after_send = 1, 1278 }; 1279 1280 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1281 const struct max310x_if_cfg *if_cfg, 1282 struct regmap *regmaps[], int irq) 1283 { 1284 int i, ret, fmin, fmax, freq; 1285 struct max310x_port *s; 1286 s32 uartclk = 0; 1287 bool xtal; 1288 1289 for (i = 0; i < devtype->nr; i++) 1290 if (IS_ERR(regmaps[i])) 1291 return PTR_ERR(regmaps[i]); 1292 1293 /* Alloc port structure */ 1294 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1295 if (!s) { 1296 dev_err(dev, "Error allocating port structure\n"); 1297 return -ENOMEM; 1298 } 1299 1300 /* Always ask for fixed clock rate from a property. */ 1301 device_property_read_u32(dev, "clock-frequency", &uartclk); 1302 1303 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1304 if (xtal) 1305 s->clk = devm_clk_get_optional(dev, "xtal"); 1306 else 1307 s->clk = devm_clk_get_optional(dev, "osc"); 1308 if (IS_ERR(s->clk)) 1309 return PTR_ERR(s->clk); 1310 1311 ret = clk_prepare_enable(s->clk); 1312 if (ret) 1313 return ret; 1314 1315 freq = clk_get_rate(s->clk); 1316 if (freq == 0) 1317 freq = uartclk; 1318 if (freq == 0) { 1319 dev_err(dev, "Cannot get clock rate\n"); 1320 ret = -EINVAL; 1321 goto out_clk; 1322 } 1323 1324 if (xtal) { 1325 fmin = 1000000; 1326 fmax = 4000000; 1327 } else { 1328 fmin = 500000; 1329 fmax = 35000000; 1330 } 1331 1332 /* Check frequency limits */ 1333 if (freq < fmin || freq > fmax) { 1334 ret = -ERANGE; 1335 goto out_clk; 1336 } 1337 1338 s->regmap = regmaps[0]; 1339 s->devtype = devtype; 1340 s->if_cfg = if_cfg; 1341 dev_set_drvdata(dev, s); 1342 1343 /* Check device to ensure we are talking to what we expect */ 1344 ret = devtype->detect(dev); 1345 if (ret) 1346 goto out_clk; 1347 1348 for (i = 0; i < devtype->nr; i++) { 1349 /* Reset port */ 1350 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1351 MAX310X_MODE2_RST_BIT); 1352 /* Clear port reset */ 1353 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1354 1355 /* Wait for port startup */ 1356 do { 1357 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret); 1358 } while (ret != 0x01); 1359 1360 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1361 } 1362 1363 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1364 if (uartclk < 0) { 1365 ret = uartclk; 1366 goto out_uart; 1367 } 1368 1369 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1370 1371 for (i = 0; i < devtype->nr; i++) { 1372 unsigned int line; 1373 1374 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1375 if (line == MAX310X_UART_NRMAX) { 1376 ret = -ERANGE; 1377 goto out_uart; 1378 } 1379 1380 /* Initialize port data */ 1381 s->p[i].port.line = line; 1382 s->p[i].port.dev = dev; 1383 s->p[i].port.irq = irq; 1384 s->p[i].port.type = PORT_MAX310X; 1385 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1386 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1387 s->p[i].port.iotype = UPIO_PORT; 1388 s->p[i].port.iobase = i; 1389 /* 1390 * Use all ones as membase to make sure uart_configure_port() in 1391 * serial_core.c does not abort for SPI/I2C devices where the 1392 * membase address is not applicable. 1393 */ 1394 s->p[i].port.membase = (void __iomem *)~0; 1395 s->p[i].port.uartclk = uartclk; 1396 s->p[i].port.rs485_config = max310x_rs485_config; 1397 s->p[i].port.rs485_supported = max310x_rs485_supported; 1398 s->p[i].port.ops = &max310x_ops; 1399 s->p[i].regmap = regmaps[i]; 1400 1401 /* Disable all interrupts */ 1402 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1403 /* Clear IRQ status register */ 1404 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1405 /* Initialize queue for start TX */ 1406 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1407 /* Initialize queue for changing LOOPBACK mode */ 1408 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1409 /* Initialize queue for changing RS485 mode */ 1410 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1411 1412 /* Register port */ 1413 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1414 if (ret) { 1415 s->p[i].port.dev = NULL; 1416 goto out_uart; 1417 } 1418 set_bit(line, max310x_lines); 1419 1420 /* Go to suspend mode */ 1421 devtype->power(&s->p[i].port, 0); 1422 } 1423 1424 #ifdef CONFIG_GPIOLIB 1425 /* Setup GPIO controller */ 1426 s->gpio.owner = THIS_MODULE; 1427 s->gpio.parent = dev; 1428 s->gpio.label = devtype->name; 1429 s->gpio.direction_input = max310x_gpio_direction_input; 1430 s->gpio.get = max310x_gpio_get; 1431 s->gpio.direction_output= max310x_gpio_direction_output; 1432 s->gpio.set = max310x_gpio_set; 1433 s->gpio.set_config = max310x_gpio_set_config; 1434 s->gpio.base = -1; 1435 s->gpio.ngpio = devtype->nr * 4; 1436 s->gpio.can_sleep = 1; 1437 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1438 if (ret) 1439 goto out_uart; 1440 #endif 1441 1442 /* Setup interrupt */ 1443 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1444 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1445 if (!ret) 1446 return 0; 1447 1448 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1449 1450 out_uart: 1451 for (i = 0; i < devtype->nr; i++) { 1452 if (s->p[i].port.dev) { 1453 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1454 clear_bit(s->p[i].port.line, max310x_lines); 1455 } 1456 } 1457 1458 out_clk: 1459 clk_disable_unprepare(s->clk); 1460 1461 return ret; 1462 } 1463 1464 static void max310x_remove(struct device *dev) 1465 { 1466 struct max310x_port *s = dev_get_drvdata(dev); 1467 int i; 1468 1469 for (i = 0; i < s->devtype->nr; i++) { 1470 cancel_work_sync(&s->p[i].tx_work); 1471 cancel_work_sync(&s->p[i].md_work); 1472 cancel_work_sync(&s->p[i].rs_work); 1473 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1474 clear_bit(s->p[i].port.line, max310x_lines); 1475 s->devtype->power(&s->p[i].port, 0); 1476 } 1477 1478 clk_disable_unprepare(s->clk); 1479 } 1480 1481 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1482 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1483 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1484 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1485 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1486 { } 1487 }; 1488 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1489 1490 static struct regmap_config regcfg = { 1491 .reg_bits = 8, 1492 .val_bits = 8, 1493 .write_flag_mask = MAX310X_WRITE_BIT, 1494 .cache_type = REGCACHE_RBTREE, 1495 .max_register = MAX310X_REG_1F, 1496 .writeable_reg = max310x_reg_writeable, 1497 .volatile_reg = max310x_reg_volatile, 1498 .precious_reg = max310x_reg_precious, 1499 .writeable_noinc_reg = max310x_reg_noinc, 1500 .readable_noinc_reg = max310x_reg_noinc, 1501 .max_raw_read = MAX310X_FIFO_SIZE, 1502 .max_raw_write = MAX310X_FIFO_SIZE, 1503 }; 1504 1505 #ifdef CONFIG_SPI_MASTER 1506 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1507 { 1508 struct max310x_port *s = dev_get_drvdata(dev); 1509 1510 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1511 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1512 } 1513 1514 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1515 .extended_reg_enable = max310x_spi_extended_reg_enable, 1516 .rev_id_reg = MAX310X_SPI_REVID_EXTREG, 1517 }; 1518 1519 static int max310x_spi_probe(struct spi_device *spi) 1520 { 1521 const struct max310x_devtype *devtype; 1522 struct regmap *regmaps[4]; 1523 unsigned int i; 1524 int ret; 1525 1526 /* Setup SPI bus */ 1527 spi->bits_per_word = 8; 1528 spi->mode = spi->mode ? : SPI_MODE_0; 1529 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1530 ret = spi_setup(spi); 1531 if (ret) 1532 return ret; 1533 1534 devtype = device_get_match_data(&spi->dev); 1535 if (!devtype) 1536 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; 1537 1538 for (i = 0; i < devtype->nr; i++) { 1539 u8 port_mask = i * 0x20; 1540 regcfg.read_flag_mask = port_mask; 1541 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1542 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1543 } 1544 1545 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1546 } 1547 1548 static void max310x_spi_remove(struct spi_device *spi) 1549 { 1550 max310x_remove(&spi->dev); 1551 } 1552 1553 static const struct spi_device_id max310x_id_table[] = { 1554 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1555 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1556 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1557 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1558 { } 1559 }; 1560 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1561 1562 static struct spi_driver max310x_spi_driver = { 1563 .driver = { 1564 .name = MAX310X_NAME, 1565 .of_match_table = max310x_dt_ids, 1566 .pm = &max310x_pm_ops, 1567 }, 1568 .probe = max310x_spi_probe, 1569 .remove = max310x_spi_remove, 1570 .id_table = max310x_id_table, 1571 }; 1572 #endif 1573 1574 #ifdef CONFIG_I2C 1575 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1576 { 1577 return 0; 1578 } 1579 1580 static struct regmap_config regcfg_i2c = { 1581 .reg_bits = 8, 1582 .val_bits = 8, 1583 .cache_type = REGCACHE_RBTREE, 1584 .writeable_reg = max310x_reg_writeable, 1585 .volatile_reg = max310x_reg_volatile, 1586 .precious_reg = max310x_reg_precious, 1587 .max_register = MAX310X_I2C_REVID_EXTREG, 1588 .writeable_noinc_reg = max310x_reg_noinc, 1589 .readable_noinc_reg = max310x_reg_noinc, 1590 .max_raw_read = MAX310X_FIFO_SIZE, 1591 .max_raw_write = MAX310X_FIFO_SIZE, 1592 }; 1593 1594 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1595 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1596 .rev_id_reg = MAX310X_I2C_REVID_EXTREG, 1597 }; 1598 1599 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1600 unsigned int nr) 1601 { 1602 /* 1603 * For MAX14830 and MAX3109, the slave address depends on what the 1604 * A0 and A1 pins are tied to. 1605 * See Table I2C Address Map of the datasheet. 1606 * Based on that table, the following formulas were determined. 1607 * UART1 - UART0 = 0x10 1608 * UART2 - UART1 = 0x20 + 0x10 1609 * UART3 - UART2 = 0x10 1610 */ 1611 1612 addr -= nr * 0x10; 1613 1614 if (nr >= 2) 1615 addr -= 0x20; 1616 1617 return addr; 1618 } 1619 1620 static int max310x_i2c_probe(struct i2c_client *client) 1621 { 1622 const struct max310x_devtype *devtype = 1623 device_get_match_data(&client->dev); 1624 struct i2c_client *port_client; 1625 struct regmap *regmaps[4]; 1626 unsigned int i; 1627 u8 port_addr; 1628 1629 if (client->addr < devtype->slave_addr.min || 1630 client->addr > devtype->slave_addr.max) 1631 return dev_err_probe(&client->dev, -EINVAL, 1632 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1633 client->addr, devtype->slave_addr.min, 1634 devtype->slave_addr.max); 1635 1636 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1637 1638 for (i = 1; i < devtype->nr; i++) { 1639 port_addr = max310x_i2c_slave_addr(client->addr, i); 1640 port_client = devm_i2c_new_dummy_device(&client->dev, 1641 client->adapter, 1642 port_addr); 1643 1644 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1645 } 1646 1647 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1648 regmaps, client->irq); 1649 } 1650 1651 static void max310x_i2c_remove(struct i2c_client *client) 1652 { 1653 max310x_remove(&client->dev); 1654 } 1655 1656 static struct i2c_driver max310x_i2c_driver = { 1657 .driver = { 1658 .name = MAX310X_NAME, 1659 .of_match_table = max310x_dt_ids, 1660 .pm = &max310x_pm_ops, 1661 }, 1662 .probe = max310x_i2c_probe, 1663 .remove = max310x_i2c_remove, 1664 }; 1665 #endif 1666 1667 static int __init max310x_uart_init(void) 1668 { 1669 int ret; 1670 1671 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1672 1673 ret = uart_register_driver(&max310x_uart); 1674 if (ret) 1675 return ret; 1676 1677 #ifdef CONFIG_SPI_MASTER 1678 ret = spi_register_driver(&max310x_spi_driver); 1679 if (ret) 1680 goto err_spi_register; 1681 #endif 1682 1683 #ifdef CONFIG_I2C 1684 ret = i2c_add_driver(&max310x_i2c_driver); 1685 if (ret) 1686 goto err_i2c_register; 1687 #endif 1688 1689 return 0; 1690 1691 #ifdef CONFIG_I2C 1692 err_i2c_register: 1693 spi_unregister_driver(&max310x_spi_driver); 1694 #endif 1695 1696 err_spi_register: 1697 uart_unregister_driver(&max310x_uart); 1698 1699 return ret; 1700 } 1701 module_init(max310x_uart_init); 1702 1703 static void __exit max310x_uart_exit(void) 1704 { 1705 #ifdef CONFIG_I2C 1706 i2c_del_driver(&max310x_i2c_driver); 1707 #endif 1708 1709 #ifdef CONFIG_SPI_MASTER 1710 spi_unregister_driver(&max310x_spi_driver); 1711 #endif 1712 1713 uart_unregister_driver(&max310x_uart); 1714 } 1715 module_exit(max310x_uart_exit); 1716 1717 MODULE_LICENSE("GPL"); 1718 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1719 MODULE_DESCRIPTION("MAX310X serial driver"); 1720