1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 29 #define MAX310X_NAME "max310x" 30 #define MAX310X_MAJOR 204 31 #define MAX310X_MINOR 209 32 #define MAX310X_UART_NRMAX 16 33 34 /* MAX310X register definitions */ 35 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 36 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 37 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 38 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 39 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 40 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 41 #define MAX310X_REG_05 (0x05) 42 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 43 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 44 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 45 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 46 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 47 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 48 #define MAX310X_LCR_REG (0x0b) /* LCR */ 49 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 51 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 52 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 53 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 56 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 57 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 58 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 59 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 60 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 63 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 67 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 68 #define MAX310X_REG_1F (0x1f) 69 70 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 71 72 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 74 75 /* Extended registers */ 76 #define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 77 #define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */ 78 79 /* IRQ register bits */ 80 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 81 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 82 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 83 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 84 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 85 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 86 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 87 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 88 89 /* LSR register bits */ 90 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 91 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 92 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 93 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 94 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 95 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 97 98 /* Special character register bits */ 99 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 100 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 101 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 102 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 103 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 105 106 /* Status register bits */ 107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 111 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 112 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 113 114 /* MODE1 register bits */ 115 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 116 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 119 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 120 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 122 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 123 124 /* MODE2 register bits */ 125 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 126 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 129 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 130 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 132 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 133 134 /* LCR register bits */ 135 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 136 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 137 * 138 * Word length bits table: 139 * 00 -> 5 bit words 140 * 01 -> 6 bit words 141 * 10 -> 7 bit words 142 * 11 -> 8 bit words 143 */ 144 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 145 * 146 * STOP length bit table: 147 * 0 -> 1 stop bit 148 * 1 -> 1-1.5 stop bits if 149 * word length is 5, 150 * 2 stop bits otherwise 151 */ 152 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 153 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 155 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 156 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 157 158 /* IRDA register bits */ 159 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 160 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 161 162 /* Flow control trigger level register masks */ 163 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 164 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 165 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 166 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 167 168 /* FIFO interrupt trigger level register masks */ 169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 171 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 172 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 173 174 /* Flow control register bits */ 175 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 176 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 177 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 178 * are used in conjunction with 179 * XOFF2 for definition of 180 * special character */ 181 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 182 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 183 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 184 * 185 * SWFLOW bits 1 & 0 table: 186 * 00 -> no transmitter flow 187 * control 188 * 01 -> receiver compares 189 * XON2 and XOFF2 190 * and controls 191 * transmitter 192 * 10 -> receiver compares 193 * XON1 and XOFF1 194 * and controls 195 * transmitter 196 * 11 -> receiver compares 197 * XON1, XON2, XOFF1 and 198 * XOFF2 and controls 199 * transmitter 200 */ 201 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 202 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 203 * 204 * SWFLOW bits 3 & 2 table: 205 * 00 -> no received flow 206 * control 207 * 01 -> transmitter generates 208 * XON2 and XOFF2 209 * 10 -> transmitter generates 210 * XON1 and XOFF1 211 * 11 -> transmitter generates 212 * XON1, XON2, XOFF1 and 213 * XOFF2 214 */ 215 216 /* PLL configuration register masks */ 217 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 218 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 219 220 /* Baud rate generator configuration register bits */ 221 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 222 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 223 224 /* Clock source register bits */ 225 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 226 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 227 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 228 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 229 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 230 231 /* Global commands */ 232 #define MAX310X_EXTREG_ENBL (0xce) 233 #define MAX310X_EXTREG_DSBL (0xcd) 234 235 /* Misc definitions */ 236 #define MAX310X_FIFO_SIZE (128) 237 #define MAX310x_REV_MASK (0xf8) 238 #define MAX310X_WRITE_BIT 0x80 239 240 /* Crystal-related definitions */ 241 #define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */ 242 #define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */ 243 244 /* MAX3107 specific */ 245 #define MAX3107_REV_ID (0xa0) 246 247 /* MAX3109 specific */ 248 #define MAX3109_REV_ID (0xc0) 249 250 /* MAX14830 specific */ 251 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 252 #define MAX14830_REV_ID (0xb0) 253 254 struct max310x_if_cfg { 255 int (*extended_reg_enable)(struct device *dev, bool enable); 256 257 unsigned int rev_id_reg; 258 }; 259 260 struct max310x_devtype { 261 struct { 262 unsigned short min; 263 unsigned short max; 264 } slave_addr; 265 char name[9]; 266 int nr; 267 u8 mode1; 268 int (*detect)(struct device *); 269 void (*power)(struct uart_port *, int); 270 }; 271 272 struct max310x_one { 273 struct uart_port port; 274 struct work_struct tx_work; 275 struct work_struct md_work; 276 struct work_struct rs_work; 277 struct regmap *regmap; 278 279 u8 rx_buf[MAX310X_FIFO_SIZE]; 280 }; 281 #define to_max310x_port(_port) \ 282 container_of(_port, struct max310x_one, port) 283 284 struct max310x_port { 285 const struct max310x_devtype *devtype; 286 const struct max310x_if_cfg *if_cfg; 287 struct regmap *regmap; 288 struct clk *clk; 289 #ifdef CONFIG_GPIOLIB 290 struct gpio_chip gpio; 291 #endif 292 struct max310x_one p[]; 293 }; 294 295 static struct uart_driver max310x_uart = { 296 .owner = THIS_MODULE, 297 .driver_name = MAX310X_NAME, 298 .dev_name = "ttyMAX", 299 .major = MAX310X_MAJOR, 300 .minor = MAX310X_MINOR, 301 .nr = MAX310X_UART_NRMAX, 302 }; 303 304 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 305 306 static u8 max310x_port_read(struct uart_port *port, u8 reg) 307 { 308 struct max310x_one *one = to_max310x_port(port); 309 unsigned int val = 0; 310 311 regmap_read(one->regmap, reg, &val); 312 313 return val; 314 } 315 316 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 317 { 318 struct max310x_one *one = to_max310x_port(port); 319 320 regmap_write(one->regmap, reg, val); 321 } 322 323 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 324 { 325 struct max310x_one *one = to_max310x_port(port); 326 327 regmap_update_bits(one->regmap, reg, mask, val); 328 } 329 330 static int max3107_detect(struct device *dev) 331 { 332 struct max310x_port *s = dev_get_drvdata(dev); 333 unsigned int val = 0; 334 int ret; 335 336 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 337 if (ret) 338 return ret; 339 340 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 341 dev_err(dev, 342 "%s ID 0x%02x does not match\n", s->devtype->name, val); 343 return -ENODEV; 344 } 345 346 return 0; 347 } 348 349 static int max3108_detect(struct device *dev) 350 { 351 struct max310x_port *s = dev_get_drvdata(dev); 352 unsigned int val = 0; 353 int ret; 354 355 /* MAX3108 have not REV ID register, we just check default value 356 * from clocksource register to make sure everything works. 357 */ 358 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 359 if (ret) 360 return ret; 361 362 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 363 dev_err(dev, "%s not present\n", s->devtype->name); 364 return -ENODEV; 365 } 366 367 return 0; 368 } 369 370 static int max3109_detect(struct device *dev) 371 { 372 struct max310x_port *s = dev_get_drvdata(dev); 373 unsigned int val = 0; 374 int ret; 375 376 ret = s->if_cfg->extended_reg_enable(dev, true); 377 if (ret) 378 return ret; 379 380 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 381 s->if_cfg->extended_reg_enable(dev, false); 382 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 383 dev_err(dev, 384 "%s ID 0x%02x does not match\n", s->devtype->name, val); 385 return -ENODEV; 386 } 387 388 return 0; 389 } 390 391 static void max310x_power(struct uart_port *port, int on) 392 { 393 max310x_port_update(port, MAX310X_MODE1_REG, 394 MAX310X_MODE1_FORCESLEEP_BIT, 395 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 396 if (on) 397 msleep(50); 398 } 399 400 static int max14830_detect(struct device *dev) 401 { 402 struct max310x_port *s = dev_get_drvdata(dev); 403 unsigned int val = 0; 404 int ret; 405 406 ret = s->if_cfg->extended_reg_enable(dev, true); 407 if (ret) 408 return ret; 409 410 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 411 s->if_cfg->extended_reg_enable(dev, false); 412 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 413 dev_err(dev, 414 "%s ID 0x%02x does not match\n", s->devtype->name, val); 415 return -ENODEV; 416 } 417 418 return 0; 419 } 420 421 static void max14830_power(struct uart_port *port, int on) 422 { 423 max310x_port_update(port, MAX310X_BRGCFG_REG, 424 MAX14830_BRGCFG_CLKDIS_BIT, 425 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 426 if (on) 427 msleep(50); 428 } 429 430 static const struct max310x_devtype max3107_devtype = { 431 .name = "MAX3107", 432 .nr = 1, 433 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 434 .detect = max3107_detect, 435 .power = max310x_power, 436 .slave_addr = { 437 .min = 0x2c, 438 .max = 0x2f, 439 }, 440 }; 441 442 static const struct max310x_devtype max3108_devtype = { 443 .name = "MAX3108", 444 .nr = 1, 445 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 446 .detect = max3108_detect, 447 .power = max310x_power, 448 .slave_addr = { 449 .min = 0x60, 450 .max = 0x6f, 451 }, 452 }; 453 454 static const struct max310x_devtype max3109_devtype = { 455 .name = "MAX3109", 456 .nr = 2, 457 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 458 .detect = max3109_detect, 459 .power = max310x_power, 460 .slave_addr = { 461 .min = 0x60, 462 .max = 0x6f, 463 }, 464 }; 465 466 static const struct max310x_devtype max14830_devtype = { 467 .name = "MAX14830", 468 .nr = 4, 469 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 470 .detect = max14830_detect, 471 .power = max14830_power, 472 .slave_addr = { 473 .min = 0x60, 474 .max = 0x6f, 475 }, 476 }; 477 478 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 479 { 480 switch (reg) { 481 case MAX310X_IRQSTS_REG: 482 case MAX310X_LSR_IRQSTS_REG: 483 case MAX310X_SPCHR_IRQSTS_REG: 484 case MAX310X_STS_IRQSTS_REG: 485 case MAX310X_TXFIFOLVL_REG: 486 case MAX310X_RXFIFOLVL_REG: 487 return false; 488 default: 489 break; 490 } 491 492 return true; 493 } 494 495 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 496 { 497 switch (reg) { 498 case MAX310X_RHR_REG: 499 case MAX310X_IRQSTS_REG: 500 case MAX310X_LSR_IRQSTS_REG: 501 case MAX310X_SPCHR_IRQSTS_REG: 502 case MAX310X_STS_IRQSTS_REG: 503 case MAX310X_TXFIFOLVL_REG: 504 case MAX310X_RXFIFOLVL_REG: 505 case MAX310X_GPIODATA_REG: 506 case MAX310X_BRGDIVLSB_REG: 507 case MAX310X_REG_05: 508 case MAX310X_REG_1F: 509 return true; 510 default: 511 break; 512 } 513 514 return false; 515 } 516 517 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 518 { 519 switch (reg) { 520 case MAX310X_RHR_REG: 521 case MAX310X_IRQSTS_REG: 522 case MAX310X_SPCHR_IRQSTS_REG: 523 case MAX310X_STS_IRQSTS_REG: 524 return true; 525 default: 526 break; 527 } 528 529 return false; 530 } 531 532 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 533 { 534 return reg == MAX310X_RHR_REG; 535 } 536 537 static int max310x_set_baud(struct uart_port *port, int baud) 538 { 539 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 540 541 /* 542 * Calculate the integer divisor first. Select a proper mode 543 * in case if the requested baud is too high for the pre-defined 544 * clocks frequency. 545 */ 546 div = port->uartclk / baud; 547 if (div < 8) { 548 /* Mode x4 */ 549 c = 4; 550 mode = MAX310X_BRGCFG_4XMODE_BIT; 551 } else if (div < 16) { 552 /* Mode x2 */ 553 c = 8; 554 mode = MAX310X_BRGCFG_2XMODE_BIT; 555 } else { 556 c = 16; 557 } 558 559 /* Calculate the divisor in accordance with the fraction coefficient */ 560 div /= c; 561 F = c*baud; 562 563 /* Calculate the baud rate fraction */ 564 if (div > 0) 565 frac = (16*(port->uartclk % F)) / F; 566 else 567 div = 1; 568 569 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 570 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 571 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 572 573 /* Return the actual baud rate we just programmed */ 574 return (16*port->uartclk) / (c*(16*div + frac)); 575 } 576 577 static int max310x_update_best_err(unsigned long f, long *besterr) 578 { 579 /* Use baudrate 115200 for calculate error */ 580 long err = f % (460800 * 16); 581 582 if ((*besterr < 0) || (*besterr > err)) { 583 *besterr = err; 584 return 0; 585 } 586 587 return 1; 588 } 589 590 static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 591 unsigned long freq, bool xtal) 592 { 593 unsigned int div, clksrc, pllcfg = 0; 594 long besterr = -1; 595 unsigned long fdiv, fmul, bestfreq = freq; 596 597 /* First, update error without PLL */ 598 max310x_update_best_err(freq, &besterr); 599 600 /* Try all possible PLL dividers */ 601 for (div = 1; (div <= 63) && besterr; div++) { 602 fdiv = DIV_ROUND_CLOSEST(freq, div); 603 604 /* Try multiplier 6 */ 605 fmul = fdiv * 6; 606 if ((fdiv >= 500000) && (fdiv <= 800000)) 607 if (!max310x_update_best_err(fmul, &besterr)) { 608 pllcfg = (0 << 6) | div; 609 bestfreq = fmul; 610 } 611 /* Try multiplier 48 */ 612 fmul = fdiv * 48; 613 if ((fdiv >= 850000) && (fdiv <= 1200000)) 614 if (!max310x_update_best_err(fmul, &besterr)) { 615 pllcfg = (1 << 6) | div; 616 bestfreq = fmul; 617 } 618 /* Try multiplier 96 */ 619 fmul = fdiv * 96; 620 if ((fdiv >= 425000) && (fdiv <= 1000000)) 621 if (!max310x_update_best_err(fmul, &besterr)) { 622 pllcfg = (2 << 6) | div; 623 bestfreq = fmul; 624 } 625 /* Try multiplier 144 */ 626 fmul = fdiv * 144; 627 if ((fdiv >= 390000) && (fdiv <= 667000)) 628 if (!max310x_update_best_err(fmul, &besterr)) { 629 pllcfg = (3 << 6) | div; 630 bestfreq = fmul; 631 } 632 } 633 634 /* Configure clock source */ 635 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 636 637 /* Configure PLL */ 638 if (pllcfg) { 639 clksrc |= MAX310X_CLKSRC_PLL_BIT; 640 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 641 } else 642 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 643 644 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 645 646 /* Wait for crystal */ 647 if (xtal) { 648 bool stable = false; 649 unsigned int try = 0, val = 0; 650 651 do { 652 msleep(MAX310X_XTAL_WAIT_DELAY_MS); 653 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 654 655 if (val & MAX310X_STS_CLKREADY_BIT) 656 stable = true; 657 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES)); 658 659 if (!stable) 660 dev_warn(dev, "clock is not stable yet\n"); 661 } 662 663 return bestfreq; 664 } 665 666 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 667 { 668 struct max310x_one *one = to_max310x_port(port); 669 670 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 671 } 672 673 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 674 { 675 struct max310x_one *one = to_max310x_port(port); 676 677 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 678 } 679 680 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 681 { 682 struct max310x_one *one = to_max310x_port(port); 683 unsigned int sts, i; 684 u8 ch, flag; 685 686 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 687 /* We are just reading, happily ignoring any error conditions. 688 * Break condition, parity checking, framing errors -- they 689 * are all ignored. That means that we can do a batch-read. 690 * 691 * There is a small opportunity for race if the RX FIFO 692 * overruns while we're reading the buffer; the datasheets says 693 * that the LSR register applies to the "current" character. 694 * That's also the reason why we cannot do batched reads when 695 * asked to check the individual statuses. 696 * */ 697 698 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 699 max310x_batch_read(port, one->rx_buf, rxlen); 700 701 port->icount.rx += rxlen; 702 flag = TTY_NORMAL; 703 sts &= port->read_status_mask; 704 705 if (sts & MAX310X_LSR_RXOVR_BIT) { 706 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 707 port->icount.overrun++; 708 } 709 710 for (i = 0; i < (rxlen - 1); ++i) 711 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 712 713 /* 714 * Handle the overrun case for the last character only, since 715 * the RxFIFO overflow happens after it is pushed to the FIFO 716 * tail. 717 */ 718 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 719 one->rx_buf[rxlen-1], flag); 720 721 } else { 722 if (unlikely(rxlen >= port->fifosize)) { 723 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 724 port->icount.buf_overrun++; 725 /* Ensure sanity of RX level */ 726 rxlen = port->fifosize; 727 } 728 729 while (rxlen--) { 730 ch = max310x_port_read(port, MAX310X_RHR_REG); 731 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 732 733 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 734 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 735 736 port->icount.rx++; 737 flag = TTY_NORMAL; 738 739 if (unlikely(sts)) { 740 if (sts & MAX310X_LSR_RXBRK_BIT) { 741 port->icount.brk++; 742 if (uart_handle_break(port)) 743 continue; 744 } else if (sts & MAX310X_LSR_RXPAR_BIT) 745 port->icount.parity++; 746 else if (sts & MAX310X_LSR_FRERR_BIT) 747 port->icount.frame++; 748 else if (sts & MAX310X_LSR_RXOVR_BIT) 749 port->icount.overrun++; 750 751 sts &= port->read_status_mask; 752 if (sts & MAX310X_LSR_RXBRK_BIT) 753 flag = TTY_BREAK; 754 else if (sts & MAX310X_LSR_RXPAR_BIT) 755 flag = TTY_PARITY; 756 else if (sts & MAX310X_LSR_FRERR_BIT) 757 flag = TTY_FRAME; 758 else if (sts & MAX310X_LSR_RXOVR_BIT) 759 flag = TTY_OVERRUN; 760 } 761 762 if (uart_handle_sysrq_char(port, ch)) 763 continue; 764 765 if (sts & port->ignore_status_mask) 766 continue; 767 768 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 769 } 770 } 771 772 tty_flip_buffer_push(&port->state->port); 773 } 774 775 static void max310x_handle_tx(struct uart_port *port) 776 { 777 struct circ_buf *xmit = &port->state->xmit; 778 unsigned int txlen, to_send, until_end; 779 780 if (unlikely(port->x_char)) { 781 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 782 port->icount.tx++; 783 port->x_char = 0; 784 return; 785 } 786 787 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 788 return; 789 790 /* Get length of data pending in circular buffer */ 791 to_send = uart_circ_chars_pending(xmit); 792 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 793 if (likely(to_send)) { 794 /* Limit to size of TX FIFO */ 795 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 796 txlen = port->fifosize - txlen; 797 to_send = (to_send > txlen) ? txlen : to_send; 798 799 if (until_end < to_send) { 800 /* It's a circ buffer -- wrap around. 801 * We could do that in one SPI transaction, but meh. */ 802 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 803 max310x_batch_write(port, xmit->buf, to_send - until_end); 804 } else { 805 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 806 } 807 uart_xmit_advance(port, to_send); 808 } 809 810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 811 uart_write_wakeup(port); 812 } 813 814 static void max310x_start_tx(struct uart_port *port) 815 { 816 struct max310x_one *one = to_max310x_port(port); 817 818 schedule_work(&one->tx_work); 819 } 820 821 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 822 { 823 struct uart_port *port = &s->p[portno].port; 824 irqreturn_t res = IRQ_NONE; 825 826 do { 827 unsigned int ists, lsr, rxlen; 828 829 /* Read IRQ status & RX FIFO level */ 830 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 831 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 832 if (!ists && !rxlen) 833 break; 834 835 res = IRQ_HANDLED; 836 837 if (ists & MAX310X_IRQ_CTS_BIT) { 838 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 839 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 840 } 841 if (rxlen) 842 max310x_handle_rx(port, rxlen); 843 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 844 max310x_start_tx(port); 845 } while (1); 846 return res; 847 } 848 849 static irqreturn_t max310x_ist(int irq, void *dev_id) 850 { 851 struct max310x_port *s = (struct max310x_port *)dev_id; 852 bool handled = false; 853 854 if (s->devtype->nr > 1) { 855 do { 856 unsigned int val = ~0; 857 858 WARN_ON_ONCE(regmap_read(s->regmap, 859 MAX310X_GLOBALIRQ_REG, &val)); 860 val = ((1 << s->devtype->nr) - 1) & ~val; 861 if (!val) 862 break; 863 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 864 handled = true; 865 } while (1); 866 } else { 867 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 868 handled = true; 869 } 870 871 return IRQ_RETVAL(handled); 872 } 873 874 static void max310x_tx_proc(struct work_struct *ws) 875 { 876 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 877 878 max310x_handle_tx(&one->port); 879 } 880 881 static unsigned int max310x_tx_empty(struct uart_port *port) 882 { 883 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 884 885 return lvl ? 0 : TIOCSER_TEMT; 886 } 887 888 static unsigned int max310x_get_mctrl(struct uart_port *port) 889 { 890 /* DCD and DSR are not wired and CTS/RTS is handled automatically 891 * so just indicate DSR and CAR asserted 892 */ 893 return TIOCM_DSR | TIOCM_CAR; 894 } 895 896 static void max310x_md_proc(struct work_struct *ws) 897 { 898 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 899 900 max310x_port_update(&one->port, MAX310X_MODE2_REG, 901 MAX310X_MODE2_LOOPBACK_BIT, 902 (one->port.mctrl & TIOCM_LOOP) ? 903 MAX310X_MODE2_LOOPBACK_BIT : 0); 904 } 905 906 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 907 { 908 struct max310x_one *one = to_max310x_port(port); 909 910 schedule_work(&one->md_work); 911 } 912 913 static void max310x_break_ctl(struct uart_port *port, int break_state) 914 { 915 max310x_port_update(port, MAX310X_LCR_REG, 916 MAX310X_LCR_TXBREAK_BIT, 917 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 918 } 919 920 static void max310x_set_termios(struct uart_port *port, 921 struct ktermios *termios, 922 const struct ktermios *old) 923 { 924 unsigned int lcr = 0, flow = 0; 925 int baud; 926 927 /* Mask termios capabilities we don't support */ 928 termios->c_cflag &= ~CMSPAR; 929 930 /* Word size */ 931 switch (termios->c_cflag & CSIZE) { 932 case CS5: 933 break; 934 case CS6: 935 lcr = MAX310X_LCR_LENGTH0_BIT; 936 break; 937 case CS7: 938 lcr = MAX310X_LCR_LENGTH1_BIT; 939 break; 940 case CS8: 941 default: 942 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 943 break; 944 } 945 946 /* Parity */ 947 if (termios->c_cflag & PARENB) { 948 lcr |= MAX310X_LCR_PARITY_BIT; 949 if (!(termios->c_cflag & PARODD)) 950 lcr |= MAX310X_LCR_EVENPARITY_BIT; 951 } 952 953 /* Stop bits */ 954 if (termios->c_cflag & CSTOPB) 955 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 956 957 /* Update LCR register */ 958 max310x_port_write(port, MAX310X_LCR_REG, lcr); 959 960 /* Set read status mask */ 961 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 962 if (termios->c_iflag & INPCK) 963 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 964 MAX310X_LSR_FRERR_BIT; 965 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 966 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 967 968 /* Set status ignore mask */ 969 port->ignore_status_mask = 0; 970 if (termios->c_iflag & IGNBRK) 971 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 972 if (!(termios->c_cflag & CREAD)) 973 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 974 MAX310X_LSR_RXOVR_BIT | 975 MAX310X_LSR_FRERR_BIT | 976 MAX310X_LSR_RXBRK_BIT; 977 978 /* Configure flow control */ 979 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 980 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 981 982 /* Disable transmitter before enabling AutoCTS or auto transmitter 983 * flow control 984 */ 985 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 986 max310x_port_update(port, MAX310X_MODE1_REG, 987 MAX310X_MODE1_TXDIS_BIT, 988 MAX310X_MODE1_TXDIS_BIT); 989 } 990 991 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 992 993 if (termios->c_cflag & CRTSCTS) { 994 /* Enable AUTORTS and AUTOCTS */ 995 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 996 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 997 MAX310X_FLOWCTRL_AUTORTS_BIT; 998 } 999 if (termios->c_iflag & IXON) 1000 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 1001 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1002 if (termios->c_iflag & IXOFF) { 1003 port->status |= UPSTAT_AUTOXOFF; 1004 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 1005 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1006 } 1007 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 1008 1009 /* Enable transmitter after disabling AutoCTS and auto transmitter 1010 * flow control 1011 */ 1012 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1013 max310x_port_update(port, MAX310X_MODE1_REG, 1014 MAX310X_MODE1_TXDIS_BIT, 1015 0); 1016 } 1017 1018 /* Get baud rate generator configuration */ 1019 baud = uart_get_baud_rate(port, termios, old, 1020 port->uartclk / 16 / 0xffff, 1021 port->uartclk / 4); 1022 1023 /* Setup baudrate generator */ 1024 baud = max310x_set_baud(port, baud); 1025 1026 /* Update timeout according to new baud rate */ 1027 uart_update_timeout(port, termios->c_cflag, baud); 1028 } 1029 1030 static void max310x_rs_proc(struct work_struct *ws) 1031 { 1032 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1033 unsigned int delay, mode1 = 0, mode2 = 0; 1034 1035 delay = (one->port.rs485.delay_rts_before_send << 4) | 1036 one->port.rs485.delay_rts_after_send; 1037 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1038 1039 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1040 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1041 1042 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1043 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1044 } 1045 1046 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1047 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1048 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1049 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1050 } 1051 1052 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1053 struct serial_rs485 *rs485) 1054 { 1055 struct max310x_one *one = to_max310x_port(port); 1056 1057 if ((rs485->delay_rts_before_send > 0x0f) || 1058 (rs485->delay_rts_after_send > 0x0f)) 1059 return -ERANGE; 1060 1061 port->rs485 = *rs485; 1062 1063 schedule_work(&one->rs_work); 1064 1065 return 0; 1066 } 1067 1068 static int max310x_startup(struct uart_port *port) 1069 { 1070 struct max310x_port *s = dev_get_drvdata(port->dev); 1071 unsigned int val; 1072 1073 s->devtype->power(port, 1); 1074 1075 /* Configure MODE1 register */ 1076 max310x_port_update(port, MAX310X_MODE1_REG, 1077 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1078 1079 /* Configure MODE2 register & Reset FIFOs*/ 1080 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1081 max310x_port_write(port, MAX310X_MODE2_REG, val); 1082 max310x_port_update(port, MAX310X_MODE2_REG, 1083 MAX310X_MODE2_FIFORST_BIT, 0); 1084 1085 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1086 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1087 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1088 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1089 1090 if (port->rs485.flags & SER_RS485_ENABLED) { 1091 max310x_port_update(port, MAX310X_MODE1_REG, 1092 MAX310X_MODE1_TRNSCVCTRL_BIT, 1093 MAX310X_MODE1_TRNSCVCTRL_BIT); 1094 1095 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1096 max310x_port_update(port, MAX310X_MODE2_REG, 1097 MAX310X_MODE2_ECHOSUPR_BIT, 1098 MAX310X_MODE2_ECHOSUPR_BIT); 1099 } 1100 1101 /* Configure flow control levels */ 1102 /* Flow control halt level 96, resume level 48 */ 1103 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1104 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1105 1106 /* Clear IRQ status register */ 1107 max310x_port_read(port, MAX310X_IRQSTS_REG); 1108 1109 /* Enable RX, TX, CTS change interrupts */ 1110 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1111 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1112 1113 return 0; 1114 } 1115 1116 static void max310x_shutdown(struct uart_port *port) 1117 { 1118 struct max310x_port *s = dev_get_drvdata(port->dev); 1119 1120 /* Disable all interrupts */ 1121 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1122 1123 s->devtype->power(port, 0); 1124 } 1125 1126 static const char *max310x_type(struct uart_port *port) 1127 { 1128 struct max310x_port *s = dev_get_drvdata(port->dev); 1129 1130 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1131 } 1132 1133 static int max310x_request_port(struct uart_port *port) 1134 { 1135 /* Do nothing */ 1136 return 0; 1137 } 1138 1139 static void max310x_config_port(struct uart_port *port, int flags) 1140 { 1141 if (flags & UART_CONFIG_TYPE) 1142 port->type = PORT_MAX310X; 1143 } 1144 1145 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1146 { 1147 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1148 return -EINVAL; 1149 if (s->irq != port->irq) 1150 return -EINVAL; 1151 1152 return 0; 1153 } 1154 1155 static void max310x_null_void(struct uart_port *port) 1156 { 1157 /* Do nothing */ 1158 } 1159 1160 static const struct uart_ops max310x_ops = { 1161 .tx_empty = max310x_tx_empty, 1162 .set_mctrl = max310x_set_mctrl, 1163 .get_mctrl = max310x_get_mctrl, 1164 .stop_tx = max310x_null_void, 1165 .start_tx = max310x_start_tx, 1166 .stop_rx = max310x_null_void, 1167 .break_ctl = max310x_break_ctl, 1168 .startup = max310x_startup, 1169 .shutdown = max310x_shutdown, 1170 .set_termios = max310x_set_termios, 1171 .type = max310x_type, 1172 .request_port = max310x_request_port, 1173 .release_port = max310x_null_void, 1174 .config_port = max310x_config_port, 1175 .verify_port = max310x_verify_port, 1176 }; 1177 1178 static int __maybe_unused max310x_suspend(struct device *dev) 1179 { 1180 struct max310x_port *s = dev_get_drvdata(dev); 1181 int i; 1182 1183 for (i = 0; i < s->devtype->nr; i++) { 1184 uart_suspend_port(&max310x_uart, &s->p[i].port); 1185 s->devtype->power(&s->p[i].port, 0); 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int __maybe_unused max310x_resume(struct device *dev) 1192 { 1193 struct max310x_port *s = dev_get_drvdata(dev); 1194 int i; 1195 1196 for (i = 0; i < s->devtype->nr; i++) { 1197 s->devtype->power(&s->p[i].port, 1); 1198 uart_resume_port(&max310x_uart, &s->p[i].port); 1199 } 1200 1201 return 0; 1202 } 1203 1204 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1205 1206 #ifdef CONFIG_GPIOLIB 1207 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1208 { 1209 unsigned int val; 1210 struct max310x_port *s = gpiochip_get_data(chip); 1211 struct uart_port *port = &s->p[offset / 4].port; 1212 1213 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1214 1215 return !!((val >> 4) & (1 << (offset % 4))); 1216 } 1217 1218 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1219 { 1220 struct max310x_port *s = gpiochip_get_data(chip); 1221 struct uart_port *port = &s->p[offset / 4].port; 1222 1223 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1224 value ? 1 << (offset % 4) : 0); 1225 } 1226 1227 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1228 { 1229 struct max310x_port *s = gpiochip_get_data(chip); 1230 struct uart_port *port = &s->p[offset / 4].port; 1231 1232 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1233 1234 return 0; 1235 } 1236 1237 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1238 unsigned offset, int value) 1239 { 1240 struct max310x_port *s = gpiochip_get_data(chip); 1241 struct uart_port *port = &s->p[offset / 4].port; 1242 1243 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1244 value ? 1 << (offset % 4) : 0); 1245 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1246 1 << (offset % 4)); 1247 1248 return 0; 1249 } 1250 1251 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1252 unsigned long config) 1253 { 1254 struct max310x_port *s = gpiochip_get_data(chip); 1255 struct uart_port *port = &s->p[offset / 4].port; 1256 1257 switch (pinconf_to_config_param(config)) { 1258 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1259 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1260 1 << ((offset % 4) + 4), 1261 1 << ((offset % 4) + 4)); 1262 return 0; 1263 case PIN_CONFIG_DRIVE_PUSH_PULL: 1264 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1265 1 << ((offset % 4) + 4), 0); 1266 return 0; 1267 default: 1268 return -ENOTSUPP; 1269 } 1270 } 1271 #endif 1272 1273 static const struct serial_rs485 max310x_rs485_supported = { 1274 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1275 .delay_rts_before_send = 1, 1276 .delay_rts_after_send = 1, 1277 }; 1278 1279 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1280 const struct max310x_if_cfg *if_cfg, 1281 struct regmap *regmaps[], int irq) 1282 { 1283 int i, ret, fmin, fmax, freq; 1284 struct max310x_port *s; 1285 u32 uartclk = 0; 1286 bool xtal; 1287 1288 for (i = 0; i < devtype->nr; i++) 1289 if (IS_ERR(regmaps[i])) 1290 return PTR_ERR(regmaps[i]); 1291 1292 /* Alloc port structure */ 1293 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1294 if (!s) { 1295 dev_err(dev, "Error allocating port structure\n"); 1296 return -ENOMEM; 1297 } 1298 1299 /* Always ask for fixed clock rate from a property. */ 1300 device_property_read_u32(dev, "clock-frequency", &uartclk); 1301 1302 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1303 if (xtal) 1304 s->clk = devm_clk_get_optional(dev, "xtal"); 1305 else 1306 s->clk = devm_clk_get_optional(dev, "osc"); 1307 if (IS_ERR(s->clk)) 1308 return PTR_ERR(s->clk); 1309 1310 ret = clk_prepare_enable(s->clk); 1311 if (ret) 1312 return ret; 1313 1314 freq = clk_get_rate(s->clk); 1315 if (freq == 0) 1316 freq = uartclk; 1317 if (freq == 0) { 1318 dev_err(dev, "Cannot get clock rate\n"); 1319 ret = -EINVAL; 1320 goto out_clk; 1321 } 1322 1323 if (xtal) { 1324 fmin = 1000000; 1325 fmax = 4000000; 1326 } else { 1327 fmin = 500000; 1328 fmax = 35000000; 1329 } 1330 1331 /* Check frequency limits */ 1332 if (freq < fmin || freq > fmax) { 1333 ret = -ERANGE; 1334 goto out_clk; 1335 } 1336 1337 s->regmap = regmaps[0]; 1338 s->devtype = devtype; 1339 s->if_cfg = if_cfg; 1340 dev_set_drvdata(dev, s); 1341 1342 /* Check device to ensure we are talking to what we expect */ 1343 ret = devtype->detect(dev); 1344 if (ret) 1345 goto out_clk; 1346 1347 for (i = 0; i < devtype->nr; i++) { 1348 /* Reset port */ 1349 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1350 MAX310X_MODE2_RST_BIT); 1351 /* Clear port reset */ 1352 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1353 1354 /* Wait for port startup */ 1355 do { 1356 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret); 1357 } while (ret != 0x01); 1358 1359 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1360 } 1361 1362 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1363 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1364 1365 for (i = 0; i < devtype->nr; i++) { 1366 unsigned int line; 1367 1368 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1369 if (line == MAX310X_UART_NRMAX) { 1370 ret = -ERANGE; 1371 goto out_uart; 1372 } 1373 1374 /* Initialize port data */ 1375 s->p[i].port.line = line; 1376 s->p[i].port.dev = dev; 1377 s->p[i].port.irq = irq; 1378 s->p[i].port.type = PORT_MAX310X; 1379 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1380 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1381 s->p[i].port.iotype = UPIO_PORT; 1382 s->p[i].port.iobase = i; 1383 /* 1384 * Use all ones as membase to make sure uart_configure_port() in 1385 * serial_core.c does not abort for SPI/I2C devices where the 1386 * membase address is not applicable. 1387 */ 1388 s->p[i].port.membase = (void __iomem *)~0; 1389 s->p[i].port.uartclk = uartclk; 1390 s->p[i].port.rs485_config = max310x_rs485_config; 1391 s->p[i].port.rs485_supported = max310x_rs485_supported; 1392 s->p[i].port.ops = &max310x_ops; 1393 s->p[i].regmap = regmaps[i]; 1394 1395 /* Disable all interrupts */ 1396 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1397 /* Clear IRQ status register */ 1398 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1399 /* Initialize queue for start TX */ 1400 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1401 /* Initialize queue for changing LOOPBACK mode */ 1402 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1403 /* Initialize queue for changing RS485 mode */ 1404 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1405 1406 /* Register port */ 1407 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1408 if (ret) { 1409 s->p[i].port.dev = NULL; 1410 goto out_uart; 1411 } 1412 set_bit(line, max310x_lines); 1413 1414 /* Go to suspend mode */ 1415 devtype->power(&s->p[i].port, 0); 1416 } 1417 1418 #ifdef CONFIG_GPIOLIB 1419 /* Setup GPIO controller */ 1420 s->gpio.owner = THIS_MODULE; 1421 s->gpio.parent = dev; 1422 s->gpio.label = devtype->name; 1423 s->gpio.direction_input = max310x_gpio_direction_input; 1424 s->gpio.get = max310x_gpio_get; 1425 s->gpio.direction_output= max310x_gpio_direction_output; 1426 s->gpio.set = max310x_gpio_set; 1427 s->gpio.set_config = max310x_gpio_set_config; 1428 s->gpio.base = -1; 1429 s->gpio.ngpio = devtype->nr * 4; 1430 s->gpio.can_sleep = 1; 1431 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1432 if (ret) 1433 goto out_uart; 1434 #endif 1435 1436 /* Setup interrupt */ 1437 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1438 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1439 if (!ret) 1440 return 0; 1441 1442 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1443 1444 out_uart: 1445 for (i = 0; i < devtype->nr; i++) { 1446 if (s->p[i].port.dev) { 1447 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1448 clear_bit(s->p[i].port.line, max310x_lines); 1449 } 1450 } 1451 1452 out_clk: 1453 clk_disable_unprepare(s->clk); 1454 1455 return ret; 1456 } 1457 1458 static void max310x_remove(struct device *dev) 1459 { 1460 struct max310x_port *s = dev_get_drvdata(dev); 1461 int i; 1462 1463 for (i = 0; i < s->devtype->nr; i++) { 1464 cancel_work_sync(&s->p[i].tx_work); 1465 cancel_work_sync(&s->p[i].md_work); 1466 cancel_work_sync(&s->p[i].rs_work); 1467 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1468 clear_bit(s->p[i].port.line, max310x_lines); 1469 s->devtype->power(&s->p[i].port, 0); 1470 } 1471 1472 clk_disable_unprepare(s->clk); 1473 } 1474 1475 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1476 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1477 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1478 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1479 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1480 { } 1481 }; 1482 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1483 1484 static struct regmap_config regcfg = { 1485 .reg_bits = 8, 1486 .val_bits = 8, 1487 .write_flag_mask = MAX310X_WRITE_BIT, 1488 .cache_type = REGCACHE_RBTREE, 1489 .max_register = MAX310X_REG_1F, 1490 .writeable_reg = max310x_reg_writeable, 1491 .volatile_reg = max310x_reg_volatile, 1492 .precious_reg = max310x_reg_precious, 1493 .writeable_noinc_reg = max310x_reg_noinc, 1494 .readable_noinc_reg = max310x_reg_noinc, 1495 .max_raw_read = MAX310X_FIFO_SIZE, 1496 .max_raw_write = MAX310X_FIFO_SIZE, 1497 }; 1498 1499 #ifdef CONFIG_SPI_MASTER 1500 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1501 { 1502 struct max310x_port *s = dev_get_drvdata(dev); 1503 1504 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1505 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1506 } 1507 1508 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1509 .extended_reg_enable = max310x_spi_extended_reg_enable, 1510 .rev_id_reg = MAX310X_SPI_REVID_EXTREG, 1511 }; 1512 1513 static int max310x_spi_probe(struct spi_device *spi) 1514 { 1515 const struct max310x_devtype *devtype; 1516 struct regmap *regmaps[4]; 1517 unsigned int i; 1518 int ret; 1519 1520 /* Setup SPI bus */ 1521 spi->bits_per_word = 8; 1522 spi->mode = spi->mode ? : SPI_MODE_0; 1523 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1524 ret = spi_setup(spi); 1525 if (ret) 1526 return ret; 1527 1528 devtype = device_get_match_data(&spi->dev); 1529 if (!devtype) 1530 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; 1531 1532 for (i = 0; i < devtype->nr; i++) { 1533 u8 port_mask = i * 0x20; 1534 regcfg.read_flag_mask = port_mask; 1535 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1536 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1537 } 1538 1539 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1540 } 1541 1542 static void max310x_spi_remove(struct spi_device *spi) 1543 { 1544 max310x_remove(&spi->dev); 1545 } 1546 1547 static const struct spi_device_id max310x_id_table[] = { 1548 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1549 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1550 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1551 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1552 { } 1553 }; 1554 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1555 1556 static struct spi_driver max310x_spi_driver = { 1557 .driver = { 1558 .name = MAX310X_NAME, 1559 .of_match_table = max310x_dt_ids, 1560 .pm = &max310x_pm_ops, 1561 }, 1562 .probe = max310x_spi_probe, 1563 .remove = max310x_spi_remove, 1564 .id_table = max310x_id_table, 1565 }; 1566 #endif 1567 1568 #ifdef CONFIG_I2C 1569 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1570 { 1571 return 0; 1572 } 1573 1574 static struct regmap_config regcfg_i2c = { 1575 .reg_bits = 8, 1576 .val_bits = 8, 1577 .cache_type = REGCACHE_RBTREE, 1578 .writeable_reg = max310x_reg_writeable, 1579 .volatile_reg = max310x_reg_volatile, 1580 .precious_reg = max310x_reg_precious, 1581 .max_register = MAX310X_I2C_REVID_EXTREG, 1582 .writeable_noinc_reg = max310x_reg_noinc, 1583 .readable_noinc_reg = max310x_reg_noinc, 1584 .max_raw_read = MAX310X_FIFO_SIZE, 1585 .max_raw_write = MAX310X_FIFO_SIZE, 1586 }; 1587 1588 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1589 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1590 .rev_id_reg = MAX310X_I2C_REVID_EXTREG, 1591 }; 1592 1593 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1594 unsigned int nr) 1595 { 1596 /* 1597 * For MAX14830 and MAX3109, the slave address depends on what the 1598 * A0 and A1 pins are tied to. 1599 * See Table I2C Address Map of the datasheet. 1600 * Based on that table, the following formulas were determined. 1601 * UART1 - UART0 = 0x10 1602 * UART2 - UART1 = 0x20 + 0x10 1603 * UART3 - UART2 = 0x10 1604 */ 1605 1606 addr -= nr * 0x10; 1607 1608 if (nr >= 2) 1609 addr -= 0x20; 1610 1611 return addr; 1612 } 1613 1614 static int max310x_i2c_probe(struct i2c_client *client) 1615 { 1616 const struct max310x_devtype *devtype = 1617 device_get_match_data(&client->dev); 1618 struct i2c_client *port_client; 1619 struct regmap *regmaps[4]; 1620 unsigned int i; 1621 u8 port_addr; 1622 1623 if (client->addr < devtype->slave_addr.min || 1624 client->addr > devtype->slave_addr.max) 1625 return dev_err_probe(&client->dev, -EINVAL, 1626 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1627 client->addr, devtype->slave_addr.min, 1628 devtype->slave_addr.max); 1629 1630 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1631 1632 for (i = 1; i < devtype->nr; i++) { 1633 port_addr = max310x_i2c_slave_addr(client->addr, i); 1634 port_client = devm_i2c_new_dummy_device(&client->dev, 1635 client->adapter, 1636 port_addr); 1637 1638 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1639 } 1640 1641 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1642 regmaps, client->irq); 1643 } 1644 1645 static void max310x_i2c_remove(struct i2c_client *client) 1646 { 1647 max310x_remove(&client->dev); 1648 } 1649 1650 static struct i2c_driver max310x_i2c_driver = { 1651 .driver = { 1652 .name = MAX310X_NAME, 1653 .of_match_table = max310x_dt_ids, 1654 .pm = &max310x_pm_ops, 1655 }, 1656 .probe = max310x_i2c_probe, 1657 .remove = max310x_i2c_remove, 1658 }; 1659 #endif 1660 1661 static int __init max310x_uart_init(void) 1662 { 1663 int ret; 1664 1665 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1666 1667 ret = uart_register_driver(&max310x_uart); 1668 if (ret) 1669 return ret; 1670 1671 #ifdef CONFIG_SPI_MASTER 1672 ret = spi_register_driver(&max310x_spi_driver); 1673 if (ret) 1674 goto err_spi_register; 1675 #endif 1676 1677 #ifdef CONFIG_I2C 1678 ret = i2c_add_driver(&max310x_i2c_driver); 1679 if (ret) 1680 goto err_i2c_register; 1681 #endif 1682 1683 return 0; 1684 1685 #ifdef CONFIG_I2C 1686 err_i2c_register: 1687 spi_unregister_driver(&max310x_spi_driver); 1688 #endif 1689 1690 err_spi_register: 1691 uart_unregister_driver(&max310x_uart); 1692 1693 return ret; 1694 } 1695 module_init(max310x_uart_init); 1696 1697 static void __exit max310x_uart_exit(void) 1698 { 1699 #ifdef CONFIG_I2C 1700 i2c_del_driver(&max310x_i2c_driver); 1701 #endif 1702 1703 #ifdef CONFIG_SPI_MASTER 1704 spi_unregister_driver(&max310x_spi_driver); 1705 #endif 1706 1707 uart_unregister_driver(&max310x_uart); 1708 } 1709 module_exit(max310x_uart_exit); 1710 1711 MODULE_LICENSE("GPL"); 1712 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1713 MODULE_DESCRIPTION("MAX310X serial driver"); 1714