1 /* 2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * 17 * Copyright (C) 2004 Infineon IFAP DC COM CPE 18 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 19 * Copyright (C) 2007 John Crispin <blogic@openwrt.org> 20 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 21 */ 22 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/ioport.h> 26 #include <linux/init.h> 27 #include <linux/console.h> 28 #include <linux/sysrq.h> 29 #include <linux/device.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/of_platform.h> 35 #include <linux/of_address.h> 36 #include <linux/of_irq.h> 37 #include <linux/io.h> 38 #include <linux/clk.h> 39 #include <linux/gpio.h> 40 41 #include <lantiq_soc.h> 42 43 #define PORT_LTQ_ASC 111 44 #define MAXPORTS 2 45 #define UART_DUMMY_UER_RX 1 46 #define DRVNAME "lantiq,asc" 47 #ifdef __BIG_ENDIAN 48 #define LTQ_ASC_TBUF (0x0020 + 3) 49 #define LTQ_ASC_RBUF (0x0024 + 3) 50 #else 51 #define LTQ_ASC_TBUF 0x0020 52 #define LTQ_ASC_RBUF 0x0024 53 #endif 54 #define LTQ_ASC_FSTAT 0x0048 55 #define LTQ_ASC_WHBSTATE 0x0018 56 #define LTQ_ASC_STATE 0x0014 57 #define LTQ_ASC_IRNCR 0x00F8 58 #define LTQ_ASC_CLC 0x0000 59 #define LTQ_ASC_ID 0x0008 60 #define LTQ_ASC_PISEL 0x0004 61 #define LTQ_ASC_TXFCON 0x0044 62 #define LTQ_ASC_RXFCON 0x0040 63 #define LTQ_ASC_CON 0x0010 64 #define LTQ_ASC_BG 0x0050 65 #define LTQ_ASC_IRNREN 0x00F4 66 67 #define ASC_IRNREN_TX 0x1 68 #define ASC_IRNREN_RX 0x2 69 #define ASC_IRNREN_ERR 0x4 70 #define ASC_IRNREN_TX_BUF 0x8 71 #define ASC_IRNCR_TIR 0x1 72 #define ASC_IRNCR_RIR 0x2 73 #define ASC_IRNCR_EIR 0x4 74 75 #define ASCOPT_CSIZE 0x3 76 #define TXFIFO_FL 1 77 #define RXFIFO_FL 1 78 #define ASCCLC_DISS 0x2 79 #define ASCCLC_RMCMASK 0x0000FF00 80 #define ASCCLC_RMCOFFSET 8 81 #define ASCCON_M_8ASYNC 0x0 82 #define ASCCON_M_7ASYNC 0x2 83 #define ASCCON_ODD 0x00000020 84 #define ASCCON_STP 0x00000080 85 #define ASCCON_BRS 0x00000100 86 #define ASCCON_FDE 0x00000200 87 #define ASCCON_R 0x00008000 88 #define ASCCON_FEN 0x00020000 89 #define ASCCON_ROEN 0x00080000 90 #define ASCCON_TOEN 0x00100000 91 #define ASCSTATE_PE 0x00010000 92 #define ASCSTATE_FE 0x00020000 93 #define ASCSTATE_ROE 0x00080000 94 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 95 #define ASCWHBSTATE_CLRREN 0x00000001 96 #define ASCWHBSTATE_SETREN 0x00000002 97 #define ASCWHBSTATE_CLRPE 0x00000004 98 #define ASCWHBSTATE_CLRFE 0x00000008 99 #define ASCWHBSTATE_CLRROE 0x00000020 100 #define ASCTXFCON_TXFEN 0x0001 101 #define ASCTXFCON_TXFFLU 0x0002 102 #define ASCTXFCON_TXFITLMASK 0x3F00 103 #define ASCTXFCON_TXFITLOFF 8 104 #define ASCRXFCON_RXFEN 0x0001 105 #define ASCRXFCON_RXFFLU 0x0002 106 #define ASCRXFCON_RXFITLMASK 0x3F00 107 #define ASCRXFCON_RXFITLOFF 8 108 #define ASCFSTAT_RXFFLMASK 0x003F 109 #define ASCFSTAT_TXFFLMASK 0x3F00 110 #define ASCFSTAT_TXFREEMASK 0x3F000000 111 #define ASCFSTAT_TXFREEOFF 24 112 113 static void lqasc_tx_chars(struct uart_port *port); 114 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 115 static struct uart_driver lqasc_reg; 116 static DEFINE_SPINLOCK(ltq_asc_lock); 117 118 struct ltq_uart_port { 119 struct uart_port port; 120 /* clock used to derive divider */ 121 struct clk *fpiclk; 122 /* clock gating of the ASC core */ 123 struct clk *clk; 124 unsigned int tx_irq; 125 unsigned int rx_irq; 126 unsigned int err_irq; 127 }; 128 129 static inline struct 130 ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 131 { 132 return container_of(port, struct ltq_uart_port, port); 133 } 134 135 static void 136 lqasc_stop_tx(struct uart_port *port) 137 { 138 return; 139 } 140 141 static void 142 lqasc_start_tx(struct uart_port *port) 143 { 144 unsigned long flags; 145 spin_lock_irqsave(<q_asc_lock, flags); 146 lqasc_tx_chars(port); 147 spin_unlock_irqrestore(<q_asc_lock, flags); 148 return; 149 } 150 151 static void 152 lqasc_stop_rx(struct uart_port *port) 153 { 154 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 155 } 156 157 static void 158 lqasc_enable_ms(struct uart_port *port) 159 { 160 } 161 162 static int 163 lqasc_rx_chars(struct uart_port *port) 164 { 165 struct tty_port *tport = &port->state->port; 166 struct tty_struct *tty = tty_port_tty_get(tport); 167 unsigned int ch = 0, rsr = 0, fifocnt; 168 169 if (!tty) { 170 dev_dbg(port->dev, "%s:tty is busy now", __func__); 171 return -EBUSY; 172 } 173 fifocnt = 174 ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; 175 while (fifocnt--) { 176 u8 flag = TTY_NORMAL; 177 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); 178 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) 179 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 180 tty_flip_buffer_push(tty); 181 port->icount.rx++; 182 183 /* 184 * Note that the error handling code is 185 * out of the main execution path 186 */ 187 if (rsr & ASCSTATE_ANY) { 188 if (rsr & ASCSTATE_PE) { 189 port->icount.parity++; 190 ltq_w32_mask(0, ASCWHBSTATE_CLRPE, 191 port->membase + LTQ_ASC_WHBSTATE); 192 } else if (rsr & ASCSTATE_FE) { 193 port->icount.frame++; 194 ltq_w32_mask(0, ASCWHBSTATE_CLRFE, 195 port->membase + LTQ_ASC_WHBSTATE); 196 } 197 if (rsr & ASCSTATE_ROE) { 198 port->icount.overrun++; 199 ltq_w32_mask(0, ASCWHBSTATE_CLRROE, 200 port->membase + LTQ_ASC_WHBSTATE); 201 } 202 203 rsr &= port->read_status_mask; 204 205 if (rsr & ASCSTATE_PE) 206 flag = TTY_PARITY; 207 else if (rsr & ASCSTATE_FE) 208 flag = TTY_FRAME; 209 } 210 211 if ((rsr & port->ignore_status_mask) == 0) 212 tty_insert_flip_char(tport, ch, flag); 213 214 if (rsr & ASCSTATE_ROE) 215 /* 216 * Overrun is special, since it's reported 217 * immediately, and doesn't affect the current 218 * character 219 */ 220 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 221 } 222 if (ch != 0) 223 tty_flip_buffer_push(tty); 224 tty_kref_put(tty); 225 return 0; 226 } 227 228 static void 229 lqasc_tx_chars(struct uart_port *port) 230 { 231 struct circ_buf *xmit = &port->state->xmit; 232 if (uart_tx_stopped(port)) { 233 lqasc_stop_tx(port); 234 return; 235 } 236 237 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & 238 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { 239 if (port->x_char) { 240 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); 241 port->icount.tx++; 242 port->x_char = 0; 243 continue; 244 } 245 246 if (uart_circ_empty(xmit)) 247 break; 248 249 ltq_w8(port->state->xmit.buf[port->state->xmit.tail], 250 port->membase + LTQ_ASC_TBUF); 251 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 252 port->icount.tx++; 253 } 254 255 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 256 uart_write_wakeup(port); 257 } 258 259 static irqreturn_t 260 lqasc_tx_int(int irq, void *_port) 261 { 262 unsigned long flags; 263 struct uart_port *port = (struct uart_port *)_port; 264 spin_lock_irqsave(<q_asc_lock, flags); 265 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 266 spin_unlock_irqrestore(<q_asc_lock, flags); 267 lqasc_start_tx(port); 268 return IRQ_HANDLED; 269 } 270 271 static irqreturn_t 272 lqasc_err_int(int irq, void *_port) 273 { 274 unsigned long flags; 275 struct uart_port *port = (struct uart_port *)_port; 276 spin_lock_irqsave(<q_asc_lock, flags); 277 /* clear any pending interrupts */ 278 ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 279 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 280 spin_unlock_irqrestore(<q_asc_lock, flags); 281 return IRQ_HANDLED; 282 } 283 284 static irqreturn_t 285 lqasc_rx_int(int irq, void *_port) 286 { 287 unsigned long flags; 288 struct uart_port *port = (struct uart_port *)_port; 289 spin_lock_irqsave(<q_asc_lock, flags); 290 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 291 lqasc_rx_chars(port); 292 spin_unlock_irqrestore(<q_asc_lock, flags); 293 return IRQ_HANDLED; 294 } 295 296 static unsigned int 297 lqasc_tx_empty(struct uart_port *port) 298 { 299 int status; 300 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; 301 return status ? 0 : TIOCSER_TEMT; 302 } 303 304 static unsigned int 305 lqasc_get_mctrl(struct uart_port *port) 306 { 307 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 308 } 309 310 static void 311 lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 312 { 313 } 314 315 static void 316 lqasc_break_ctl(struct uart_port *port, int break_state) 317 { 318 } 319 320 static int 321 lqasc_startup(struct uart_port *port) 322 { 323 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 324 int retval; 325 326 if (ltq_port->clk) 327 clk_enable(ltq_port->clk); 328 port->uartclk = clk_get_rate(ltq_port->fpiclk); 329 330 ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 331 port->membase + LTQ_ASC_CLC); 332 333 ltq_w32(0, port->membase + LTQ_ASC_PISEL); 334 ltq_w32( 335 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 336 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 337 port->membase + LTQ_ASC_TXFCON); 338 ltq_w32( 339 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 340 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 341 port->membase + LTQ_ASC_RXFCON); 342 /* make sure other settings are written to hardware before 343 * setting enable bits 344 */ 345 wmb(); 346 ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 347 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 348 349 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 350 0, "asc_tx", port); 351 if (retval) { 352 pr_err("failed to request lqasc_tx_int\n"); 353 return retval; 354 } 355 356 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 357 0, "asc_rx", port); 358 if (retval) { 359 pr_err("failed to request lqasc_rx_int\n"); 360 goto err1; 361 } 362 363 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 364 0, "asc_err", port); 365 if (retval) { 366 pr_err("failed to request lqasc_err_int\n"); 367 goto err2; 368 } 369 370 ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 371 port->membase + LTQ_ASC_IRNREN); 372 return 0; 373 374 err2: 375 free_irq(ltq_port->rx_irq, port); 376 err1: 377 free_irq(ltq_port->tx_irq, port); 378 return retval; 379 } 380 381 static void 382 lqasc_shutdown(struct uart_port *port) 383 { 384 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 385 free_irq(ltq_port->tx_irq, port); 386 free_irq(ltq_port->rx_irq, port); 387 free_irq(ltq_port->err_irq, port); 388 389 ltq_w32(0, port->membase + LTQ_ASC_CON); 390 ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 391 port->membase + LTQ_ASC_RXFCON); 392 ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 393 port->membase + LTQ_ASC_TXFCON); 394 if (ltq_port->clk) 395 clk_disable(ltq_port->clk); 396 } 397 398 static void 399 lqasc_set_termios(struct uart_port *port, 400 struct ktermios *new, struct ktermios *old) 401 { 402 unsigned int cflag; 403 unsigned int iflag; 404 unsigned int divisor; 405 unsigned int baud; 406 unsigned int con = 0; 407 unsigned long flags; 408 409 cflag = new->c_cflag; 410 iflag = new->c_iflag; 411 412 switch (cflag & CSIZE) { 413 case CS7: 414 con = ASCCON_M_7ASYNC; 415 break; 416 417 case CS5: 418 case CS6: 419 default: 420 new->c_cflag &= ~ CSIZE; 421 new->c_cflag |= CS8; 422 con = ASCCON_M_8ASYNC; 423 break; 424 } 425 426 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 427 428 if (cflag & CSTOPB) 429 con |= ASCCON_STP; 430 431 if (cflag & PARENB) { 432 if (!(cflag & PARODD)) 433 con &= ~ASCCON_ODD; 434 else 435 con |= ASCCON_ODD; 436 } 437 438 port->read_status_mask = ASCSTATE_ROE; 439 if (iflag & INPCK) 440 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 441 442 port->ignore_status_mask = 0; 443 if (iflag & IGNPAR) 444 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 445 446 if (iflag & IGNBRK) { 447 /* 448 * If we're ignoring parity and break indicators, 449 * ignore overruns too (for real raw support). 450 */ 451 if (iflag & IGNPAR) 452 port->ignore_status_mask |= ASCSTATE_ROE; 453 } 454 455 if ((cflag & CREAD) == 0) 456 port->ignore_status_mask |= UART_DUMMY_UER_RX; 457 458 /* set error signals - framing, parity and overrun, enable receiver */ 459 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 460 461 spin_lock_irqsave(<q_asc_lock, flags); 462 463 /* set up CON */ 464 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); 465 466 /* Set baud rate - take a divider of 2 into account */ 467 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 468 divisor = uart_get_divisor(port, baud); 469 divisor = divisor / 2 - 1; 470 471 /* disable the baudrate generator */ 472 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 473 474 /* make sure the fractional divider is off */ 475 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 476 477 /* set up to use divisor of 2 */ 478 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 479 480 /* now we can write the new baudrate into the register */ 481 ltq_w32(divisor, port->membase + LTQ_ASC_BG); 482 483 /* turn the baudrate generator back on */ 484 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); 485 486 /* enable rx */ 487 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 488 489 spin_unlock_irqrestore(<q_asc_lock, flags); 490 491 /* Don't rewrite B0 */ 492 if (tty_termios_baud_rate(new)) 493 tty_termios_encode_baud_rate(new, baud, baud); 494 495 uart_update_timeout(port, cflag, baud); 496 } 497 498 static const char* 499 lqasc_type(struct uart_port *port) 500 { 501 if (port->type == PORT_LTQ_ASC) 502 return DRVNAME; 503 else 504 return NULL; 505 } 506 507 static void 508 lqasc_release_port(struct uart_port *port) 509 { 510 if (port->flags & UPF_IOREMAP) { 511 iounmap(port->membase); 512 port->membase = NULL; 513 } 514 } 515 516 static int 517 lqasc_request_port(struct uart_port *port) 518 { 519 struct platform_device *pdev = to_platform_device(port->dev); 520 struct resource *res; 521 int size; 522 523 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 524 if (!res) { 525 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 526 return -ENODEV; 527 } 528 size = resource_size(res); 529 530 res = devm_request_mem_region(&pdev->dev, res->start, 531 size, dev_name(&pdev->dev)); 532 if (!res) { 533 dev_err(&pdev->dev, "cannot request I/O memory region"); 534 return -EBUSY; 535 } 536 537 if (port->flags & UPF_IOREMAP) { 538 port->membase = devm_ioremap_nocache(&pdev->dev, 539 port->mapbase, size); 540 if (port->membase == NULL) 541 return -ENOMEM; 542 } 543 return 0; 544 } 545 546 static void 547 lqasc_config_port(struct uart_port *port, int flags) 548 { 549 if (flags & UART_CONFIG_TYPE) { 550 port->type = PORT_LTQ_ASC; 551 lqasc_request_port(port); 552 } 553 } 554 555 static int 556 lqasc_verify_port(struct uart_port *port, 557 struct serial_struct *ser) 558 { 559 int ret = 0; 560 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 561 ret = -EINVAL; 562 if (ser->irq < 0 || ser->irq >= NR_IRQS) 563 ret = -EINVAL; 564 if (ser->baud_base < 9600) 565 ret = -EINVAL; 566 return ret; 567 } 568 569 static struct uart_ops lqasc_pops = { 570 .tx_empty = lqasc_tx_empty, 571 .set_mctrl = lqasc_set_mctrl, 572 .get_mctrl = lqasc_get_mctrl, 573 .stop_tx = lqasc_stop_tx, 574 .start_tx = lqasc_start_tx, 575 .stop_rx = lqasc_stop_rx, 576 .enable_ms = lqasc_enable_ms, 577 .break_ctl = lqasc_break_ctl, 578 .startup = lqasc_startup, 579 .shutdown = lqasc_shutdown, 580 .set_termios = lqasc_set_termios, 581 .type = lqasc_type, 582 .release_port = lqasc_release_port, 583 .request_port = lqasc_request_port, 584 .config_port = lqasc_config_port, 585 .verify_port = lqasc_verify_port, 586 }; 587 588 static void 589 lqasc_console_putchar(struct uart_port *port, int ch) 590 { 591 int fifofree; 592 593 if (!port->membase) 594 return; 595 596 do { 597 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) 598 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; 599 } while (fifofree == 0); 600 ltq_w8(ch, port->membase + LTQ_ASC_TBUF); 601 } 602 603 604 static void 605 lqasc_console_write(struct console *co, const char *s, u_int count) 606 { 607 struct ltq_uart_port *ltq_port; 608 struct uart_port *port; 609 unsigned long flags; 610 611 if (co->index >= MAXPORTS) 612 return; 613 614 ltq_port = lqasc_port[co->index]; 615 if (!ltq_port) 616 return; 617 618 port = <q_port->port; 619 620 spin_lock_irqsave(<q_asc_lock, flags); 621 uart_console_write(port, s, count, lqasc_console_putchar); 622 spin_unlock_irqrestore(<q_asc_lock, flags); 623 } 624 625 static int __init 626 lqasc_console_setup(struct console *co, char *options) 627 { 628 struct ltq_uart_port *ltq_port; 629 struct uart_port *port; 630 int baud = 115200; 631 int bits = 8; 632 int parity = 'n'; 633 int flow = 'n'; 634 635 if (co->index >= MAXPORTS) 636 return -ENODEV; 637 638 ltq_port = lqasc_port[co->index]; 639 if (!ltq_port) 640 return -ENODEV; 641 642 port = <q_port->port; 643 644 port->uartclk = clk_get_rate(ltq_port->fpiclk); 645 646 if (options) 647 uart_parse_options(options, &baud, &parity, &bits, &flow); 648 return uart_set_options(port, co, baud, parity, bits, flow); 649 } 650 651 static struct console lqasc_console = { 652 .name = "ttyLTQ", 653 .write = lqasc_console_write, 654 .device = uart_console_device, 655 .setup = lqasc_console_setup, 656 .flags = CON_PRINTBUFFER, 657 .index = -1, 658 .data = &lqasc_reg, 659 }; 660 661 static int __init 662 lqasc_console_init(void) 663 { 664 register_console(&lqasc_console); 665 return 0; 666 } 667 console_initcall(lqasc_console_init); 668 669 static struct uart_driver lqasc_reg = { 670 .owner = THIS_MODULE, 671 .driver_name = DRVNAME, 672 .dev_name = "ttyLTQ", 673 .major = 0, 674 .minor = 0, 675 .nr = MAXPORTS, 676 .cons = &lqasc_console, 677 }; 678 679 static int __init 680 lqasc_probe(struct platform_device *pdev) 681 { 682 struct device_node *node = pdev->dev.of_node; 683 struct ltq_uart_port *ltq_port; 684 struct uart_port *port; 685 struct resource *mmres, irqres[3]; 686 int line = 0; 687 int ret; 688 689 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 690 ret = of_irq_to_resource_table(node, irqres, 3); 691 if (!mmres || (ret != 3)) { 692 dev_err(&pdev->dev, 693 "failed to get memory/irq for serial port\n"); 694 return -ENODEV; 695 } 696 697 /* check if this is the console port */ 698 if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC)) 699 line = 1; 700 701 if (lqasc_port[line]) { 702 dev_err(&pdev->dev, "port %d already allocated\n", line); 703 return -EBUSY; 704 } 705 706 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 707 GFP_KERNEL); 708 if (!ltq_port) 709 return -ENOMEM; 710 711 port = <q_port->port; 712 713 port->iotype = SERIAL_IO_MEM; 714 port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP; 715 port->ops = &lqasc_pops; 716 port->fifosize = 16; 717 port->type = PORT_LTQ_ASC, 718 port->line = line; 719 port->dev = &pdev->dev; 720 /* unused, just to be backward-compatible */ 721 port->irq = irqres[0].start; 722 port->mapbase = mmres->start; 723 724 ltq_port->fpiclk = clk_get_fpi(); 725 if (IS_ERR(ltq_port->fpiclk)) { 726 pr_err("failed to get fpi clk\n"); 727 return -ENOENT; 728 } 729 730 /* not all asc ports have clock gates, lets ignore the return code */ 731 ltq_port->clk = clk_get(&pdev->dev, NULL); 732 733 ltq_port->tx_irq = irqres[0].start; 734 ltq_port->rx_irq = irqres[1].start; 735 ltq_port->err_irq = irqres[2].start; 736 737 lqasc_port[line] = ltq_port; 738 platform_set_drvdata(pdev, ltq_port); 739 740 ret = uart_add_one_port(&lqasc_reg, port); 741 742 return ret; 743 } 744 745 static const struct of_device_id ltq_asc_match[] = { 746 { .compatible = DRVNAME }, 747 {}, 748 }; 749 MODULE_DEVICE_TABLE(of, ltq_asc_match); 750 751 static struct platform_driver lqasc_driver = { 752 .driver = { 753 .name = DRVNAME, 754 .owner = THIS_MODULE, 755 .of_match_table = ltq_asc_match, 756 }, 757 }; 758 759 int __init 760 init_lqasc(void) 761 { 762 int ret; 763 764 ret = uart_register_driver(&lqasc_reg); 765 if (ret != 0) 766 return ret; 767 768 ret = platform_driver_probe(&lqasc_driver, lqasc_probe); 769 if (ret != 0) 770 uart_unregister_driver(&lqasc_reg); 771 772 return ret; 773 } 774 775 module_init(init_lqasc); 776 777 MODULE_DESCRIPTION("Lantiq serial port driver"); 778 MODULE_LICENSE("GPL"); 779