1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * This is a generic driver for ARM AMBA-type serial ports. They 24 * have a lot of 16550-like features, but are not register compatible. 25 * Note that although they do have CTS, DCD and DSR inputs, they do 26 * not have an RI input, nor do they have DTR or RTS outputs. If 27 * required, these have to be supplied via some other means (eg, GPIO) 28 * and hooked into this driver. 29 */ 30 31 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 32 #define SUPPORT_SYSRQ 33 #endif 34 35 #include <linux/module.h> 36 #include <linux/ioport.h> 37 #include <linux/init.h> 38 #include <linux/console.h> 39 #include <linux/sysrq.h> 40 #include <linux/device.h> 41 #include <linux/tty.h> 42 #include <linux/tty_flip.h> 43 #include <linux/serial_core.h> 44 #include <linux/serial.h> 45 #include <linux/amba/bus.h> 46 #include <linux/amba/serial.h> 47 #include <linux/clk.h> 48 #include <linux/slab.h> 49 #include <linux/io.h> 50 51 #define UART_NR 8 52 53 #define SERIAL_AMBA_MAJOR 204 54 #define SERIAL_AMBA_MINOR 16 55 #define SERIAL_AMBA_NR UART_NR 56 57 #define AMBA_ISR_PASS_LIMIT 256 58 59 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 60 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 61 62 #define UART_DUMMY_RSR_RX 256 63 #define UART_PORT_SIZE 64 64 65 /* 66 * We wrap our port structure around the generic uart_port. 67 */ 68 struct uart_amba_port { 69 struct uart_port port; 70 struct clk *clk; 71 struct amba_device *dev; 72 struct amba_pl010_data *data; 73 unsigned int old_status; 74 }; 75 76 static void pl010_stop_tx(struct uart_port *port) 77 { 78 struct uart_amba_port *uap = 79 container_of(port, struct uart_amba_port, port); 80 unsigned int cr; 81 82 cr = readb(uap->port.membase + UART010_CR); 83 cr &= ~UART010_CR_TIE; 84 writel(cr, uap->port.membase + UART010_CR); 85 } 86 87 static void pl010_start_tx(struct uart_port *port) 88 { 89 struct uart_amba_port *uap = 90 container_of(port, struct uart_amba_port, port); 91 unsigned int cr; 92 93 cr = readb(uap->port.membase + UART010_CR); 94 cr |= UART010_CR_TIE; 95 writel(cr, uap->port.membase + UART010_CR); 96 } 97 98 static void pl010_stop_rx(struct uart_port *port) 99 { 100 struct uart_amba_port *uap = 101 container_of(port, struct uart_amba_port, port); 102 unsigned int cr; 103 104 cr = readb(uap->port.membase + UART010_CR); 105 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 106 writel(cr, uap->port.membase + UART010_CR); 107 } 108 109 static void pl010_enable_ms(struct uart_port *port) 110 { 111 struct uart_amba_port *uap = 112 container_of(port, struct uart_amba_port, port); 113 unsigned int cr; 114 115 cr = readb(uap->port.membase + UART010_CR); 116 cr |= UART010_CR_MSIE; 117 writel(cr, uap->port.membase + UART010_CR); 118 } 119 120 static void pl010_rx_chars(struct uart_amba_port *uap) 121 { 122 unsigned int status, ch, flag, rsr, max_count = 256; 123 124 status = readb(uap->port.membase + UART01x_FR); 125 while (UART_RX_DATA(status) && max_count--) { 126 ch = readb(uap->port.membase + UART01x_DR); 127 flag = TTY_NORMAL; 128 129 uap->port.icount.rx++; 130 131 /* 132 * Note that the error handling code is 133 * out of the main execution path 134 */ 135 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 136 if (unlikely(rsr & UART01x_RSR_ANY)) { 137 writel(0, uap->port.membase + UART01x_ECR); 138 139 if (rsr & UART01x_RSR_BE) { 140 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 141 uap->port.icount.brk++; 142 if (uart_handle_break(&uap->port)) 143 goto ignore_char; 144 } else if (rsr & UART01x_RSR_PE) 145 uap->port.icount.parity++; 146 else if (rsr & UART01x_RSR_FE) 147 uap->port.icount.frame++; 148 if (rsr & UART01x_RSR_OE) 149 uap->port.icount.overrun++; 150 151 rsr &= uap->port.read_status_mask; 152 153 if (rsr & UART01x_RSR_BE) 154 flag = TTY_BREAK; 155 else if (rsr & UART01x_RSR_PE) 156 flag = TTY_PARITY; 157 else if (rsr & UART01x_RSR_FE) 158 flag = TTY_FRAME; 159 } 160 161 if (uart_handle_sysrq_char(&uap->port, ch)) 162 goto ignore_char; 163 164 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); 165 166 ignore_char: 167 status = readb(uap->port.membase + UART01x_FR); 168 } 169 spin_unlock(&uap->port.lock); 170 tty_flip_buffer_push(&uap->port.state->port); 171 spin_lock(&uap->port.lock); 172 } 173 174 static void pl010_tx_chars(struct uart_amba_port *uap) 175 { 176 struct circ_buf *xmit = &uap->port.state->xmit; 177 int count; 178 179 if (uap->port.x_char) { 180 writel(uap->port.x_char, uap->port.membase + UART01x_DR); 181 uap->port.icount.tx++; 182 uap->port.x_char = 0; 183 return; 184 } 185 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 186 pl010_stop_tx(&uap->port); 187 return; 188 } 189 190 count = uap->port.fifosize >> 1; 191 do { 192 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); 193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 194 uap->port.icount.tx++; 195 if (uart_circ_empty(xmit)) 196 break; 197 } while (--count > 0); 198 199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 200 uart_write_wakeup(&uap->port); 201 202 if (uart_circ_empty(xmit)) 203 pl010_stop_tx(&uap->port); 204 } 205 206 static void pl010_modem_status(struct uart_amba_port *uap) 207 { 208 unsigned int status, delta; 209 210 writel(0, uap->port.membase + UART010_ICR); 211 212 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 213 214 delta = status ^ uap->old_status; 215 uap->old_status = status; 216 217 if (!delta) 218 return; 219 220 if (delta & UART01x_FR_DCD) 221 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 222 223 if (delta & UART01x_FR_DSR) 224 uap->port.icount.dsr++; 225 226 if (delta & UART01x_FR_CTS) 227 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 228 229 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 230 } 231 232 static irqreturn_t pl010_int(int irq, void *dev_id) 233 { 234 struct uart_amba_port *uap = dev_id; 235 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 236 int handled = 0; 237 238 spin_lock(&uap->port.lock); 239 240 status = readb(uap->port.membase + UART010_IIR); 241 if (status) { 242 do { 243 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 244 pl010_rx_chars(uap); 245 if (status & UART010_IIR_MIS) 246 pl010_modem_status(uap); 247 if (status & UART010_IIR_TIS) 248 pl010_tx_chars(uap); 249 250 if (pass_counter-- == 0) 251 break; 252 253 status = readb(uap->port.membase + UART010_IIR); 254 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 255 UART010_IIR_TIS)); 256 handled = 1; 257 } 258 259 spin_unlock(&uap->port.lock); 260 261 return IRQ_RETVAL(handled); 262 } 263 264 static unsigned int pl010_tx_empty(struct uart_port *port) 265 { 266 struct uart_amba_port *uap = 267 container_of(port, struct uart_amba_port, port); 268 unsigned int status = readb(uap->port.membase + UART01x_FR); 269 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 270 } 271 272 static unsigned int pl010_get_mctrl(struct uart_port *port) 273 { 274 struct uart_amba_port *uap = 275 container_of(port, struct uart_amba_port, port); 276 unsigned int result = 0; 277 unsigned int status; 278 279 status = readb(uap->port.membase + UART01x_FR); 280 if (status & UART01x_FR_DCD) 281 result |= TIOCM_CAR; 282 if (status & UART01x_FR_DSR) 283 result |= TIOCM_DSR; 284 if (status & UART01x_FR_CTS) 285 result |= TIOCM_CTS; 286 287 return result; 288 } 289 290 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 291 { 292 struct uart_amba_port *uap = 293 container_of(port, struct uart_amba_port, port); 294 295 if (uap->data) 296 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); 297 } 298 299 static void pl010_break_ctl(struct uart_port *port, int break_state) 300 { 301 struct uart_amba_port *uap = 302 container_of(port, struct uart_amba_port, port); 303 unsigned long flags; 304 unsigned int lcr_h; 305 306 spin_lock_irqsave(&uap->port.lock, flags); 307 lcr_h = readb(uap->port.membase + UART010_LCRH); 308 if (break_state == -1) 309 lcr_h |= UART01x_LCRH_BRK; 310 else 311 lcr_h &= ~UART01x_LCRH_BRK; 312 writel(lcr_h, uap->port.membase + UART010_LCRH); 313 spin_unlock_irqrestore(&uap->port.lock, flags); 314 } 315 316 static int pl010_startup(struct uart_port *port) 317 { 318 struct uart_amba_port *uap = 319 container_of(port, struct uart_amba_port, port); 320 int retval; 321 322 /* 323 * Try to enable the clock producer. 324 */ 325 retval = clk_prepare_enable(uap->clk); 326 if (retval) 327 goto out; 328 329 uap->port.uartclk = clk_get_rate(uap->clk); 330 331 /* 332 * Allocate the IRQ 333 */ 334 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); 335 if (retval) 336 goto clk_dis; 337 338 /* 339 * initialise the old status of the modem signals 340 */ 341 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 342 343 /* 344 * Finally, enable interrupts 345 */ 346 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 347 uap->port.membase + UART010_CR); 348 349 return 0; 350 351 clk_dis: 352 clk_disable_unprepare(uap->clk); 353 out: 354 return retval; 355 } 356 357 static void pl010_shutdown(struct uart_port *port) 358 { 359 struct uart_amba_port *uap = 360 container_of(port, struct uart_amba_port, port); 361 362 /* 363 * Free the interrupt 364 */ 365 free_irq(uap->port.irq, uap); 366 367 /* 368 * disable all interrupts, disable the port 369 */ 370 writel(0, uap->port.membase + UART010_CR); 371 372 /* disable break condition and fifos */ 373 writel(readb(uap->port.membase + UART010_LCRH) & 374 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 375 uap->port.membase + UART010_LCRH); 376 377 /* 378 * Shut down the clock producer 379 */ 380 clk_disable_unprepare(uap->clk); 381 } 382 383 static void 384 pl010_set_termios(struct uart_port *port, struct ktermios *termios, 385 struct ktermios *old) 386 { 387 struct uart_amba_port *uap = 388 container_of(port, struct uart_amba_port, port); 389 unsigned int lcr_h, old_cr; 390 unsigned long flags; 391 unsigned int baud, quot; 392 393 /* 394 * Ask the core to calculate the divisor for us. 395 */ 396 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); 397 quot = uart_get_divisor(port, baud); 398 399 switch (termios->c_cflag & CSIZE) { 400 case CS5: 401 lcr_h = UART01x_LCRH_WLEN_5; 402 break; 403 case CS6: 404 lcr_h = UART01x_LCRH_WLEN_6; 405 break; 406 case CS7: 407 lcr_h = UART01x_LCRH_WLEN_7; 408 break; 409 default: // CS8 410 lcr_h = UART01x_LCRH_WLEN_8; 411 break; 412 } 413 if (termios->c_cflag & CSTOPB) 414 lcr_h |= UART01x_LCRH_STP2; 415 if (termios->c_cflag & PARENB) { 416 lcr_h |= UART01x_LCRH_PEN; 417 if (!(termios->c_cflag & PARODD)) 418 lcr_h |= UART01x_LCRH_EPS; 419 } 420 if (uap->port.fifosize > 1) 421 lcr_h |= UART01x_LCRH_FEN; 422 423 spin_lock_irqsave(&uap->port.lock, flags); 424 425 /* 426 * Update the per-port timeout. 427 */ 428 uart_update_timeout(port, termios->c_cflag, baud); 429 430 uap->port.read_status_mask = UART01x_RSR_OE; 431 if (termios->c_iflag & INPCK) 432 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 433 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 434 uap->port.read_status_mask |= UART01x_RSR_BE; 435 436 /* 437 * Characters to ignore 438 */ 439 uap->port.ignore_status_mask = 0; 440 if (termios->c_iflag & IGNPAR) 441 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 442 if (termios->c_iflag & IGNBRK) { 443 uap->port.ignore_status_mask |= UART01x_RSR_BE; 444 /* 445 * If we're ignoring parity and break indicators, 446 * ignore overruns too (for real raw support). 447 */ 448 if (termios->c_iflag & IGNPAR) 449 uap->port.ignore_status_mask |= UART01x_RSR_OE; 450 } 451 452 /* 453 * Ignore all characters if CREAD is not set. 454 */ 455 if ((termios->c_cflag & CREAD) == 0) 456 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; 457 458 /* first, disable everything */ 459 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; 460 461 if (UART_ENABLE_MS(port, termios->c_cflag)) 462 old_cr |= UART010_CR_MSIE; 463 464 writel(0, uap->port.membase + UART010_CR); 465 466 /* Set baud rate */ 467 quot -= 1; 468 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); 469 writel(quot & 0xff, uap->port.membase + UART010_LCRL); 470 471 /* 472 * ----------v----------v----------v----------v----- 473 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 474 * ----------^----------^----------^----------^----- 475 */ 476 writel(lcr_h, uap->port.membase + UART010_LCRH); 477 writel(old_cr, uap->port.membase + UART010_CR); 478 479 spin_unlock_irqrestore(&uap->port.lock, flags); 480 } 481 482 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios) 483 { 484 if (termios->c_line == N_PPS) { 485 port->flags |= UPF_HARDPPS_CD; 486 pl010_enable_ms(port); 487 } else 488 port->flags &= ~UPF_HARDPPS_CD; 489 } 490 491 static const char *pl010_type(struct uart_port *port) 492 { 493 return port->type == PORT_AMBA ? "AMBA" : NULL; 494 } 495 496 /* 497 * Release the memory region(s) being used by 'port' 498 */ 499 static void pl010_release_port(struct uart_port *port) 500 { 501 release_mem_region(port->mapbase, UART_PORT_SIZE); 502 } 503 504 /* 505 * Request the memory region(s) being used by 'port' 506 */ 507 static int pl010_request_port(struct uart_port *port) 508 { 509 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") 510 != NULL ? 0 : -EBUSY; 511 } 512 513 /* 514 * Configure/autoconfigure the port. 515 */ 516 static void pl010_config_port(struct uart_port *port, int flags) 517 { 518 if (flags & UART_CONFIG_TYPE) { 519 port->type = PORT_AMBA; 520 pl010_request_port(port); 521 } 522 } 523 524 /* 525 * verify the new serial_struct (for TIOCSSERIAL). 526 */ 527 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 528 { 529 int ret = 0; 530 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 531 ret = -EINVAL; 532 if (ser->irq < 0 || ser->irq >= nr_irqs) 533 ret = -EINVAL; 534 if (ser->baud_base < 9600) 535 ret = -EINVAL; 536 return ret; 537 } 538 539 static struct uart_ops amba_pl010_pops = { 540 .tx_empty = pl010_tx_empty, 541 .set_mctrl = pl010_set_mctrl, 542 .get_mctrl = pl010_get_mctrl, 543 .stop_tx = pl010_stop_tx, 544 .start_tx = pl010_start_tx, 545 .stop_rx = pl010_stop_rx, 546 .enable_ms = pl010_enable_ms, 547 .break_ctl = pl010_break_ctl, 548 .startup = pl010_startup, 549 .shutdown = pl010_shutdown, 550 .set_termios = pl010_set_termios, 551 .set_ldisc = pl010_set_ldisc, 552 .type = pl010_type, 553 .release_port = pl010_release_port, 554 .request_port = pl010_request_port, 555 .config_port = pl010_config_port, 556 .verify_port = pl010_verify_port, 557 }; 558 559 static struct uart_amba_port *amba_ports[UART_NR]; 560 561 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 562 563 static void pl010_console_putchar(struct uart_port *port, int ch) 564 { 565 struct uart_amba_port *uap = 566 container_of(port, struct uart_amba_port, port); 567 unsigned int status; 568 569 do { 570 status = readb(uap->port.membase + UART01x_FR); 571 barrier(); 572 } while (!UART_TX_READY(status)); 573 writel(ch, uap->port.membase + UART01x_DR); 574 } 575 576 static void 577 pl010_console_write(struct console *co, const char *s, unsigned int count) 578 { 579 struct uart_amba_port *uap = amba_ports[co->index]; 580 unsigned int status, old_cr; 581 582 clk_enable(uap->clk); 583 584 /* 585 * First save the CR then disable the interrupts 586 */ 587 old_cr = readb(uap->port.membase + UART010_CR); 588 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); 589 590 uart_console_write(&uap->port, s, count, pl010_console_putchar); 591 592 /* 593 * Finally, wait for transmitter to become empty 594 * and restore the TCR 595 */ 596 do { 597 status = readb(uap->port.membase + UART01x_FR); 598 barrier(); 599 } while (status & UART01x_FR_BUSY); 600 writel(old_cr, uap->port.membase + UART010_CR); 601 602 clk_disable(uap->clk); 603 } 604 605 static void __init 606 pl010_console_get_options(struct uart_amba_port *uap, int *baud, 607 int *parity, int *bits) 608 { 609 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { 610 unsigned int lcr_h, quot; 611 lcr_h = readb(uap->port.membase + UART010_LCRH); 612 613 *parity = 'n'; 614 if (lcr_h & UART01x_LCRH_PEN) { 615 if (lcr_h & UART01x_LCRH_EPS) 616 *parity = 'e'; 617 else 618 *parity = 'o'; 619 } 620 621 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 622 *bits = 7; 623 else 624 *bits = 8; 625 626 quot = readb(uap->port.membase + UART010_LCRL) | 627 readb(uap->port.membase + UART010_LCRM) << 8; 628 *baud = uap->port.uartclk / (16 * (quot + 1)); 629 } 630 } 631 632 static int __init pl010_console_setup(struct console *co, char *options) 633 { 634 struct uart_amba_port *uap; 635 int baud = 38400; 636 int bits = 8; 637 int parity = 'n'; 638 int flow = 'n'; 639 int ret; 640 641 /* 642 * Check whether an invalid uart number has been specified, and 643 * if so, search for the first available port that does have 644 * console support. 645 */ 646 if (co->index >= UART_NR) 647 co->index = 0; 648 uap = amba_ports[co->index]; 649 if (!uap) 650 return -ENODEV; 651 652 ret = clk_prepare(uap->clk); 653 if (ret) 654 return ret; 655 656 uap->port.uartclk = clk_get_rate(uap->clk); 657 658 if (options) 659 uart_parse_options(options, &baud, &parity, &bits, &flow); 660 else 661 pl010_console_get_options(uap, &baud, &parity, &bits); 662 663 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 664 } 665 666 static struct uart_driver amba_reg; 667 static struct console amba_console = { 668 .name = "ttyAM", 669 .write = pl010_console_write, 670 .device = uart_console_device, 671 .setup = pl010_console_setup, 672 .flags = CON_PRINTBUFFER, 673 .index = -1, 674 .data = &amba_reg, 675 }; 676 677 #define AMBA_CONSOLE &amba_console 678 #else 679 #define AMBA_CONSOLE NULL 680 #endif 681 682 static struct uart_driver amba_reg = { 683 .owner = THIS_MODULE, 684 .driver_name = "ttyAM", 685 .dev_name = "ttyAM", 686 .major = SERIAL_AMBA_MAJOR, 687 .minor = SERIAL_AMBA_MINOR, 688 .nr = UART_NR, 689 .cons = AMBA_CONSOLE, 690 }; 691 692 static int pl010_probe(struct amba_device *dev, const struct amba_id *id) 693 { 694 struct uart_amba_port *uap; 695 void __iomem *base; 696 int i, ret; 697 698 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 699 if (amba_ports[i] == NULL) 700 break; 701 702 if (i == ARRAY_SIZE(amba_ports)) 703 return -EBUSY; 704 705 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 706 GFP_KERNEL); 707 if (!uap) 708 return -ENOMEM; 709 710 base = devm_ioremap(&dev->dev, dev->res.start, 711 resource_size(&dev->res)); 712 if (!base) 713 return -ENOMEM; 714 715 uap->clk = devm_clk_get(&dev->dev, NULL); 716 if (IS_ERR(uap->clk)) 717 return PTR_ERR(uap->clk); 718 719 uap->port.dev = &dev->dev; 720 uap->port.mapbase = dev->res.start; 721 uap->port.membase = base; 722 uap->port.iotype = UPIO_MEM; 723 uap->port.irq = dev->irq[0]; 724 uap->port.fifosize = 16; 725 uap->port.ops = &amba_pl010_pops; 726 uap->port.flags = UPF_BOOT_AUTOCONF; 727 uap->port.line = i; 728 uap->dev = dev; 729 uap->data = dev_get_platdata(&dev->dev); 730 731 amba_ports[i] = uap; 732 733 amba_set_drvdata(dev, uap); 734 ret = uart_add_one_port(&amba_reg, &uap->port); 735 if (ret) 736 amba_ports[i] = NULL; 737 738 return ret; 739 } 740 741 static int pl010_remove(struct amba_device *dev) 742 { 743 struct uart_amba_port *uap = amba_get_drvdata(dev); 744 int i; 745 746 uart_remove_one_port(&amba_reg, &uap->port); 747 748 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 749 if (amba_ports[i] == uap) 750 amba_ports[i] = NULL; 751 752 return 0; 753 } 754 755 #ifdef CONFIG_PM_SLEEP 756 static int pl010_suspend(struct device *dev) 757 { 758 struct uart_amba_port *uap = dev_get_drvdata(dev); 759 760 if (uap) 761 uart_suspend_port(&amba_reg, &uap->port); 762 763 return 0; 764 } 765 766 static int pl010_resume(struct device *dev) 767 { 768 struct uart_amba_port *uap = dev_get_drvdata(dev); 769 770 if (uap) 771 uart_resume_port(&amba_reg, &uap->port); 772 773 return 0; 774 } 775 #endif 776 777 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume); 778 779 static struct amba_id pl010_ids[] = { 780 { 781 .id = 0x00041010, 782 .mask = 0x000fffff, 783 }, 784 { 0, 0 }, 785 }; 786 787 MODULE_DEVICE_TABLE(amba, pl010_ids); 788 789 static struct amba_driver pl010_driver = { 790 .drv = { 791 .name = "uart-pl010", 792 .pm = &pl010_dev_pm_ops, 793 }, 794 .id_table = pl010_ids, 795 .probe = pl010_probe, 796 .remove = pl010_remove, 797 }; 798 799 static int __init pl010_init(void) 800 { 801 int ret; 802 803 printk(KERN_INFO "Serial: AMBA driver\n"); 804 805 ret = uart_register_driver(&amba_reg); 806 if (ret == 0) { 807 ret = amba_driver_register(&pl010_driver); 808 if (ret) 809 uart_unregister_driver(&amba_reg); 810 } 811 return ret; 812 } 813 814 static void __exit pl010_exit(void) 815 { 816 amba_driver_unregister(&pl010_driver); 817 uart_unregister_driver(&amba_reg); 818 } 819 820 module_init(pl010_init); 821 module_exit(pl010_exit); 822 823 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 824 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 825 MODULE_LICENSE("GPL"); 826