1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 216603153SAndreas Noever /* 3*15c6784cSMika Westerberg * Thunderbolt driver - NHI driver 416603153SAndreas Noever * 516603153SAndreas Noever * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6*15c6784cSMika Westerberg * Copyright (C) 2018, Intel Corporation 716603153SAndreas Noever */ 816603153SAndreas Noever 916603153SAndreas Noever #ifndef DSL3510_H_ 1016603153SAndreas Noever #define DSL3510_H_ 1116603153SAndreas Noever 123b3d9f4dSMika Westerberg #include <linux/thunderbolt.h> 1316603153SAndreas Noever 14cd446ee2SMika Westerberg enum nhi_fw_mode { 15cd446ee2SMika Westerberg NHI_FW_SAFE_MODE, 16cd446ee2SMika Westerberg NHI_FW_AUTH_MODE, 17cd446ee2SMika Westerberg NHI_FW_EP_MODE, 18cd446ee2SMika Westerberg NHI_FW_CM_MODE, 19cd446ee2SMika Westerberg }; 20cd446ee2SMika Westerberg 21cd446ee2SMika Westerberg enum nhi_mailbox_cmd { 22cd446ee2SMika Westerberg NHI_MAILBOX_SAVE_DEVS = 0x05, 23e6b245ccSMika Westerberg NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06, 24cd446ee2SMika Westerberg NHI_MAILBOX_DRV_UNLOADS = 0x07, 25d1ff7024SMika Westerberg NHI_MAILBOX_DISCONNECT_PA = 0x10, 26d1ff7024SMika Westerberg NHI_MAILBOX_DISCONNECT_PB = 0x11, 27cd446ee2SMika Westerberg NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23, 28cd446ee2SMika Westerberg }; 29cd446ee2SMika Westerberg 30cd446ee2SMika Westerberg int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data); 31cd446ee2SMika Westerberg enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi); 32cd446ee2SMika Westerberg 335e2781bcSMika Westerberg /* 345e2781bcSMika Westerberg * PCI IDs used in this driver from Win Ridge forward. There is no 355e2781bcSMika Westerberg * need for the PCI quirk anymore as we will use ICM also on Apple 365e2781bcSMika Westerberg * hardware. 375e2781bcSMika Westerberg */ 385e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d 395e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e 405e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf 415e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0 425e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2 435e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3 445e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9 455e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da 465e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc 475e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd 485e2781bcSMika Westerberg #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de 494bac471dSRadion Mirchevsky #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7 504bac471dSRadion Mirchevsky #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8 514bac471dSRadion Mirchevsky #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea 524bac471dSRadion Mirchevsky #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb 534bac471dSRadion Mirchevsky #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef 545e2781bcSMika Westerberg 5516603153SAndreas Noever #endif 56