1 /* 2 * Sonics Silicon Backplane 3 * Broadcom ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include <linux/ssb/ssb.h> 12 #include <linux/ssb/ssb_regs.h> 13 #include <linux/pci.h> 14 15 #include "ssb_private.h" 16 17 18 /* Clock sources */ 19 enum ssb_clksrc { 20 /* PCI clock */ 21 SSB_CHIPCO_CLKSRC_PCI, 22 /* Crystal slow clock oscillator */ 23 SSB_CHIPCO_CLKSRC_XTALOS, 24 /* Low power oscillator */ 25 SSB_CHIPCO_CLKSRC_LOPWROS, 26 }; 27 28 29 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, 30 u32 mask, u32 value) 31 { 32 value &= mask; 33 value |= chipco_read32(cc, offset) & ~mask; 34 chipco_write32(cc, offset, value); 35 36 return value; 37 } 38 39 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, 40 enum ssb_clkmode mode) 41 { 42 struct ssb_device *ccdev = cc->dev; 43 struct ssb_bus *bus; 44 u32 tmp; 45 46 if (!ccdev) 47 return; 48 bus = ccdev->bus; 49 /* chipcommon cores prior to rev6 don't support dynamic clock control */ 50 if (ccdev->id.revision < 6) 51 return; 52 /* chipcommon cores rev10 are a whole new ball game */ 53 if (ccdev->id.revision >= 10) 54 return; 55 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 56 return; 57 58 switch (mode) { 59 case SSB_CLKMODE_SLOW: 60 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 61 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; 62 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 63 break; 64 case SSB_CLKMODE_FAST: 65 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ 66 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 67 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; 68 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; 69 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 70 break; 71 case SSB_CLKMODE_DYNAMIC: 72 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 73 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; 74 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; 75 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; 76 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) 77 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; 78 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 79 80 /* for dynamic control, we have to release our xtal_pu "force on" */ 81 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) 82 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); 83 break; 84 default: 85 SSB_WARN_ON(1); 86 } 87 } 88 89 /* Get the Slow Clock Source */ 90 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) 91 { 92 struct ssb_bus *bus = cc->dev->bus; 93 u32 uninitialized_var(tmp); 94 95 if (cc->dev->id.revision < 6) { 96 if (bus->bustype == SSB_BUSTYPE_SSB || 97 bus->bustype == SSB_BUSTYPE_PCMCIA) 98 return SSB_CHIPCO_CLKSRC_XTALOS; 99 if (bus->bustype == SSB_BUSTYPE_PCI) { 100 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); 101 if (tmp & 0x10) 102 return SSB_CHIPCO_CLKSRC_PCI; 103 return SSB_CHIPCO_CLKSRC_XTALOS; 104 } 105 } 106 if (cc->dev->id.revision < 10) { 107 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 108 tmp &= 0x7; 109 if (tmp == 0) 110 return SSB_CHIPCO_CLKSRC_LOPWROS; 111 if (tmp == 1) 112 return SSB_CHIPCO_CLKSRC_XTALOS; 113 if (tmp == 2) 114 return SSB_CHIPCO_CLKSRC_PCI; 115 } 116 117 return SSB_CHIPCO_CLKSRC_XTALOS; 118 } 119 120 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ 121 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) 122 { 123 int uninitialized_var(limit); 124 enum ssb_clksrc clocksrc; 125 int divisor = 1; 126 u32 tmp; 127 128 clocksrc = chipco_pctl_get_slowclksrc(cc); 129 if (cc->dev->id.revision < 6) { 130 switch (clocksrc) { 131 case SSB_CHIPCO_CLKSRC_PCI: 132 divisor = 64; 133 break; 134 case SSB_CHIPCO_CLKSRC_XTALOS: 135 divisor = 32; 136 break; 137 default: 138 SSB_WARN_ON(1); 139 } 140 } else if (cc->dev->id.revision < 10) { 141 switch (clocksrc) { 142 case SSB_CHIPCO_CLKSRC_LOPWROS: 143 break; 144 case SSB_CHIPCO_CLKSRC_XTALOS: 145 case SSB_CHIPCO_CLKSRC_PCI: 146 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 147 divisor = (tmp >> 16) + 1; 148 divisor *= 4; 149 break; 150 } 151 } else { 152 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); 153 divisor = (tmp >> 16) + 1; 154 divisor *= 4; 155 } 156 157 switch (clocksrc) { 158 case SSB_CHIPCO_CLKSRC_LOPWROS: 159 if (get_max) 160 limit = 43000; 161 else 162 limit = 25000; 163 break; 164 case SSB_CHIPCO_CLKSRC_XTALOS: 165 if (get_max) 166 limit = 20200000; 167 else 168 limit = 19800000; 169 break; 170 case SSB_CHIPCO_CLKSRC_PCI: 171 if (get_max) 172 limit = 34000000; 173 else 174 limit = 25000000; 175 break; 176 } 177 limit /= divisor; 178 179 return limit; 180 } 181 182 static void chipco_powercontrol_init(struct ssb_chipcommon *cc) 183 { 184 struct ssb_bus *bus = cc->dev->bus; 185 186 if (bus->chip_id == 0x4321) { 187 if (bus->chip_rev == 0) 188 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); 189 else if (bus->chip_rev == 1) 190 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); 191 } 192 193 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 194 return; 195 196 if (cc->dev->id.revision >= 10) { 197 /* Set Idle Power clock rate to 1Mhz */ 198 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, 199 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & 200 0x0000FFFF) | 0x00040000); 201 } else { 202 int maxfreq; 203 204 maxfreq = chipco_pctl_clockfreqlimit(cc, 1); 205 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, 206 (maxfreq * 150 + 999999) / 1000000); 207 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, 208 (maxfreq * 15 + 999999) / 1000000); 209 } 210 } 211 212 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) 213 { 214 struct ssb_bus *bus = cc->dev->bus; 215 int minfreq; 216 unsigned int tmp; 217 u32 pll_on_delay; 218 219 if (bus->bustype != SSB_BUSTYPE_PCI) 220 return; 221 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 222 return; 223 224 minfreq = chipco_pctl_clockfreqlimit(cc, 0); 225 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); 226 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; 227 SSB_WARN_ON(tmp & ~0xFFFF); 228 229 cc->fast_pwrup_delay = tmp; 230 } 231 232 void ssb_chipcommon_init(struct ssb_chipcommon *cc) 233 { 234 if (!cc->dev) 235 return; /* We don't have a ChipCommon */ 236 if (cc->dev->id.revision >= 11) 237 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); 238 ssb_pmu_init(cc); 239 chipco_powercontrol_init(cc); 240 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); 241 calc_fast_powerup_delay(cc); 242 } 243 244 void ssb_chipco_suspend(struct ssb_chipcommon *cc) 245 { 246 if (!cc->dev) 247 return; 248 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 249 } 250 251 void ssb_chipco_resume(struct ssb_chipcommon *cc) 252 { 253 if (!cc->dev) 254 return; 255 chipco_powercontrol_init(cc); 256 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); 257 } 258 259 /* Get the processor clock */ 260 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, 261 u32 *plltype, u32 *n, u32 *m) 262 { 263 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); 264 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 265 switch (*plltype) { 266 case SSB_PLLTYPE_2: 267 case SSB_PLLTYPE_4: 268 case SSB_PLLTYPE_6: 269 case SSB_PLLTYPE_7: 270 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); 271 break; 272 case SSB_PLLTYPE_3: 273 /* 5350 uses m2 to control mips */ 274 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); 275 break; 276 default: 277 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); 278 break; 279 } 280 } 281 282 /* Get the bus clock */ 283 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, 284 u32 *plltype, u32 *n, u32 *m) 285 { 286 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); 287 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 288 switch (*plltype) { 289 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 290 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); 291 break; 292 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 293 if (cc->dev->bus->chip_id != 0x5365) { 294 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); 295 break; 296 } 297 /* Fallthough */ 298 default: 299 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); 300 } 301 } 302 303 void ssb_chipco_timing_init(struct ssb_chipcommon *cc, 304 unsigned long ns) 305 { 306 struct ssb_device *dev = cc->dev; 307 struct ssb_bus *bus = dev->bus; 308 u32 tmp; 309 310 /* set register for external IO to control LED. */ 311 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); 312 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ 313 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ 314 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ 315 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ 316 317 /* Set timing for the flash */ 318 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ 319 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ 320 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ 321 if ((bus->chip_id == 0x5365) || 322 (dev->id.revision < 9)) 323 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); 324 if ((bus->chip_id == 0x5365) || 325 (dev->id.revision < 9) || 326 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0))) 327 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); 328 329 if (bus->chip_id == 0x5350) { 330 /* Enable EXTIF */ 331 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ 332 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ 333 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ 334 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ 335 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ 336 } 337 } 338 339 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 340 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) 341 { 342 /* instant NMI */ 343 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); 344 } 345 346 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) 347 { 348 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value); 349 } 350 351 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask) 352 { 353 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask; 354 } 355 356 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) 357 { 358 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; 359 } 360 361 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) 362 { 363 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); 364 } 365 366 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) 367 { 368 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); 369 } 370 371 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) 372 { 373 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); 374 } 375 EXPORT_SYMBOL(ssb_chipco_gpio_control); 376 377 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) 378 { 379 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); 380 } 381 382 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) 383 { 384 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); 385 } 386 387 #ifdef CONFIG_SSB_SERIAL 388 int ssb_chipco_serial_init(struct ssb_chipcommon *cc, 389 struct ssb_serial_port *ports) 390 { 391 struct ssb_bus *bus = cc->dev->bus; 392 int nr_ports = 0; 393 u32 plltype; 394 unsigned int irq; 395 u32 baud_base, div; 396 u32 i, n; 397 unsigned int ccrev = cc->dev->id.revision; 398 399 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 400 irq = ssb_mips_irq(cc->dev); 401 402 if (plltype == SSB_PLLTYPE_1) { 403 /* PLL clock */ 404 baud_base = ssb_calc_clock_rate(plltype, 405 chipco_read32(cc, SSB_CHIPCO_CLOCK_N), 406 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); 407 div = 1; 408 } else { 409 if (ccrev == 20) { 410 /* BCM5354 uses constant 25MHz clock */ 411 baud_base = 25000000; 412 div = 48; 413 /* Set the override bit so we don't divide it */ 414 chipco_write32(cc, SSB_CHIPCO_CORECTL, 415 chipco_read32(cc, SSB_CHIPCO_CORECTL) 416 | SSB_CHIPCO_CORECTL_UARTCLK0); 417 } else if ((ccrev >= 11) && (ccrev != 15)) { 418 /* Fixed ALP clock */ 419 baud_base = 20000000; 420 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { 421 /* FIXME: baud_base is different for devices with a PMU */ 422 SSB_WARN_ON(1); 423 } 424 div = 1; 425 if (ccrev >= 21) { 426 /* Turn off UART clock before switching clocksource. */ 427 chipco_write32(cc, SSB_CHIPCO_CORECTL, 428 chipco_read32(cc, SSB_CHIPCO_CORECTL) 429 & ~SSB_CHIPCO_CORECTL_UARTCLKEN); 430 } 431 /* Set the override bit so we don't divide it */ 432 chipco_write32(cc, SSB_CHIPCO_CORECTL, 433 chipco_read32(cc, SSB_CHIPCO_CORECTL) 434 | SSB_CHIPCO_CORECTL_UARTCLK0); 435 if (ccrev >= 21) { 436 /* Re-enable the UART clock. */ 437 chipco_write32(cc, SSB_CHIPCO_CORECTL, 438 chipco_read32(cc, SSB_CHIPCO_CORECTL) 439 | SSB_CHIPCO_CORECTL_UARTCLKEN); 440 } 441 } else if (ccrev >= 3) { 442 /* Internal backplane clock */ 443 baud_base = ssb_clockspeed(bus); 444 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) 445 & SSB_CHIPCO_CLKDIV_UART; 446 } else { 447 /* Fixed internal backplane clock */ 448 baud_base = 88000000; 449 div = 48; 450 } 451 452 /* Clock source depends on strapping if UartClkOverride is unset */ 453 if ((ccrev > 0) && 454 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { 455 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == 456 SSB_CHIPCO_CAP_UARTCLK_INT) { 457 /* Internal divided backplane clock */ 458 baud_base /= div; 459 } else { 460 /* Assume external clock of 1.8432 MHz */ 461 baud_base = 1843200; 462 } 463 } 464 } 465 466 /* Determine the registers of the UARTs */ 467 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); 468 for (i = 0; i < n; i++) { 469 void __iomem *cc_mmio; 470 void __iomem *uart_regs; 471 472 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); 473 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; 474 /* Offset changed at after rev 0 */ 475 if (ccrev == 0) 476 uart_regs += (i * 8); 477 else 478 uart_regs += (i * 256); 479 480 nr_ports++; 481 ports[i].regs = uart_regs; 482 ports[i].irq = irq; 483 ports[i].baud_base = baud_base; 484 ports[i].reg_shift = 0; 485 } 486 487 return nr_ports; 488 } 489 #endif /* CONFIG_SSB_SERIAL */ 490