1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/device.h> 19 #include <linux/ioport.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/interrupt.h> 23 #include <linux/kernel.h> 24 #include <linux/platform_device.h> 25 #include <linux/spi/pxa2xx_spi.h> 26 #include <linux/spi/spi.h> 27 #include <linux/delay.h> 28 #include <linux/gpio.h> 29 #include <linux/slab.h> 30 #include <linux/clk.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/acpi.h> 33 34 #include "spi-pxa2xx.h" 35 36 MODULE_AUTHOR("Stephen Street"); 37 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 38 MODULE_LICENSE("GPL"); 39 MODULE_ALIAS("platform:pxa2xx-spi"); 40 41 #define TIMOUT_DFLT 1000 42 43 /* 44 * for testing SSCR1 changes that require SSP restart, basically 45 * everything except the service and interrupt enables, the pxa270 developer 46 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 47 * list, but the PXA255 dev man says all bits without really meaning the 48 * service and interrupt enables 49 */ 50 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 51 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 52 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 53 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 54 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 55 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 56 57 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 58 | QUARK_X1000_SSCR1_EFWR \ 59 | QUARK_X1000_SSCR1_RFT \ 60 | QUARK_X1000_SSCR1_TFT \ 61 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 62 63 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 64 #define SPI_CS_CONTROL_SW_MODE BIT(0) 65 #define SPI_CS_CONTROL_CS_HIGH BIT(1) 66 67 struct lpss_config { 68 /* LPSS offset from drv_data->ioaddr */ 69 unsigned offset; 70 /* Register offsets from drv_data->lpss_base or -1 */ 71 int reg_general; 72 int reg_ssp; 73 int reg_cs_ctrl; 74 /* FIFO thresholds */ 75 u32 rx_threshold; 76 u32 tx_threshold_lo; 77 u32 tx_threshold_hi; 78 }; 79 80 /* Keep these sorted with enum pxa_ssp_type */ 81 static const struct lpss_config lpss_platforms[] = { 82 { /* LPSS_LPT_SSP */ 83 .offset = 0x800, 84 .reg_general = 0x08, 85 .reg_ssp = 0x0c, 86 .reg_cs_ctrl = 0x18, 87 .rx_threshold = 64, 88 .tx_threshold_lo = 160, 89 .tx_threshold_hi = 224, 90 }, 91 { /* LPSS_BYT_SSP */ 92 .offset = 0x400, 93 .reg_general = 0x08, 94 .reg_ssp = 0x0c, 95 .reg_cs_ctrl = 0x18, 96 .rx_threshold = 64, 97 .tx_threshold_lo = 160, 98 .tx_threshold_hi = 224, 99 }, 100 }; 101 102 static inline const struct lpss_config 103 *lpss_get_config(const struct driver_data *drv_data) 104 { 105 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 106 } 107 108 static bool is_lpss_ssp(const struct driver_data *drv_data) 109 { 110 switch (drv_data->ssp_type) { 111 case LPSS_LPT_SSP: 112 case LPSS_BYT_SSP: 113 return true; 114 default: 115 return false; 116 } 117 } 118 119 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 120 { 121 return drv_data->ssp_type == QUARK_X1000_SSP; 122 } 123 124 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 125 { 126 switch (drv_data->ssp_type) { 127 case QUARK_X1000_SSP: 128 return QUARK_X1000_SSCR1_CHANGE_MASK; 129 default: 130 return SSCR1_CHANGE_MASK; 131 } 132 } 133 134 static u32 135 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 136 { 137 switch (drv_data->ssp_type) { 138 case QUARK_X1000_SSP: 139 return RX_THRESH_QUARK_X1000_DFLT; 140 default: 141 return RX_THRESH_DFLT; 142 } 143 } 144 145 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 146 { 147 u32 mask; 148 149 switch (drv_data->ssp_type) { 150 case QUARK_X1000_SSP: 151 mask = QUARK_X1000_SSSR_TFL_MASK; 152 break; 153 default: 154 mask = SSSR_TFL_MASK; 155 break; 156 } 157 158 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 159 } 160 161 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 162 u32 *sccr1_reg) 163 { 164 u32 mask; 165 166 switch (drv_data->ssp_type) { 167 case QUARK_X1000_SSP: 168 mask = QUARK_X1000_SSCR1_RFT; 169 break; 170 default: 171 mask = SSCR1_RFT; 172 break; 173 } 174 *sccr1_reg &= ~mask; 175 } 176 177 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 178 u32 *sccr1_reg, u32 threshold) 179 { 180 switch (drv_data->ssp_type) { 181 case QUARK_X1000_SSP: 182 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 183 break; 184 default: 185 *sccr1_reg |= SSCR1_RxTresh(threshold); 186 break; 187 } 188 } 189 190 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 191 u32 clk_div, u8 bits) 192 { 193 switch (drv_data->ssp_type) { 194 case QUARK_X1000_SSP: 195 return clk_div 196 | QUARK_X1000_SSCR0_Motorola 197 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 198 | SSCR0_SSE; 199 default: 200 return clk_div 201 | SSCR0_Motorola 202 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 203 | SSCR0_SSE 204 | (bits > 16 ? SSCR0_EDSS : 0); 205 } 206 } 207 208 /* 209 * Read and write LPSS SSP private registers. Caller must first check that 210 * is_lpss_ssp() returns true before these can be called. 211 */ 212 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 213 { 214 WARN_ON(!drv_data->lpss_base); 215 return readl(drv_data->lpss_base + offset); 216 } 217 218 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 219 unsigned offset, u32 value) 220 { 221 WARN_ON(!drv_data->lpss_base); 222 writel(value, drv_data->lpss_base + offset); 223 } 224 225 /* 226 * lpss_ssp_setup - perform LPSS SSP specific setup 227 * @drv_data: pointer to the driver private data 228 * 229 * Perform LPSS SSP specific setup. This function must be called first if 230 * one is going to use LPSS SSP private registers. 231 */ 232 static void lpss_ssp_setup(struct driver_data *drv_data) 233 { 234 const struct lpss_config *config; 235 u32 value; 236 237 config = lpss_get_config(drv_data); 238 drv_data->lpss_base = drv_data->ioaddr + config->offset; 239 240 /* Enable software chip select control */ 241 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 242 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 243 244 /* Enable multiblock DMA transfers */ 245 if (drv_data->master_info->enable_dma) { 246 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 247 248 if (config->reg_general >= 0) { 249 value = __lpss_ssp_read_priv(drv_data, 250 config->reg_general); 251 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; 252 __lpss_ssp_write_priv(drv_data, 253 config->reg_general, value); 254 } 255 } 256 } 257 258 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 259 { 260 const struct lpss_config *config; 261 u32 value; 262 263 config = lpss_get_config(drv_data); 264 265 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 266 if (enable) 267 value &= ~SPI_CS_CONTROL_CS_HIGH; 268 else 269 value |= SPI_CS_CONTROL_CS_HIGH; 270 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 271 } 272 273 static void cs_assert(struct driver_data *drv_data) 274 { 275 struct chip_data *chip = drv_data->cur_chip; 276 277 if (drv_data->ssp_type == CE4100_SSP) { 278 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); 279 return; 280 } 281 282 if (chip->cs_control) { 283 chip->cs_control(PXA2XX_CS_ASSERT); 284 return; 285 } 286 287 if (gpio_is_valid(chip->gpio_cs)) { 288 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 289 return; 290 } 291 292 if (is_lpss_ssp(drv_data)) 293 lpss_ssp_cs_control(drv_data, true); 294 } 295 296 static void cs_deassert(struct driver_data *drv_data) 297 { 298 struct chip_data *chip = drv_data->cur_chip; 299 300 if (drv_data->ssp_type == CE4100_SSP) 301 return; 302 303 if (chip->cs_control) { 304 chip->cs_control(PXA2XX_CS_DEASSERT); 305 return; 306 } 307 308 if (gpio_is_valid(chip->gpio_cs)) { 309 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 310 return; 311 } 312 313 if (is_lpss_ssp(drv_data)) 314 lpss_ssp_cs_control(drv_data, false); 315 } 316 317 int pxa2xx_spi_flush(struct driver_data *drv_data) 318 { 319 unsigned long limit = loops_per_jiffy << 1; 320 321 do { 322 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 323 pxa2xx_spi_read(drv_data, SSDR); 324 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 325 write_SSSR_CS(drv_data, SSSR_ROR); 326 327 return limit; 328 } 329 330 static int null_writer(struct driver_data *drv_data) 331 { 332 u8 n_bytes = drv_data->n_bytes; 333 334 if (pxa2xx_spi_txfifo_full(drv_data) 335 || (drv_data->tx == drv_data->tx_end)) 336 return 0; 337 338 pxa2xx_spi_write(drv_data, SSDR, 0); 339 drv_data->tx += n_bytes; 340 341 return 1; 342 } 343 344 static int null_reader(struct driver_data *drv_data) 345 { 346 u8 n_bytes = drv_data->n_bytes; 347 348 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 349 && (drv_data->rx < drv_data->rx_end)) { 350 pxa2xx_spi_read(drv_data, SSDR); 351 drv_data->rx += n_bytes; 352 } 353 354 return drv_data->rx == drv_data->rx_end; 355 } 356 357 static int u8_writer(struct driver_data *drv_data) 358 { 359 if (pxa2xx_spi_txfifo_full(drv_data) 360 || (drv_data->tx == drv_data->tx_end)) 361 return 0; 362 363 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 364 ++drv_data->tx; 365 366 return 1; 367 } 368 369 static int u8_reader(struct driver_data *drv_data) 370 { 371 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 372 && (drv_data->rx < drv_data->rx_end)) { 373 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 374 ++drv_data->rx; 375 } 376 377 return drv_data->rx == drv_data->rx_end; 378 } 379 380 static int u16_writer(struct driver_data *drv_data) 381 { 382 if (pxa2xx_spi_txfifo_full(drv_data) 383 || (drv_data->tx == drv_data->tx_end)) 384 return 0; 385 386 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 387 drv_data->tx += 2; 388 389 return 1; 390 } 391 392 static int u16_reader(struct driver_data *drv_data) 393 { 394 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 395 && (drv_data->rx < drv_data->rx_end)) { 396 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 397 drv_data->rx += 2; 398 } 399 400 return drv_data->rx == drv_data->rx_end; 401 } 402 403 static int u32_writer(struct driver_data *drv_data) 404 { 405 if (pxa2xx_spi_txfifo_full(drv_data) 406 || (drv_data->tx == drv_data->tx_end)) 407 return 0; 408 409 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 410 drv_data->tx += 4; 411 412 return 1; 413 } 414 415 static int u32_reader(struct driver_data *drv_data) 416 { 417 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 418 && (drv_data->rx < drv_data->rx_end)) { 419 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 420 drv_data->rx += 4; 421 } 422 423 return drv_data->rx == drv_data->rx_end; 424 } 425 426 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 427 { 428 struct spi_message *msg = drv_data->cur_msg; 429 struct spi_transfer *trans = drv_data->cur_transfer; 430 431 /* Move to next transfer */ 432 if (trans->transfer_list.next != &msg->transfers) { 433 drv_data->cur_transfer = 434 list_entry(trans->transfer_list.next, 435 struct spi_transfer, 436 transfer_list); 437 return RUNNING_STATE; 438 } else 439 return DONE_STATE; 440 } 441 442 /* caller already set message->status; dma and pio irqs are blocked */ 443 static void giveback(struct driver_data *drv_data) 444 { 445 struct spi_transfer* last_transfer; 446 struct spi_message *msg; 447 448 msg = drv_data->cur_msg; 449 drv_data->cur_msg = NULL; 450 drv_data->cur_transfer = NULL; 451 452 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 453 transfer_list); 454 455 /* Delay if requested before any change in chip select */ 456 if (last_transfer->delay_usecs) 457 udelay(last_transfer->delay_usecs); 458 459 /* Drop chip select UNLESS cs_change is true or we are returning 460 * a message with an error, or next message is for another chip 461 */ 462 if (!last_transfer->cs_change) 463 cs_deassert(drv_data); 464 else { 465 struct spi_message *next_msg; 466 467 /* Holding of cs was hinted, but we need to make sure 468 * the next message is for the same chip. Don't waste 469 * time with the following tests unless this was hinted. 470 * 471 * We cannot postpone this until pump_messages, because 472 * after calling msg->complete (below) the driver that 473 * sent the current message could be unloaded, which 474 * could invalidate the cs_control() callback... 475 */ 476 477 /* get a pointer to the next message, if any */ 478 next_msg = spi_get_next_queued_message(drv_data->master); 479 480 /* see if the next and current messages point 481 * to the same chip 482 */ 483 if (next_msg && next_msg->spi != msg->spi) 484 next_msg = NULL; 485 if (!next_msg || msg->state == ERROR_STATE) 486 cs_deassert(drv_data); 487 } 488 489 drv_data->cur_chip = NULL; 490 spi_finalize_current_message(drv_data->master); 491 } 492 493 static void reset_sccr1(struct driver_data *drv_data) 494 { 495 struct chip_data *chip = drv_data->cur_chip; 496 u32 sccr1_reg; 497 498 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 499 sccr1_reg &= ~SSCR1_RFT; 500 sccr1_reg |= chip->threshold; 501 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 502 } 503 504 static void int_error_stop(struct driver_data *drv_data, const char* msg) 505 { 506 /* Stop and reset SSP */ 507 write_SSSR_CS(drv_data, drv_data->clear_sr); 508 reset_sccr1(drv_data); 509 if (!pxa25x_ssp_comp(drv_data)) 510 pxa2xx_spi_write(drv_data, SSTO, 0); 511 pxa2xx_spi_flush(drv_data); 512 pxa2xx_spi_write(drv_data, SSCR0, 513 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 514 515 dev_err(&drv_data->pdev->dev, "%s\n", msg); 516 517 drv_data->cur_msg->state = ERROR_STATE; 518 tasklet_schedule(&drv_data->pump_transfers); 519 } 520 521 static void int_transfer_complete(struct driver_data *drv_data) 522 { 523 /* Stop SSP */ 524 write_SSSR_CS(drv_data, drv_data->clear_sr); 525 reset_sccr1(drv_data); 526 if (!pxa25x_ssp_comp(drv_data)) 527 pxa2xx_spi_write(drv_data, SSTO, 0); 528 529 /* Update total byte transferred return count actual bytes read */ 530 drv_data->cur_msg->actual_length += drv_data->len - 531 (drv_data->rx_end - drv_data->rx); 532 533 /* Transfer delays and chip select release are 534 * handled in pump_transfers or giveback 535 */ 536 537 /* Move to next transfer */ 538 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 539 540 /* Schedule transfer tasklet */ 541 tasklet_schedule(&drv_data->pump_transfers); 542 } 543 544 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 545 { 546 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 547 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 548 549 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 550 551 if (irq_status & SSSR_ROR) { 552 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 553 return IRQ_HANDLED; 554 } 555 556 if (irq_status & SSSR_TINT) { 557 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 558 if (drv_data->read(drv_data)) { 559 int_transfer_complete(drv_data); 560 return IRQ_HANDLED; 561 } 562 } 563 564 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 565 do { 566 if (drv_data->read(drv_data)) { 567 int_transfer_complete(drv_data); 568 return IRQ_HANDLED; 569 } 570 } while (drv_data->write(drv_data)); 571 572 if (drv_data->read(drv_data)) { 573 int_transfer_complete(drv_data); 574 return IRQ_HANDLED; 575 } 576 577 if (drv_data->tx == drv_data->tx_end) { 578 u32 bytes_left; 579 u32 sccr1_reg; 580 581 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 582 sccr1_reg &= ~SSCR1_TIE; 583 584 /* 585 * PXA25x_SSP has no timeout, set up rx threshould for the 586 * remaining RX bytes. 587 */ 588 if (pxa25x_ssp_comp(drv_data)) { 589 u32 rx_thre; 590 591 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 592 593 bytes_left = drv_data->rx_end - drv_data->rx; 594 switch (drv_data->n_bytes) { 595 case 4: 596 bytes_left >>= 1; 597 case 2: 598 bytes_left >>= 1; 599 } 600 601 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 602 if (rx_thre > bytes_left) 603 rx_thre = bytes_left; 604 605 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 606 } 607 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 608 } 609 610 /* We did something */ 611 return IRQ_HANDLED; 612 } 613 614 static irqreturn_t ssp_int(int irq, void *dev_id) 615 { 616 struct driver_data *drv_data = dev_id; 617 u32 sccr1_reg; 618 u32 mask = drv_data->mask_sr; 619 u32 status; 620 621 /* 622 * The IRQ might be shared with other peripherals so we must first 623 * check that are we RPM suspended or not. If we are we assume that 624 * the IRQ was not for us (we shouldn't be RPM suspended when the 625 * interrupt is enabled). 626 */ 627 if (pm_runtime_suspended(&drv_data->pdev->dev)) 628 return IRQ_NONE; 629 630 /* 631 * If the device is not yet in RPM suspended state and we get an 632 * interrupt that is meant for another device, check if status bits 633 * are all set to one. That means that the device is already 634 * powered off. 635 */ 636 status = pxa2xx_spi_read(drv_data, SSSR); 637 if (status == ~0) 638 return IRQ_NONE; 639 640 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 641 642 /* Ignore possible writes if we don't need to write */ 643 if (!(sccr1_reg & SSCR1_TIE)) 644 mask &= ~SSSR_TFS; 645 646 /* Ignore RX timeout interrupt if it is disabled */ 647 if (!(sccr1_reg & SSCR1_TINTE)) 648 mask &= ~SSSR_TINT; 649 650 if (!(status & mask)) 651 return IRQ_NONE; 652 653 if (!drv_data->cur_msg) { 654 655 pxa2xx_spi_write(drv_data, SSCR0, 656 pxa2xx_spi_read(drv_data, SSCR0) 657 & ~SSCR0_SSE); 658 pxa2xx_spi_write(drv_data, SSCR1, 659 pxa2xx_spi_read(drv_data, SSCR1) 660 & ~drv_data->int_cr1); 661 if (!pxa25x_ssp_comp(drv_data)) 662 pxa2xx_spi_write(drv_data, SSTO, 0); 663 write_SSSR_CS(drv_data, drv_data->clear_sr); 664 665 dev_err(&drv_data->pdev->dev, 666 "bad message state in interrupt handler\n"); 667 668 /* Never fail */ 669 return IRQ_HANDLED; 670 } 671 672 return drv_data->transfer_handler(drv_data); 673 } 674 675 /* 676 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 677 * input frequency by fractions of 2^24. It also has a divider by 5. 678 * 679 * There are formulas to get baud rate value for given input frequency and 680 * divider parameters, such as DDS_CLK_RATE and SCR: 681 * 682 * Fsys = 200MHz 683 * 684 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 685 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 686 * 687 * DDS_CLK_RATE either 2^n or 2^n / 5. 688 * SCR is in range 0 .. 255 689 * 690 * Divisor = 5^i * 2^j * 2 * k 691 * i = [0, 1] i = 1 iff j = 0 or j > 3 692 * j = [0, 23] j = 0 iff i = 1 693 * k = [1, 256] 694 * Special case: j = 0, i = 1: Divisor = 2 / 5 695 * 696 * Accordingly to the specification the recommended values for DDS_CLK_RATE 697 * are: 698 * Case 1: 2^n, n = [0, 23] 699 * Case 2: 2^24 * 2 / 5 (0x666666) 700 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 701 * 702 * In all cases the lowest possible value is better. 703 * 704 * The function calculates parameters for all cases and chooses the one closest 705 * to the asked baud rate. 706 */ 707 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 708 { 709 unsigned long xtal = 200000000; 710 unsigned long fref = xtal / 2; /* mandatory division by 2, 711 see (2) */ 712 /* case 3 */ 713 unsigned long fref1 = fref / 2; /* case 1 */ 714 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 715 unsigned long scale; 716 unsigned long q, q1, q2; 717 long r, r1, r2; 718 u32 mul; 719 720 /* Case 1 */ 721 722 /* Set initial value for DDS_CLK_RATE */ 723 mul = (1 << 24) >> 1; 724 725 /* Calculate initial quot */ 726 q1 = DIV_ROUND_CLOSEST(fref1, rate); 727 728 /* Scale q1 if it's too big */ 729 if (q1 > 256) { 730 /* Scale q1 to range [1, 512] */ 731 scale = fls_long(q1 - 1); 732 if (scale > 9) { 733 q1 >>= scale - 9; 734 mul >>= scale - 9; 735 } 736 737 /* Round the result if we have a remainder */ 738 q1 += q1 & 1; 739 } 740 741 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 742 scale = __ffs(q1); 743 q1 >>= scale; 744 mul >>= scale; 745 746 /* Get the remainder */ 747 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 748 749 /* Case 2 */ 750 751 q2 = DIV_ROUND_CLOSEST(fref2, rate); 752 r2 = abs(fref2 / q2 - rate); 753 754 /* 755 * Choose the best between two: less remainder we have the better. We 756 * can't go case 2 if q2 is greater than 256 since SCR register can 757 * hold only values 0 .. 255. 758 */ 759 if (r2 >= r1 || q2 > 256) { 760 /* case 1 is better */ 761 r = r1; 762 q = q1; 763 } else { 764 /* case 2 is better */ 765 r = r2; 766 q = q2; 767 mul = (1 << 24) * 2 / 5; 768 } 769 770 /* Check case 3 only If the divisor is big enough */ 771 if (fref / rate >= 80) { 772 u64 fssp; 773 u32 m; 774 775 /* Calculate initial quot */ 776 q1 = DIV_ROUND_CLOSEST(fref, rate); 777 m = (1 << 24) / q1; 778 779 /* Get the remainder */ 780 fssp = (u64)fref * m; 781 do_div(fssp, 1 << 24); 782 r1 = abs(fssp - rate); 783 784 /* Choose this one if it suits better */ 785 if (r1 < r) { 786 /* case 3 is better */ 787 q = 1; 788 mul = m; 789 } 790 } 791 792 *dds = mul; 793 return q - 1; 794 } 795 796 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 797 { 798 unsigned long ssp_clk = drv_data->max_clk_rate; 799 const struct ssp_device *ssp = drv_data->ssp; 800 801 rate = min_t(int, ssp_clk, rate); 802 803 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 804 return (ssp_clk / (2 * rate) - 1) & 0xff; 805 else 806 return (ssp_clk / rate - 1) & 0xfff; 807 } 808 809 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 810 struct chip_data *chip, int rate) 811 { 812 unsigned int clk_div; 813 814 switch (drv_data->ssp_type) { 815 case QUARK_X1000_SSP: 816 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 817 break; 818 default: 819 clk_div = ssp_get_clk_div(drv_data, rate); 820 break; 821 } 822 return clk_div << 8; 823 } 824 825 static void pump_transfers(unsigned long data) 826 { 827 struct driver_data *drv_data = (struct driver_data *)data; 828 struct spi_message *message = NULL; 829 struct spi_transfer *transfer = NULL; 830 struct spi_transfer *previous = NULL; 831 struct chip_data *chip = NULL; 832 u32 clk_div = 0; 833 u8 bits = 0; 834 u32 speed = 0; 835 u32 cr0; 836 u32 cr1; 837 u32 dma_thresh = drv_data->cur_chip->dma_threshold; 838 u32 dma_burst = drv_data->cur_chip->dma_burst_size; 839 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 840 841 /* Get current state information */ 842 message = drv_data->cur_msg; 843 transfer = drv_data->cur_transfer; 844 chip = drv_data->cur_chip; 845 846 /* Handle for abort */ 847 if (message->state == ERROR_STATE) { 848 message->status = -EIO; 849 giveback(drv_data); 850 return; 851 } 852 853 /* Handle end of message */ 854 if (message->state == DONE_STATE) { 855 message->status = 0; 856 giveback(drv_data); 857 return; 858 } 859 860 /* Delay if requested at end of transfer before CS change */ 861 if (message->state == RUNNING_STATE) { 862 previous = list_entry(transfer->transfer_list.prev, 863 struct spi_transfer, 864 transfer_list); 865 if (previous->delay_usecs) 866 udelay(previous->delay_usecs); 867 868 /* Drop chip select only if cs_change is requested */ 869 if (previous->cs_change) 870 cs_deassert(drv_data); 871 } 872 873 /* Check if we can DMA this transfer */ 874 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 875 876 /* reject already-mapped transfers; PIO won't always work */ 877 if (message->is_dma_mapped 878 || transfer->rx_dma || transfer->tx_dma) { 879 dev_err(&drv_data->pdev->dev, 880 "pump_transfers: mapped transfer length of " 881 "%u is greater than %d\n", 882 transfer->len, MAX_DMA_LEN); 883 message->status = -EINVAL; 884 giveback(drv_data); 885 return; 886 } 887 888 /* warn ... we force this to PIO mode */ 889 dev_warn_ratelimited(&message->spi->dev, 890 "pump_transfers: DMA disabled for transfer length %ld " 891 "greater than %d\n", 892 (long)drv_data->len, MAX_DMA_LEN); 893 } 894 895 /* Setup the transfer state based on the type of transfer */ 896 if (pxa2xx_spi_flush(drv_data) == 0) { 897 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 898 message->status = -EIO; 899 giveback(drv_data); 900 return; 901 } 902 drv_data->n_bytes = chip->n_bytes; 903 drv_data->tx = (void *)transfer->tx_buf; 904 drv_data->tx_end = drv_data->tx + transfer->len; 905 drv_data->rx = transfer->rx_buf; 906 drv_data->rx_end = drv_data->rx + transfer->len; 907 drv_data->rx_dma = transfer->rx_dma; 908 drv_data->tx_dma = transfer->tx_dma; 909 drv_data->len = transfer->len; 910 drv_data->write = drv_data->tx ? chip->write : null_writer; 911 drv_data->read = drv_data->rx ? chip->read : null_reader; 912 913 /* Change speed and bit per word on a per transfer */ 914 cr0 = chip->cr0; 915 if (transfer->speed_hz || transfer->bits_per_word) { 916 917 bits = chip->bits_per_word; 918 speed = chip->speed_hz; 919 920 if (transfer->speed_hz) 921 speed = transfer->speed_hz; 922 923 if (transfer->bits_per_word) 924 bits = transfer->bits_per_word; 925 926 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); 927 928 if (bits <= 8) { 929 drv_data->n_bytes = 1; 930 drv_data->read = drv_data->read != null_reader ? 931 u8_reader : null_reader; 932 drv_data->write = drv_data->write != null_writer ? 933 u8_writer : null_writer; 934 } else if (bits <= 16) { 935 drv_data->n_bytes = 2; 936 drv_data->read = drv_data->read != null_reader ? 937 u16_reader : null_reader; 938 drv_data->write = drv_data->write != null_writer ? 939 u16_writer : null_writer; 940 } else if (bits <= 32) { 941 drv_data->n_bytes = 4; 942 drv_data->read = drv_data->read != null_reader ? 943 u32_reader : null_reader; 944 drv_data->write = drv_data->write != null_writer ? 945 u32_writer : null_writer; 946 } 947 /* if bits/word is changed in dma mode, then must check the 948 * thresholds and burst also */ 949 if (chip->enable_dma) { 950 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 951 message->spi, 952 bits, &dma_burst, 953 &dma_thresh)) 954 dev_warn_ratelimited(&message->spi->dev, 955 "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 956 } 957 958 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 959 } 960 961 message->state = RUNNING_STATE; 962 963 drv_data->dma_mapped = 0; 964 if (pxa2xx_spi_dma_is_possible(drv_data->len)) 965 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 966 if (drv_data->dma_mapped) { 967 968 /* Ensure we have the correct interrupt handler */ 969 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 970 971 pxa2xx_spi_dma_prepare(drv_data, dma_burst); 972 973 /* Clear status and start DMA engine */ 974 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 975 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 976 977 pxa2xx_spi_dma_start(drv_data); 978 } else { 979 /* Ensure we have the correct interrupt handler */ 980 drv_data->transfer_handler = interrupt_transfer; 981 982 /* Clear status */ 983 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 984 write_SSSR_CS(drv_data, drv_data->clear_sr); 985 } 986 987 if (is_lpss_ssp(drv_data)) { 988 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 989 != chip->lpss_rx_threshold) 990 pxa2xx_spi_write(drv_data, SSIRF, 991 chip->lpss_rx_threshold); 992 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 993 != chip->lpss_tx_threshold) 994 pxa2xx_spi_write(drv_data, SSITF, 995 chip->lpss_tx_threshold); 996 } 997 998 if (is_quark_x1000_ssp(drv_data) && 999 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 1000 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 1001 1002 /* see if we need to reload the config registers */ 1003 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 1004 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 1005 != (cr1 & change_mask)) { 1006 /* stop the SSP, and update the other bits */ 1007 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 1008 if (!pxa25x_ssp_comp(drv_data)) 1009 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1010 /* first set CR1 without interrupt and service enables */ 1011 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 1012 /* restart the SSP */ 1013 pxa2xx_spi_write(drv_data, SSCR0, cr0); 1014 1015 } else { 1016 if (!pxa25x_ssp_comp(drv_data)) 1017 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1018 } 1019 1020 cs_assert(drv_data); 1021 1022 /* after chip select, release the data by enabling service 1023 * requests and interrupts, without changing any mode bits */ 1024 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1025 } 1026 1027 static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 1028 struct spi_message *msg) 1029 { 1030 struct driver_data *drv_data = spi_master_get_devdata(master); 1031 1032 drv_data->cur_msg = msg; 1033 /* Initial message state*/ 1034 drv_data->cur_msg->state = START_STATE; 1035 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 1036 struct spi_transfer, 1037 transfer_list); 1038 1039 /* prepare to setup the SSP, in pump_transfers, using the per 1040 * chip configuration */ 1041 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 1042 1043 /* Mark as busy and launch transfers */ 1044 tasklet_schedule(&drv_data->pump_transfers); 1045 return 0; 1046 } 1047 1048 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 1049 { 1050 struct driver_data *drv_data = spi_master_get_devdata(master); 1051 1052 /* Disable the SSP now */ 1053 pxa2xx_spi_write(drv_data, SSCR0, 1054 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1055 1056 return 0; 1057 } 1058 1059 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1060 struct pxa2xx_spi_chip *chip_info) 1061 { 1062 int err = 0; 1063 1064 if (chip == NULL || chip_info == NULL) 1065 return 0; 1066 1067 /* NOTE: setup() can be called multiple times, possibly with 1068 * different chip_info, release previously requested GPIO 1069 */ 1070 if (gpio_is_valid(chip->gpio_cs)) 1071 gpio_free(chip->gpio_cs); 1072 1073 /* If (*cs_control) is provided, ignore GPIO chip select */ 1074 if (chip_info->cs_control) { 1075 chip->cs_control = chip_info->cs_control; 1076 return 0; 1077 } 1078 1079 if (gpio_is_valid(chip_info->gpio_cs)) { 1080 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1081 if (err) { 1082 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1083 chip_info->gpio_cs); 1084 return err; 1085 } 1086 1087 chip->gpio_cs = chip_info->gpio_cs; 1088 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1089 1090 err = gpio_direction_output(chip->gpio_cs, 1091 !chip->gpio_cs_inverted); 1092 } 1093 1094 return err; 1095 } 1096 1097 static int setup(struct spi_device *spi) 1098 { 1099 struct pxa2xx_spi_chip *chip_info = NULL; 1100 struct chip_data *chip; 1101 const struct lpss_config *config; 1102 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1103 unsigned int clk_div; 1104 uint tx_thres, tx_hi_thres, rx_thres; 1105 1106 switch (drv_data->ssp_type) { 1107 case QUARK_X1000_SSP: 1108 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1109 tx_hi_thres = 0; 1110 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1111 break; 1112 case LPSS_LPT_SSP: 1113 case LPSS_BYT_SSP: 1114 config = lpss_get_config(drv_data); 1115 tx_thres = config->tx_threshold_lo; 1116 tx_hi_thres = config->tx_threshold_hi; 1117 rx_thres = config->rx_threshold; 1118 break; 1119 default: 1120 tx_thres = TX_THRESH_DFLT; 1121 tx_hi_thres = 0; 1122 rx_thres = RX_THRESH_DFLT; 1123 break; 1124 } 1125 1126 /* Only alloc on first setup */ 1127 chip = spi_get_ctldata(spi); 1128 if (!chip) { 1129 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1130 if (!chip) 1131 return -ENOMEM; 1132 1133 if (drv_data->ssp_type == CE4100_SSP) { 1134 if (spi->chip_select > 4) { 1135 dev_err(&spi->dev, 1136 "failed setup: cs number must not be > 4.\n"); 1137 kfree(chip); 1138 return -EINVAL; 1139 } 1140 1141 chip->frm = spi->chip_select; 1142 } else 1143 chip->gpio_cs = -1; 1144 chip->enable_dma = 0; 1145 chip->timeout = TIMOUT_DFLT; 1146 } 1147 1148 /* protocol drivers may change the chip settings, so... 1149 * if chip_info exists, use it */ 1150 chip_info = spi->controller_data; 1151 1152 /* chip_info isn't always needed */ 1153 chip->cr1 = 0; 1154 if (chip_info) { 1155 if (chip_info->timeout) 1156 chip->timeout = chip_info->timeout; 1157 if (chip_info->tx_threshold) 1158 tx_thres = chip_info->tx_threshold; 1159 if (chip_info->tx_hi_threshold) 1160 tx_hi_thres = chip_info->tx_hi_threshold; 1161 if (chip_info->rx_threshold) 1162 rx_thres = chip_info->rx_threshold; 1163 chip->enable_dma = drv_data->master_info->enable_dma; 1164 chip->dma_threshold = 0; 1165 if (chip_info->enable_loopback) 1166 chip->cr1 = SSCR1_LBM; 1167 } else if (ACPI_HANDLE(&spi->dev)) { 1168 /* 1169 * Slave devices enumerated from ACPI namespace don't 1170 * usually have chip_info but we still might want to use 1171 * DMA with them. 1172 */ 1173 chip->enable_dma = drv_data->master_info->enable_dma; 1174 } 1175 1176 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1177 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1178 | SSITF_TxHiThresh(tx_hi_thres); 1179 1180 /* set dma burst and threshold outside of chip_info path so that if 1181 * chip_info goes away after setting chip->enable_dma, the 1182 * burst and threshold can still respond to changes in bits_per_word */ 1183 if (chip->enable_dma) { 1184 /* set up legal burst and threshold for dma */ 1185 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1186 spi->bits_per_word, 1187 &chip->dma_burst_size, 1188 &chip->dma_threshold)) { 1189 dev_warn(&spi->dev, 1190 "in setup: DMA burst size reduced to match bits_per_word\n"); 1191 } 1192 } 1193 1194 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); 1195 chip->speed_hz = spi->max_speed_hz; 1196 1197 chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, 1198 spi->bits_per_word); 1199 switch (drv_data->ssp_type) { 1200 case QUARK_X1000_SSP: 1201 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1202 & QUARK_X1000_SSCR1_RFT) 1203 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1204 & QUARK_X1000_SSCR1_TFT); 1205 break; 1206 default: 1207 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1208 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1209 break; 1210 } 1211 1212 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1213 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1214 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1215 1216 if (spi->mode & SPI_LOOP) 1217 chip->cr1 |= SSCR1_LBM; 1218 1219 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1220 if (!pxa25x_ssp_comp(drv_data)) 1221 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1222 drv_data->max_clk_rate 1223 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 1224 chip->enable_dma ? "DMA" : "PIO"); 1225 else 1226 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1227 drv_data->max_clk_rate / 2 1228 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1229 chip->enable_dma ? "DMA" : "PIO"); 1230 1231 if (spi->bits_per_word <= 8) { 1232 chip->n_bytes = 1; 1233 chip->read = u8_reader; 1234 chip->write = u8_writer; 1235 } else if (spi->bits_per_word <= 16) { 1236 chip->n_bytes = 2; 1237 chip->read = u16_reader; 1238 chip->write = u16_writer; 1239 } else if (spi->bits_per_word <= 32) { 1240 if (!is_quark_x1000_ssp(drv_data)) 1241 chip->cr0 |= SSCR0_EDSS; 1242 chip->n_bytes = 4; 1243 chip->read = u32_reader; 1244 chip->write = u32_writer; 1245 } 1246 chip->bits_per_word = spi->bits_per_word; 1247 1248 spi_set_ctldata(spi, chip); 1249 1250 if (drv_data->ssp_type == CE4100_SSP) 1251 return 0; 1252 1253 return setup_cs(spi, chip, chip_info); 1254 } 1255 1256 static void cleanup(struct spi_device *spi) 1257 { 1258 struct chip_data *chip = spi_get_ctldata(spi); 1259 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1260 1261 if (!chip) 1262 return; 1263 1264 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1265 gpio_free(chip->gpio_cs); 1266 1267 kfree(chip); 1268 } 1269 1270 #ifdef CONFIG_ACPI 1271 1272 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1273 { "INT33C0", LPSS_LPT_SSP }, 1274 { "INT33C1", LPSS_LPT_SSP }, 1275 { "INT3430", LPSS_LPT_SSP }, 1276 { "INT3431", LPSS_LPT_SSP }, 1277 { "80860F0E", LPSS_BYT_SSP }, 1278 { "8086228E", LPSS_BYT_SSP }, 1279 { }, 1280 }; 1281 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1282 1283 static struct pxa2xx_spi_master * 1284 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1285 { 1286 struct pxa2xx_spi_master *pdata; 1287 struct acpi_device *adev; 1288 struct ssp_device *ssp; 1289 struct resource *res; 1290 const struct acpi_device_id *id; 1291 int devid, type; 1292 1293 if (!ACPI_HANDLE(&pdev->dev) || 1294 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1295 return NULL; 1296 1297 id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); 1298 if (id) 1299 type = (int)id->driver_data; 1300 else 1301 return NULL; 1302 1303 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1304 if (!pdata) 1305 return NULL; 1306 1307 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1308 if (!res) 1309 return NULL; 1310 1311 ssp = &pdata->ssp; 1312 1313 ssp->phys_base = res->start; 1314 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1315 if (IS_ERR(ssp->mmio_base)) 1316 return NULL; 1317 1318 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1319 ssp->irq = platform_get_irq(pdev, 0); 1320 ssp->type = type; 1321 ssp->pdev = pdev; 1322 1323 ssp->port_id = -1; 1324 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1325 ssp->port_id = devid; 1326 1327 pdata->num_chipselect = 1; 1328 pdata->enable_dma = true; 1329 1330 return pdata; 1331 } 1332 1333 #else 1334 static inline struct pxa2xx_spi_master * 1335 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1336 { 1337 return NULL; 1338 } 1339 #endif 1340 1341 static int pxa2xx_spi_probe(struct platform_device *pdev) 1342 { 1343 struct device *dev = &pdev->dev; 1344 struct pxa2xx_spi_master *platform_info; 1345 struct spi_master *master; 1346 struct driver_data *drv_data; 1347 struct ssp_device *ssp; 1348 int status; 1349 u32 tmp; 1350 1351 platform_info = dev_get_platdata(dev); 1352 if (!platform_info) { 1353 platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1354 if (!platform_info) { 1355 dev_err(&pdev->dev, "missing platform data\n"); 1356 return -ENODEV; 1357 } 1358 } 1359 1360 ssp = pxa_ssp_request(pdev->id, pdev->name); 1361 if (!ssp) 1362 ssp = &platform_info->ssp; 1363 1364 if (!ssp->mmio_base) { 1365 dev_err(&pdev->dev, "failed to get ssp\n"); 1366 return -ENODEV; 1367 } 1368 1369 /* Allocate master with space for drv_data and null dma buffer */ 1370 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1371 if (!master) { 1372 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1373 pxa_ssp_free(ssp); 1374 return -ENOMEM; 1375 } 1376 drv_data = spi_master_get_devdata(master); 1377 drv_data->master = master; 1378 drv_data->master_info = platform_info; 1379 drv_data->pdev = pdev; 1380 drv_data->ssp = ssp; 1381 1382 master->dev.parent = &pdev->dev; 1383 master->dev.of_node = pdev->dev.of_node; 1384 /* the spi->mode bits understood by this driver: */ 1385 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1386 1387 master->bus_num = ssp->port_id; 1388 master->num_chipselect = platform_info->num_chipselect; 1389 master->dma_alignment = DMA_ALIGNMENT; 1390 master->cleanup = cleanup; 1391 master->setup = setup; 1392 master->transfer_one_message = pxa2xx_spi_transfer_one_message; 1393 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1394 master->auto_runtime_pm = true; 1395 1396 drv_data->ssp_type = ssp->type; 1397 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1398 1399 drv_data->ioaddr = ssp->mmio_base; 1400 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1401 if (pxa25x_ssp_comp(drv_data)) { 1402 switch (drv_data->ssp_type) { 1403 case QUARK_X1000_SSP: 1404 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1405 break; 1406 default: 1407 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1408 break; 1409 } 1410 1411 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1412 drv_data->dma_cr1 = 0; 1413 drv_data->clear_sr = SSSR_ROR; 1414 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1415 } else { 1416 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1417 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1418 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1419 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1420 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1421 } 1422 1423 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1424 drv_data); 1425 if (status < 0) { 1426 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1427 goto out_error_master_alloc; 1428 } 1429 1430 /* Setup DMA if requested */ 1431 drv_data->tx_channel = -1; 1432 drv_data->rx_channel = -1; 1433 if (platform_info->enable_dma) { 1434 status = pxa2xx_spi_dma_setup(drv_data); 1435 if (status) { 1436 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1437 platform_info->enable_dma = false; 1438 } 1439 } 1440 1441 /* Enable SOC clock */ 1442 clk_prepare_enable(ssp->clk); 1443 1444 drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1445 1446 /* Load default SSP configuration */ 1447 pxa2xx_spi_write(drv_data, SSCR0, 0); 1448 switch (drv_data->ssp_type) { 1449 case QUARK_X1000_SSP: 1450 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) 1451 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1452 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1453 1454 /* using the Motorola SPI protocol and use 8 bit frame */ 1455 pxa2xx_spi_write(drv_data, SSCR0, 1456 QUARK_X1000_SSCR0_Motorola 1457 | QUARK_X1000_SSCR0_DataSize(8)); 1458 break; 1459 default: 1460 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1461 SSCR1_TxTresh(TX_THRESH_DFLT); 1462 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1463 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1464 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1465 break; 1466 } 1467 1468 if (!pxa25x_ssp_comp(drv_data)) 1469 pxa2xx_spi_write(drv_data, SSTO, 0); 1470 1471 if (!is_quark_x1000_ssp(drv_data)) 1472 pxa2xx_spi_write(drv_data, SSPSP, 0); 1473 1474 if (is_lpss_ssp(drv_data)) 1475 lpss_ssp_setup(drv_data); 1476 1477 tasklet_init(&drv_data->pump_transfers, pump_transfers, 1478 (unsigned long)drv_data); 1479 1480 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1481 pm_runtime_use_autosuspend(&pdev->dev); 1482 pm_runtime_set_active(&pdev->dev); 1483 pm_runtime_enable(&pdev->dev); 1484 1485 /* Register with the SPI framework */ 1486 platform_set_drvdata(pdev, drv_data); 1487 status = devm_spi_register_master(&pdev->dev, master); 1488 if (status != 0) { 1489 dev_err(&pdev->dev, "problem registering spi master\n"); 1490 goto out_error_clock_enabled; 1491 } 1492 1493 return status; 1494 1495 out_error_clock_enabled: 1496 clk_disable_unprepare(ssp->clk); 1497 pxa2xx_spi_dma_release(drv_data); 1498 free_irq(ssp->irq, drv_data); 1499 1500 out_error_master_alloc: 1501 spi_master_put(master); 1502 pxa_ssp_free(ssp); 1503 return status; 1504 } 1505 1506 static int pxa2xx_spi_remove(struct platform_device *pdev) 1507 { 1508 struct driver_data *drv_data = platform_get_drvdata(pdev); 1509 struct ssp_device *ssp; 1510 1511 if (!drv_data) 1512 return 0; 1513 ssp = drv_data->ssp; 1514 1515 pm_runtime_get_sync(&pdev->dev); 1516 1517 /* Disable the SSP at the peripheral and SOC level */ 1518 pxa2xx_spi_write(drv_data, SSCR0, 0); 1519 clk_disable_unprepare(ssp->clk); 1520 1521 /* Release DMA */ 1522 if (drv_data->master_info->enable_dma) 1523 pxa2xx_spi_dma_release(drv_data); 1524 1525 pm_runtime_put_noidle(&pdev->dev); 1526 pm_runtime_disable(&pdev->dev); 1527 1528 /* Release IRQ */ 1529 free_irq(ssp->irq, drv_data); 1530 1531 /* Release SSP */ 1532 pxa_ssp_free(ssp); 1533 1534 return 0; 1535 } 1536 1537 static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1538 { 1539 int status = 0; 1540 1541 if ((status = pxa2xx_spi_remove(pdev)) != 0) 1542 dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1543 } 1544 1545 #ifdef CONFIG_PM_SLEEP 1546 static int pxa2xx_spi_suspend(struct device *dev) 1547 { 1548 struct driver_data *drv_data = dev_get_drvdata(dev); 1549 struct ssp_device *ssp = drv_data->ssp; 1550 int status = 0; 1551 1552 status = spi_master_suspend(drv_data->master); 1553 if (status != 0) 1554 return status; 1555 pxa2xx_spi_write(drv_data, SSCR0, 0); 1556 1557 if (!pm_runtime_suspended(dev)) 1558 clk_disable_unprepare(ssp->clk); 1559 1560 return 0; 1561 } 1562 1563 static int pxa2xx_spi_resume(struct device *dev) 1564 { 1565 struct driver_data *drv_data = dev_get_drvdata(dev); 1566 struct ssp_device *ssp = drv_data->ssp; 1567 int status = 0; 1568 1569 pxa2xx_spi_dma_resume(drv_data); 1570 1571 /* Enable the SSP clock */ 1572 if (!pm_runtime_suspended(dev)) 1573 clk_prepare_enable(ssp->clk); 1574 1575 /* Restore LPSS private register bits */ 1576 if (is_lpss_ssp(drv_data)) 1577 lpss_ssp_setup(drv_data); 1578 1579 /* Start the queue running */ 1580 status = spi_master_resume(drv_data->master); 1581 if (status != 0) { 1582 dev_err(dev, "problem starting queue (%d)\n", status); 1583 return status; 1584 } 1585 1586 return 0; 1587 } 1588 #endif 1589 1590 #ifdef CONFIG_PM 1591 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1592 { 1593 struct driver_data *drv_data = dev_get_drvdata(dev); 1594 1595 clk_disable_unprepare(drv_data->ssp->clk); 1596 return 0; 1597 } 1598 1599 static int pxa2xx_spi_runtime_resume(struct device *dev) 1600 { 1601 struct driver_data *drv_data = dev_get_drvdata(dev); 1602 1603 clk_prepare_enable(drv_data->ssp->clk); 1604 return 0; 1605 } 1606 #endif 1607 1608 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1609 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1610 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1611 pxa2xx_spi_runtime_resume, NULL) 1612 }; 1613 1614 static struct platform_driver driver = { 1615 .driver = { 1616 .name = "pxa2xx-spi", 1617 .pm = &pxa2xx_spi_pm_ops, 1618 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1619 }, 1620 .probe = pxa2xx_spi_probe, 1621 .remove = pxa2xx_spi_remove, 1622 .shutdown = pxa2xx_spi_shutdown, 1623 }; 1624 1625 static int __init pxa2xx_spi_init(void) 1626 { 1627 return platform_driver_register(&driver); 1628 } 1629 subsys_initcall(pxa2xx_spi_init); 1630 1631 static void __exit pxa2xx_spi_exit(void) 1632 { 1633 platform_driver_unregister(&driver); 1634 } 1635 module_exit(pxa2xx_spi_exit); 1636