1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3a0d2642eSMika Westerberg * Copyright (C) 2013, Intel Corporation 4ca632f55SGrant Likely * 5ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 6ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 7ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 8ca632f55SGrant Likely * (at your option) any later version. 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 11ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 12ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ca632f55SGrant Likely * GNU General Public License for more details. 14ca632f55SGrant Likely * 15ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 16ca632f55SGrant Likely * along with this program; if not, write to the Free Software 17ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18ca632f55SGrant Likely */ 19ca632f55SGrant Likely 20ca632f55SGrant Likely #include <linux/init.h> 21ca632f55SGrant Likely #include <linux/module.h> 22ca632f55SGrant Likely #include <linux/device.h> 23ca632f55SGrant Likely #include <linux/ioport.h> 24ca632f55SGrant Likely #include <linux/errno.h> 25cbfd6a21SSachin Kamat #include <linux/err.h> 26ca632f55SGrant Likely #include <linux/interrupt.h> 27ca632f55SGrant Likely #include <linux/platform_device.h> 28ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 29ca632f55SGrant Likely #include <linux/spi/spi.h> 30ca632f55SGrant Likely #include <linux/delay.h> 31ca632f55SGrant Likely #include <linux/gpio.h> 32ca632f55SGrant Likely #include <linux/slab.h> 333343b7a6SMika Westerberg #include <linux/clk.h> 347d94a505SMika Westerberg #include <linux/pm_runtime.h> 35a3496855SMika Westerberg #include <linux/acpi.h> 36ca632f55SGrant Likely 37ca632f55SGrant Likely #include <asm/io.h> 38ca632f55SGrant Likely #include <asm/irq.h> 39ca632f55SGrant Likely #include <asm/delay.h> 40ca632f55SGrant Likely 41cd7bed00SMika Westerberg #include "spi-pxa2xx.h" 42ca632f55SGrant Likely 43ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 44ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 45ca632f55SGrant Likely MODULE_LICENSE("GPL"); 46ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define MAX_BUSES 3 49ca632f55SGrant Likely 50ca632f55SGrant Likely #define TIMOUT_DFLT 1000 51ca632f55SGrant Likely 52ca632f55SGrant Likely /* 53ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 54ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 55ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 56ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 57ca632f55SGrant Likely * service and interrupt enables 58ca632f55SGrant Likely */ 59ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 60ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 61ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 62ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 63ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 64ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 65ca632f55SGrant Likely 66a0d2642eSMika Westerberg #define LPSS_RX_THRESH_DFLT 64 67a0d2642eSMika Westerberg #define LPSS_TX_LOTHRESH_DFLT 160 68a0d2642eSMika Westerberg #define LPSS_TX_HITHRESH_DFLT 224 69a0d2642eSMika Westerberg 70a0d2642eSMika Westerberg /* Offset from drv_data->lpss_base */ 711de70612SMika Westerberg #define GENERAL_REG 0x08 721de70612SMika Westerberg #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 730054e28dSMika Westerberg #define SSP_REG 0x0c 74a0d2642eSMika Westerberg #define SPI_CS_CONTROL 0x18 75a0d2642eSMika Westerberg #define SPI_CS_CONTROL_SW_MODE BIT(0) 76a0d2642eSMika Westerberg #define SPI_CS_CONTROL_CS_HIGH BIT(1) 77a0d2642eSMika Westerberg 78a0d2642eSMika Westerberg static bool is_lpss_ssp(const struct driver_data *drv_data) 79a0d2642eSMika Westerberg { 80a0d2642eSMika Westerberg return drv_data->ssp_type == LPSS_SSP; 81a0d2642eSMika Westerberg } 82a0d2642eSMika Westerberg 83a0d2642eSMika Westerberg /* 84a0d2642eSMika Westerberg * Read and write LPSS SSP private registers. Caller must first check that 85a0d2642eSMika Westerberg * is_lpss_ssp() returns true before these can be called. 86a0d2642eSMika Westerberg */ 87a0d2642eSMika Westerberg static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 88a0d2642eSMika Westerberg { 89a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 90a0d2642eSMika Westerberg return readl(drv_data->lpss_base + offset); 91a0d2642eSMika Westerberg } 92a0d2642eSMika Westerberg 93a0d2642eSMika Westerberg static void __lpss_ssp_write_priv(struct driver_data *drv_data, 94a0d2642eSMika Westerberg unsigned offset, u32 value) 95a0d2642eSMika Westerberg { 96a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 97a0d2642eSMika Westerberg writel(value, drv_data->lpss_base + offset); 98a0d2642eSMika Westerberg } 99a0d2642eSMika Westerberg 100a0d2642eSMika Westerberg /* 101a0d2642eSMika Westerberg * lpss_ssp_setup - perform LPSS SSP specific setup 102a0d2642eSMika Westerberg * @drv_data: pointer to the driver private data 103a0d2642eSMika Westerberg * 104a0d2642eSMika Westerberg * Perform LPSS SSP specific setup. This function must be called first if 105a0d2642eSMika Westerberg * one is going to use LPSS SSP private registers. 106a0d2642eSMika Westerberg */ 107a0d2642eSMika Westerberg static void lpss_ssp_setup(struct driver_data *drv_data) 108a0d2642eSMika Westerberg { 109a0d2642eSMika Westerberg unsigned offset = 0x400; 110a0d2642eSMika Westerberg u32 value, orig; 111a0d2642eSMika Westerberg 112a0d2642eSMika Westerberg if (!is_lpss_ssp(drv_data)) 113a0d2642eSMika Westerberg return; 114a0d2642eSMika Westerberg 115a0d2642eSMika Westerberg /* 116a0d2642eSMika Westerberg * Perform auto-detection of the LPSS SSP private registers. They 117a0d2642eSMika Westerberg * can be either at 1k or 2k offset from the base address. 118a0d2642eSMika Westerberg */ 119a0d2642eSMika Westerberg orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 120a0d2642eSMika Westerberg 121e61f487fSChew, Chiau Ee /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ 122a0d2642eSMika Westerberg value = orig | SPI_CS_CONTROL_SW_MODE; 123a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 124a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 125a0d2642eSMika Westerberg if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { 126a0d2642eSMika Westerberg offset = 0x800; 127a0d2642eSMika Westerberg goto detection_done; 128a0d2642eSMika Westerberg } 129a0d2642eSMika Westerberg 130e61f487fSChew, Chiau Ee orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 131e61f487fSChew, Chiau Ee 132e61f487fSChew, Chiau Ee /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ 133e61f487fSChew, Chiau Ee value = orig & ~SPI_CS_CONTROL_SW_MODE; 134a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 135a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 136e61f487fSChew, Chiau Ee if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { 137a0d2642eSMika Westerberg offset = 0x800; 138a0d2642eSMika Westerberg goto detection_done; 139a0d2642eSMika Westerberg } 140a0d2642eSMika Westerberg 141a0d2642eSMika Westerberg detection_done: 142a0d2642eSMika Westerberg /* Now set the LPSS base */ 143a0d2642eSMika Westerberg drv_data->lpss_base = drv_data->ioaddr + offset; 144a0d2642eSMika Westerberg 145a0d2642eSMika Westerberg /* Enable software chip select control */ 146a0d2642eSMika Westerberg value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 147a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 1480054e28dSMika Westerberg 1490054e28dSMika Westerberg /* Enable multiblock DMA transfers */ 1501de70612SMika Westerberg if (drv_data->master_info->enable_dma) { 1510054e28dSMika Westerberg __lpss_ssp_write_priv(drv_data, SSP_REG, 1); 1521de70612SMika Westerberg 1531de70612SMika Westerberg value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); 1541de70612SMika Westerberg value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; 1551de70612SMika Westerberg __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); 1561de70612SMika Westerberg } 157a0d2642eSMika Westerberg } 158a0d2642eSMika Westerberg 159a0d2642eSMika Westerberg static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 160a0d2642eSMika Westerberg { 161a0d2642eSMika Westerberg u32 value; 162a0d2642eSMika Westerberg 163a0d2642eSMika Westerberg if (!is_lpss_ssp(drv_data)) 164a0d2642eSMika Westerberg return; 165a0d2642eSMika Westerberg 166a0d2642eSMika Westerberg value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 167a0d2642eSMika Westerberg if (enable) 168a0d2642eSMika Westerberg value &= ~SPI_CS_CONTROL_CS_HIGH; 169a0d2642eSMika Westerberg else 170a0d2642eSMika Westerberg value |= SPI_CS_CONTROL_CS_HIGH; 171a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 172a0d2642eSMika Westerberg } 173a0d2642eSMika Westerberg 174ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 175ca632f55SGrant Likely { 176ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 177ca632f55SGrant Likely 178ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 179ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 180ca632f55SGrant Likely return; 181ca632f55SGrant Likely } 182ca632f55SGrant Likely 183ca632f55SGrant Likely if (chip->cs_control) { 184ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 185ca632f55SGrant Likely return; 186ca632f55SGrant Likely } 187ca632f55SGrant Likely 188a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 189ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 190a0d2642eSMika Westerberg return; 191a0d2642eSMika Westerberg } 192a0d2642eSMika Westerberg 193a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, true); 194ca632f55SGrant Likely } 195ca632f55SGrant Likely 196ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 197ca632f55SGrant Likely { 198ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 199ca632f55SGrant Likely 200ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 201ca632f55SGrant Likely return; 202ca632f55SGrant Likely 203ca632f55SGrant Likely if (chip->cs_control) { 204ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 205ca632f55SGrant Likely return; 206ca632f55SGrant Likely } 207ca632f55SGrant Likely 208a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 209ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 210a0d2642eSMika Westerberg return; 211a0d2642eSMika Westerberg } 212a0d2642eSMika Westerberg 213a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, false); 214ca632f55SGrant Likely } 215ca632f55SGrant Likely 216cd7bed00SMika Westerberg int pxa2xx_spi_flush(struct driver_data *drv_data) 217ca632f55SGrant Likely { 218ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 219ca632f55SGrant Likely 220ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 221ca632f55SGrant Likely 222ca632f55SGrant Likely do { 223ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 224ca632f55SGrant Likely read_SSDR(reg); 225ca632f55SGrant Likely } 226ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 227ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 228ca632f55SGrant Likely 229ca632f55SGrant Likely return limit; 230ca632f55SGrant Likely } 231ca632f55SGrant Likely 232ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 233ca632f55SGrant Likely { 234ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 235ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 236ca632f55SGrant Likely 237ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 238ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 239ca632f55SGrant Likely return 0; 240ca632f55SGrant Likely 241ca632f55SGrant Likely write_SSDR(0, reg); 242ca632f55SGrant Likely drv_data->tx += n_bytes; 243ca632f55SGrant Likely 244ca632f55SGrant Likely return 1; 245ca632f55SGrant Likely } 246ca632f55SGrant Likely 247ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 248ca632f55SGrant Likely { 249ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 250ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 251ca632f55SGrant Likely 252ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 253ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 254ca632f55SGrant Likely read_SSDR(reg); 255ca632f55SGrant Likely drv_data->rx += n_bytes; 256ca632f55SGrant Likely } 257ca632f55SGrant Likely 258ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 259ca632f55SGrant Likely } 260ca632f55SGrant Likely 261ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 262ca632f55SGrant Likely { 263ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 264ca632f55SGrant Likely 265ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 266ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 267ca632f55SGrant Likely return 0; 268ca632f55SGrant Likely 269ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 270ca632f55SGrant Likely ++drv_data->tx; 271ca632f55SGrant Likely 272ca632f55SGrant Likely return 1; 273ca632f55SGrant Likely } 274ca632f55SGrant Likely 275ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 276ca632f55SGrant Likely { 277ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 278ca632f55SGrant Likely 279ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 280ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 281ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 282ca632f55SGrant Likely ++drv_data->rx; 283ca632f55SGrant Likely } 284ca632f55SGrant Likely 285ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 286ca632f55SGrant Likely } 287ca632f55SGrant Likely 288ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 289ca632f55SGrant Likely { 290ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 291ca632f55SGrant Likely 292ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 293ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 294ca632f55SGrant Likely return 0; 295ca632f55SGrant Likely 296ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 297ca632f55SGrant Likely drv_data->tx += 2; 298ca632f55SGrant Likely 299ca632f55SGrant Likely return 1; 300ca632f55SGrant Likely } 301ca632f55SGrant Likely 302ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 303ca632f55SGrant Likely { 304ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 305ca632f55SGrant Likely 306ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 307ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 308ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 309ca632f55SGrant Likely drv_data->rx += 2; 310ca632f55SGrant Likely } 311ca632f55SGrant Likely 312ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 313ca632f55SGrant Likely } 314ca632f55SGrant Likely 315ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 316ca632f55SGrant Likely { 317ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 318ca632f55SGrant Likely 319ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 320ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 321ca632f55SGrant Likely return 0; 322ca632f55SGrant Likely 323ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 324ca632f55SGrant Likely drv_data->tx += 4; 325ca632f55SGrant Likely 326ca632f55SGrant Likely return 1; 327ca632f55SGrant Likely } 328ca632f55SGrant Likely 329ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 330ca632f55SGrant Likely { 331ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 332ca632f55SGrant Likely 333ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 334ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 335ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 336ca632f55SGrant Likely drv_data->rx += 4; 337ca632f55SGrant Likely } 338ca632f55SGrant Likely 339ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 340ca632f55SGrant Likely } 341ca632f55SGrant Likely 342cd7bed00SMika Westerberg void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 343ca632f55SGrant Likely { 344ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 345ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 346ca632f55SGrant Likely 347ca632f55SGrant Likely /* Move to next transfer */ 348ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 349ca632f55SGrant Likely drv_data->cur_transfer = 350ca632f55SGrant Likely list_entry(trans->transfer_list.next, 351ca632f55SGrant Likely struct spi_transfer, 352ca632f55SGrant Likely transfer_list); 353ca632f55SGrant Likely return RUNNING_STATE; 354ca632f55SGrant Likely } else 355ca632f55SGrant Likely return DONE_STATE; 356ca632f55SGrant Likely } 357ca632f55SGrant Likely 358ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 359ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 360ca632f55SGrant Likely { 361ca632f55SGrant Likely struct spi_transfer* last_transfer; 362ca632f55SGrant Likely struct spi_message *msg; 363ca632f55SGrant Likely 364ca632f55SGrant Likely msg = drv_data->cur_msg; 365ca632f55SGrant Likely drv_data->cur_msg = NULL; 366ca632f55SGrant Likely drv_data->cur_transfer = NULL; 367ca632f55SGrant Likely 36823e2c2aaSAxel Lin last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 369ca632f55SGrant Likely transfer_list); 370ca632f55SGrant Likely 371ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 372ca632f55SGrant Likely if (last_transfer->delay_usecs) 373ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 374ca632f55SGrant Likely 375ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 376ca632f55SGrant Likely * a message with an error, or next message is for another chip 377ca632f55SGrant Likely */ 378ca632f55SGrant Likely if (!last_transfer->cs_change) 379ca632f55SGrant Likely cs_deassert(drv_data); 380ca632f55SGrant Likely else { 381ca632f55SGrant Likely struct spi_message *next_msg; 382ca632f55SGrant Likely 383ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 384ca632f55SGrant Likely * the next message is for the same chip. Don't waste 385ca632f55SGrant Likely * time with the following tests unless this was hinted. 386ca632f55SGrant Likely * 387ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 388ca632f55SGrant Likely * after calling msg->complete (below) the driver that 389ca632f55SGrant Likely * sent the current message could be unloaded, which 390ca632f55SGrant Likely * could invalidate the cs_control() callback... 391ca632f55SGrant Likely */ 392ca632f55SGrant Likely 393ca632f55SGrant Likely /* get a pointer to the next message, if any */ 3947f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 395ca632f55SGrant Likely 396ca632f55SGrant Likely /* see if the next and current messages point 397ca632f55SGrant Likely * to the same chip 398ca632f55SGrant Likely */ 399ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 400ca632f55SGrant Likely next_msg = NULL; 401ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 402ca632f55SGrant Likely cs_deassert(drv_data); 403ca632f55SGrant Likely } 404ca632f55SGrant Likely 4057f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 406ca632f55SGrant Likely drv_data->cur_chip = NULL; 407ca632f55SGrant Likely } 408ca632f55SGrant Likely 409ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 410ca632f55SGrant Likely { 411ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 412ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 413ca632f55SGrant Likely u32 sccr1_reg; 414ca632f55SGrant Likely 415ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 416ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 417ca632f55SGrant Likely sccr1_reg |= chip->threshold; 418ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 419ca632f55SGrant Likely } 420ca632f55SGrant Likely 421ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 422ca632f55SGrant Likely { 423ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 424ca632f55SGrant Likely 425ca632f55SGrant Likely /* Stop and reset SSP */ 426ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 427ca632f55SGrant Likely reset_sccr1(drv_data); 428ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 429ca632f55SGrant Likely write_SSTO(0, reg); 430cd7bed00SMika Westerberg pxa2xx_spi_flush(drv_data); 431ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 432ca632f55SGrant Likely 433ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 434ca632f55SGrant Likely 435ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 436ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 437ca632f55SGrant Likely } 438ca632f55SGrant Likely 439ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 440ca632f55SGrant Likely { 441ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 442ca632f55SGrant Likely 443ca632f55SGrant Likely /* Stop SSP */ 444ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 445ca632f55SGrant Likely reset_sccr1(drv_data); 446ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 447ca632f55SGrant Likely write_SSTO(0, reg); 448ca632f55SGrant Likely 449ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 450ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 451ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 452ca632f55SGrant Likely 453ca632f55SGrant Likely /* Transfer delays and chip select release are 454ca632f55SGrant Likely * handled in pump_transfers or giveback 455ca632f55SGrant Likely */ 456ca632f55SGrant Likely 457ca632f55SGrant Likely /* Move to next transfer */ 458cd7bed00SMika Westerberg drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 459ca632f55SGrant Likely 460ca632f55SGrant Likely /* Schedule transfer tasklet */ 461ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 462ca632f55SGrant Likely } 463ca632f55SGrant Likely 464ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 465ca632f55SGrant Likely { 466ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 467ca632f55SGrant Likely 468ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 469ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 470ca632f55SGrant Likely 471ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 472ca632f55SGrant Likely 473ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 474ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 475ca632f55SGrant Likely return IRQ_HANDLED; 476ca632f55SGrant Likely } 477ca632f55SGrant Likely 478ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 479ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 480ca632f55SGrant Likely if (drv_data->read(drv_data)) { 481ca632f55SGrant Likely int_transfer_complete(drv_data); 482ca632f55SGrant Likely return IRQ_HANDLED; 483ca632f55SGrant Likely } 484ca632f55SGrant Likely } 485ca632f55SGrant Likely 486ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 487ca632f55SGrant Likely do { 488ca632f55SGrant Likely if (drv_data->read(drv_data)) { 489ca632f55SGrant Likely int_transfer_complete(drv_data); 490ca632f55SGrant Likely return IRQ_HANDLED; 491ca632f55SGrant Likely } 492ca632f55SGrant Likely } while (drv_data->write(drv_data)); 493ca632f55SGrant Likely 494ca632f55SGrant Likely if (drv_data->read(drv_data)) { 495ca632f55SGrant Likely int_transfer_complete(drv_data); 496ca632f55SGrant Likely return IRQ_HANDLED; 497ca632f55SGrant Likely } 498ca632f55SGrant Likely 499ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 500ca632f55SGrant Likely u32 bytes_left; 501ca632f55SGrant Likely u32 sccr1_reg; 502ca632f55SGrant Likely 503ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 504ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 505ca632f55SGrant Likely 506ca632f55SGrant Likely /* 507ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 508ca632f55SGrant Likely * remaining RX bytes. 509ca632f55SGrant Likely */ 510ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 511ca632f55SGrant Likely 512ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 513ca632f55SGrant Likely 514ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 515ca632f55SGrant Likely switch (drv_data->n_bytes) { 516ca632f55SGrant Likely case 4: 517ca632f55SGrant Likely bytes_left >>= 1; 518ca632f55SGrant Likely case 2: 519ca632f55SGrant Likely bytes_left >>= 1; 520ca632f55SGrant Likely } 521ca632f55SGrant Likely 522ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 523ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 524ca632f55SGrant Likely 525ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 526ca632f55SGrant Likely } 527ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 528ca632f55SGrant Likely } 529ca632f55SGrant Likely 530ca632f55SGrant Likely /* We did something */ 531ca632f55SGrant Likely return IRQ_HANDLED; 532ca632f55SGrant Likely } 533ca632f55SGrant Likely 534ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 535ca632f55SGrant Likely { 536ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 537ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 5387d94a505SMika Westerberg u32 sccr1_reg; 539ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 540ca632f55SGrant Likely u32 status; 541ca632f55SGrant Likely 5427d94a505SMika Westerberg /* 5437d94a505SMika Westerberg * The IRQ might be shared with other peripherals so we must first 5447d94a505SMika Westerberg * check that are we RPM suspended or not. If we are we assume that 5457d94a505SMika Westerberg * the IRQ was not for us (we shouldn't be RPM suspended when the 5467d94a505SMika Westerberg * interrupt is enabled). 5477d94a505SMika Westerberg */ 5487d94a505SMika Westerberg if (pm_runtime_suspended(&drv_data->pdev->dev)) 5497d94a505SMika Westerberg return IRQ_NONE; 5507d94a505SMika Westerberg 551269e4a41SMika Westerberg /* 552269e4a41SMika Westerberg * If the device is not yet in RPM suspended state and we get an 553269e4a41SMika Westerberg * interrupt that is meant for another device, check if status bits 554269e4a41SMika Westerberg * are all set to one. That means that the device is already 555269e4a41SMika Westerberg * powered off. 556269e4a41SMika Westerberg */ 557ca632f55SGrant Likely status = read_SSSR(reg); 558269e4a41SMika Westerberg if (status == ~0) 559269e4a41SMika Westerberg return IRQ_NONE; 560269e4a41SMika Westerberg 561269e4a41SMika Westerberg sccr1_reg = read_SSCR1(reg); 562ca632f55SGrant Likely 563ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 564ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 565ca632f55SGrant Likely mask &= ~SSSR_TFS; 566ca632f55SGrant Likely 567ca632f55SGrant Likely if (!(status & mask)) 568ca632f55SGrant Likely return IRQ_NONE; 569ca632f55SGrant Likely 570ca632f55SGrant Likely if (!drv_data->cur_msg) { 571ca632f55SGrant Likely 572ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 573ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 574ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 575ca632f55SGrant Likely write_SSTO(0, reg); 576ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 577ca632f55SGrant Likely 578f6bd03a7SJarkko Nikula dev_err(&drv_data->pdev->dev, 579f6bd03a7SJarkko Nikula "bad message state in interrupt handler\n"); 580ca632f55SGrant Likely 581ca632f55SGrant Likely /* Never fail */ 582ca632f55SGrant Likely return IRQ_HANDLED; 583ca632f55SGrant Likely } 584ca632f55SGrant Likely 585ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 586ca632f55SGrant Likely } 587ca632f55SGrant Likely 5883343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 589ca632f55SGrant Likely { 5903343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 5913343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 5923343b7a6SMika Westerberg 5933343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 594ca632f55SGrant Likely 595ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 596ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 597ca632f55SGrant Likely else 598ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 599ca632f55SGrant Likely } 600ca632f55SGrant Likely 601ca632f55SGrant Likely static void pump_transfers(unsigned long data) 602ca632f55SGrant Likely { 603ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 604ca632f55SGrant Likely struct spi_message *message = NULL; 605ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 606ca632f55SGrant Likely struct spi_transfer *previous = NULL; 607ca632f55SGrant Likely struct chip_data *chip = NULL; 608ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 609ca632f55SGrant Likely u32 clk_div = 0; 610ca632f55SGrant Likely u8 bits = 0; 611ca632f55SGrant Likely u32 speed = 0; 612ca632f55SGrant Likely u32 cr0; 613ca632f55SGrant Likely u32 cr1; 614ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 615ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 616ca632f55SGrant Likely 617ca632f55SGrant Likely /* Get current state information */ 618ca632f55SGrant Likely message = drv_data->cur_msg; 619ca632f55SGrant Likely transfer = drv_data->cur_transfer; 620ca632f55SGrant Likely chip = drv_data->cur_chip; 621ca632f55SGrant Likely 622ca632f55SGrant Likely /* Handle for abort */ 623ca632f55SGrant Likely if (message->state == ERROR_STATE) { 624ca632f55SGrant Likely message->status = -EIO; 625ca632f55SGrant Likely giveback(drv_data); 626ca632f55SGrant Likely return; 627ca632f55SGrant Likely } 628ca632f55SGrant Likely 629ca632f55SGrant Likely /* Handle end of message */ 630ca632f55SGrant Likely if (message->state == DONE_STATE) { 631ca632f55SGrant Likely message->status = 0; 632ca632f55SGrant Likely giveback(drv_data); 633ca632f55SGrant Likely return; 634ca632f55SGrant Likely } 635ca632f55SGrant Likely 636ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 637ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 638ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 639ca632f55SGrant Likely struct spi_transfer, 640ca632f55SGrant Likely transfer_list); 641ca632f55SGrant Likely if (previous->delay_usecs) 642ca632f55SGrant Likely udelay(previous->delay_usecs); 643ca632f55SGrant Likely 644ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 645ca632f55SGrant Likely if (previous->cs_change) 646ca632f55SGrant Likely cs_deassert(drv_data); 647ca632f55SGrant Likely } 648ca632f55SGrant Likely 649cd7bed00SMika Westerberg /* Check if we can DMA this transfer */ 650cd7bed00SMika Westerberg if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 651ca632f55SGrant Likely 652ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 653ca632f55SGrant Likely if (message->is_dma_mapped 654ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 655ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 656f6bd03a7SJarkko Nikula "pump_transfers: mapped transfer length of " 657f6bd03a7SJarkko Nikula "%u is greater than %d\n", 658ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 659ca632f55SGrant Likely message->status = -EINVAL; 660ca632f55SGrant Likely giveback(drv_data); 661ca632f55SGrant Likely return; 662ca632f55SGrant Likely } 663ca632f55SGrant Likely 664ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 665f6bd03a7SJarkko Nikula dev_warn_ratelimited(&message->spi->dev, 666f6bd03a7SJarkko Nikula "pump_transfers: DMA disabled for transfer length %ld " 667ca632f55SGrant Likely "greater than %d\n", 668ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 669ca632f55SGrant Likely } 670ca632f55SGrant Likely 671ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 672cd7bed00SMika Westerberg if (pxa2xx_spi_flush(drv_data) == 0) { 673ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 674ca632f55SGrant Likely message->status = -EIO; 675ca632f55SGrant Likely giveback(drv_data); 676ca632f55SGrant Likely return; 677ca632f55SGrant Likely } 678ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 679ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 680ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 681ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 682ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 683ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 684ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 685cd7bed00SMika Westerberg drv_data->len = transfer->len; 686ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 687ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 688ca632f55SGrant Likely 689ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 690ca632f55SGrant Likely cr0 = chip->cr0; 691ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 692ca632f55SGrant Likely 693ca632f55SGrant Likely bits = chip->bits_per_word; 694ca632f55SGrant Likely speed = chip->speed_hz; 695ca632f55SGrant Likely 696ca632f55SGrant Likely if (transfer->speed_hz) 697ca632f55SGrant Likely speed = transfer->speed_hz; 698ca632f55SGrant Likely 699ca632f55SGrant Likely if (transfer->bits_per_word) 700ca632f55SGrant Likely bits = transfer->bits_per_word; 701ca632f55SGrant Likely 7023343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, speed); 703ca632f55SGrant Likely 704ca632f55SGrant Likely if (bits <= 8) { 705ca632f55SGrant Likely drv_data->n_bytes = 1; 706ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 707ca632f55SGrant Likely u8_reader : null_reader; 708ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 709ca632f55SGrant Likely u8_writer : null_writer; 710ca632f55SGrant Likely } else if (bits <= 16) { 711ca632f55SGrant Likely drv_data->n_bytes = 2; 712ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 713ca632f55SGrant Likely u16_reader : null_reader; 714ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 715ca632f55SGrant Likely u16_writer : null_writer; 716ca632f55SGrant Likely } else if (bits <= 32) { 717ca632f55SGrant Likely drv_data->n_bytes = 4; 718ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 719ca632f55SGrant Likely u32_reader : null_reader; 720ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 721ca632f55SGrant Likely u32_writer : null_writer; 722ca632f55SGrant Likely } 723ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 724ca632f55SGrant Likely * thresholds and burst also */ 725ca632f55SGrant Likely if (chip->enable_dma) { 726cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 727cd7bed00SMika Westerberg message->spi, 728ca632f55SGrant Likely bits, &dma_burst, 729ca632f55SGrant Likely &dma_thresh)) 730f6bd03a7SJarkko Nikula dev_warn_ratelimited(&message->spi->dev, 731f6bd03a7SJarkko Nikula "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 732ca632f55SGrant Likely } 733ca632f55SGrant Likely 734ca632f55SGrant Likely cr0 = clk_div 735ca632f55SGrant Likely | SSCR0_Motorola 736ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 737ca632f55SGrant Likely | SSCR0_SSE 738ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 739ca632f55SGrant Likely } 740ca632f55SGrant Likely 741ca632f55SGrant Likely message->state = RUNNING_STATE; 742ca632f55SGrant Likely 743ca632f55SGrant Likely drv_data->dma_mapped = 0; 744cd7bed00SMika Westerberg if (pxa2xx_spi_dma_is_possible(drv_data->len)) 745cd7bed00SMika Westerberg drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 746ca632f55SGrant Likely if (drv_data->dma_mapped) { 747ca632f55SGrant Likely 748ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 749cd7bed00SMika Westerberg drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 750ca632f55SGrant Likely 751cd7bed00SMika Westerberg pxa2xx_spi_dma_prepare(drv_data, dma_burst); 752ca632f55SGrant Likely 753ca632f55SGrant Likely /* Clear status and start DMA engine */ 754ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 755ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 756cd7bed00SMika Westerberg 757cd7bed00SMika Westerberg pxa2xx_spi_dma_start(drv_data); 758ca632f55SGrant Likely } else { 759ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 760ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 761ca632f55SGrant Likely 762ca632f55SGrant Likely /* Clear status */ 763ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 764ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 765ca632f55SGrant Likely } 766ca632f55SGrant Likely 767a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 768a0d2642eSMika Westerberg if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) 769a0d2642eSMika Westerberg write_SSIRF(chip->lpss_rx_threshold, reg); 770a0d2642eSMika Westerberg if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) 771a0d2642eSMika Westerberg write_SSITF(chip->lpss_tx_threshold, reg); 772a0d2642eSMika Westerberg } 773a0d2642eSMika Westerberg 774ca632f55SGrant Likely /* see if we need to reload the config registers */ 775ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 776ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 777ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 778ca632f55SGrant Likely 779ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 780ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 781ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 782ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 783ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 784ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 785ca632f55SGrant Likely /* restart the SSP */ 786ca632f55SGrant Likely write_SSCR0(cr0, reg); 787ca632f55SGrant Likely 788ca632f55SGrant Likely } else { 789ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 790ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 791ca632f55SGrant Likely } 792ca632f55SGrant Likely 793ca632f55SGrant Likely cs_assert(drv_data); 794ca632f55SGrant Likely 795ca632f55SGrant Likely /* after chip select, release the data by enabling service 796ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 797ca632f55SGrant Likely write_SSCR1(cr1, reg); 798ca632f55SGrant Likely } 799ca632f55SGrant Likely 8007f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 8017f86bde9SMika Westerberg struct spi_message *msg) 802ca632f55SGrant Likely { 8037f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 804ca632f55SGrant Likely 8057f86bde9SMika Westerberg drv_data->cur_msg = msg; 806ca632f55SGrant Likely /* Initial message state*/ 807ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 808ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 809ca632f55SGrant Likely struct spi_transfer, 810ca632f55SGrant Likely transfer_list); 811ca632f55SGrant Likely 812ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 813ca632f55SGrant Likely * chip configuration */ 814ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 815ca632f55SGrant Likely 816ca632f55SGrant Likely /* Mark as busy and launch transfers */ 817ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 818ca632f55SGrant Likely return 0; 819ca632f55SGrant Likely } 820ca632f55SGrant Likely 8217d94a505SMika Westerberg static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 8227d94a505SMika Westerberg { 8237d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 8247d94a505SMika Westerberg 8257d94a505SMika Westerberg /* Disable the SSP now */ 8267d94a505SMika Westerberg write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, 8277d94a505SMika Westerberg drv_data->ioaddr); 8287d94a505SMika Westerberg 8297d94a505SMika Westerberg return 0; 8307d94a505SMika Westerberg } 8317d94a505SMika Westerberg 832ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 833ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 834ca632f55SGrant Likely { 835ca632f55SGrant Likely int err = 0; 836ca632f55SGrant Likely 837ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 838ca632f55SGrant Likely return 0; 839ca632f55SGrant Likely 840ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 841ca632f55SGrant Likely * different chip_info, release previously requested GPIO 842ca632f55SGrant Likely */ 843ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 844ca632f55SGrant Likely gpio_free(chip->gpio_cs); 845ca632f55SGrant Likely 846ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 847ca632f55SGrant Likely if (chip_info->cs_control) { 848ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 849ca632f55SGrant Likely return 0; 850ca632f55SGrant Likely } 851ca632f55SGrant Likely 852ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 853ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 854ca632f55SGrant Likely if (err) { 855f6bd03a7SJarkko Nikula dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 856f6bd03a7SJarkko Nikula chip_info->gpio_cs); 857ca632f55SGrant Likely return err; 858ca632f55SGrant Likely } 859ca632f55SGrant Likely 860ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 861ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 862ca632f55SGrant Likely 863ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 864ca632f55SGrant Likely !chip->gpio_cs_inverted); 865ca632f55SGrant Likely } 866ca632f55SGrant Likely 867ca632f55SGrant Likely return err; 868ca632f55SGrant Likely } 869ca632f55SGrant Likely 870ca632f55SGrant Likely static int setup(struct spi_device *spi) 871ca632f55SGrant Likely { 872ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 873ca632f55SGrant Likely struct chip_data *chip; 874ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 875ca632f55SGrant Likely unsigned int clk_div; 876a0d2642eSMika Westerberg uint tx_thres, tx_hi_thres, rx_thres; 877a0d2642eSMika Westerberg 878a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 879a0d2642eSMika Westerberg tx_thres = LPSS_TX_LOTHRESH_DFLT; 880a0d2642eSMika Westerberg tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 881a0d2642eSMika Westerberg rx_thres = LPSS_RX_THRESH_DFLT; 882a0d2642eSMika Westerberg } else { 883a0d2642eSMika Westerberg tx_thres = TX_THRESH_DFLT; 884a0d2642eSMika Westerberg tx_hi_thres = 0; 885a0d2642eSMika Westerberg rx_thres = RX_THRESH_DFLT; 886a0d2642eSMika Westerberg } 887ca632f55SGrant Likely 888ca632f55SGrant Likely /* Only alloc on first setup */ 889ca632f55SGrant Likely chip = spi_get_ctldata(spi); 890ca632f55SGrant Likely if (!chip) { 891ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 8929deae459SJingoo Han if (!chip) 893ca632f55SGrant Likely return -ENOMEM; 894ca632f55SGrant Likely 895ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 896ca632f55SGrant Likely if (spi->chip_select > 4) { 897f6bd03a7SJarkko Nikula dev_err(&spi->dev, 898f6bd03a7SJarkko Nikula "failed setup: cs number must not be > 4.\n"); 899ca632f55SGrant Likely kfree(chip); 900ca632f55SGrant Likely return -EINVAL; 901ca632f55SGrant Likely } 902ca632f55SGrant Likely 903ca632f55SGrant Likely chip->frm = spi->chip_select; 904ca632f55SGrant Likely } else 905ca632f55SGrant Likely chip->gpio_cs = -1; 906ca632f55SGrant Likely chip->enable_dma = 0; 907ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 908ca632f55SGrant Likely } 909ca632f55SGrant Likely 910ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 911ca632f55SGrant Likely * if chip_info exists, use it */ 912ca632f55SGrant Likely chip_info = spi->controller_data; 913ca632f55SGrant Likely 914ca632f55SGrant Likely /* chip_info isn't always needed */ 915ca632f55SGrant Likely chip->cr1 = 0; 916ca632f55SGrant Likely if (chip_info) { 917ca632f55SGrant Likely if (chip_info->timeout) 918ca632f55SGrant Likely chip->timeout = chip_info->timeout; 919ca632f55SGrant Likely if (chip_info->tx_threshold) 920ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 921a0d2642eSMika Westerberg if (chip_info->tx_hi_threshold) 922a0d2642eSMika Westerberg tx_hi_thres = chip_info->tx_hi_threshold; 923ca632f55SGrant Likely if (chip_info->rx_threshold) 924ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 925ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 926ca632f55SGrant Likely chip->dma_threshold = 0; 927ca632f55SGrant Likely if (chip_info->enable_loopback) 928ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 929a3496855SMika Westerberg } else if (ACPI_HANDLE(&spi->dev)) { 930a3496855SMika Westerberg /* 931a3496855SMika Westerberg * Slave devices enumerated from ACPI namespace don't 932a3496855SMika Westerberg * usually have chip_info but we still might want to use 933a3496855SMika Westerberg * DMA with them. 934a3496855SMika Westerberg */ 935a3496855SMika Westerberg chip->enable_dma = drv_data->master_info->enable_dma; 936ca632f55SGrant Likely } 937ca632f55SGrant Likely 938ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 939ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 940ca632f55SGrant Likely 941a0d2642eSMika Westerberg chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 942a0d2642eSMika Westerberg chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 943a0d2642eSMika Westerberg | SSITF_TxHiThresh(tx_hi_thres); 944a0d2642eSMika Westerberg 945ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 946ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 947ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 948ca632f55SGrant Likely if (chip->enable_dma) { 949ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 950cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 951cd7bed00SMika Westerberg spi->bits_per_word, 952ca632f55SGrant Likely &chip->dma_burst_size, 953ca632f55SGrant Likely &chip->dma_threshold)) { 954f6bd03a7SJarkko Nikula dev_warn(&spi->dev, 955f6bd03a7SJarkko Nikula "in setup: DMA burst size reduced to match bits_per_word\n"); 956ca632f55SGrant Likely } 957ca632f55SGrant Likely } 958ca632f55SGrant Likely 9593343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 960ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 961ca632f55SGrant Likely 962ca632f55SGrant Likely chip->cr0 = clk_div 963ca632f55SGrant Likely | SSCR0_Motorola 964ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 965ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 966ca632f55SGrant Likely | SSCR0_SSE 967ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 968ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 969ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 970ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 971ca632f55SGrant Likely 972b833172fSMika Westerberg if (spi->mode & SPI_LOOP) 973b833172fSMika Westerberg chip->cr1 |= SSCR1_LBM; 974b833172fSMika Westerberg 975ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 976ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 977ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 9783343b7a6SMika Westerberg drv_data->max_clk_rate 979ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 980ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 981ca632f55SGrant Likely else 982ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 9833343b7a6SMika Westerberg drv_data->max_clk_rate / 2 984ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 985ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 986ca632f55SGrant Likely 987ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 988ca632f55SGrant Likely chip->n_bytes = 1; 989ca632f55SGrant Likely chip->read = u8_reader; 990ca632f55SGrant Likely chip->write = u8_writer; 991ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 992ca632f55SGrant Likely chip->n_bytes = 2; 993ca632f55SGrant Likely chip->read = u16_reader; 994ca632f55SGrant Likely chip->write = u16_writer; 995ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 996ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 997ca632f55SGrant Likely chip->n_bytes = 4; 998ca632f55SGrant Likely chip->read = u32_reader; 999ca632f55SGrant Likely chip->write = u32_writer; 1000ca632f55SGrant Likely } 1001ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 1002ca632f55SGrant Likely 1003ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1004ca632f55SGrant Likely 1005ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 1006ca632f55SGrant Likely return 0; 1007ca632f55SGrant Likely 1008ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 1009ca632f55SGrant Likely } 1010ca632f55SGrant Likely 1011ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 1012ca632f55SGrant Likely { 1013ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1014ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely if (!chip) 1017ca632f55SGrant Likely return; 1018ca632f55SGrant Likely 1019ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1020ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1021ca632f55SGrant Likely 1022ca632f55SGrant Likely kfree(chip); 1023ca632f55SGrant Likely } 1024ca632f55SGrant Likely 1025a3496855SMika Westerberg #ifdef CONFIG_ACPI 1026a3496855SMika Westerberg static struct pxa2xx_spi_master * 1027a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1028a3496855SMika Westerberg { 1029a3496855SMika Westerberg struct pxa2xx_spi_master *pdata; 1030a3496855SMika Westerberg struct acpi_device *adev; 1031a3496855SMika Westerberg struct ssp_device *ssp; 1032a3496855SMika Westerberg struct resource *res; 1033a3496855SMika Westerberg int devid; 1034a3496855SMika Westerberg 1035a3496855SMika Westerberg if (!ACPI_HANDLE(&pdev->dev) || 1036a3496855SMika Westerberg acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1037a3496855SMika Westerberg return NULL; 1038a3496855SMika Westerberg 1039cc0ee987SMika Westerberg pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 10409deae459SJingoo Han if (!pdata) 1041a3496855SMika Westerberg return NULL; 1042a3496855SMika Westerberg 1043a3496855SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1044a3496855SMika Westerberg if (!res) 1045a3496855SMika Westerberg return NULL; 1046a3496855SMika Westerberg 1047a3496855SMika Westerberg ssp = &pdata->ssp; 1048a3496855SMika Westerberg 1049a3496855SMika Westerberg ssp->phys_base = res->start; 1050cbfd6a21SSachin Kamat ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1051cbfd6a21SSachin Kamat if (IS_ERR(ssp->mmio_base)) 10526dc81f6fSMika Westerberg return NULL; 1053a3496855SMika Westerberg 1054a3496855SMika Westerberg ssp->clk = devm_clk_get(&pdev->dev, NULL); 1055a3496855SMika Westerberg ssp->irq = platform_get_irq(pdev, 0); 1056a3496855SMika Westerberg ssp->type = LPSS_SSP; 1057a3496855SMika Westerberg ssp->pdev = pdev; 1058a3496855SMika Westerberg 1059a3496855SMika Westerberg ssp->port_id = -1; 1060a3496855SMika Westerberg if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1061a3496855SMika Westerberg ssp->port_id = devid; 1062a3496855SMika Westerberg 1063a3496855SMika Westerberg pdata->num_chipselect = 1; 1064cddb339bSMika Westerberg pdata->enable_dma = true; 1065a3496855SMika Westerberg 1066a3496855SMika Westerberg return pdata; 1067a3496855SMika Westerberg } 1068a3496855SMika Westerberg 1069a3496855SMika Westerberg static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1070a3496855SMika Westerberg { "INT33C0", 0 }, 1071a3496855SMika Westerberg { "INT33C1", 0 }, 107254acbd96SMika Westerberg { "INT3430", 0 }, 107354acbd96SMika Westerberg { "INT3431", 0 }, 10744b30f2a1SMika Westerberg { "80860F0E", 0 }, 1075aca26364SAlan Cox { "8086228E", 0 }, 1076a3496855SMika Westerberg { }, 1077a3496855SMika Westerberg }; 1078a3496855SMika Westerberg MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1079a3496855SMika Westerberg #else 1080a3496855SMika Westerberg static inline struct pxa2xx_spi_master * 1081a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1082a3496855SMika Westerberg { 1083a3496855SMika Westerberg return NULL; 1084a3496855SMika Westerberg } 1085a3496855SMika Westerberg #endif 1086a3496855SMika Westerberg 1087fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 1088ca632f55SGrant Likely { 1089ca632f55SGrant Likely struct device *dev = &pdev->dev; 1090ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 1091ca632f55SGrant Likely struct spi_master *master; 1092ca632f55SGrant Likely struct driver_data *drv_data; 1093ca632f55SGrant Likely struct ssp_device *ssp; 1094ca632f55SGrant Likely int status; 1095ca632f55SGrant Likely 1096851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 1097851bacf5SMika Westerberg if (!platform_info) { 1098a3496855SMika Westerberg platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1099a3496855SMika Westerberg if (!platform_info) { 1100851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 1101851bacf5SMika Westerberg return -ENODEV; 1102851bacf5SMika Westerberg } 1103a3496855SMika Westerberg } 1104ca632f55SGrant Likely 1105ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 1106851bacf5SMika Westerberg if (!ssp) 1107851bacf5SMika Westerberg ssp = &platform_info->ssp; 1108851bacf5SMika Westerberg 1109851bacf5SMika Westerberg if (!ssp->mmio_base) { 1110851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 1111ca632f55SGrant Likely return -ENODEV; 1112ca632f55SGrant Likely } 1113ca632f55SGrant Likely 1114ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 1115ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1116ca632f55SGrant Likely if (!master) { 1117ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1118ca632f55SGrant Likely pxa_ssp_free(ssp); 1119ca632f55SGrant Likely return -ENOMEM; 1120ca632f55SGrant Likely } 1121ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 1122ca632f55SGrant Likely drv_data->master = master; 1123ca632f55SGrant Likely drv_data->master_info = platform_info; 1124ca632f55SGrant Likely drv_data->pdev = pdev; 1125ca632f55SGrant Likely drv_data->ssp = ssp; 1126ca632f55SGrant Likely 1127ca632f55SGrant Likely master->dev.parent = &pdev->dev; 1128ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 1129ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1130b833172fSMika Westerberg master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1131ca632f55SGrant Likely 1132851bacf5SMika Westerberg master->bus_num = ssp->port_id; 1133ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 1134ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 1135ca632f55SGrant Likely master->cleanup = cleanup; 1136ca632f55SGrant Likely master->setup = setup; 11377f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 11387d94a505SMika Westerberg master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 11397dd62787SMark Brown master->auto_runtime_pm = true; 1140ca632f55SGrant Likely 1141ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 11422b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1143ca632f55SGrant Likely 1144ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 1145ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 1146ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 114724778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1148ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1149ca632f55SGrant Likely drv_data->dma_cr1 = 0; 1150ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 1151ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1152ca632f55SGrant Likely } else { 115324778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1154ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 11555928808eSMika Westerberg drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1156ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1157ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1158ca632f55SGrant Likely } 1159ca632f55SGrant Likely 1160ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1161ca632f55SGrant Likely drv_data); 1162ca632f55SGrant Likely if (status < 0) { 1163ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1164ca632f55SGrant Likely goto out_error_master_alloc; 1165ca632f55SGrant Likely } 1166ca632f55SGrant Likely 1167ca632f55SGrant Likely /* Setup DMA if requested */ 1168ca632f55SGrant Likely drv_data->tx_channel = -1; 1169ca632f55SGrant Likely drv_data->rx_channel = -1; 1170ca632f55SGrant Likely if (platform_info->enable_dma) { 1171cd7bed00SMika Westerberg status = pxa2xx_spi_dma_setup(drv_data); 1172cd7bed00SMika Westerberg if (status) { 1173cddb339bSMika Westerberg dev_dbg(dev, "no DMA channels available, using PIO\n"); 1174cd7bed00SMika Westerberg platform_info->enable_dma = false; 1175ca632f55SGrant Likely } 1176ca632f55SGrant Likely } 1177ca632f55SGrant Likely 1178ca632f55SGrant Likely /* Enable SOC clock */ 11793343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 11803343b7a6SMika Westerberg 11813343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1182ca632f55SGrant Likely 1183ca632f55SGrant Likely /* Load default SSP configuration */ 1184ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1185ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1186ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 1187ca632f55SGrant Likely drv_data->ioaddr); 1188ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 1189ca632f55SGrant Likely | SSCR0_Motorola 1190ca632f55SGrant Likely | SSCR0_DataSize(8), 1191ca632f55SGrant Likely drv_data->ioaddr); 1192ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1193ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 1194ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 1195ca632f55SGrant Likely 1196a0d2642eSMika Westerberg lpss_ssp_setup(drv_data); 1197a0d2642eSMika Westerberg 11987f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 11997f86bde9SMika Westerberg (unsigned long)drv_data); 1200ca632f55SGrant Likely 1201836d1a22SAntonio Ospite pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1202836d1a22SAntonio Ospite pm_runtime_use_autosuspend(&pdev->dev); 1203836d1a22SAntonio Ospite pm_runtime_set_active(&pdev->dev); 1204836d1a22SAntonio Ospite pm_runtime_enable(&pdev->dev); 1205836d1a22SAntonio Ospite 1206ca632f55SGrant Likely /* Register with the SPI framework */ 1207ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1208a807fcd0SJingoo Han status = devm_spi_register_master(&pdev->dev, master); 1209ca632f55SGrant Likely if (status != 0) { 1210ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 12117f86bde9SMika Westerberg goto out_error_clock_enabled; 1212ca632f55SGrant Likely } 1213ca632f55SGrant Likely 1214ca632f55SGrant Likely return status; 1215ca632f55SGrant Likely 1216ca632f55SGrant Likely out_error_clock_enabled: 12173343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1218cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1219ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1220ca632f55SGrant Likely 1221ca632f55SGrant Likely out_error_master_alloc: 1222ca632f55SGrant Likely spi_master_put(master); 1223ca632f55SGrant Likely pxa_ssp_free(ssp); 1224ca632f55SGrant Likely return status; 1225ca632f55SGrant Likely } 1226ca632f55SGrant Likely 1227ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1228ca632f55SGrant Likely { 1229ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1230ca632f55SGrant Likely struct ssp_device *ssp; 1231ca632f55SGrant Likely 1232ca632f55SGrant Likely if (!drv_data) 1233ca632f55SGrant Likely return 0; 1234ca632f55SGrant Likely ssp = drv_data->ssp; 1235ca632f55SGrant Likely 12367d94a505SMika Westerberg pm_runtime_get_sync(&pdev->dev); 12377d94a505SMika Westerberg 1238ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1239ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 12403343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1241ca632f55SGrant Likely 1242ca632f55SGrant Likely /* Release DMA */ 1243cd7bed00SMika Westerberg if (drv_data->master_info->enable_dma) 1244cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1245ca632f55SGrant Likely 12467d94a505SMika Westerberg pm_runtime_put_noidle(&pdev->dev); 12477d94a505SMika Westerberg pm_runtime_disable(&pdev->dev); 12487d94a505SMika Westerberg 1249ca632f55SGrant Likely /* Release IRQ */ 1250ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1251ca632f55SGrant Likely 1252ca632f55SGrant Likely /* Release SSP */ 1253ca632f55SGrant Likely pxa_ssp_free(ssp); 1254ca632f55SGrant Likely 1255ca632f55SGrant Likely return 0; 1256ca632f55SGrant Likely } 1257ca632f55SGrant Likely 1258ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1259ca632f55SGrant Likely { 1260ca632f55SGrant Likely int status = 0; 1261ca632f55SGrant Likely 1262ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1263ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1264ca632f55SGrant Likely } 1265ca632f55SGrant Likely 1266382cebb0SMika Westerberg #ifdef CONFIG_PM_SLEEP 1267ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1268ca632f55SGrant Likely { 1269ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1270ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1271ca632f55SGrant Likely int status = 0; 1272ca632f55SGrant Likely 12737f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1274ca632f55SGrant Likely if (status != 0) 1275ca632f55SGrant Likely return status; 1276ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 12772b9375b9SDmitry Eremin-Solenikov 12782b9375b9SDmitry Eremin-Solenikov if (!pm_runtime_suspended(dev)) 12793343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1280ca632f55SGrant Likely 1281ca632f55SGrant Likely return 0; 1282ca632f55SGrant Likely } 1283ca632f55SGrant Likely 1284ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1285ca632f55SGrant Likely { 1286ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1287ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1288ca632f55SGrant Likely int status = 0; 1289ca632f55SGrant Likely 1290cd7bed00SMika Westerberg pxa2xx_spi_dma_resume(drv_data); 1291ca632f55SGrant Likely 1292ca632f55SGrant Likely /* Enable the SSP clock */ 12932b9375b9SDmitry Eremin-Solenikov if (!pm_runtime_suspended(dev)) 12943343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1295ca632f55SGrant Likely 1296c50325f7SChew, Chiau Ee /* Restore LPSS private register bits */ 1297c50325f7SChew, Chiau Ee lpss_ssp_setup(drv_data); 1298c50325f7SChew, Chiau Ee 1299ca632f55SGrant Likely /* Start the queue running */ 13007f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1301ca632f55SGrant Likely if (status != 0) { 1302ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1303ca632f55SGrant Likely return status; 1304ca632f55SGrant Likely } 1305ca632f55SGrant Likely 1306ca632f55SGrant Likely return 0; 1307ca632f55SGrant Likely } 13087d94a505SMika Westerberg #endif 13097d94a505SMika Westerberg 1310*ec833050SRafael J. Wysocki #ifdef CONFIG_PM 13117d94a505SMika Westerberg static int pxa2xx_spi_runtime_suspend(struct device *dev) 13127d94a505SMika Westerberg { 13137d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 13147d94a505SMika Westerberg 13157d94a505SMika Westerberg clk_disable_unprepare(drv_data->ssp->clk); 13167d94a505SMika Westerberg return 0; 13177d94a505SMika Westerberg } 13187d94a505SMika Westerberg 13197d94a505SMika Westerberg static int pxa2xx_spi_runtime_resume(struct device *dev) 13207d94a505SMika Westerberg { 13217d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 13227d94a505SMika Westerberg 13237d94a505SMika Westerberg clk_prepare_enable(drv_data->ssp->clk); 13247d94a505SMika Westerberg return 0; 13257d94a505SMika Westerberg } 13267d94a505SMika Westerberg #endif 1327ca632f55SGrant Likely 1328ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 13297d94a505SMika Westerberg SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 13307d94a505SMika Westerberg SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 13317d94a505SMika Westerberg pxa2xx_spi_runtime_resume, NULL) 1332ca632f55SGrant Likely }; 1333ca632f55SGrant Likely 1334ca632f55SGrant Likely static struct platform_driver driver = { 1335ca632f55SGrant Likely .driver = { 1336ca632f55SGrant Likely .name = "pxa2xx-spi", 1337ca632f55SGrant Likely .owner = THIS_MODULE, 1338ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1339a3496855SMika Westerberg .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1340ca632f55SGrant Likely }, 1341ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1342ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1343ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1344ca632f55SGrant Likely }; 1345ca632f55SGrant Likely 1346ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1347ca632f55SGrant Likely { 1348ca632f55SGrant Likely return platform_driver_register(&driver); 1349ca632f55SGrant Likely } 1350ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1351ca632f55SGrant Likely 1352ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1353ca632f55SGrant Likely { 1354ca632f55SGrant Likely platform_driver_unregister(&driver); 1355ca632f55SGrant Likely } 1356ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1357