1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 5ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 6ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 7ca632f55SGrant Likely * (at your option) any later version. 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 10ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 11ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12ca632f55SGrant Likely * GNU General Public License for more details. 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 15ca632f55SGrant Likely * along with this program; if not, write to the Free Software 16ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17ca632f55SGrant Likely */ 18ca632f55SGrant Likely 19ca632f55SGrant Likely #include <linux/init.h> 20ca632f55SGrant Likely #include <linux/module.h> 21ca632f55SGrant Likely #include <linux/device.h> 22ca632f55SGrant Likely #include <linux/ioport.h> 23ca632f55SGrant Likely #include <linux/errno.h> 24ca632f55SGrant Likely #include <linux/interrupt.h> 25ca632f55SGrant Likely #include <linux/platform_device.h> 26ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 27ca632f55SGrant Likely #include <linux/spi/spi.h> 28ca632f55SGrant Likely #include <linux/workqueue.h> 29ca632f55SGrant Likely #include <linux/delay.h> 30ca632f55SGrant Likely #include <linux/gpio.h> 31ca632f55SGrant Likely #include <linux/slab.h> 323343b7a6SMika Westerberg #include <linux/clk.h> 337d94a505SMika Westerberg #include <linux/pm_runtime.h> 34ca632f55SGrant Likely 35ca632f55SGrant Likely #include <asm/io.h> 36ca632f55SGrant Likely #include <asm/irq.h> 37ca632f55SGrant Likely #include <asm/delay.h> 38ca632f55SGrant Likely 39cd7bed00SMika Westerberg #include "spi-pxa2xx.h" 40ca632f55SGrant Likely 41ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 42ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 43ca632f55SGrant Likely MODULE_LICENSE("GPL"); 44ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 45ca632f55SGrant Likely 46ca632f55SGrant Likely #define MAX_BUSES 3 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define TIMOUT_DFLT 1000 49ca632f55SGrant Likely 50ca632f55SGrant Likely /* 51ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 52ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 53ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 54ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 55ca632f55SGrant Likely * service and interrupt enables 56ca632f55SGrant Likely */ 57ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 58ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 59ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 60ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 61ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 62ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 63ca632f55SGrant Likely 64ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 65ca632f55SGrant Likely { 66ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 67ca632f55SGrant Likely 68ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 69ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 70ca632f55SGrant Likely return; 71ca632f55SGrant Likely } 72ca632f55SGrant Likely 73ca632f55SGrant Likely if (chip->cs_control) { 74ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 75ca632f55SGrant Likely return; 76ca632f55SGrant Likely } 77ca632f55SGrant Likely 78ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 79ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 80ca632f55SGrant Likely } 81ca632f55SGrant Likely 82ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 83ca632f55SGrant Likely { 84ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 85ca632f55SGrant Likely 86ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 87ca632f55SGrant Likely return; 88ca632f55SGrant Likely 89ca632f55SGrant Likely if (chip->cs_control) { 90ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 91ca632f55SGrant Likely return; 92ca632f55SGrant Likely } 93ca632f55SGrant Likely 94ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 95ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 96ca632f55SGrant Likely } 97ca632f55SGrant Likely 98cd7bed00SMika Westerberg int pxa2xx_spi_flush(struct driver_data *drv_data) 99ca632f55SGrant Likely { 100ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 101ca632f55SGrant Likely 102ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 103ca632f55SGrant Likely 104ca632f55SGrant Likely do { 105ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 106ca632f55SGrant Likely read_SSDR(reg); 107ca632f55SGrant Likely } 108ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 109ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 110ca632f55SGrant Likely 111ca632f55SGrant Likely return limit; 112ca632f55SGrant Likely } 113ca632f55SGrant Likely 114ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 115ca632f55SGrant Likely { 116ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 117ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 118ca632f55SGrant Likely 119ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 120ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 121ca632f55SGrant Likely return 0; 122ca632f55SGrant Likely 123ca632f55SGrant Likely write_SSDR(0, reg); 124ca632f55SGrant Likely drv_data->tx += n_bytes; 125ca632f55SGrant Likely 126ca632f55SGrant Likely return 1; 127ca632f55SGrant Likely } 128ca632f55SGrant Likely 129ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 130ca632f55SGrant Likely { 131ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 132ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 133ca632f55SGrant Likely 134ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 135ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 136ca632f55SGrant Likely read_SSDR(reg); 137ca632f55SGrant Likely drv_data->rx += n_bytes; 138ca632f55SGrant Likely } 139ca632f55SGrant Likely 140ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 141ca632f55SGrant Likely } 142ca632f55SGrant Likely 143ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 144ca632f55SGrant Likely { 145ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 146ca632f55SGrant Likely 147ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 148ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 149ca632f55SGrant Likely return 0; 150ca632f55SGrant Likely 151ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 152ca632f55SGrant Likely ++drv_data->tx; 153ca632f55SGrant Likely 154ca632f55SGrant Likely return 1; 155ca632f55SGrant Likely } 156ca632f55SGrant Likely 157ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 158ca632f55SGrant Likely { 159ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 160ca632f55SGrant Likely 161ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 162ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 163ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 164ca632f55SGrant Likely ++drv_data->rx; 165ca632f55SGrant Likely } 166ca632f55SGrant Likely 167ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 168ca632f55SGrant Likely } 169ca632f55SGrant Likely 170ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 171ca632f55SGrant Likely { 172ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 173ca632f55SGrant Likely 174ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 175ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 176ca632f55SGrant Likely return 0; 177ca632f55SGrant Likely 178ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 179ca632f55SGrant Likely drv_data->tx += 2; 180ca632f55SGrant Likely 181ca632f55SGrant Likely return 1; 182ca632f55SGrant Likely } 183ca632f55SGrant Likely 184ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 185ca632f55SGrant Likely { 186ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 187ca632f55SGrant Likely 188ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 189ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 190ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 191ca632f55SGrant Likely drv_data->rx += 2; 192ca632f55SGrant Likely } 193ca632f55SGrant Likely 194ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 195ca632f55SGrant Likely } 196ca632f55SGrant Likely 197ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 198ca632f55SGrant Likely { 199ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 200ca632f55SGrant Likely 201ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 202ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 203ca632f55SGrant Likely return 0; 204ca632f55SGrant Likely 205ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 206ca632f55SGrant Likely drv_data->tx += 4; 207ca632f55SGrant Likely 208ca632f55SGrant Likely return 1; 209ca632f55SGrant Likely } 210ca632f55SGrant Likely 211ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 212ca632f55SGrant Likely { 213ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 214ca632f55SGrant Likely 215ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 216ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 217ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 218ca632f55SGrant Likely drv_data->rx += 4; 219ca632f55SGrant Likely } 220ca632f55SGrant Likely 221ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 222ca632f55SGrant Likely } 223ca632f55SGrant Likely 224cd7bed00SMika Westerberg void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 225ca632f55SGrant Likely { 226ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 227ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 228ca632f55SGrant Likely 229ca632f55SGrant Likely /* Move to next transfer */ 230ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 231ca632f55SGrant Likely drv_data->cur_transfer = 232ca632f55SGrant Likely list_entry(trans->transfer_list.next, 233ca632f55SGrant Likely struct spi_transfer, 234ca632f55SGrant Likely transfer_list); 235ca632f55SGrant Likely return RUNNING_STATE; 236ca632f55SGrant Likely } else 237ca632f55SGrant Likely return DONE_STATE; 238ca632f55SGrant Likely } 239ca632f55SGrant Likely 240ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 241ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 242ca632f55SGrant Likely { 243ca632f55SGrant Likely struct spi_transfer* last_transfer; 244ca632f55SGrant Likely struct spi_message *msg; 245ca632f55SGrant Likely 246ca632f55SGrant Likely msg = drv_data->cur_msg; 247ca632f55SGrant Likely drv_data->cur_msg = NULL; 248ca632f55SGrant Likely drv_data->cur_transfer = NULL; 249ca632f55SGrant Likely 250ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 251ca632f55SGrant Likely struct spi_transfer, 252ca632f55SGrant Likely transfer_list); 253ca632f55SGrant Likely 254ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 255ca632f55SGrant Likely if (last_transfer->delay_usecs) 256ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 257ca632f55SGrant Likely 258ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 259ca632f55SGrant Likely * a message with an error, or next message is for another chip 260ca632f55SGrant Likely */ 261ca632f55SGrant Likely if (!last_transfer->cs_change) 262ca632f55SGrant Likely cs_deassert(drv_data); 263ca632f55SGrant Likely else { 264ca632f55SGrant Likely struct spi_message *next_msg; 265ca632f55SGrant Likely 266ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 267ca632f55SGrant Likely * the next message is for the same chip. Don't waste 268ca632f55SGrant Likely * time with the following tests unless this was hinted. 269ca632f55SGrant Likely * 270ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 271ca632f55SGrant Likely * after calling msg->complete (below) the driver that 272ca632f55SGrant Likely * sent the current message could be unloaded, which 273ca632f55SGrant Likely * could invalidate the cs_control() callback... 274ca632f55SGrant Likely */ 275ca632f55SGrant Likely 276ca632f55SGrant Likely /* get a pointer to the next message, if any */ 2777f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 278ca632f55SGrant Likely 279ca632f55SGrant Likely /* see if the next and current messages point 280ca632f55SGrant Likely * to the same chip 281ca632f55SGrant Likely */ 282ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 283ca632f55SGrant Likely next_msg = NULL; 284ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 285ca632f55SGrant Likely cs_deassert(drv_data); 286ca632f55SGrant Likely } 287ca632f55SGrant Likely 2887f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 289ca632f55SGrant Likely drv_data->cur_chip = NULL; 290ca632f55SGrant Likely } 291ca632f55SGrant Likely 292ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 293ca632f55SGrant Likely { 294ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 295ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 296ca632f55SGrant Likely u32 sccr1_reg; 297ca632f55SGrant Likely 298ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 299ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 300ca632f55SGrant Likely sccr1_reg |= chip->threshold; 301ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 302ca632f55SGrant Likely } 303ca632f55SGrant Likely 304ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 305ca632f55SGrant Likely { 306ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 307ca632f55SGrant Likely 308ca632f55SGrant Likely /* Stop and reset SSP */ 309ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 310ca632f55SGrant Likely reset_sccr1(drv_data); 311ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 312ca632f55SGrant Likely write_SSTO(0, reg); 313cd7bed00SMika Westerberg pxa2xx_spi_flush(drv_data); 314ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 315ca632f55SGrant Likely 316ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 317ca632f55SGrant Likely 318ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 319ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 320ca632f55SGrant Likely } 321ca632f55SGrant Likely 322ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 323ca632f55SGrant Likely { 324ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 325ca632f55SGrant Likely 326ca632f55SGrant Likely /* Stop SSP */ 327ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 328ca632f55SGrant Likely reset_sccr1(drv_data); 329ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 330ca632f55SGrant Likely write_SSTO(0, reg); 331ca632f55SGrant Likely 332ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 333ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 334ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 335ca632f55SGrant Likely 336ca632f55SGrant Likely /* Transfer delays and chip select release are 337ca632f55SGrant Likely * handled in pump_transfers or giveback 338ca632f55SGrant Likely */ 339ca632f55SGrant Likely 340ca632f55SGrant Likely /* Move to next transfer */ 341cd7bed00SMika Westerberg drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 342ca632f55SGrant Likely 343ca632f55SGrant Likely /* Schedule transfer tasklet */ 344ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 345ca632f55SGrant Likely } 346ca632f55SGrant Likely 347ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 348ca632f55SGrant Likely { 349ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 350ca632f55SGrant Likely 351ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 352ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 353ca632f55SGrant Likely 354ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 355ca632f55SGrant Likely 356ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 357ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 358ca632f55SGrant Likely return IRQ_HANDLED; 359ca632f55SGrant Likely } 360ca632f55SGrant Likely 361ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 362ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 363ca632f55SGrant Likely if (drv_data->read(drv_data)) { 364ca632f55SGrant Likely int_transfer_complete(drv_data); 365ca632f55SGrant Likely return IRQ_HANDLED; 366ca632f55SGrant Likely } 367ca632f55SGrant Likely } 368ca632f55SGrant Likely 369ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 370ca632f55SGrant Likely do { 371ca632f55SGrant Likely if (drv_data->read(drv_data)) { 372ca632f55SGrant Likely int_transfer_complete(drv_data); 373ca632f55SGrant Likely return IRQ_HANDLED; 374ca632f55SGrant Likely } 375ca632f55SGrant Likely } while (drv_data->write(drv_data)); 376ca632f55SGrant Likely 377ca632f55SGrant Likely if (drv_data->read(drv_data)) { 378ca632f55SGrant Likely int_transfer_complete(drv_data); 379ca632f55SGrant Likely return IRQ_HANDLED; 380ca632f55SGrant Likely } 381ca632f55SGrant Likely 382ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 383ca632f55SGrant Likely u32 bytes_left; 384ca632f55SGrant Likely u32 sccr1_reg; 385ca632f55SGrant Likely 386ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 387ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 388ca632f55SGrant Likely 389ca632f55SGrant Likely /* 390ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 391ca632f55SGrant Likely * remaining RX bytes. 392ca632f55SGrant Likely */ 393ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 394ca632f55SGrant Likely 395ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 396ca632f55SGrant Likely 397ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 398ca632f55SGrant Likely switch (drv_data->n_bytes) { 399ca632f55SGrant Likely case 4: 400ca632f55SGrant Likely bytes_left >>= 1; 401ca632f55SGrant Likely case 2: 402ca632f55SGrant Likely bytes_left >>= 1; 403ca632f55SGrant Likely } 404ca632f55SGrant Likely 405ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 406ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 407ca632f55SGrant Likely 408ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 409ca632f55SGrant Likely } 410ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 411ca632f55SGrant Likely } 412ca632f55SGrant Likely 413ca632f55SGrant Likely /* We did something */ 414ca632f55SGrant Likely return IRQ_HANDLED; 415ca632f55SGrant Likely } 416ca632f55SGrant Likely 417ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 418ca632f55SGrant Likely { 419ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 420ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 4217d94a505SMika Westerberg u32 sccr1_reg; 422ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 423ca632f55SGrant Likely u32 status; 424ca632f55SGrant Likely 4257d94a505SMika Westerberg /* 4267d94a505SMika Westerberg * The IRQ might be shared with other peripherals so we must first 4277d94a505SMika Westerberg * check that are we RPM suspended or not. If we are we assume that 4287d94a505SMika Westerberg * the IRQ was not for us (we shouldn't be RPM suspended when the 4297d94a505SMika Westerberg * interrupt is enabled). 4307d94a505SMika Westerberg */ 4317d94a505SMika Westerberg if (pm_runtime_suspended(&drv_data->pdev->dev)) 4327d94a505SMika Westerberg return IRQ_NONE; 4337d94a505SMika Westerberg 4347d94a505SMika Westerberg sccr1_reg = read_SSCR1(reg); 435ca632f55SGrant Likely status = read_SSSR(reg); 436ca632f55SGrant Likely 437ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 438ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 439ca632f55SGrant Likely mask &= ~SSSR_TFS; 440ca632f55SGrant Likely 441ca632f55SGrant Likely if (!(status & mask)) 442ca632f55SGrant Likely return IRQ_NONE; 443ca632f55SGrant Likely 444ca632f55SGrant Likely if (!drv_data->cur_msg) { 445ca632f55SGrant Likely 446ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 447ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 448ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 449ca632f55SGrant Likely write_SSTO(0, reg); 450ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 451ca632f55SGrant Likely 452ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "bad message state " 453ca632f55SGrant Likely "in interrupt handler\n"); 454ca632f55SGrant Likely 455ca632f55SGrant Likely /* Never fail */ 456ca632f55SGrant Likely return IRQ_HANDLED; 457ca632f55SGrant Likely } 458ca632f55SGrant Likely 459ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 460ca632f55SGrant Likely } 461ca632f55SGrant Likely 4623343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 463ca632f55SGrant Likely { 4643343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 4653343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 4663343b7a6SMika Westerberg 4673343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 468ca632f55SGrant Likely 469ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 470ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 471ca632f55SGrant Likely else 472ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 473ca632f55SGrant Likely } 474ca632f55SGrant Likely 475ca632f55SGrant Likely static void pump_transfers(unsigned long data) 476ca632f55SGrant Likely { 477ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 478ca632f55SGrant Likely struct spi_message *message = NULL; 479ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 480ca632f55SGrant Likely struct spi_transfer *previous = NULL; 481ca632f55SGrant Likely struct chip_data *chip = NULL; 482ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 483ca632f55SGrant Likely u32 clk_div = 0; 484ca632f55SGrant Likely u8 bits = 0; 485ca632f55SGrant Likely u32 speed = 0; 486ca632f55SGrant Likely u32 cr0; 487ca632f55SGrant Likely u32 cr1; 488ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 489ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 490ca632f55SGrant Likely 491ca632f55SGrant Likely /* Get current state information */ 492ca632f55SGrant Likely message = drv_data->cur_msg; 493ca632f55SGrant Likely transfer = drv_data->cur_transfer; 494ca632f55SGrant Likely chip = drv_data->cur_chip; 495ca632f55SGrant Likely 496ca632f55SGrant Likely /* Handle for abort */ 497ca632f55SGrant Likely if (message->state == ERROR_STATE) { 498ca632f55SGrant Likely message->status = -EIO; 499ca632f55SGrant Likely giveback(drv_data); 500ca632f55SGrant Likely return; 501ca632f55SGrant Likely } 502ca632f55SGrant Likely 503ca632f55SGrant Likely /* Handle end of message */ 504ca632f55SGrant Likely if (message->state == DONE_STATE) { 505ca632f55SGrant Likely message->status = 0; 506ca632f55SGrant Likely giveback(drv_data); 507ca632f55SGrant Likely return; 508ca632f55SGrant Likely } 509ca632f55SGrant Likely 510ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 511ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 512ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 513ca632f55SGrant Likely struct spi_transfer, 514ca632f55SGrant Likely transfer_list); 515ca632f55SGrant Likely if (previous->delay_usecs) 516ca632f55SGrant Likely udelay(previous->delay_usecs); 517ca632f55SGrant Likely 518ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 519ca632f55SGrant Likely if (previous->cs_change) 520ca632f55SGrant Likely cs_deassert(drv_data); 521ca632f55SGrant Likely } 522ca632f55SGrant Likely 523cd7bed00SMika Westerberg /* Check if we can DMA this transfer */ 524cd7bed00SMika Westerberg if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 525ca632f55SGrant Likely 526ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 527ca632f55SGrant Likely if (message->is_dma_mapped 528ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 529ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 530ca632f55SGrant Likely "pump_transfers: mapped transfer length " 531ca632f55SGrant Likely "of %u is greater than %d\n", 532ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 533ca632f55SGrant Likely message->status = -EINVAL; 534ca632f55SGrant Likely giveback(drv_data); 535ca632f55SGrant Likely return; 536ca632f55SGrant Likely } 537ca632f55SGrant Likely 538ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 539ca632f55SGrant Likely if (printk_ratelimit()) 540ca632f55SGrant Likely dev_warn(&message->spi->dev, "pump_transfers: " 541ca632f55SGrant Likely "DMA disabled for transfer length %ld " 542ca632f55SGrant Likely "greater than %d\n", 543ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 544ca632f55SGrant Likely } 545ca632f55SGrant Likely 546ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 547cd7bed00SMika Westerberg if (pxa2xx_spi_flush(drv_data) == 0) { 548ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 549ca632f55SGrant Likely message->status = -EIO; 550ca632f55SGrant Likely giveback(drv_data); 551ca632f55SGrant Likely return; 552ca632f55SGrant Likely } 553ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 554ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 555ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 556ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 557ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 558ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 559ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 560cd7bed00SMika Westerberg drv_data->len = transfer->len; 561ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 562ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 563ca632f55SGrant Likely 564ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 565ca632f55SGrant Likely cr0 = chip->cr0; 566ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 567ca632f55SGrant Likely 568ca632f55SGrant Likely bits = chip->bits_per_word; 569ca632f55SGrant Likely speed = chip->speed_hz; 570ca632f55SGrant Likely 571ca632f55SGrant Likely if (transfer->speed_hz) 572ca632f55SGrant Likely speed = transfer->speed_hz; 573ca632f55SGrant Likely 574ca632f55SGrant Likely if (transfer->bits_per_word) 575ca632f55SGrant Likely bits = transfer->bits_per_word; 576ca632f55SGrant Likely 5773343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, speed); 578ca632f55SGrant Likely 579ca632f55SGrant Likely if (bits <= 8) { 580ca632f55SGrant Likely drv_data->n_bytes = 1; 581ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 582ca632f55SGrant Likely u8_reader : null_reader; 583ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 584ca632f55SGrant Likely u8_writer : null_writer; 585ca632f55SGrant Likely } else if (bits <= 16) { 586ca632f55SGrant Likely drv_data->n_bytes = 2; 587ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 588ca632f55SGrant Likely u16_reader : null_reader; 589ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 590ca632f55SGrant Likely u16_writer : null_writer; 591ca632f55SGrant Likely } else if (bits <= 32) { 592ca632f55SGrant Likely drv_data->n_bytes = 4; 593ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 594ca632f55SGrant Likely u32_reader : null_reader; 595ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 596ca632f55SGrant Likely u32_writer : null_writer; 597ca632f55SGrant Likely } 598ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 599ca632f55SGrant Likely * thresholds and burst also */ 600ca632f55SGrant Likely if (chip->enable_dma) { 601cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 602cd7bed00SMika Westerberg message->spi, 603ca632f55SGrant Likely bits, &dma_burst, 604ca632f55SGrant Likely &dma_thresh)) 605ca632f55SGrant Likely if (printk_ratelimit()) 606ca632f55SGrant Likely dev_warn(&message->spi->dev, 607ca632f55SGrant Likely "pump_transfers: " 608ca632f55SGrant Likely "DMA burst size reduced to " 609ca632f55SGrant Likely "match bits_per_word\n"); 610ca632f55SGrant Likely } 611ca632f55SGrant Likely 612ca632f55SGrant Likely cr0 = clk_div 613ca632f55SGrant Likely | SSCR0_Motorola 614ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 615ca632f55SGrant Likely | SSCR0_SSE 616ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 617ca632f55SGrant Likely } 618ca632f55SGrant Likely 619ca632f55SGrant Likely message->state = RUNNING_STATE; 620ca632f55SGrant Likely 621ca632f55SGrant Likely drv_data->dma_mapped = 0; 622cd7bed00SMika Westerberg if (pxa2xx_spi_dma_is_possible(drv_data->len)) 623cd7bed00SMika Westerberg drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 624ca632f55SGrant Likely if (drv_data->dma_mapped) { 625ca632f55SGrant Likely 626ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 627cd7bed00SMika Westerberg drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 628ca632f55SGrant Likely 629cd7bed00SMika Westerberg pxa2xx_spi_dma_prepare(drv_data, dma_burst); 630ca632f55SGrant Likely 631ca632f55SGrant Likely /* Clear status and start DMA engine */ 632ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 633ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 634cd7bed00SMika Westerberg 635cd7bed00SMika Westerberg pxa2xx_spi_dma_start(drv_data); 636ca632f55SGrant Likely } else { 637ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 638ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 639ca632f55SGrant Likely 640ca632f55SGrant Likely /* Clear status */ 641ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 642ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 643ca632f55SGrant Likely } 644ca632f55SGrant Likely 645ca632f55SGrant Likely /* see if we need to reload the config registers */ 646ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 647ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 648ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 649ca632f55SGrant Likely 650ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 651ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 652ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 653ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 654ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 655ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 656ca632f55SGrant Likely /* restart the SSP */ 657ca632f55SGrant Likely write_SSCR0(cr0, reg); 658ca632f55SGrant Likely 659ca632f55SGrant Likely } else { 660ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 661ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 662ca632f55SGrant Likely } 663ca632f55SGrant Likely 664ca632f55SGrant Likely cs_assert(drv_data); 665ca632f55SGrant Likely 666ca632f55SGrant Likely /* after chip select, release the data by enabling service 667ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 668ca632f55SGrant Likely write_SSCR1(cr1, reg); 669ca632f55SGrant Likely } 670ca632f55SGrant Likely 6717f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 6727f86bde9SMika Westerberg struct spi_message *msg) 673ca632f55SGrant Likely { 6747f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 675ca632f55SGrant Likely 6767f86bde9SMika Westerberg drv_data->cur_msg = msg; 677ca632f55SGrant Likely /* Initial message state*/ 678ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 679ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 680ca632f55SGrant Likely struct spi_transfer, 681ca632f55SGrant Likely transfer_list); 682ca632f55SGrant Likely 683ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 684ca632f55SGrant Likely * chip configuration */ 685ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 686ca632f55SGrant Likely 687ca632f55SGrant Likely /* Mark as busy and launch transfers */ 688ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 689ca632f55SGrant Likely return 0; 690ca632f55SGrant Likely } 691ca632f55SGrant Likely 6927d94a505SMika Westerberg static int pxa2xx_spi_prepare_transfer(struct spi_master *master) 6937d94a505SMika Westerberg { 6947d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 6957d94a505SMika Westerberg 6967d94a505SMika Westerberg pm_runtime_get_sync(&drv_data->pdev->dev); 6977d94a505SMika Westerberg return 0; 6987d94a505SMika Westerberg } 6997d94a505SMika Westerberg 7007d94a505SMika Westerberg static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 7017d94a505SMika Westerberg { 7027d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 7037d94a505SMika Westerberg 7047d94a505SMika Westerberg /* Disable the SSP now */ 7057d94a505SMika Westerberg write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, 7067d94a505SMika Westerberg drv_data->ioaddr); 7077d94a505SMika Westerberg 7087d94a505SMika Westerberg pm_runtime_mark_last_busy(&drv_data->pdev->dev); 7097d94a505SMika Westerberg pm_runtime_put_autosuspend(&drv_data->pdev->dev); 7107d94a505SMika Westerberg return 0; 7117d94a505SMika Westerberg } 7127d94a505SMika Westerberg 713ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 714ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 715ca632f55SGrant Likely { 716ca632f55SGrant Likely int err = 0; 717ca632f55SGrant Likely 718ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 719ca632f55SGrant Likely return 0; 720ca632f55SGrant Likely 721ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 722ca632f55SGrant Likely * different chip_info, release previously requested GPIO 723ca632f55SGrant Likely */ 724ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 725ca632f55SGrant Likely gpio_free(chip->gpio_cs); 726ca632f55SGrant Likely 727ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 728ca632f55SGrant Likely if (chip_info->cs_control) { 729ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 730ca632f55SGrant Likely return 0; 731ca632f55SGrant Likely } 732ca632f55SGrant Likely 733ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 734ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 735ca632f55SGrant Likely if (err) { 736ca632f55SGrant Likely dev_err(&spi->dev, "failed to request chip select " 737ca632f55SGrant Likely "GPIO%d\n", chip_info->gpio_cs); 738ca632f55SGrant Likely return err; 739ca632f55SGrant Likely } 740ca632f55SGrant Likely 741ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 742ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 743ca632f55SGrant Likely 744ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 745ca632f55SGrant Likely !chip->gpio_cs_inverted); 746ca632f55SGrant Likely } 747ca632f55SGrant Likely 748ca632f55SGrant Likely return err; 749ca632f55SGrant Likely } 750ca632f55SGrant Likely 751ca632f55SGrant Likely static int setup(struct spi_device *spi) 752ca632f55SGrant Likely { 753ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 754ca632f55SGrant Likely struct chip_data *chip; 755ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 756ca632f55SGrant Likely unsigned int clk_div; 757ca632f55SGrant Likely uint tx_thres = TX_THRESH_DFLT; 758ca632f55SGrant Likely uint rx_thres = RX_THRESH_DFLT; 759ca632f55SGrant Likely 760ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data) 761ca632f55SGrant Likely && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { 762ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 763ca632f55SGrant Likely "b/w not 4-32 for type non-PXA25x_SSP\n", 764ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 765ca632f55SGrant Likely return -EINVAL; 766ca632f55SGrant Likely } else if (pxa25x_ssp_comp(drv_data) 767ca632f55SGrant Likely && (spi->bits_per_word < 4 768ca632f55SGrant Likely || spi->bits_per_word > 16)) { 769ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 770ca632f55SGrant Likely "b/w not 4-16 for type PXA25x_SSP\n", 771ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 772ca632f55SGrant Likely return -EINVAL; 773ca632f55SGrant Likely } 774ca632f55SGrant Likely 775ca632f55SGrant Likely /* Only alloc on first setup */ 776ca632f55SGrant Likely chip = spi_get_ctldata(spi); 777ca632f55SGrant Likely if (!chip) { 778ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 779ca632f55SGrant Likely if (!chip) { 780ca632f55SGrant Likely dev_err(&spi->dev, 781ca632f55SGrant Likely "failed setup: can't allocate chip data\n"); 782ca632f55SGrant Likely return -ENOMEM; 783ca632f55SGrant Likely } 784ca632f55SGrant Likely 785ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 786ca632f55SGrant Likely if (spi->chip_select > 4) { 787ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: " 788ca632f55SGrant Likely "cs number must not be > 4.\n"); 789ca632f55SGrant Likely kfree(chip); 790ca632f55SGrant Likely return -EINVAL; 791ca632f55SGrant Likely } 792ca632f55SGrant Likely 793ca632f55SGrant Likely chip->frm = spi->chip_select; 794ca632f55SGrant Likely } else 795ca632f55SGrant Likely chip->gpio_cs = -1; 796ca632f55SGrant Likely chip->enable_dma = 0; 797ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 798ca632f55SGrant Likely } 799ca632f55SGrant Likely 800ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 801ca632f55SGrant Likely * if chip_info exists, use it */ 802ca632f55SGrant Likely chip_info = spi->controller_data; 803ca632f55SGrant Likely 804ca632f55SGrant Likely /* chip_info isn't always needed */ 805ca632f55SGrant Likely chip->cr1 = 0; 806ca632f55SGrant Likely if (chip_info) { 807ca632f55SGrant Likely if (chip_info->timeout) 808ca632f55SGrant Likely chip->timeout = chip_info->timeout; 809ca632f55SGrant Likely if (chip_info->tx_threshold) 810ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 811ca632f55SGrant Likely if (chip_info->rx_threshold) 812ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 813ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 814ca632f55SGrant Likely chip->dma_threshold = 0; 815ca632f55SGrant Likely if (chip_info->enable_loopback) 816ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 817ca632f55SGrant Likely } 818ca632f55SGrant Likely 819ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 820ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 821ca632f55SGrant Likely 822ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 823ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 824ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 825ca632f55SGrant Likely if (chip->enable_dma) { 826ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 827cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 828cd7bed00SMika Westerberg spi->bits_per_word, 829ca632f55SGrant Likely &chip->dma_burst_size, 830ca632f55SGrant Likely &chip->dma_threshold)) { 831ca632f55SGrant Likely dev_warn(&spi->dev, "in setup: DMA burst size reduced " 832ca632f55SGrant Likely "to match bits_per_word\n"); 833ca632f55SGrant Likely } 834ca632f55SGrant Likely } 835ca632f55SGrant Likely 8363343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 837ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 838ca632f55SGrant Likely 839ca632f55SGrant Likely chip->cr0 = clk_div 840ca632f55SGrant Likely | SSCR0_Motorola 841ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 842ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 843ca632f55SGrant Likely | SSCR0_SSE 844ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 845ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 846ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 847ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 848ca632f55SGrant Likely 849*b833172fSMika Westerberg if (spi->mode & SPI_LOOP) 850*b833172fSMika Westerberg chip->cr1 |= SSCR1_LBM; 851*b833172fSMika Westerberg 852ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 853ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 854ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 8553343b7a6SMika Westerberg drv_data->max_clk_rate 856ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 857ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 858ca632f55SGrant Likely else 859ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 8603343b7a6SMika Westerberg drv_data->max_clk_rate / 2 861ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 862ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 863ca632f55SGrant Likely 864ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 865ca632f55SGrant Likely chip->n_bytes = 1; 866ca632f55SGrant Likely chip->read = u8_reader; 867ca632f55SGrant Likely chip->write = u8_writer; 868ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 869ca632f55SGrant Likely chip->n_bytes = 2; 870ca632f55SGrant Likely chip->read = u16_reader; 871ca632f55SGrant Likely chip->write = u16_writer; 872ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 873ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 874ca632f55SGrant Likely chip->n_bytes = 4; 875ca632f55SGrant Likely chip->read = u32_reader; 876ca632f55SGrant Likely chip->write = u32_writer; 877ca632f55SGrant Likely } else { 878ca632f55SGrant Likely dev_err(&spi->dev, "invalid wordsize\n"); 879ca632f55SGrant Likely return -ENODEV; 880ca632f55SGrant Likely } 881ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 882ca632f55SGrant Likely 883ca632f55SGrant Likely spi_set_ctldata(spi, chip); 884ca632f55SGrant Likely 885ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 886ca632f55SGrant Likely return 0; 887ca632f55SGrant Likely 888ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 889ca632f55SGrant Likely } 890ca632f55SGrant Likely 891ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 892ca632f55SGrant Likely { 893ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 894ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 895ca632f55SGrant Likely 896ca632f55SGrant Likely if (!chip) 897ca632f55SGrant Likely return; 898ca632f55SGrant Likely 899ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 900ca632f55SGrant Likely gpio_free(chip->gpio_cs); 901ca632f55SGrant Likely 902ca632f55SGrant Likely kfree(chip); 903ca632f55SGrant Likely } 904ca632f55SGrant Likely 905fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 906ca632f55SGrant Likely { 907ca632f55SGrant Likely struct device *dev = &pdev->dev; 908ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 909ca632f55SGrant Likely struct spi_master *master; 910ca632f55SGrant Likely struct driver_data *drv_data; 911ca632f55SGrant Likely struct ssp_device *ssp; 912ca632f55SGrant Likely int status; 913ca632f55SGrant Likely 914851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 915851bacf5SMika Westerberg if (!platform_info) { 916851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 917851bacf5SMika Westerberg return -ENODEV; 918851bacf5SMika Westerberg } 919ca632f55SGrant Likely 920ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 921851bacf5SMika Westerberg if (!ssp) 922851bacf5SMika Westerberg ssp = &platform_info->ssp; 923851bacf5SMika Westerberg 924851bacf5SMika Westerberg if (!ssp->mmio_base) { 925851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 926ca632f55SGrant Likely return -ENODEV; 927ca632f55SGrant Likely } 928ca632f55SGrant Likely 929ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 930ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 931ca632f55SGrant Likely if (!master) { 932ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 933ca632f55SGrant Likely pxa_ssp_free(ssp); 934ca632f55SGrant Likely return -ENOMEM; 935ca632f55SGrant Likely } 936ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 937ca632f55SGrant Likely drv_data->master = master; 938ca632f55SGrant Likely drv_data->master_info = platform_info; 939ca632f55SGrant Likely drv_data->pdev = pdev; 940ca632f55SGrant Likely drv_data->ssp = ssp; 941ca632f55SGrant Likely 942ca632f55SGrant Likely master->dev.parent = &pdev->dev; 943ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 944ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 945*b833172fSMika Westerberg master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 946ca632f55SGrant Likely 947851bacf5SMika Westerberg master->bus_num = ssp->port_id; 948ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 949ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 950ca632f55SGrant Likely master->cleanup = cleanup; 951ca632f55SGrant Likely master->setup = setup; 9527f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 9537d94a505SMika Westerberg master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; 9547d94a505SMika Westerberg master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 955ca632f55SGrant Likely 956ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 9572b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 958ca632f55SGrant Likely 959ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 960ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 961ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 962ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 963ca632f55SGrant Likely drv_data->dma_cr1 = 0; 964ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 965ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 966ca632f55SGrant Likely } else { 967ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 9685928808eSMika Westerberg drv_data->dma_cr1 = DEFAULT_DMA_CR1; 969ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 970ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 971ca632f55SGrant Likely } 972ca632f55SGrant Likely 973ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 974ca632f55SGrant Likely drv_data); 975ca632f55SGrant Likely if (status < 0) { 976ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 977ca632f55SGrant Likely goto out_error_master_alloc; 978ca632f55SGrant Likely } 979ca632f55SGrant Likely 980ca632f55SGrant Likely /* Setup DMA if requested */ 981ca632f55SGrant Likely drv_data->tx_channel = -1; 982ca632f55SGrant Likely drv_data->rx_channel = -1; 983ca632f55SGrant Likely if (platform_info->enable_dma) { 984cd7bed00SMika Westerberg status = pxa2xx_spi_dma_setup(drv_data); 985cd7bed00SMika Westerberg if (status) { 986cd7bed00SMika Westerberg dev_warn(dev, "failed to setup DMA, using PIO\n"); 987cd7bed00SMika Westerberg platform_info->enable_dma = false; 988ca632f55SGrant Likely } 989ca632f55SGrant Likely } 990ca632f55SGrant Likely 991ca632f55SGrant Likely /* Enable SOC clock */ 9923343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 9933343b7a6SMika Westerberg 9943343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 995ca632f55SGrant Likely 996ca632f55SGrant Likely /* Load default SSP configuration */ 997ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 998ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 999ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 1000ca632f55SGrant Likely drv_data->ioaddr); 1001ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 1002ca632f55SGrant Likely | SSCR0_Motorola 1003ca632f55SGrant Likely | SSCR0_DataSize(8), 1004ca632f55SGrant Likely drv_data->ioaddr); 1005ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1006ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 1007ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 1008ca632f55SGrant Likely 10097f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 10107f86bde9SMika Westerberg (unsigned long)drv_data); 1011ca632f55SGrant Likely 1012ca632f55SGrant Likely /* Register with the SPI framework */ 1013ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1014ca632f55SGrant Likely status = spi_register_master(master); 1015ca632f55SGrant Likely if (status != 0) { 1016ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 10177f86bde9SMika Westerberg goto out_error_clock_enabled; 1018ca632f55SGrant Likely } 1019ca632f55SGrant Likely 10207d94a505SMika Westerberg pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 10217d94a505SMika Westerberg pm_runtime_use_autosuspend(&pdev->dev); 10227d94a505SMika Westerberg pm_runtime_set_active(&pdev->dev); 10237d94a505SMika Westerberg pm_runtime_enable(&pdev->dev); 10247d94a505SMika Westerberg 1025ca632f55SGrant Likely return status; 1026ca632f55SGrant Likely 1027ca632f55SGrant Likely out_error_clock_enabled: 10283343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1029cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1030ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1031ca632f55SGrant Likely 1032ca632f55SGrant Likely out_error_master_alloc: 1033ca632f55SGrant Likely spi_master_put(master); 1034ca632f55SGrant Likely pxa_ssp_free(ssp); 1035ca632f55SGrant Likely return status; 1036ca632f55SGrant Likely } 1037ca632f55SGrant Likely 1038ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1039ca632f55SGrant Likely { 1040ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1041ca632f55SGrant Likely struct ssp_device *ssp; 1042ca632f55SGrant Likely 1043ca632f55SGrant Likely if (!drv_data) 1044ca632f55SGrant Likely return 0; 1045ca632f55SGrant Likely ssp = drv_data->ssp; 1046ca632f55SGrant Likely 10477d94a505SMika Westerberg pm_runtime_get_sync(&pdev->dev); 10487d94a505SMika Westerberg 1049ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1050ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 10513343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1052ca632f55SGrant Likely 1053ca632f55SGrant Likely /* Release DMA */ 1054cd7bed00SMika Westerberg if (drv_data->master_info->enable_dma) 1055cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1056ca632f55SGrant Likely 10577d94a505SMika Westerberg pm_runtime_put_noidle(&pdev->dev); 10587d94a505SMika Westerberg pm_runtime_disable(&pdev->dev); 10597d94a505SMika Westerberg 1060ca632f55SGrant Likely /* Release IRQ */ 1061ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1062ca632f55SGrant Likely 1063ca632f55SGrant Likely /* Release SSP */ 1064ca632f55SGrant Likely pxa_ssp_free(ssp); 1065ca632f55SGrant Likely 1066ca632f55SGrant Likely /* Disconnect from the SPI framework */ 1067ca632f55SGrant Likely spi_unregister_master(drv_data->master); 1068ca632f55SGrant Likely 1069ca632f55SGrant Likely /* Prevent double remove */ 1070ca632f55SGrant Likely platform_set_drvdata(pdev, NULL); 1071ca632f55SGrant Likely 1072ca632f55SGrant Likely return 0; 1073ca632f55SGrant Likely } 1074ca632f55SGrant Likely 1075ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1076ca632f55SGrant Likely { 1077ca632f55SGrant Likely int status = 0; 1078ca632f55SGrant Likely 1079ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1080ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1081ca632f55SGrant Likely } 1082ca632f55SGrant Likely 1083ca632f55SGrant Likely #ifdef CONFIG_PM 1084ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1085ca632f55SGrant Likely { 1086ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1087ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1088ca632f55SGrant Likely int status = 0; 1089ca632f55SGrant Likely 10907f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1091ca632f55SGrant Likely if (status != 0) 1092ca632f55SGrant Likely return status; 1093ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 10943343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1095ca632f55SGrant Likely 1096ca632f55SGrant Likely return 0; 1097ca632f55SGrant Likely } 1098ca632f55SGrant Likely 1099ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1100ca632f55SGrant Likely { 1101ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1102ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1103ca632f55SGrant Likely int status = 0; 1104ca632f55SGrant Likely 1105cd7bed00SMika Westerberg pxa2xx_spi_dma_resume(drv_data); 1106ca632f55SGrant Likely 1107ca632f55SGrant Likely /* Enable the SSP clock */ 11083343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1109ca632f55SGrant Likely 1110ca632f55SGrant Likely /* Start the queue running */ 11117f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1112ca632f55SGrant Likely if (status != 0) { 1113ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1114ca632f55SGrant Likely return status; 1115ca632f55SGrant Likely } 1116ca632f55SGrant Likely 1117ca632f55SGrant Likely return 0; 1118ca632f55SGrant Likely } 11197d94a505SMika Westerberg #endif 11207d94a505SMika Westerberg 11217d94a505SMika Westerberg #ifdef CONFIG_PM_RUNTIME 11227d94a505SMika Westerberg static int pxa2xx_spi_runtime_suspend(struct device *dev) 11237d94a505SMika Westerberg { 11247d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 11257d94a505SMika Westerberg 11267d94a505SMika Westerberg clk_disable_unprepare(drv_data->ssp->clk); 11277d94a505SMika Westerberg return 0; 11287d94a505SMika Westerberg } 11297d94a505SMika Westerberg 11307d94a505SMika Westerberg static int pxa2xx_spi_runtime_resume(struct device *dev) 11317d94a505SMika Westerberg { 11327d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 11337d94a505SMika Westerberg 11347d94a505SMika Westerberg clk_prepare_enable(drv_data->ssp->clk); 11357d94a505SMika Westerberg return 0; 11367d94a505SMika Westerberg } 11377d94a505SMika Westerberg #endif 1138ca632f55SGrant Likely 1139ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 11407d94a505SMika Westerberg SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 11417d94a505SMika Westerberg SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 11427d94a505SMika Westerberg pxa2xx_spi_runtime_resume, NULL) 1143ca632f55SGrant Likely }; 1144ca632f55SGrant Likely 1145ca632f55SGrant Likely static struct platform_driver driver = { 1146ca632f55SGrant Likely .driver = { 1147ca632f55SGrant Likely .name = "pxa2xx-spi", 1148ca632f55SGrant Likely .owner = THIS_MODULE, 1149ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1150ca632f55SGrant Likely }, 1151ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1152ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1153ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1154ca632f55SGrant Likely }; 1155ca632f55SGrant Likely 1156ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1157ca632f55SGrant Likely { 1158ca632f55SGrant Likely return platform_driver_register(&driver); 1159ca632f55SGrant Likely } 1160ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1161ca632f55SGrant Likely 1162ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1163ca632f55SGrant Likely { 1164ca632f55SGrant Likely platform_driver_unregister(&driver); 1165ca632f55SGrant Likely } 1166ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1167