1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 5ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 6ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 7ca632f55SGrant Likely * (at your option) any later version. 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 10ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 11ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12ca632f55SGrant Likely * GNU General Public License for more details. 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 15ca632f55SGrant Likely * along with this program; if not, write to the Free Software 16ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17ca632f55SGrant Likely */ 18ca632f55SGrant Likely 19ca632f55SGrant Likely #include <linux/init.h> 20ca632f55SGrant Likely #include <linux/module.h> 21ca632f55SGrant Likely #include <linux/device.h> 22ca632f55SGrant Likely #include <linux/ioport.h> 23ca632f55SGrant Likely #include <linux/errno.h> 24ca632f55SGrant Likely #include <linux/interrupt.h> 25ca632f55SGrant Likely #include <linux/platform_device.h> 26ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 27ca632f55SGrant Likely #include <linux/dma-mapping.h> 28ca632f55SGrant Likely #include <linux/spi/spi.h> 29ca632f55SGrant Likely #include <linux/workqueue.h> 30ca632f55SGrant Likely #include <linux/delay.h> 31ca632f55SGrant Likely #include <linux/gpio.h> 32ca632f55SGrant Likely #include <linux/slab.h> 33ca632f55SGrant Likely 34ca632f55SGrant Likely #include <asm/io.h> 35ca632f55SGrant Likely #include <asm/irq.h> 36ca632f55SGrant Likely #include <asm/delay.h> 37ca632f55SGrant Likely 38ca632f55SGrant Likely 39ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 40ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 41ca632f55SGrant Likely MODULE_LICENSE("GPL"); 42ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 43ca632f55SGrant Likely 44ca632f55SGrant Likely #define MAX_BUSES 3 45ca632f55SGrant Likely 46ca632f55SGrant Likely #define TIMOUT_DFLT 1000 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) 49ca632f55SGrant Likely #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) 502b9b84f4SMika Westerberg #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT) 51ca632f55SGrant Likely #define MAX_DMA_LEN 8191 52ca632f55SGrant Likely #define DMA_ALIGNMENT 8 53ca632f55SGrant Likely 54ca632f55SGrant Likely /* 55ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 56ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 57ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 58ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 59ca632f55SGrant Likely * service and interrupt enables 60ca632f55SGrant Likely */ 61ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 62ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 63ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 64ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 65ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 66ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 67ca632f55SGrant Likely 68ca632f55SGrant Likely #define DEFINE_SSP_REG(reg, off) \ 69ca632f55SGrant Likely static inline u32 read_##reg(void const __iomem *p) \ 70ca632f55SGrant Likely { return __raw_readl(p + (off)); } \ 71ca632f55SGrant Likely \ 72ca632f55SGrant Likely static inline void write_##reg(u32 v, void __iomem *p) \ 73ca632f55SGrant Likely { __raw_writel(v, p + (off)); } 74ca632f55SGrant Likely 75ca632f55SGrant Likely DEFINE_SSP_REG(SSCR0, 0x00) 76ca632f55SGrant Likely DEFINE_SSP_REG(SSCR1, 0x04) 77ca632f55SGrant Likely DEFINE_SSP_REG(SSSR, 0x08) 78ca632f55SGrant Likely DEFINE_SSP_REG(SSITR, 0x0c) 79ca632f55SGrant Likely DEFINE_SSP_REG(SSDR, 0x10) 80ca632f55SGrant Likely DEFINE_SSP_REG(SSTO, 0x28) 81ca632f55SGrant Likely DEFINE_SSP_REG(SSPSP, 0x2c) 82ca632f55SGrant Likely 83ca632f55SGrant Likely #define START_STATE ((void*)0) 84ca632f55SGrant Likely #define RUNNING_STATE ((void*)1) 85ca632f55SGrant Likely #define DONE_STATE ((void*)2) 86ca632f55SGrant Likely #define ERROR_STATE ((void*)-1) 87ca632f55SGrant Likely 88ca632f55SGrant Likely struct driver_data { 89ca632f55SGrant Likely /* Driver model hookup */ 90ca632f55SGrant Likely struct platform_device *pdev; 91ca632f55SGrant Likely 92ca632f55SGrant Likely /* SSP Info */ 93ca632f55SGrant Likely struct ssp_device *ssp; 94ca632f55SGrant Likely 95ca632f55SGrant Likely /* SPI framework hookup */ 96ca632f55SGrant Likely enum pxa_ssp_type ssp_type; 97ca632f55SGrant Likely struct spi_master *master; 98ca632f55SGrant Likely 99ca632f55SGrant Likely /* PXA hookup */ 100ca632f55SGrant Likely struct pxa2xx_spi_master *master_info; 101ca632f55SGrant Likely 102ca632f55SGrant Likely /* DMA setup stuff */ 103ca632f55SGrant Likely int rx_channel; 104ca632f55SGrant Likely int tx_channel; 105ca632f55SGrant Likely u32 *null_dma_buf; 106ca632f55SGrant Likely 107ca632f55SGrant Likely /* SSP register addresses */ 108ca632f55SGrant Likely void __iomem *ioaddr; 109ca632f55SGrant Likely u32 ssdr_physical; 110ca632f55SGrant Likely 111ca632f55SGrant Likely /* SSP masks*/ 112ca632f55SGrant Likely u32 dma_cr1; 113ca632f55SGrant Likely u32 int_cr1; 114ca632f55SGrant Likely u32 clear_sr; 115ca632f55SGrant Likely u32 mask_sr; 116ca632f55SGrant Likely 117ca632f55SGrant Likely /* Message Transfer pump */ 118ca632f55SGrant Likely struct tasklet_struct pump_transfers; 119ca632f55SGrant Likely 120ca632f55SGrant Likely /* Current message transfer state info */ 121ca632f55SGrant Likely struct spi_message* cur_msg; 122ca632f55SGrant Likely struct spi_transfer* cur_transfer; 123ca632f55SGrant Likely struct chip_data *cur_chip; 124ca632f55SGrant Likely size_t len; 125ca632f55SGrant Likely void *tx; 126ca632f55SGrant Likely void *tx_end; 127ca632f55SGrant Likely void *rx; 128ca632f55SGrant Likely void *rx_end; 129ca632f55SGrant Likely int dma_mapped; 130ca632f55SGrant Likely dma_addr_t rx_dma; 131ca632f55SGrant Likely dma_addr_t tx_dma; 132ca632f55SGrant Likely size_t rx_map_len; 133ca632f55SGrant Likely size_t tx_map_len; 134ca632f55SGrant Likely u8 n_bytes; 135ca632f55SGrant Likely u32 dma_width; 136ca632f55SGrant Likely int (*write)(struct driver_data *drv_data); 137ca632f55SGrant Likely int (*read)(struct driver_data *drv_data); 138ca632f55SGrant Likely irqreturn_t (*transfer_handler)(struct driver_data *drv_data); 139ca632f55SGrant Likely void (*cs_control)(u32 command); 140ca632f55SGrant Likely }; 141ca632f55SGrant Likely 142ca632f55SGrant Likely struct chip_data { 143ca632f55SGrant Likely u32 cr0; 144ca632f55SGrant Likely u32 cr1; 145ca632f55SGrant Likely u32 psp; 146ca632f55SGrant Likely u32 timeout; 147ca632f55SGrant Likely u8 n_bytes; 148ca632f55SGrant Likely u32 dma_width; 149ca632f55SGrant Likely u32 dma_burst_size; 150ca632f55SGrant Likely u32 threshold; 151ca632f55SGrant Likely u32 dma_threshold; 152ca632f55SGrant Likely u8 enable_dma; 153ca632f55SGrant Likely u8 bits_per_word; 154ca632f55SGrant Likely u32 speed_hz; 155ca632f55SGrant Likely union { 156ca632f55SGrant Likely int gpio_cs; 157ca632f55SGrant Likely unsigned int frm; 158ca632f55SGrant Likely }; 159ca632f55SGrant Likely int gpio_cs_inverted; 160ca632f55SGrant Likely int (*write)(struct driver_data *drv_data); 161ca632f55SGrant Likely int (*read)(struct driver_data *drv_data); 162ca632f55SGrant Likely void (*cs_control)(u32 command); 163ca632f55SGrant Likely }; 164ca632f55SGrant Likely 165ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 166ca632f55SGrant Likely { 167ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 168ca632f55SGrant Likely 169ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 170ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 171ca632f55SGrant Likely return; 172ca632f55SGrant Likely } 173ca632f55SGrant Likely 174ca632f55SGrant Likely if (chip->cs_control) { 175ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 176ca632f55SGrant Likely return; 177ca632f55SGrant Likely } 178ca632f55SGrant Likely 179ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 180ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 181ca632f55SGrant Likely } 182ca632f55SGrant Likely 183ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 184ca632f55SGrant Likely { 185ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 186ca632f55SGrant Likely 187ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 188ca632f55SGrant Likely return; 189ca632f55SGrant Likely 190ca632f55SGrant Likely if (chip->cs_control) { 191ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 192ca632f55SGrant Likely return; 193ca632f55SGrant Likely } 194ca632f55SGrant Likely 195ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 196ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 197ca632f55SGrant Likely } 198ca632f55SGrant Likely 199ca632f55SGrant Likely static void write_SSSR_CS(struct driver_data *drv_data, u32 val) 200ca632f55SGrant Likely { 201ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 202ca632f55SGrant Likely 203ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 204ca632f55SGrant Likely val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; 205ca632f55SGrant Likely 206ca632f55SGrant Likely write_SSSR(val, reg); 207ca632f55SGrant Likely } 208ca632f55SGrant Likely 209ca632f55SGrant Likely static int pxa25x_ssp_comp(struct driver_data *drv_data) 210ca632f55SGrant Likely { 211ca632f55SGrant Likely if (drv_data->ssp_type == PXA25x_SSP) 212ca632f55SGrant Likely return 1; 213ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 214ca632f55SGrant Likely return 1; 215ca632f55SGrant Likely return 0; 216ca632f55SGrant Likely } 217ca632f55SGrant Likely 218ca632f55SGrant Likely static int flush(struct driver_data *drv_data) 219ca632f55SGrant Likely { 220ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 221ca632f55SGrant Likely 222ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 223ca632f55SGrant Likely 224ca632f55SGrant Likely do { 225ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 226ca632f55SGrant Likely read_SSDR(reg); 227ca632f55SGrant Likely } 228ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 229ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 230ca632f55SGrant Likely 231ca632f55SGrant Likely return limit; 232ca632f55SGrant Likely } 233ca632f55SGrant Likely 234ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 235ca632f55SGrant Likely { 236ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 237ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 238ca632f55SGrant Likely 239ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 240ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 241ca632f55SGrant Likely return 0; 242ca632f55SGrant Likely 243ca632f55SGrant Likely write_SSDR(0, reg); 244ca632f55SGrant Likely drv_data->tx += n_bytes; 245ca632f55SGrant Likely 246ca632f55SGrant Likely return 1; 247ca632f55SGrant Likely } 248ca632f55SGrant Likely 249ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 250ca632f55SGrant Likely { 251ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 252ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 253ca632f55SGrant Likely 254ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 255ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 256ca632f55SGrant Likely read_SSDR(reg); 257ca632f55SGrant Likely drv_data->rx += n_bytes; 258ca632f55SGrant Likely } 259ca632f55SGrant Likely 260ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 261ca632f55SGrant Likely } 262ca632f55SGrant Likely 263ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 264ca632f55SGrant Likely { 265ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 266ca632f55SGrant Likely 267ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 268ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 269ca632f55SGrant Likely return 0; 270ca632f55SGrant Likely 271ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 272ca632f55SGrant Likely ++drv_data->tx; 273ca632f55SGrant Likely 274ca632f55SGrant Likely return 1; 275ca632f55SGrant Likely } 276ca632f55SGrant Likely 277ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 278ca632f55SGrant Likely { 279ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 280ca632f55SGrant Likely 281ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 282ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 283ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 284ca632f55SGrant Likely ++drv_data->rx; 285ca632f55SGrant Likely } 286ca632f55SGrant Likely 287ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 288ca632f55SGrant Likely } 289ca632f55SGrant Likely 290ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 291ca632f55SGrant Likely { 292ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 293ca632f55SGrant Likely 294ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 295ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 296ca632f55SGrant Likely return 0; 297ca632f55SGrant Likely 298ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 299ca632f55SGrant Likely drv_data->tx += 2; 300ca632f55SGrant Likely 301ca632f55SGrant Likely return 1; 302ca632f55SGrant Likely } 303ca632f55SGrant Likely 304ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 305ca632f55SGrant Likely { 306ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 307ca632f55SGrant Likely 308ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 309ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 310ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 311ca632f55SGrant Likely drv_data->rx += 2; 312ca632f55SGrant Likely } 313ca632f55SGrant Likely 314ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 315ca632f55SGrant Likely } 316ca632f55SGrant Likely 317ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 318ca632f55SGrant Likely { 319ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 320ca632f55SGrant Likely 321ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 322ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 323ca632f55SGrant Likely return 0; 324ca632f55SGrant Likely 325ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 326ca632f55SGrant Likely drv_data->tx += 4; 327ca632f55SGrant Likely 328ca632f55SGrant Likely return 1; 329ca632f55SGrant Likely } 330ca632f55SGrant Likely 331ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 332ca632f55SGrant Likely { 333ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 334ca632f55SGrant Likely 335ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 336ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 337ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 338ca632f55SGrant Likely drv_data->rx += 4; 339ca632f55SGrant Likely } 340ca632f55SGrant Likely 341ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 342ca632f55SGrant Likely } 343ca632f55SGrant Likely 344ca632f55SGrant Likely static void *next_transfer(struct driver_data *drv_data) 345ca632f55SGrant Likely { 346ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 347ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 348ca632f55SGrant Likely 349ca632f55SGrant Likely /* Move to next transfer */ 350ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 351ca632f55SGrant Likely drv_data->cur_transfer = 352ca632f55SGrant Likely list_entry(trans->transfer_list.next, 353ca632f55SGrant Likely struct spi_transfer, 354ca632f55SGrant Likely transfer_list); 355ca632f55SGrant Likely return RUNNING_STATE; 356ca632f55SGrant Likely } else 357ca632f55SGrant Likely return DONE_STATE; 358ca632f55SGrant Likely } 359ca632f55SGrant Likely 360ca632f55SGrant Likely static int map_dma_buffers(struct driver_data *drv_data) 361ca632f55SGrant Likely { 362ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 363ca632f55SGrant Likely struct device *dev = &msg->spi->dev; 364ca632f55SGrant Likely 365ca632f55SGrant Likely if (!drv_data->cur_chip->enable_dma) 366ca632f55SGrant Likely return 0; 367ca632f55SGrant Likely 368ca632f55SGrant Likely if (msg->is_dma_mapped) 369ca632f55SGrant Likely return drv_data->rx_dma && drv_data->tx_dma; 370ca632f55SGrant Likely 371ca632f55SGrant Likely if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) 372ca632f55SGrant Likely return 0; 373ca632f55SGrant Likely 374ca632f55SGrant Likely /* Modify setup if rx buffer is null */ 375ca632f55SGrant Likely if (drv_data->rx == NULL) { 376ca632f55SGrant Likely *drv_data->null_dma_buf = 0; 377ca632f55SGrant Likely drv_data->rx = drv_data->null_dma_buf; 378ca632f55SGrant Likely drv_data->rx_map_len = 4; 379ca632f55SGrant Likely } else 380ca632f55SGrant Likely drv_data->rx_map_len = drv_data->len; 381ca632f55SGrant Likely 382ca632f55SGrant Likely 383ca632f55SGrant Likely /* Modify setup if tx buffer is null */ 384ca632f55SGrant Likely if (drv_data->tx == NULL) { 385ca632f55SGrant Likely *drv_data->null_dma_buf = 0; 386ca632f55SGrant Likely drv_data->tx = drv_data->null_dma_buf; 387ca632f55SGrant Likely drv_data->tx_map_len = 4; 388ca632f55SGrant Likely } else 389ca632f55SGrant Likely drv_data->tx_map_len = drv_data->len; 390ca632f55SGrant Likely 391ca632f55SGrant Likely /* Stream map the tx buffer. Always do DMA_TO_DEVICE first 392ca632f55SGrant Likely * so we flush the cache *before* invalidating it, in case 393ca632f55SGrant Likely * the tx and rx buffers overlap. 394ca632f55SGrant Likely */ 395ca632f55SGrant Likely drv_data->tx_dma = dma_map_single(dev, drv_data->tx, 396ca632f55SGrant Likely drv_data->tx_map_len, DMA_TO_DEVICE); 397ca632f55SGrant Likely if (dma_mapping_error(dev, drv_data->tx_dma)) 398ca632f55SGrant Likely return 0; 399ca632f55SGrant Likely 400ca632f55SGrant Likely /* Stream map the rx buffer */ 401ca632f55SGrant Likely drv_data->rx_dma = dma_map_single(dev, drv_data->rx, 402ca632f55SGrant Likely drv_data->rx_map_len, DMA_FROM_DEVICE); 403ca632f55SGrant Likely if (dma_mapping_error(dev, drv_data->rx_dma)) { 404ca632f55SGrant Likely dma_unmap_single(dev, drv_data->tx_dma, 405ca632f55SGrant Likely drv_data->tx_map_len, DMA_TO_DEVICE); 406ca632f55SGrant Likely return 0; 407ca632f55SGrant Likely } 408ca632f55SGrant Likely 409ca632f55SGrant Likely return 1; 410ca632f55SGrant Likely } 411ca632f55SGrant Likely 412ca632f55SGrant Likely static void unmap_dma_buffers(struct driver_data *drv_data) 413ca632f55SGrant Likely { 414ca632f55SGrant Likely struct device *dev; 415ca632f55SGrant Likely 416ca632f55SGrant Likely if (!drv_data->dma_mapped) 417ca632f55SGrant Likely return; 418ca632f55SGrant Likely 419ca632f55SGrant Likely if (!drv_data->cur_msg->is_dma_mapped) { 420ca632f55SGrant Likely dev = &drv_data->cur_msg->spi->dev; 421ca632f55SGrant Likely dma_unmap_single(dev, drv_data->rx_dma, 422ca632f55SGrant Likely drv_data->rx_map_len, DMA_FROM_DEVICE); 423ca632f55SGrant Likely dma_unmap_single(dev, drv_data->tx_dma, 424ca632f55SGrant Likely drv_data->tx_map_len, DMA_TO_DEVICE); 425ca632f55SGrant Likely } 426ca632f55SGrant Likely 427ca632f55SGrant Likely drv_data->dma_mapped = 0; 428ca632f55SGrant Likely } 429ca632f55SGrant Likely 430ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 431ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 432ca632f55SGrant Likely { 433ca632f55SGrant Likely struct spi_transfer* last_transfer; 434ca632f55SGrant Likely struct spi_message *msg; 435ca632f55SGrant Likely 436ca632f55SGrant Likely msg = drv_data->cur_msg; 437ca632f55SGrant Likely drv_data->cur_msg = NULL; 438ca632f55SGrant Likely drv_data->cur_transfer = NULL; 439ca632f55SGrant Likely 440ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 441ca632f55SGrant Likely struct spi_transfer, 442ca632f55SGrant Likely transfer_list); 443ca632f55SGrant Likely 444ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 445ca632f55SGrant Likely if (last_transfer->delay_usecs) 446ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 447ca632f55SGrant Likely 448ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 449ca632f55SGrant Likely * a message with an error, or next message is for another chip 450ca632f55SGrant Likely */ 451ca632f55SGrant Likely if (!last_transfer->cs_change) 452ca632f55SGrant Likely cs_deassert(drv_data); 453ca632f55SGrant Likely else { 454ca632f55SGrant Likely struct spi_message *next_msg; 455ca632f55SGrant Likely 456ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 457ca632f55SGrant Likely * the next message is for the same chip. Don't waste 458ca632f55SGrant Likely * time with the following tests unless this was hinted. 459ca632f55SGrant Likely * 460ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 461ca632f55SGrant Likely * after calling msg->complete (below) the driver that 462ca632f55SGrant Likely * sent the current message could be unloaded, which 463ca632f55SGrant Likely * could invalidate the cs_control() callback... 464ca632f55SGrant Likely */ 465ca632f55SGrant Likely 466ca632f55SGrant Likely /* get a pointer to the next message, if any */ 467*7f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 468ca632f55SGrant Likely 469ca632f55SGrant Likely /* see if the next and current messages point 470ca632f55SGrant Likely * to the same chip 471ca632f55SGrant Likely */ 472ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 473ca632f55SGrant Likely next_msg = NULL; 474ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 475ca632f55SGrant Likely cs_deassert(drv_data); 476ca632f55SGrant Likely } 477ca632f55SGrant Likely 478*7f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 479ca632f55SGrant Likely drv_data->cur_chip = NULL; 480ca632f55SGrant Likely } 481ca632f55SGrant Likely 482ca632f55SGrant Likely static int wait_ssp_rx_stall(void const __iomem *ioaddr) 483ca632f55SGrant Likely { 484ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 485ca632f55SGrant Likely 486ca632f55SGrant Likely while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) 487ca632f55SGrant Likely cpu_relax(); 488ca632f55SGrant Likely 489ca632f55SGrant Likely return limit; 490ca632f55SGrant Likely } 491ca632f55SGrant Likely 492ca632f55SGrant Likely static int wait_dma_channel_stop(int channel) 493ca632f55SGrant Likely { 494ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 495ca632f55SGrant Likely 496ca632f55SGrant Likely while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) 497ca632f55SGrant Likely cpu_relax(); 498ca632f55SGrant Likely 499ca632f55SGrant Likely return limit; 500ca632f55SGrant Likely } 501ca632f55SGrant Likely 502ca632f55SGrant Likely static void dma_error_stop(struct driver_data *drv_data, const char *msg) 503ca632f55SGrant Likely { 504ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 505ca632f55SGrant Likely 506ca632f55SGrant Likely /* Stop and reset */ 507ca632f55SGrant Likely DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 508ca632f55SGrant Likely DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 509ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 510ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 511ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 512ca632f55SGrant Likely write_SSTO(0, reg); 513ca632f55SGrant Likely flush(drv_data); 514ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 515ca632f55SGrant Likely 516ca632f55SGrant Likely unmap_dma_buffers(drv_data); 517ca632f55SGrant Likely 518ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 519ca632f55SGrant Likely 520ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 521ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 522ca632f55SGrant Likely } 523ca632f55SGrant Likely 524ca632f55SGrant Likely static void dma_transfer_complete(struct driver_data *drv_data) 525ca632f55SGrant Likely { 526ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 527ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 528ca632f55SGrant Likely 529ca632f55SGrant Likely /* Clear and disable interrupts on SSP and DMA channels*/ 530ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 531ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 532ca632f55SGrant Likely DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 533ca632f55SGrant Likely DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 534ca632f55SGrant Likely 535ca632f55SGrant Likely if (wait_dma_channel_stop(drv_data->rx_channel) == 0) 536ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 537ca632f55SGrant Likely "dma_handler: dma rx channel stop failed\n"); 538ca632f55SGrant Likely 539ca632f55SGrant Likely if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) 540ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 541ca632f55SGrant Likely "dma_transfer: ssp rx stall failed\n"); 542ca632f55SGrant Likely 543ca632f55SGrant Likely unmap_dma_buffers(drv_data); 544ca632f55SGrant Likely 545ca632f55SGrant Likely /* update the buffer pointer for the amount completed in dma */ 546ca632f55SGrant Likely drv_data->rx += drv_data->len - 547ca632f55SGrant Likely (DCMD(drv_data->rx_channel) & DCMD_LENGTH); 548ca632f55SGrant Likely 549ca632f55SGrant Likely /* read trailing data from fifo, it does not matter how many 550ca632f55SGrant Likely * bytes are in the fifo just read until buffer is full 551ca632f55SGrant Likely * or fifo is empty, which ever occurs first */ 552ca632f55SGrant Likely drv_data->read(drv_data); 553ca632f55SGrant Likely 554ca632f55SGrant Likely /* return count of what was actually read */ 555ca632f55SGrant Likely msg->actual_length += drv_data->len - 556ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 557ca632f55SGrant Likely 558ca632f55SGrant Likely /* Transfer delays and chip select release are 559ca632f55SGrant Likely * handled in pump_transfers or giveback 560ca632f55SGrant Likely */ 561ca632f55SGrant Likely 562ca632f55SGrant Likely /* Move to next transfer */ 563ca632f55SGrant Likely msg->state = next_transfer(drv_data); 564ca632f55SGrant Likely 565ca632f55SGrant Likely /* Schedule transfer tasklet */ 566ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 567ca632f55SGrant Likely } 568ca632f55SGrant Likely 569ca632f55SGrant Likely static void dma_handler(int channel, void *data) 570ca632f55SGrant Likely { 571ca632f55SGrant Likely struct driver_data *drv_data = data; 572ca632f55SGrant Likely u32 irq_status = DCSR(channel) & DMA_INT_MASK; 573ca632f55SGrant Likely 574ca632f55SGrant Likely if (irq_status & DCSR_BUSERR) { 575ca632f55SGrant Likely 576ca632f55SGrant Likely if (channel == drv_data->tx_channel) 577ca632f55SGrant Likely dma_error_stop(drv_data, 578ca632f55SGrant Likely "dma_handler: " 579ca632f55SGrant Likely "bad bus address on tx channel"); 580ca632f55SGrant Likely else 581ca632f55SGrant Likely dma_error_stop(drv_data, 582ca632f55SGrant Likely "dma_handler: " 583ca632f55SGrant Likely "bad bus address on rx channel"); 584ca632f55SGrant Likely return; 585ca632f55SGrant Likely } 586ca632f55SGrant Likely 587ca632f55SGrant Likely /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ 588ca632f55SGrant Likely if ((channel == drv_data->tx_channel) 589ca632f55SGrant Likely && (irq_status & DCSR_ENDINTR) 590ca632f55SGrant Likely && (drv_data->ssp_type == PXA25x_SSP)) { 591ca632f55SGrant Likely 592ca632f55SGrant Likely /* Wait for rx to stall */ 593ca632f55SGrant Likely if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) 594ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 595ca632f55SGrant Likely "dma_handler: ssp rx stall failed\n"); 596ca632f55SGrant Likely 597ca632f55SGrant Likely /* finish this transfer, start the next */ 598ca632f55SGrant Likely dma_transfer_complete(drv_data); 599ca632f55SGrant Likely } 600ca632f55SGrant Likely } 601ca632f55SGrant Likely 602ca632f55SGrant Likely static irqreturn_t dma_transfer(struct driver_data *drv_data) 603ca632f55SGrant Likely { 604ca632f55SGrant Likely u32 irq_status; 605ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 606ca632f55SGrant Likely 607ca632f55SGrant Likely irq_status = read_SSSR(reg) & drv_data->mask_sr; 608ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 609ca632f55SGrant Likely dma_error_stop(drv_data, "dma_transfer: fifo overrun"); 610ca632f55SGrant Likely return IRQ_HANDLED; 611ca632f55SGrant Likely } 612ca632f55SGrant Likely 613ca632f55SGrant Likely /* Check for false positive timeout */ 614ca632f55SGrant Likely if ((irq_status & SSSR_TINT) 615ca632f55SGrant Likely && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { 616ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 617ca632f55SGrant Likely return IRQ_HANDLED; 618ca632f55SGrant Likely } 619ca632f55SGrant Likely 620ca632f55SGrant Likely if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { 621ca632f55SGrant Likely 622ca632f55SGrant Likely /* Clear and disable timeout interrupt, do the rest in 623ca632f55SGrant Likely * dma_transfer_complete */ 624ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 625ca632f55SGrant Likely write_SSTO(0, reg); 626ca632f55SGrant Likely 627ca632f55SGrant Likely /* finish this transfer, start the next */ 628ca632f55SGrant Likely dma_transfer_complete(drv_data); 629ca632f55SGrant Likely 630ca632f55SGrant Likely return IRQ_HANDLED; 631ca632f55SGrant Likely } 632ca632f55SGrant Likely 633ca632f55SGrant Likely /* Opps problem detected */ 634ca632f55SGrant Likely return IRQ_NONE; 635ca632f55SGrant Likely } 636ca632f55SGrant Likely 637ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 638ca632f55SGrant Likely { 639ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 640ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 641ca632f55SGrant Likely u32 sccr1_reg; 642ca632f55SGrant Likely 643ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 644ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 645ca632f55SGrant Likely sccr1_reg |= chip->threshold; 646ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 647ca632f55SGrant Likely } 648ca632f55SGrant Likely 649ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 650ca632f55SGrant Likely { 651ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 652ca632f55SGrant Likely 653ca632f55SGrant Likely /* Stop and reset SSP */ 654ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 655ca632f55SGrant Likely reset_sccr1(drv_data); 656ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 657ca632f55SGrant Likely write_SSTO(0, reg); 658ca632f55SGrant Likely flush(drv_data); 659ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 660ca632f55SGrant Likely 661ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 662ca632f55SGrant Likely 663ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 664ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 665ca632f55SGrant Likely } 666ca632f55SGrant Likely 667ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 668ca632f55SGrant Likely { 669ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 670ca632f55SGrant Likely 671ca632f55SGrant Likely /* Stop SSP */ 672ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 673ca632f55SGrant Likely reset_sccr1(drv_data); 674ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 675ca632f55SGrant Likely write_SSTO(0, reg); 676ca632f55SGrant Likely 677ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 678ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 679ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 680ca632f55SGrant Likely 681ca632f55SGrant Likely /* Transfer delays and chip select release are 682ca632f55SGrant Likely * handled in pump_transfers or giveback 683ca632f55SGrant Likely */ 684ca632f55SGrant Likely 685ca632f55SGrant Likely /* Move to next transfer */ 686ca632f55SGrant Likely drv_data->cur_msg->state = next_transfer(drv_data); 687ca632f55SGrant Likely 688ca632f55SGrant Likely /* Schedule transfer tasklet */ 689ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 690ca632f55SGrant Likely } 691ca632f55SGrant Likely 692ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 693ca632f55SGrant Likely { 694ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 695ca632f55SGrant Likely 696ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 697ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 698ca632f55SGrant Likely 699ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 700ca632f55SGrant Likely 701ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 702ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 703ca632f55SGrant Likely return IRQ_HANDLED; 704ca632f55SGrant Likely } 705ca632f55SGrant Likely 706ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 707ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 708ca632f55SGrant Likely if (drv_data->read(drv_data)) { 709ca632f55SGrant Likely int_transfer_complete(drv_data); 710ca632f55SGrant Likely return IRQ_HANDLED; 711ca632f55SGrant Likely } 712ca632f55SGrant Likely } 713ca632f55SGrant Likely 714ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 715ca632f55SGrant Likely do { 716ca632f55SGrant Likely if (drv_data->read(drv_data)) { 717ca632f55SGrant Likely int_transfer_complete(drv_data); 718ca632f55SGrant Likely return IRQ_HANDLED; 719ca632f55SGrant Likely } 720ca632f55SGrant Likely } while (drv_data->write(drv_data)); 721ca632f55SGrant Likely 722ca632f55SGrant Likely if (drv_data->read(drv_data)) { 723ca632f55SGrant Likely int_transfer_complete(drv_data); 724ca632f55SGrant Likely return IRQ_HANDLED; 725ca632f55SGrant Likely } 726ca632f55SGrant Likely 727ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 728ca632f55SGrant Likely u32 bytes_left; 729ca632f55SGrant Likely u32 sccr1_reg; 730ca632f55SGrant Likely 731ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 732ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 733ca632f55SGrant Likely 734ca632f55SGrant Likely /* 735ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 736ca632f55SGrant Likely * remaining RX bytes. 737ca632f55SGrant Likely */ 738ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 739ca632f55SGrant Likely 740ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 741ca632f55SGrant Likely 742ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 743ca632f55SGrant Likely switch (drv_data->n_bytes) { 744ca632f55SGrant Likely case 4: 745ca632f55SGrant Likely bytes_left >>= 1; 746ca632f55SGrant Likely case 2: 747ca632f55SGrant Likely bytes_left >>= 1; 748ca632f55SGrant Likely } 749ca632f55SGrant Likely 750ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 751ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 752ca632f55SGrant Likely 753ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 754ca632f55SGrant Likely } 755ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 756ca632f55SGrant Likely } 757ca632f55SGrant Likely 758ca632f55SGrant Likely /* We did something */ 759ca632f55SGrant Likely return IRQ_HANDLED; 760ca632f55SGrant Likely } 761ca632f55SGrant Likely 762ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 763ca632f55SGrant Likely { 764ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 765ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 766ca632f55SGrant Likely u32 sccr1_reg = read_SSCR1(reg); 767ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 768ca632f55SGrant Likely u32 status; 769ca632f55SGrant Likely 770ca632f55SGrant Likely status = read_SSSR(reg); 771ca632f55SGrant Likely 772ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 773ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 774ca632f55SGrant Likely mask &= ~SSSR_TFS; 775ca632f55SGrant Likely 776ca632f55SGrant Likely if (!(status & mask)) 777ca632f55SGrant Likely return IRQ_NONE; 778ca632f55SGrant Likely 779ca632f55SGrant Likely if (!drv_data->cur_msg) { 780ca632f55SGrant Likely 781ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 782ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 783ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 784ca632f55SGrant Likely write_SSTO(0, reg); 785ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 786ca632f55SGrant Likely 787ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "bad message state " 788ca632f55SGrant Likely "in interrupt handler\n"); 789ca632f55SGrant Likely 790ca632f55SGrant Likely /* Never fail */ 791ca632f55SGrant Likely return IRQ_HANDLED; 792ca632f55SGrant Likely } 793ca632f55SGrant Likely 794ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 795ca632f55SGrant Likely } 796ca632f55SGrant Likely 797ca632f55SGrant Likely static int set_dma_burst_and_threshold(struct chip_data *chip, 798ca632f55SGrant Likely struct spi_device *spi, 799ca632f55SGrant Likely u8 bits_per_word, u32 *burst_code, 800ca632f55SGrant Likely u32 *threshold) 801ca632f55SGrant Likely { 802ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = 803ca632f55SGrant Likely (struct pxa2xx_spi_chip *)spi->controller_data; 804ca632f55SGrant Likely int bytes_per_word; 805ca632f55SGrant Likely int burst_bytes; 806ca632f55SGrant Likely int thresh_words; 807ca632f55SGrant Likely int req_burst_size; 808ca632f55SGrant Likely int retval = 0; 809ca632f55SGrant Likely 810ca632f55SGrant Likely /* Set the threshold (in registers) to equal the same amount of data 811ca632f55SGrant Likely * as represented by burst size (in bytes). The computation below 812ca632f55SGrant Likely * is (burst_size rounded up to nearest 8 byte, word or long word) 813ca632f55SGrant Likely * divided by (bytes/register); the tx threshold is the inverse of 814ca632f55SGrant Likely * the rx, so that there will always be enough data in the rx fifo 815ca632f55SGrant Likely * to satisfy a burst, and there will always be enough space in the 816ca632f55SGrant Likely * tx fifo to accept a burst (a tx burst will overwrite the fifo if 817ca632f55SGrant Likely * there is not enough space), there must always remain enough empty 818ca632f55SGrant Likely * space in the rx fifo for any data loaded to the tx fifo. 819ca632f55SGrant Likely * Whenever burst_size (in bytes) equals bits/word, the fifo threshold 820ca632f55SGrant Likely * will be 8, or half the fifo; 821ca632f55SGrant Likely * The threshold can only be set to 2, 4 or 8, but not 16, because 822ca632f55SGrant Likely * to burst 16 to the tx fifo, the fifo would have to be empty; 823ca632f55SGrant Likely * however, the minimum fifo trigger level is 1, and the tx will 824ca632f55SGrant Likely * request service when the fifo is at this level, with only 15 spaces. 825ca632f55SGrant Likely */ 826ca632f55SGrant Likely 827ca632f55SGrant Likely /* find bytes/word */ 828ca632f55SGrant Likely if (bits_per_word <= 8) 829ca632f55SGrant Likely bytes_per_word = 1; 830ca632f55SGrant Likely else if (bits_per_word <= 16) 831ca632f55SGrant Likely bytes_per_word = 2; 832ca632f55SGrant Likely else 833ca632f55SGrant Likely bytes_per_word = 4; 834ca632f55SGrant Likely 835ca632f55SGrant Likely /* use struct pxa2xx_spi_chip->dma_burst_size if available */ 836ca632f55SGrant Likely if (chip_info) 837ca632f55SGrant Likely req_burst_size = chip_info->dma_burst_size; 838ca632f55SGrant Likely else { 839ca632f55SGrant Likely switch (chip->dma_burst_size) { 840ca632f55SGrant Likely default: 841ca632f55SGrant Likely /* if the default burst size is not set, 842ca632f55SGrant Likely * do it now */ 843ca632f55SGrant Likely chip->dma_burst_size = DCMD_BURST8; 844ca632f55SGrant Likely case DCMD_BURST8: 845ca632f55SGrant Likely req_burst_size = 8; 846ca632f55SGrant Likely break; 847ca632f55SGrant Likely case DCMD_BURST16: 848ca632f55SGrant Likely req_burst_size = 16; 849ca632f55SGrant Likely break; 850ca632f55SGrant Likely case DCMD_BURST32: 851ca632f55SGrant Likely req_burst_size = 32; 852ca632f55SGrant Likely break; 853ca632f55SGrant Likely } 854ca632f55SGrant Likely } 855ca632f55SGrant Likely if (req_burst_size <= 8) { 856ca632f55SGrant Likely *burst_code = DCMD_BURST8; 857ca632f55SGrant Likely burst_bytes = 8; 858ca632f55SGrant Likely } else if (req_burst_size <= 16) { 859ca632f55SGrant Likely if (bytes_per_word == 1) { 860ca632f55SGrant Likely /* don't burst more than 1/2 the fifo */ 861ca632f55SGrant Likely *burst_code = DCMD_BURST8; 862ca632f55SGrant Likely burst_bytes = 8; 863ca632f55SGrant Likely retval = 1; 864ca632f55SGrant Likely } else { 865ca632f55SGrant Likely *burst_code = DCMD_BURST16; 866ca632f55SGrant Likely burst_bytes = 16; 867ca632f55SGrant Likely } 868ca632f55SGrant Likely } else { 869ca632f55SGrant Likely if (bytes_per_word == 1) { 870ca632f55SGrant Likely /* don't burst more than 1/2 the fifo */ 871ca632f55SGrant Likely *burst_code = DCMD_BURST8; 872ca632f55SGrant Likely burst_bytes = 8; 873ca632f55SGrant Likely retval = 1; 874ca632f55SGrant Likely } else if (bytes_per_word == 2) { 875ca632f55SGrant Likely /* don't burst more than 1/2 the fifo */ 876ca632f55SGrant Likely *burst_code = DCMD_BURST16; 877ca632f55SGrant Likely burst_bytes = 16; 878ca632f55SGrant Likely retval = 1; 879ca632f55SGrant Likely } else { 880ca632f55SGrant Likely *burst_code = DCMD_BURST32; 881ca632f55SGrant Likely burst_bytes = 32; 882ca632f55SGrant Likely } 883ca632f55SGrant Likely } 884ca632f55SGrant Likely 885ca632f55SGrant Likely thresh_words = burst_bytes / bytes_per_word; 886ca632f55SGrant Likely 887ca632f55SGrant Likely /* thresh_words will be between 2 and 8 */ 888ca632f55SGrant Likely *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) 889ca632f55SGrant Likely | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); 890ca632f55SGrant Likely 891ca632f55SGrant Likely return retval; 892ca632f55SGrant Likely } 893ca632f55SGrant Likely 894ca632f55SGrant Likely static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) 895ca632f55SGrant Likely { 896ca632f55SGrant Likely unsigned long ssp_clk = clk_get_rate(ssp->clk); 897ca632f55SGrant Likely 898ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 899ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 900ca632f55SGrant Likely else 901ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 902ca632f55SGrant Likely } 903ca632f55SGrant Likely 904ca632f55SGrant Likely static void pump_transfers(unsigned long data) 905ca632f55SGrant Likely { 906ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 907ca632f55SGrant Likely struct spi_message *message = NULL; 908ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 909ca632f55SGrant Likely struct spi_transfer *previous = NULL; 910ca632f55SGrant Likely struct chip_data *chip = NULL; 911ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 912ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 913ca632f55SGrant Likely u32 clk_div = 0; 914ca632f55SGrant Likely u8 bits = 0; 915ca632f55SGrant Likely u32 speed = 0; 916ca632f55SGrant Likely u32 cr0; 917ca632f55SGrant Likely u32 cr1; 918ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 919ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 920ca632f55SGrant Likely 921ca632f55SGrant Likely /* Get current state information */ 922ca632f55SGrant Likely message = drv_data->cur_msg; 923ca632f55SGrant Likely transfer = drv_data->cur_transfer; 924ca632f55SGrant Likely chip = drv_data->cur_chip; 925ca632f55SGrant Likely 926ca632f55SGrant Likely /* Handle for abort */ 927ca632f55SGrant Likely if (message->state == ERROR_STATE) { 928ca632f55SGrant Likely message->status = -EIO; 929ca632f55SGrant Likely giveback(drv_data); 930ca632f55SGrant Likely return; 931ca632f55SGrant Likely } 932ca632f55SGrant Likely 933ca632f55SGrant Likely /* Handle end of message */ 934ca632f55SGrant Likely if (message->state == DONE_STATE) { 935ca632f55SGrant Likely message->status = 0; 936ca632f55SGrant Likely giveback(drv_data); 937ca632f55SGrant Likely return; 938ca632f55SGrant Likely } 939ca632f55SGrant Likely 940ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 941ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 942ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 943ca632f55SGrant Likely struct spi_transfer, 944ca632f55SGrant Likely transfer_list); 945ca632f55SGrant Likely if (previous->delay_usecs) 946ca632f55SGrant Likely udelay(previous->delay_usecs); 947ca632f55SGrant Likely 948ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 949ca632f55SGrant Likely if (previous->cs_change) 950ca632f55SGrant Likely cs_deassert(drv_data); 951ca632f55SGrant Likely } 952ca632f55SGrant Likely 953ca632f55SGrant Likely /* Check for transfers that need multiple DMA segments */ 954ca632f55SGrant Likely if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 955ca632f55SGrant Likely 956ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 957ca632f55SGrant Likely if (message->is_dma_mapped 958ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 959ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 960ca632f55SGrant Likely "pump_transfers: mapped transfer length " 961ca632f55SGrant Likely "of %u is greater than %d\n", 962ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 963ca632f55SGrant Likely message->status = -EINVAL; 964ca632f55SGrant Likely giveback(drv_data); 965ca632f55SGrant Likely return; 966ca632f55SGrant Likely } 967ca632f55SGrant Likely 968ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 969ca632f55SGrant Likely if (printk_ratelimit()) 970ca632f55SGrant Likely dev_warn(&message->spi->dev, "pump_transfers: " 971ca632f55SGrant Likely "DMA disabled for transfer length %ld " 972ca632f55SGrant Likely "greater than %d\n", 973ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 974ca632f55SGrant Likely } 975ca632f55SGrant Likely 976ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 977ca632f55SGrant Likely if (flush(drv_data) == 0) { 978ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 979ca632f55SGrant Likely message->status = -EIO; 980ca632f55SGrant Likely giveback(drv_data); 981ca632f55SGrant Likely return; 982ca632f55SGrant Likely } 983ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 984ca632f55SGrant Likely drv_data->dma_width = chip->dma_width; 985ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 986ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 987ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 988ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 989ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 990ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 991ca632f55SGrant Likely drv_data->len = transfer->len & DCMD_LENGTH; 992ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 993ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 994ca632f55SGrant Likely 995ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 996ca632f55SGrant Likely cr0 = chip->cr0; 997ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 998ca632f55SGrant Likely 999ca632f55SGrant Likely bits = chip->bits_per_word; 1000ca632f55SGrant Likely speed = chip->speed_hz; 1001ca632f55SGrant Likely 1002ca632f55SGrant Likely if (transfer->speed_hz) 1003ca632f55SGrant Likely speed = transfer->speed_hz; 1004ca632f55SGrant Likely 1005ca632f55SGrant Likely if (transfer->bits_per_word) 1006ca632f55SGrant Likely bits = transfer->bits_per_word; 1007ca632f55SGrant Likely 1008ca632f55SGrant Likely clk_div = ssp_get_clk_div(ssp, speed); 1009ca632f55SGrant Likely 1010ca632f55SGrant Likely if (bits <= 8) { 1011ca632f55SGrant Likely drv_data->n_bytes = 1; 1012ca632f55SGrant Likely drv_data->dma_width = DCMD_WIDTH1; 1013ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 1014ca632f55SGrant Likely u8_reader : null_reader; 1015ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 1016ca632f55SGrant Likely u8_writer : null_writer; 1017ca632f55SGrant Likely } else if (bits <= 16) { 1018ca632f55SGrant Likely drv_data->n_bytes = 2; 1019ca632f55SGrant Likely drv_data->dma_width = DCMD_WIDTH2; 1020ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 1021ca632f55SGrant Likely u16_reader : null_reader; 1022ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 1023ca632f55SGrant Likely u16_writer : null_writer; 1024ca632f55SGrant Likely } else if (bits <= 32) { 1025ca632f55SGrant Likely drv_data->n_bytes = 4; 1026ca632f55SGrant Likely drv_data->dma_width = DCMD_WIDTH4; 1027ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 1028ca632f55SGrant Likely u32_reader : null_reader; 1029ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 1030ca632f55SGrant Likely u32_writer : null_writer; 1031ca632f55SGrant Likely } 1032ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 1033ca632f55SGrant Likely * thresholds and burst also */ 1034ca632f55SGrant Likely if (chip->enable_dma) { 1035ca632f55SGrant Likely if (set_dma_burst_and_threshold(chip, message->spi, 1036ca632f55SGrant Likely bits, &dma_burst, 1037ca632f55SGrant Likely &dma_thresh)) 1038ca632f55SGrant Likely if (printk_ratelimit()) 1039ca632f55SGrant Likely dev_warn(&message->spi->dev, 1040ca632f55SGrant Likely "pump_transfers: " 1041ca632f55SGrant Likely "DMA burst size reduced to " 1042ca632f55SGrant Likely "match bits_per_word\n"); 1043ca632f55SGrant Likely } 1044ca632f55SGrant Likely 1045ca632f55SGrant Likely cr0 = clk_div 1046ca632f55SGrant Likely | SSCR0_Motorola 1047ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 1048ca632f55SGrant Likely | SSCR0_SSE 1049ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 1050ca632f55SGrant Likely } 1051ca632f55SGrant Likely 1052ca632f55SGrant Likely message->state = RUNNING_STATE; 1053ca632f55SGrant Likely 1054ca632f55SGrant Likely /* Try to map dma buffer and do a dma transfer if successful, but 1055ca632f55SGrant Likely * only if the length is non-zero and less than MAX_DMA_LEN. 1056ca632f55SGrant Likely * 1057ca632f55SGrant Likely * Zero-length non-descriptor DMA is illegal on PXA2xx; force use 1058ca632f55SGrant Likely * of PIO instead. Care is needed above because the transfer may 1059ca632f55SGrant Likely * have have been passed with buffers that are already dma mapped. 1060ca632f55SGrant Likely * A zero-length transfer in PIO mode will not try to write/read 1061ca632f55SGrant Likely * to/from the buffers 1062ca632f55SGrant Likely * 1063ca632f55SGrant Likely * REVISIT large transfers are exactly where we most want to be 1064ca632f55SGrant Likely * using DMA. If this happens much, split those transfers into 1065ca632f55SGrant Likely * multiple DMA segments rather than forcing PIO. 1066ca632f55SGrant Likely */ 1067ca632f55SGrant Likely drv_data->dma_mapped = 0; 1068ca632f55SGrant Likely if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) 1069ca632f55SGrant Likely drv_data->dma_mapped = map_dma_buffers(drv_data); 1070ca632f55SGrant Likely if (drv_data->dma_mapped) { 1071ca632f55SGrant Likely 1072ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 1073ca632f55SGrant Likely drv_data->transfer_handler = dma_transfer; 1074ca632f55SGrant Likely 1075ca632f55SGrant Likely /* Setup rx DMA Channel */ 1076ca632f55SGrant Likely DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 1077ca632f55SGrant Likely DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; 1078ca632f55SGrant Likely DTADR(drv_data->rx_channel) = drv_data->rx_dma; 1079ca632f55SGrant Likely if (drv_data->rx == drv_data->null_dma_buf) 1080ca632f55SGrant Likely /* No target address increment */ 1081ca632f55SGrant Likely DCMD(drv_data->rx_channel) = DCMD_FLOWSRC 1082ca632f55SGrant Likely | drv_data->dma_width 1083ca632f55SGrant Likely | dma_burst 1084ca632f55SGrant Likely | drv_data->len; 1085ca632f55SGrant Likely else 1086ca632f55SGrant Likely DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR 1087ca632f55SGrant Likely | DCMD_FLOWSRC 1088ca632f55SGrant Likely | drv_data->dma_width 1089ca632f55SGrant Likely | dma_burst 1090ca632f55SGrant Likely | drv_data->len; 1091ca632f55SGrant Likely 1092ca632f55SGrant Likely /* Setup tx DMA Channel */ 1093ca632f55SGrant Likely DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 1094ca632f55SGrant Likely DSADR(drv_data->tx_channel) = drv_data->tx_dma; 1095ca632f55SGrant Likely DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; 1096ca632f55SGrant Likely if (drv_data->tx == drv_data->null_dma_buf) 1097ca632f55SGrant Likely /* No source address increment */ 1098ca632f55SGrant Likely DCMD(drv_data->tx_channel) = DCMD_FLOWTRG 1099ca632f55SGrant Likely | drv_data->dma_width 1100ca632f55SGrant Likely | dma_burst 1101ca632f55SGrant Likely | drv_data->len; 1102ca632f55SGrant Likely else 1103ca632f55SGrant Likely DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR 1104ca632f55SGrant Likely | DCMD_FLOWTRG 1105ca632f55SGrant Likely | drv_data->dma_width 1106ca632f55SGrant Likely | dma_burst 1107ca632f55SGrant Likely | drv_data->len; 1108ca632f55SGrant Likely 1109ca632f55SGrant Likely /* Enable dma end irqs on SSP to detect end of transfer */ 1110ca632f55SGrant Likely if (drv_data->ssp_type == PXA25x_SSP) 1111ca632f55SGrant Likely DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; 1112ca632f55SGrant Likely 1113ca632f55SGrant Likely /* Clear status and start DMA engine */ 1114ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1115ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 1116ca632f55SGrant Likely DCSR(drv_data->rx_channel) |= DCSR_RUN; 1117ca632f55SGrant Likely DCSR(drv_data->tx_channel) |= DCSR_RUN; 1118ca632f55SGrant Likely } else { 1119ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 1120ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 1121ca632f55SGrant Likely 1122ca632f55SGrant Likely /* Clear status */ 1123ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1124ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 1125ca632f55SGrant Likely } 1126ca632f55SGrant Likely 1127ca632f55SGrant Likely /* see if we need to reload the config registers */ 1128ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 1129ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 1130ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 1131ca632f55SGrant Likely 1132ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 1133ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 1134ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1135ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 1136ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 1137ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 1138ca632f55SGrant Likely /* restart the SSP */ 1139ca632f55SGrant Likely write_SSCR0(cr0, reg); 1140ca632f55SGrant Likely 1141ca632f55SGrant Likely } else { 1142ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1143ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 1144ca632f55SGrant Likely } 1145ca632f55SGrant Likely 1146ca632f55SGrant Likely cs_assert(drv_data); 1147ca632f55SGrant Likely 1148ca632f55SGrant Likely /* after chip select, release the data by enabling service 1149ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 1150ca632f55SGrant Likely write_SSCR1(cr1, reg); 1151ca632f55SGrant Likely } 1152ca632f55SGrant Likely 1153*7f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 1154*7f86bde9SMika Westerberg struct spi_message *msg) 1155ca632f55SGrant Likely { 1156*7f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 1157ca632f55SGrant Likely 1158*7f86bde9SMika Westerberg drv_data->cur_msg = msg; 1159ca632f55SGrant Likely /* Initial message state*/ 1160ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 1161ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 1162ca632f55SGrant Likely struct spi_transfer, 1163ca632f55SGrant Likely transfer_list); 1164ca632f55SGrant Likely 1165ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 1166ca632f55SGrant Likely * chip configuration */ 1167ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 1168ca632f55SGrant Likely 1169ca632f55SGrant Likely /* Mark as busy and launch transfers */ 1170ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 1171ca632f55SGrant Likely return 0; 1172ca632f55SGrant Likely } 1173ca632f55SGrant Likely 1174ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1175ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 1176ca632f55SGrant Likely { 1177ca632f55SGrant Likely int err = 0; 1178ca632f55SGrant Likely 1179ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 1180ca632f55SGrant Likely return 0; 1181ca632f55SGrant Likely 1182ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 1183ca632f55SGrant Likely * different chip_info, release previously requested GPIO 1184ca632f55SGrant Likely */ 1185ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 1186ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1187ca632f55SGrant Likely 1188ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 1189ca632f55SGrant Likely if (chip_info->cs_control) { 1190ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1191ca632f55SGrant Likely return 0; 1192ca632f55SGrant Likely } 1193ca632f55SGrant Likely 1194ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 1195ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1196ca632f55SGrant Likely if (err) { 1197ca632f55SGrant Likely dev_err(&spi->dev, "failed to request chip select " 1198ca632f55SGrant Likely "GPIO%d\n", chip_info->gpio_cs); 1199ca632f55SGrant Likely return err; 1200ca632f55SGrant Likely } 1201ca632f55SGrant Likely 1202ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 1203ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1204ca632f55SGrant Likely 1205ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 1206ca632f55SGrant Likely !chip->gpio_cs_inverted); 1207ca632f55SGrant Likely } 1208ca632f55SGrant Likely 1209ca632f55SGrant Likely return err; 1210ca632f55SGrant Likely } 1211ca632f55SGrant Likely 1212ca632f55SGrant Likely static int setup(struct spi_device *spi) 1213ca632f55SGrant Likely { 1214ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 1215ca632f55SGrant Likely struct chip_data *chip; 1216ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1217ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1218ca632f55SGrant Likely unsigned int clk_div; 1219ca632f55SGrant Likely uint tx_thres = TX_THRESH_DFLT; 1220ca632f55SGrant Likely uint rx_thres = RX_THRESH_DFLT; 1221ca632f55SGrant Likely 1222ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data) 1223ca632f55SGrant Likely && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { 1224ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 1225ca632f55SGrant Likely "b/w not 4-32 for type non-PXA25x_SSP\n", 1226ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 1227ca632f55SGrant Likely return -EINVAL; 1228ca632f55SGrant Likely } else if (pxa25x_ssp_comp(drv_data) 1229ca632f55SGrant Likely && (spi->bits_per_word < 4 1230ca632f55SGrant Likely || spi->bits_per_word > 16)) { 1231ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 1232ca632f55SGrant Likely "b/w not 4-16 for type PXA25x_SSP\n", 1233ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 1234ca632f55SGrant Likely return -EINVAL; 1235ca632f55SGrant Likely } 1236ca632f55SGrant Likely 1237ca632f55SGrant Likely /* Only alloc on first setup */ 1238ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1239ca632f55SGrant Likely if (!chip) { 1240ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1241ca632f55SGrant Likely if (!chip) { 1242ca632f55SGrant Likely dev_err(&spi->dev, 1243ca632f55SGrant Likely "failed setup: can't allocate chip data\n"); 1244ca632f55SGrant Likely return -ENOMEM; 1245ca632f55SGrant Likely } 1246ca632f55SGrant Likely 1247ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 1248ca632f55SGrant Likely if (spi->chip_select > 4) { 1249ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: " 1250ca632f55SGrant Likely "cs number must not be > 4.\n"); 1251ca632f55SGrant Likely kfree(chip); 1252ca632f55SGrant Likely return -EINVAL; 1253ca632f55SGrant Likely } 1254ca632f55SGrant Likely 1255ca632f55SGrant Likely chip->frm = spi->chip_select; 1256ca632f55SGrant Likely } else 1257ca632f55SGrant Likely chip->gpio_cs = -1; 1258ca632f55SGrant Likely chip->enable_dma = 0; 1259ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 1260ca632f55SGrant Likely chip->dma_burst_size = drv_data->master_info->enable_dma ? 1261ca632f55SGrant Likely DCMD_BURST8 : 0; 1262ca632f55SGrant Likely } 1263ca632f55SGrant Likely 1264ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 1265ca632f55SGrant Likely * if chip_info exists, use it */ 1266ca632f55SGrant Likely chip_info = spi->controller_data; 1267ca632f55SGrant Likely 1268ca632f55SGrant Likely /* chip_info isn't always needed */ 1269ca632f55SGrant Likely chip->cr1 = 0; 1270ca632f55SGrant Likely if (chip_info) { 1271ca632f55SGrant Likely if (chip_info->timeout) 1272ca632f55SGrant Likely chip->timeout = chip_info->timeout; 1273ca632f55SGrant Likely if (chip_info->tx_threshold) 1274ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 1275ca632f55SGrant Likely if (chip_info->rx_threshold) 1276ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 1277ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 1278ca632f55SGrant Likely chip->dma_threshold = 0; 1279ca632f55SGrant Likely if (chip_info->enable_loopback) 1280ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 1281ca632f55SGrant Likely } 1282ca632f55SGrant Likely 1283ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1284ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1285ca632f55SGrant Likely 1286ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 1287ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 1288ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 1289ca632f55SGrant Likely if (chip->enable_dma) { 1290ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 1291ca632f55SGrant Likely if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, 1292ca632f55SGrant Likely &chip->dma_burst_size, 1293ca632f55SGrant Likely &chip->dma_threshold)) { 1294ca632f55SGrant Likely dev_warn(&spi->dev, "in setup: DMA burst size reduced " 1295ca632f55SGrant Likely "to match bits_per_word\n"); 1296ca632f55SGrant Likely } 1297ca632f55SGrant Likely } 1298ca632f55SGrant Likely 1299ca632f55SGrant Likely clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); 1300ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 1301ca632f55SGrant Likely 1302ca632f55SGrant Likely chip->cr0 = clk_div 1303ca632f55SGrant Likely | SSCR0_Motorola 1304ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 1305ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 1306ca632f55SGrant Likely | SSCR0_SSE 1307ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 1308ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1309ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1310ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1311ca632f55SGrant Likely 1312ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1313ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1314ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1315ca632f55SGrant Likely clk_get_rate(ssp->clk) 1316ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 1317ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 1318ca632f55SGrant Likely else 1319ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1320ca632f55SGrant Likely clk_get_rate(ssp->clk) / 2 1321ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1322ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 1323ca632f55SGrant Likely 1324ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 1325ca632f55SGrant Likely chip->n_bytes = 1; 1326ca632f55SGrant Likely chip->dma_width = DCMD_WIDTH1; 1327ca632f55SGrant Likely chip->read = u8_reader; 1328ca632f55SGrant Likely chip->write = u8_writer; 1329ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 1330ca632f55SGrant Likely chip->n_bytes = 2; 1331ca632f55SGrant Likely chip->dma_width = DCMD_WIDTH2; 1332ca632f55SGrant Likely chip->read = u16_reader; 1333ca632f55SGrant Likely chip->write = u16_writer; 1334ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 1335ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 1336ca632f55SGrant Likely chip->n_bytes = 4; 1337ca632f55SGrant Likely chip->dma_width = DCMD_WIDTH4; 1338ca632f55SGrant Likely chip->read = u32_reader; 1339ca632f55SGrant Likely chip->write = u32_writer; 1340ca632f55SGrant Likely } else { 1341ca632f55SGrant Likely dev_err(&spi->dev, "invalid wordsize\n"); 1342ca632f55SGrant Likely return -ENODEV; 1343ca632f55SGrant Likely } 1344ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 1345ca632f55SGrant Likely 1346ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1347ca632f55SGrant Likely 1348ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 1349ca632f55SGrant Likely return 0; 1350ca632f55SGrant Likely 1351ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 1352ca632f55SGrant Likely } 1353ca632f55SGrant Likely 1354ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 1355ca632f55SGrant Likely { 1356ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1357ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1358ca632f55SGrant Likely 1359ca632f55SGrant Likely if (!chip) 1360ca632f55SGrant Likely return; 1361ca632f55SGrant Likely 1362ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1363ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1364ca632f55SGrant Likely 1365ca632f55SGrant Likely kfree(chip); 1366ca632f55SGrant Likely } 1367ca632f55SGrant Likely 1368fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 1369ca632f55SGrant Likely { 1370ca632f55SGrant Likely struct device *dev = &pdev->dev; 1371ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 1372ca632f55SGrant Likely struct spi_master *master; 1373ca632f55SGrant Likely struct driver_data *drv_data; 1374ca632f55SGrant Likely struct ssp_device *ssp; 1375ca632f55SGrant Likely int status; 1376ca632f55SGrant Likely 1377851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 1378851bacf5SMika Westerberg if (!platform_info) { 1379851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 1380851bacf5SMika Westerberg return -ENODEV; 1381851bacf5SMika Westerberg } 1382ca632f55SGrant Likely 1383ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 1384851bacf5SMika Westerberg if (!ssp) 1385851bacf5SMika Westerberg ssp = &platform_info->ssp; 1386851bacf5SMika Westerberg 1387851bacf5SMika Westerberg if (!ssp->mmio_base) { 1388851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 1389ca632f55SGrant Likely return -ENODEV; 1390ca632f55SGrant Likely } 1391ca632f55SGrant Likely 1392ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 1393ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1394ca632f55SGrant Likely if (!master) { 1395ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1396ca632f55SGrant Likely pxa_ssp_free(ssp); 1397ca632f55SGrant Likely return -ENOMEM; 1398ca632f55SGrant Likely } 1399ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 1400ca632f55SGrant Likely drv_data->master = master; 1401ca632f55SGrant Likely drv_data->master_info = platform_info; 1402ca632f55SGrant Likely drv_data->pdev = pdev; 1403ca632f55SGrant Likely drv_data->ssp = ssp; 1404ca632f55SGrant Likely 1405ca632f55SGrant Likely master->dev.parent = &pdev->dev; 1406ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 1407ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1408ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1409ca632f55SGrant Likely 1410851bacf5SMika Westerberg master->bus_num = ssp->port_id; 1411ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 1412ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 1413ca632f55SGrant Likely master->cleanup = cleanup; 1414ca632f55SGrant Likely master->setup = setup; 1415*7f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 1416ca632f55SGrant Likely 1417ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 14182b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1419ca632f55SGrant Likely 1420ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 1421ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 1422ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 1423ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1424ca632f55SGrant Likely drv_data->dma_cr1 = 0; 1425ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 1426ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1427ca632f55SGrant Likely } else { 1428ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1429ca632f55SGrant Likely drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; 1430ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1431ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1432ca632f55SGrant Likely } 1433ca632f55SGrant Likely 1434ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1435ca632f55SGrant Likely drv_data); 1436ca632f55SGrant Likely if (status < 0) { 1437ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1438ca632f55SGrant Likely goto out_error_master_alloc; 1439ca632f55SGrant Likely } 1440ca632f55SGrant Likely 1441ca632f55SGrant Likely /* Setup DMA if requested */ 1442ca632f55SGrant Likely drv_data->tx_channel = -1; 1443ca632f55SGrant Likely drv_data->rx_channel = -1; 1444ca632f55SGrant Likely if (platform_info->enable_dma) { 1445ca632f55SGrant Likely 1446ca632f55SGrant Likely /* Get two DMA channels (rx and tx) */ 1447ca632f55SGrant Likely drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", 1448ca632f55SGrant Likely DMA_PRIO_HIGH, 1449ca632f55SGrant Likely dma_handler, 1450ca632f55SGrant Likely drv_data); 1451ca632f55SGrant Likely if (drv_data->rx_channel < 0) { 1452ca632f55SGrant Likely dev_err(dev, "problem (%d) requesting rx channel\n", 1453ca632f55SGrant Likely drv_data->rx_channel); 1454ca632f55SGrant Likely status = -ENODEV; 1455ca632f55SGrant Likely goto out_error_irq_alloc; 1456ca632f55SGrant Likely } 1457ca632f55SGrant Likely drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", 1458ca632f55SGrant Likely DMA_PRIO_MEDIUM, 1459ca632f55SGrant Likely dma_handler, 1460ca632f55SGrant Likely drv_data); 1461ca632f55SGrant Likely if (drv_data->tx_channel < 0) { 1462ca632f55SGrant Likely dev_err(dev, "problem (%d) requesting tx channel\n", 1463ca632f55SGrant Likely drv_data->tx_channel); 1464ca632f55SGrant Likely status = -ENODEV; 1465ca632f55SGrant Likely goto out_error_dma_alloc; 1466ca632f55SGrant Likely } 1467ca632f55SGrant Likely 1468ca632f55SGrant Likely DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; 1469ca632f55SGrant Likely DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; 1470ca632f55SGrant Likely } 1471ca632f55SGrant Likely 1472ca632f55SGrant Likely /* Enable SOC clock */ 1473ca632f55SGrant Likely clk_enable(ssp->clk); 1474ca632f55SGrant Likely 1475ca632f55SGrant Likely /* Load default SSP configuration */ 1476ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1477ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1478ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 1479ca632f55SGrant Likely drv_data->ioaddr); 1480ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 1481ca632f55SGrant Likely | SSCR0_Motorola 1482ca632f55SGrant Likely | SSCR0_DataSize(8), 1483ca632f55SGrant Likely drv_data->ioaddr); 1484ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1485ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 1486ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 1487ca632f55SGrant Likely 1488*7f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 1489*7f86bde9SMika Westerberg (unsigned long)drv_data); 1490ca632f55SGrant Likely 1491ca632f55SGrant Likely /* Register with the SPI framework */ 1492ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1493ca632f55SGrant Likely status = spi_register_master(master); 1494ca632f55SGrant Likely if (status != 0) { 1495ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 1496*7f86bde9SMika Westerberg goto out_error_clock_enabled; 1497ca632f55SGrant Likely } 1498ca632f55SGrant Likely 1499ca632f55SGrant Likely return status; 1500ca632f55SGrant Likely 1501ca632f55SGrant Likely out_error_clock_enabled: 1502ca632f55SGrant Likely clk_disable(ssp->clk); 1503ca632f55SGrant Likely 1504ca632f55SGrant Likely out_error_dma_alloc: 1505ca632f55SGrant Likely if (drv_data->tx_channel != -1) 1506ca632f55SGrant Likely pxa_free_dma(drv_data->tx_channel); 1507ca632f55SGrant Likely if (drv_data->rx_channel != -1) 1508ca632f55SGrant Likely pxa_free_dma(drv_data->rx_channel); 1509ca632f55SGrant Likely 1510ca632f55SGrant Likely out_error_irq_alloc: 1511ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1512ca632f55SGrant Likely 1513ca632f55SGrant Likely out_error_master_alloc: 1514ca632f55SGrant Likely spi_master_put(master); 1515ca632f55SGrant Likely pxa_ssp_free(ssp); 1516ca632f55SGrant Likely return status; 1517ca632f55SGrant Likely } 1518ca632f55SGrant Likely 1519ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1520ca632f55SGrant Likely { 1521ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1522ca632f55SGrant Likely struct ssp_device *ssp; 1523ca632f55SGrant Likely 1524ca632f55SGrant Likely if (!drv_data) 1525ca632f55SGrant Likely return 0; 1526ca632f55SGrant Likely ssp = drv_data->ssp; 1527ca632f55SGrant Likely 1528ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1529ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1530ca632f55SGrant Likely clk_disable(ssp->clk); 1531ca632f55SGrant Likely 1532ca632f55SGrant Likely /* Release DMA */ 1533ca632f55SGrant Likely if (drv_data->master_info->enable_dma) { 1534ca632f55SGrant Likely DRCMR(ssp->drcmr_rx) = 0; 1535ca632f55SGrant Likely DRCMR(ssp->drcmr_tx) = 0; 1536ca632f55SGrant Likely pxa_free_dma(drv_data->tx_channel); 1537ca632f55SGrant Likely pxa_free_dma(drv_data->rx_channel); 1538ca632f55SGrant Likely } 1539ca632f55SGrant Likely 1540ca632f55SGrant Likely /* Release IRQ */ 1541ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1542ca632f55SGrant Likely 1543ca632f55SGrant Likely /* Release SSP */ 1544ca632f55SGrant Likely pxa_ssp_free(ssp); 1545ca632f55SGrant Likely 1546ca632f55SGrant Likely /* Disconnect from the SPI framework */ 1547ca632f55SGrant Likely spi_unregister_master(drv_data->master); 1548ca632f55SGrant Likely 1549ca632f55SGrant Likely /* Prevent double remove */ 1550ca632f55SGrant Likely platform_set_drvdata(pdev, NULL); 1551ca632f55SGrant Likely 1552ca632f55SGrant Likely return 0; 1553ca632f55SGrant Likely } 1554ca632f55SGrant Likely 1555ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1556ca632f55SGrant Likely { 1557ca632f55SGrant Likely int status = 0; 1558ca632f55SGrant Likely 1559ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1560ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1561ca632f55SGrant Likely } 1562ca632f55SGrant Likely 1563ca632f55SGrant Likely #ifdef CONFIG_PM 1564ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1565ca632f55SGrant Likely { 1566ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1567ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1568ca632f55SGrant Likely int status = 0; 1569ca632f55SGrant Likely 1570*7f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1571ca632f55SGrant Likely if (status != 0) 1572ca632f55SGrant Likely return status; 1573ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1574ca632f55SGrant Likely clk_disable(ssp->clk); 1575ca632f55SGrant Likely 1576ca632f55SGrant Likely return 0; 1577ca632f55SGrant Likely } 1578ca632f55SGrant Likely 1579ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1580ca632f55SGrant Likely { 1581ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1582ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1583ca632f55SGrant Likely int status = 0; 1584ca632f55SGrant Likely 1585ca632f55SGrant Likely if (drv_data->rx_channel != -1) 1586ca632f55SGrant Likely DRCMR(drv_data->ssp->drcmr_rx) = 1587ca632f55SGrant Likely DRCMR_MAPVLD | drv_data->rx_channel; 1588ca632f55SGrant Likely if (drv_data->tx_channel != -1) 1589ca632f55SGrant Likely DRCMR(drv_data->ssp->drcmr_tx) = 1590ca632f55SGrant Likely DRCMR_MAPVLD | drv_data->tx_channel; 1591ca632f55SGrant Likely 1592ca632f55SGrant Likely /* Enable the SSP clock */ 1593ca632f55SGrant Likely clk_enable(ssp->clk); 1594ca632f55SGrant Likely 1595ca632f55SGrant Likely /* Start the queue running */ 1596*7f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1597ca632f55SGrant Likely if (status != 0) { 1598ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1599ca632f55SGrant Likely return status; 1600ca632f55SGrant Likely } 1601ca632f55SGrant Likely 1602ca632f55SGrant Likely return 0; 1603ca632f55SGrant Likely } 1604ca632f55SGrant Likely 1605ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1606ca632f55SGrant Likely .suspend = pxa2xx_spi_suspend, 1607ca632f55SGrant Likely .resume = pxa2xx_spi_resume, 1608ca632f55SGrant Likely }; 1609ca632f55SGrant Likely #endif 1610ca632f55SGrant Likely 1611ca632f55SGrant Likely static struct platform_driver driver = { 1612ca632f55SGrant Likely .driver = { 1613ca632f55SGrant Likely .name = "pxa2xx-spi", 1614ca632f55SGrant Likely .owner = THIS_MODULE, 1615ca632f55SGrant Likely #ifdef CONFIG_PM 1616ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1617ca632f55SGrant Likely #endif 1618ca632f55SGrant Likely }, 1619ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1620ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1621ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1622ca632f55SGrant Likely }; 1623ca632f55SGrant Likely 1624ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1625ca632f55SGrant Likely { 1626ca632f55SGrant Likely return platform_driver_register(&driver); 1627ca632f55SGrant Likely } 1628ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1629ca632f55SGrant Likely 1630ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1631ca632f55SGrant Likely { 1632ca632f55SGrant Likely platform_driver_unregister(&driver); 1633ca632f55SGrant Likely } 1634ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1635