1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 5ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 6ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 7ca632f55SGrant Likely * (at your option) any later version. 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 10ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 11ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12ca632f55SGrant Likely * GNU General Public License for more details. 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 15ca632f55SGrant Likely * along with this program; if not, write to the Free Software 16ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17ca632f55SGrant Likely */ 18ca632f55SGrant Likely 19ca632f55SGrant Likely #include <linux/init.h> 20ca632f55SGrant Likely #include <linux/module.h> 21ca632f55SGrant Likely #include <linux/device.h> 22ca632f55SGrant Likely #include <linux/ioport.h> 23ca632f55SGrant Likely #include <linux/errno.h> 24ca632f55SGrant Likely #include <linux/interrupt.h> 25ca632f55SGrant Likely #include <linux/platform_device.h> 26ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 27ca632f55SGrant Likely #include <linux/spi/spi.h> 28ca632f55SGrant Likely #include <linux/workqueue.h> 29ca632f55SGrant Likely #include <linux/delay.h> 30ca632f55SGrant Likely #include <linux/gpio.h> 31ca632f55SGrant Likely #include <linux/slab.h> 323343b7a6SMika Westerberg #include <linux/clk.h> 33ca632f55SGrant Likely 34ca632f55SGrant Likely #include <asm/io.h> 35ca632f55SGrant Likely #include <asm/irq.h> 36ca632f55SGrant Likely #include <asm/delay.h> 37ca632f55SGrant Likely 38cd7bed00SMika Westerberg #include "spi-pxa2xx.h" 39ca632f55SGrant Likely 40ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 41ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 42ca632f55SGrant Likely MODULE_LICENSE("GPL"); 43ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 44ca632f55SGrant Likely 45ca632f55SGrant Likely #define MAX_BUSES 3 46ca632f55SGrant Likely 47ca632f55SGrant Likely #define TIMOUT_DFLT 1000 48ca632f55SGrant Likely 49ca632f55SGrant Likely /* 50ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 51ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 52ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 53ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 54ca632f55SGrant Likely * service and interrupt enables 55ca632f55SGrant Likely */ 56ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 57ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 58ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 59ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 60ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 61ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 62ca632f55SGrant Likely 63ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 64ca632f55SGrant Likely { 65ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 66ca632f55SGrant Likely 67ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 68ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 69ca632f55SGrant Likely return; 70ca632f55SGrant Likely } 71ca632f55SGrant Likely 72ca632f55SGrant Likely if (chip->cs_control) { 73ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 74ca632f55SGrant Likely return; 75ca632f55SGrant Likely } 76ca632f55SGrant Likely 77ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 78ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 79ca632f55SGrant Likely } 80ca632f55SGrant Likely 81ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 82ca632f55SGrant Likely { 83ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 84ca632f55SGrant Likely 85ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 86ca632f55SGrant Likely return; 87ca632f55SGrant Likely 88ca632f55SGrant Likely if (chip->cs_control) { 89ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 90ca632f55SGrant Likely return; 91ca632f55SGrant Likely } 92ca632f55SGrant Likely 93ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 94ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 95ca632f55SGrant Likely } 96ca632f55SGrant Likely 97cd7bed00SMika Westerberg int pxa2xx_spi_flush(struct driver_data *drv_data) 98ca632f55SGrant Likely { 99ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 100ca632f55SGrant Likely 101ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 102ca632f55SGrant Likely 103ca632f55SGrant Likely do { 104ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 105ca632f55SGrant Likely read_SSDR(reg); 106ca632f55SGrant Likely } 107ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 108ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 109ca632f55SGrant Likely 110ca632f55SGrant Likely return limit; 111ca632f55SGrant Likely } 112ca632f55SGrant Likely 113ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 114ca632f55SGrant Likely { 115ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 116ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 117ca632f55SGrant Likely 118ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 119ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 120ca632f55SGrant Likely return 0; 121ca632f55SGrant Likely 122ca632f55SGrant Likely write_SSDR(0, reg); 123ca632f55SGrant Likely drv_data->tx += n_bytes; 124ca632f55SGrant Likely 125ca632f55SGrant Likely return 1; 126ca632f55SGrant Likely } 127ca632f55SGrant Likely 128ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 129ca632f55SGrant Likely { 130ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 131ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 132ca632f55SGrant Likely 133ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 134ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 135ca632f55SGrant Likely read_SSDR(reg); 136ca632f55SGrant Likely drv_data->rx += n_bytes; 137ca632f55SGrant Likely } 138ca632f55SGrant Likely 139ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 140ca632f55SGrant Likely } 141ca632f55SGrant Likely 142ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 143ca632f55SGrant Likely { 144ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 145ca632f55SGrant Likely 146ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 147ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 148ca632f55SGrant Likely return 0; 149ca632f55SGrant Likely 150ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 151ca632f55SGrant Likely ++drv_data->tx; 152ca632f55SGrant Likely 153ca632f55SGrant Likely return 1; 154ca632f55SGrant Likely } 155ca632f55SGrant Likely 156ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 157ca632f55SGrant Likely { 158ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 159ca632f55SGrant Likely 160ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 161ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 162ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 163ca632f55SGrant Likely ++drv_data->rx; 164ca632f55SGrant Likely } 165ca632f55SGrant Likely 166ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 167ca632f55SGrant Likely } 168ca632f55SGrant Likely 169ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 170ca632f55SGrant Likely { 171ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 172ca632f55SGrant Likely 173ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 174ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 175ca632f55SGrant Likely return 0; 176ca632f55SGrant Likely 177ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 178ca632f55SGrant Likely drv_data->tx += 2; 179ca632f55SGrant Likely 180ca632f55SGrant Likely return 1; 181ca632f55SGrant Likely } 182ca632f55SGrant Likely 183ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 184ca632f55SGrant Likely { 185ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 186ca632f55SGrant Likely 187ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 188ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 189ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 190ca632f55SGrant Likely drv_data->rx += 2; 191ca632f55SGrant Likely } 192ca632f55SGrant Likely 193ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 194ca632f55SGrant Likely } 195ca632f55SGrant Likely 196ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 197ca632f55SGrant Likely { 198ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 199ca632f55SGrant Likely 200ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 201ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 202ca632f55SGrant Likely return 0; 203ca632f55SGrant Likely 204ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 205ca632f55SGrant Likely drv_data->tx += 4; 206ca632f55SGrant Likely 207ca632f55SGrant Likely return 1; 208ca632f55SGrant Likely } 209ca632f55SGrant Likely 210ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 211ca632f55SGrant Likely { 212ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 213ca632f55SGrant Likely 214ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 215ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 216ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 217ca632f55SGrant Likely drv_data->rx += 4; 218ca632f55SGrant Likely } 219ca632f55SGrant Likely 220ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 221ca632f55SGrant Likely } 222ca632f55SGrant Likely 223cd7bed00SMika Westerberg void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 224ca632f55SGrant Likely { 225ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 226ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 227ca632f55SGrant Likely 228ca632f55SGrant Likely /* Move to next transfer */ 229ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 230ca632f55SGrant Likely drv_data->cur_transfer = 231ca632f55SGrant Likely list_entry(trans->transfer_list.next, 232ca632f55SGrant Likely struct spi_transfer, 233ca632f55SGrant Likely transfer_list); 234ca632f55SGrant Likely return RUNNING_STATE; 235ca632f55SGrant Likely } else 236ca632f55SGrant Likely return DONE_STATE; 237ca632f55SGrant Likely } 238ca632f55SGrant Likely 239ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 240ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 241ca632f55SGrant Likely { 242ca632f55SGrant Likely struct spi_transfer* last_transfer; 243ca632f55SGrant Likely struct spi_message *msg; 244ca632f55SGrant Likely 245ca632f55SGrant Likely msg = drv_data->cur_msg; 246ca632f55SGrant Likely drv_data->cur_msg = NULL; 247ca632f55SGrant Likely drv_data->cur_transfer = NULL; 248ca632f55SGrant Likely 249ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 250ca632f55SGrant Likely struct spi_transfer, 251ca632f55SGrant Likely transfer_list); 252ca632f55SGrant Likely 253ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 254ca632f55SGrant Likely if (last_transfer->delay_usecs) 255ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 256ca632f55SGrant Likely 257ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 258ca632f55SGrant Likely * a message with an error, or next message is for another chip 259ca632f55SGrant Likely */ 260ca632f55SGrant Likely if (!last_transfer->cs_change) 261ca632f55SGrant Likely cs_deassert(drv_data); 262ca632f55SGrant Likely else { 263ca632f55SGrant Likely struct spi_message *next_msg; 264ca632f55SGrant Likely 265ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 266ca632f55SGrant Likely * the next message is for the same chip. Don't waste 267ca632f55SGrant Likely * time with the following tests unless this was hinted. 268ca632f55SGrant Likely * 269ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 270ca632f55SGrant Likely * after calling msg->complete (below) the driver that 271ca632f55SGrant Likely * sent the current message could be unloaded, which 272ca632f55SGrant Likely * could invalidate the cs_control() callback... 273ca632f55SGrant Likely */ 274ca632f55SGrant Likely 275ca632f55SGrant Likely /* get a pointer to the next message, if any */ 2767f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 277ca632f55SGrant Likely 278ca632f55SGrant Likely /* see if the next and current messages point 279ca632f55SGrant Likely * to the same chip 280ca632f55SGrant Likely */ 281ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 282ca632f55SGrant Likely next_msg = NULL; 283ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 284ca632f55SGrant Likely cs_deassert(drv_data); 285ca632f55SGrant Likely } 286ca632f55SGrant Likely 2877f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 288ca632f55SGrant Likely drv_data->cur_chip = NULL; 289ca632f55SGrant Likely } 290ca632f55SGrant Likely 291ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 292ca632f55SGrant Likely { 293ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 294ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 295ca632f55SGrant Likely u32 sccr1_reg; 296ca632f55SGrant Likely 297ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 298ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 299ca632f55SGrant Likely sccr1_reg |= chip->threshold; 300ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 301ca632f55SGrant Likely } 302ca632f55SGrant Likely 303ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 304ca632f55SGrant Likely { 305ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 306ca632f55SGrant Likely 307ca632f55SGrant Likely /* Stop and reset SSP */ 308ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 309ca632f55SGrant Likely reset_sccr1(drv_data); 310ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 311ca632f55SGrant Likely write_SSTO(0, reg); 312cd7bed00SMika Westerberg pxa2xx_spi_flush(drv_data); 313ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 314ca632f55SGrant Likely 315ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 316ca632f55SGrant Likely 317ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 318ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 319ca632f55SGrant Likely } 320ca632f55SGrant Likely 321ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 322ca632f55SGrant Likely { 323ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 324ca632f55SGrant Likely 325ca632f55SGrant Likely /* Stop SSP */ 326ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 327ca632f55SGrant Likely reset_sccr1(drv_data); 328ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 329ca632f55SGrant Likely write_SSTO(0, reg); 330ca632f55SGrant Likely 331ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 332ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 333ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 334ca632f55SGrant Likely 335ca632f55SGrant Likely /* Transfer delays and chip select release are 336ca632f55SGrant Likely * handled in pump_transfers or giveback 337ca632f55SGrant Likely */ 338ca632f55SGrant Likely 339ca632f55SGrant Likely /* Move to next transfer */ 340cd7bed00SMika Westerberg drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 341ca632f55SGrant Likely 342ca632f55SGrant Likely /* Schedule transfer tasklet */ 343ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 344ca632f55SGrant Likely } 345ca632f55SGrant Likely 346ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 347ca632f55SGrant Likely { 348ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 349ca632f55SGrant Likely 350ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 351ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 352ca632f55SGrant Likely 353ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 354ca632f55SGrant Likely 355ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 356ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 357ca632f55SGrant Likely return IRQ_HANDLED; 358ca632f55SGrant Likely } 359ca632f55SGrant Likely 360ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 361ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 362ca632f55SGrant Likely if (drv_data->read(drv_data)) { 363ca632f55SGrant Likely int_transfer_complete(drv_data); 364ca632f55SGrant Likely return IRQ_HANDLED; 365ca632f55SGrant Likely } 366ca632f55SGrant Likely } 367ca632f55SGrant Likely 368ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 369ca632f55SGrant Likely do { 370ca632f55SGrant Likely if (drv_data->read(drv_data)) { 371ca632f55SGrant Likely int_transfer_complete(drv_data); 372ca632f55SGrant Likely return IRQ_HANDLED; 373ca632f55SGrant Likely } 374ca632f55SGrant Likely } while (drv_data->write(drv_data)); 375ca632f55SGrant Likely 376ca632f55SGrant Likely if (drv_data->read(drv_data)) { 377ca632f55SGrant Likely int_transfer_complete(drv_data); 378ca632f55SGrant Likely return IRQ_HANDLED; 379ca632f55SGrant Likely } 380ca632f55SGrant Likely 381ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 382ca632f55SGrant Likely u32 bytes_left; 383ca632f55SGrant Likely u32 sccr1_reg; 384ca632f55SGrant Likely 385ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 386ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 387ca632f55SGrant Likely 388ca632f55SGrant Likely /* 389ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 390ca632f55SGrant Likely * remaining RX bytes. 391ca632f55SGrant Likely */ 392ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 393ca632f55SGrant Likely 394ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 395ca632f55SGrant Likely 396ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 397ca632f55SGrant Likely switch (drv_data->n_bytes) { 398ca632f55SGrant Likely case 4: 399ca632f55SGrant Likely bytes_left >>= 1; 400ca632f55SGrant Likely case 2: 401ca632f55SGrant Likely bytes_left >>= 1; 402ca632f55SGrant Likely } 403ca632f55SGrant Likely 404ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 405ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 406ca632f55SGrant Likely 407ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 408ca632f55SGrant Likely } 409ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 410ca632f55SGrant Likely } 411ca632f55SGrant Likely 412ca632f55SGrant Likely /* We did something */ 413ca632f55SGrant Likely return IRQ_HANDLED; 414ca632f55SGrant Likely } 415ca632f55SGrant Likely 416ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 417ca632f55SGrant Likely { 418ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 419ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 420ca632f55SGrant Likely u32 sccr1_reg = read_SSCR1(reg); 421ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 422ca632f55SGrant Likely u32 status; 423ca632f55SGrant Likely 424ca632f55SGrant Likely status = read_SSSR(reg); 425ca632f55SGrant Likely 426ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 427ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 428ca632f55SGrant Likely mask &= ~SSSR_TFS; 429ca632f55SGrant Likely 430ca632f55SGrant Likely if (!(status & mask)) 431ca632f55SGrant Likely return IRQ_NONE; 432ca632f55SGrant Likely 433ca632f55SGrant Likely if (!drv_data->cur_msg) { 434ca632f55SGrant Likely 435ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 436ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 437ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 438ca632f55SGrant Likely write_SSTO(0, reg); 439ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 440ca632f55SGrant Likely 441ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "bad message state " 442ca632f55SGrant Likely "in interrupt handler\n"); 443ca632f55SGrant Likely 444ca632f55SGrant Likely /* Never fail */ 445ca632f55SGrant Likely return IRQ_HANDLED; 446ca632f55SGrant Likely } 447ca632f55SGrant Likely 448ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 449ca632f55SGrant Likely } 450ca632f55SGrant Likely 4513343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 452ca632f55SGrant Likely { 4533343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 4543343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 4553343b7a6SMika Westerberg 4563343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 457ca632f55SGrant Likely 458ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 459ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 460ca632f55SGrant Likely else 461ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 462ca632f55SGrant Likely } 463ca632f55SGrant Likely 464ca632f55SGrant Likely static void pump_transfers(unsigned long data) 465ca632f55SGrant Likely { 466ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 467ca632f55SGrant Likely struct spi_message *message = NULL; 468ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 469ca632f55SGrant Likely struct spi_transfer *previous = NULL; 470ca632f55SGrant Likely struct chip_data *chip = NULL; 471ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 472ca632f55SGrant Likely u32 clk_div = 0; 473ca632f55SGrant Likely u8 bits = 0; 474ca632f55SGrant Likely u32 speed = 0; 475ca632f55SGrant Likely u32 cr0; 476ca632f55SGrant Likely u32 cr1; 477ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 478ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 479ca632f55SGrant Likely 480ca632f55SGrant Likely /* Get current state information */ 481ca632f55SGrant Likely message = drv_data->cur_msg; 482ca632f55SGrant Likely transfer = drv_data->cur_transfer; 483ca632f55SGrant Likely chip = drv_data->cur_chip; 484ca632f55SGrant Likely 485ca632f55SGrant Likely /* Handle for abort */ 486ca632f55SGrant Likely if (message->state == ERROR_STATE) { 487ca632f55SGrant Likely message->status = -EIO; 488ca632f55SGrant Likely giveback(drv_data); 489ca632f55SGrant Likely return; 490ca632f55SGrant Likely } 491ca632f55SGrant Likely 492ca632f55SGrant Likely /* Handle end of message */ 493ca632f55SGrant Likely if (message->state == DONE_STATE) { 494ca632f55SGrant Likely message->status = 0; 495ca632f55SGrant Likely giveback(drv_data); 496ca632f55SGrant Likely return; 497ca632f55SGrant Likely } 498ca632f55SGrant Likely 499ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 500ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 501ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 502ca632f55SGrant Likely struct spi_transfer, 503ca632f55SGrant Likely transfer_list); 504ca632f55SGrant Likely if (previous->delay_usecs) 505ca632f55SGrant Likely udelay(previous->delay_usecs); 506ca632f55SGrant Likely 507ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 508ca632f55SGrant Likely if (previous->cs_change) 509ca632f55SGrant Likely cs_deassert(drv_data); 510ca632f55SGrant Likely } 511ca632f55SGrant Likely 512cd7bed00SMika Westerberg /* Check if we can DMA this transfer */ 513cd7bed00SMika Westerberg if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 514ca632f55SGrant Likely 515ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 516ca632f55SGrant Likely if (message->is_dma_mapped 517ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 518ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 519ca632f55SGrant Likely "pump_transfers: mapped transfer length " 520ca632f55SGrant Likely "of %u is greater than %d\n", 521ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 522ca632f55SGrant Likely message->status = -EINVAL; 523ca632f55SGrant Likely giveback(drv_data); 524ca632f55SGrant Likely return; 525ca632f55SGrant Likely } 526ca632f55SGrant Likely 527ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 528ca632f55SGrant Likely if (printk_ratelimit()) 529ca632f55SGrant Likely dev_warn(&message->spi->dev, "pump_transfers: " 530ca632f55SGrant Likely "DMA disabled for transfer length %ld " 531ca632f55SGrant Likely "greater than %d\n", 532ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 533ca632f55SGrant Likely } 534ca632f55SGrant Likely 535ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 536cd7bed00SMika Westerberg if (pxa2xx_spi_flush(drv_data) == 0) { 537ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 538ca632f55SGrant Likely message->status = -EIO; 539ca632f55SGrant Likely giveback(drv_data); 540ca632f55SGrant Likely return; 541ca632f55SGrant Likely } 542ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 543ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 544ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 545ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 546ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 547ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 548ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 549cd7bed00SMika Westerberg drv_data->len = transfer->len; 550ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 551ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 552ca632f55SGrant Likely 553ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 554ca632f55SGrant Likely cr0 = chip->cr0; 555ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 556ca632f55SGrant Likely 557ca632f55SGrant Likely bits = chip->bits_per_word; 558ca632f55SGrant Likely speed = chip->speed_hz; 559ca632f55SGrant Likely 560ca632f55SGrant Likely if (transfer->speed_hz) 561ca632f55SGrant Likely speed = transfer->speed_hz; 562ca632f55SGrant Likely 563ca632f55SGrant Likely if (transfer->bits_per_word) 564ca632f55SGrant Likely bits = transfer->bits_per_word; 565ca632f55SGrant Likely 5663343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, speed); 567ca632f55SGrant Likely 568ca632f55SGrant Likely if (bits <= 8) { 569ca632f55SGrant Likely drv_data->n_bytes = 1; 570ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 571ca632f55SGrant Likely u8_reader : null_reader; 572ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 573ca632f55SGrant Likely u8_writer : null_writer; 574ca632f55SGrant Likely } else if (bits <= 16) { 575ca632f55SGrant Likely drv_data->n_bytes = 2; 576ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 577ca632f55SGrant Likely u16_reader : null_reader; 578ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 579ca632f55SGrant Likely u16_writer : null_writer; 580ca632f55SGrant Likely } else if (bits <= 32) { 581ca632f55SGrant Likely drv_data->n_bytes = 4; 582ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 583ca632f55SGrant Likely u32_reader : null_reader; 584ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 585ca632f55SGrant Likely u32_writer : null_writer; 586ca632f55SGrant Likely } 587ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 588ca632f55SGrant Likely * thresholds and burst also */ 589ca632f55SGrant Likely if (chip->enable_dma) { 590cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 591cd7bed00SMika Westerberg message->spi, 592ca632f55SGrant Likely bits, &dma_burst, 593ca632f55SGrant Likely &dma_thresh)) 594ca632f55SGrant Likely if (printk_ratelimit()) 595ca632f55SGrant Likely dev_warn(&message->spi->dev, 596ca632f55SGrant Likely "pump_transfers: " 597ca632f55SGrant Likely "DMA burst size reduced to " 598ca632f55SGrant Likely "match bits_per_word\n"); 599ca632f55SGrant Likely } 600ca632f55SGrant Likely 601ca632f55SGrant Likely cr0 = clk_div 602ca632f55SGrant Likely | SSCR0_Motorola 603ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 604ca632f55SGrant Likely | SSCR0_SSE 605ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 606ca632f55SGrant Likely } 607ca632f55SGrant Likely 608ca632f55SGrant Likely message->state = RUNNING_STATE; 609ca632f55SGrant Likely 610ca632f55SGrant Likely drv_data->dma_mapped = 0; 611cd7bed00SMika Westerberg if (pxa2xx_spi_dma_is_possible(drv_data->len)) 612cd7bed00SMika Westerberg drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 613ca632f55SGrant Likely if (drv_data->dma_mapped) { 614ca632f55SGrant Likely 615ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 616cd7bed00SMika Westerberg drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 617ca632f55SGrant Likely 618cd7bed00SMika Westerberg pxa2xx_spi_dma_prepare(drv_data, dma_burst); 619ca632f55SGrant Likely 620ca632f55SGrant Likely /* Clear status and start DMA engine */ 621ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 622ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 623cd7bed00SMika Westerberg 624cd7bed00SMika Westerberg pxa2xx_spi_dma_start(drv_data); 625ca632f55SGrant Likely } else { 626ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 627ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 628ca632f55SGrant Likely 629ca632f55SGrant Likely /* Clear status */ 630ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 631ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 632ca632f55SGrant Likely } 633ca632f55SGrant Likely 634ca632f55SGrant Likely /* see if we need to reload the config registers */ 635ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 636ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 637ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 638ca632f55SGrant Likely 639ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 640ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 641ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 642ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 643ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 644ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 645ca632f55SGrant Likely /* restart the SSP */ 646ca632f55SGrant Likely write_SSCR0(cr0, reg); 647ca632f55SGrant Likely 648ca632f55SGrant Likely } else { 649ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 650ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 651ca632f55SGrant Likely } 652ca632f55SGrant Likely 653ca632f55SGrant Likely cs_assert(drv_data); 654ca632f55SGrant Likely 655ca632f55SGrant Likely /* after chip select, release the data by enabling service 656ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 657ca632f55SGrant Likely write_SSCR1(cr1, reg); 658ca632f55SGrant Likely } 659ca632f55SGrant Likely 6607f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 6617f86bde9SMika Westerberg struct spi_message *msg) 662ca632f55SGrant Likely { 6637f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 664ca632f55SGrant Likely 6657f86bde9SMika Westerberg drv_data->cur_msg = msg; 666ca632f55SGrant Likely /* Initial message state*/ 667ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 668ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 669ca632f55SGrant Likely struct spi_transfer, 670ca632f55SGrant Likely transfer_list); 671ca632f55SGrant Likely 672ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 673ca632f55SGrant Likely * chip configuration */ 674ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 675ca632f55SGrant Likely 676ca632f55SGrant Likely /* Mark as busy and launch transfers */ 677ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 678ca632f55SGrant Likely return 0; 679ca632f55SGrant Likely } 680ca632f55SGrant Likely 681ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 682ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 683ca632f55SGrant Likely { 684ca632f55SGrant Likely int err = 0; 685ca632f55SGrant Likely 686ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 687ca632f55SGrant Likely return 0; 688ca632f55SGrant Likely 689ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 690ca632f55SGrant Likely * different chip_info, release previously requested GPIO 691ca632f55SGrant Likely */ 692ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 693ca632f55SGrant Likely gpio_free(chip->gpio_cs); 694ca632f55SGrant Likely 695ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 696ca632f55SGrant Likely if (chip_info->cs_control) { 697ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 698ca632f55SGrant Likely return 0; 699ca632f55SGrant Likely } 700ca632f55SGrant Likely 701ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 702ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 703ca632f55SGrant Likely if (err) { 704ca632f55SGrant Likely dev_err(&spi->dev, "failed to request chip select " 705ca632f55SGrant Likely "GPIO%d\n", chip_info->gpio_cs); 706ca632f55SGrant Likely return err; 707ca632f55SGrant Likely } 708ca632f55SGrant Likely 709ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 710ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 711ca632f55SGrant Likely 712ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 713ca632f55SGrant Likely !chip->gpio_cs_inverted); 714ca632f55SGrant Likely } 715ca632f55SGrant Likely 716ca632f55SGrant Likely return err; 717ca632f55SGrant Likely } 718ca632f55SGrant Likely 719ca632f55SGrant Likely static int setup(struct spi_device *spi) 720ca632f55SGrant Likely { 721ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 722ca632f55SGrant Likely struct chip_data *chip; 723ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 724ca632f55SGrant Likely unsigned int clk_div; 725ca632f55SGrant Likely uint tx_thres = TX_THRESH_DFLT; 726ca632f55SGrant Likely uint rx_thres = RX_THRESH_DFLT; 727ca632f55SGrant Likely 728ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data) 729ca632f55SGrant Likely && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { 730ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 731ca632f55SGrant Likely "b/w not 4-32 for type non-PXA25x_SSP\n", 732ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 733ca632f55SGrant Likely return -EINVAL; 734ca632f55SGrant Likely } else if (pxa25x_ssp_comp(drv_data) 735ca632f55SGrant Likely && (spi->bits_per_word < 4 736ca632f55SGrant Likely || spi->bits_per_word > 16)) { 737ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 738ca632f55SGrant Likely "b/w not 4-16 for type PXA25x_SSP\n", 739ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 740ca632f55SGrant Likely return -EINVAL; 741ca632f55SGrant Likely } 742ca632f55SGrant Likely 743ca632f55SGrant Likely /* Only alloc on first setup */ 744ca632f55SGrant Likely chip = spi_get_ctldata(spi); 745ca632f55SGrant Likely if (!chip) { 746ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 747ca632f55SGrant Likely if (!chip) { 748ca632f55SGrant Likely dev_err(&spi->dev, 749ca632f55SGrant Likely "failed setup: can't allocate chip data\n"); 750ca632f55SGrant Likely return -ENOMEM; 751ca632f55SGrant Likely } 752ca632f55SGrant Likely 753ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 754ca632f55SGrant Likely if (spi->chip_select > 4) { 755ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: " 756ca632f55SGrant Likely "cs number must not be > 4.\n"); 757ca632f55SGrant Likely kfree(chip); 758ca632f55SGrant Likely return -EINVAL; 759ca632f55SGrant Likely } 760ca632f55SGrant Likely 761ca632f55SGrant Likely chip->frm = spi->chip_select; 762ca632f55SGrant Likely } else 763ca632f55SGrant Likely chip->gpio_cs = -1; 764ca632f55SGrant Likely chip->enable_dma = 0; 765ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 766ca632f55SGrant Likely } 767ca632f55SGrant Likely 768ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 769ca632f55SGrant Likely * if chip_info exists, use it */ 770ca632f55SGrant Likely chip_info = spi->controller_data; 771ca632f55SGrant Likely 772ca632f55SGrant Likely /* chip_info isn't always needed */ 773ca632f55SGrant Likely chip->cr1 = 0; 774ca632f55SGrant Likely if (chip_info) { 775ca632f55SGrant Likely if (chip_info->timeout) 776ca632f55SGrant Likely chip->timeout = chip_info->timeout; 777ca632f55SGrant Likely if (chip_info->tx_threshold) 778ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 779ca632f55SGrant Likely if (chip_info->rx_threshold) 780ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 781ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 782ca632f55SGrant Likely chip->dma_threshold = 0; 783ca632f55SGrant Likely if (chip_info->enable_loopback) 784ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 785ca632f55SGrant Likely } 786ca632f55SGrant Likely 787ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 788ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 789ca632f55SGrant Likely 790ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 791ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 792ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 793ca632f55SGrant Likely if (chip->enable_dma) { 794ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 795cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 796cd7bed00SMika Westerberg spi->bits_per_word, 797ca632f55SGrant Likely &chip->dma_burst_size, 798ca632f55SGrant Likely &chip->dma_threshold)) { 799ca632f55SGrant Likely dev_warn(&spi->dev, "in setup: DMA burst size reduced " 800ca632f55SGrant Likely "to match bits_per_word\n"); 801ca632f55SGrant Likely } 802ca632f55SGrant Likely } 803ca632f55SGrant Likely 8043343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 805ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 806ca632f55SGrant Likely 807ca632f55SGrant Likely chip->cr0 = clk_div 808ca632f55SGrant Likely | SSCR0_Motorola 809ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 810ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 811ca632f55SGrant Likely | SSCR0_SSE 812ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 813ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 814ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 815ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 816ca632f55SGrant Likely 817ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 818ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 819ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 8203343b7a6SMika Westerberg drv_data->max_clk_rate 821ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 822ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 823ca632f55SGrant Likely else 824ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 8253343b7a6SMika Westerberg drv_data->max_clk_rate / 2 826ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 827ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 828ca632f55SGrant Likely 829ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 830ca632f55SGrant Likely chip->n_bytes = 1; 831ca632f55SGrant Likely chip->read = u8_reader; 832ca632f55SGrant Likely chip->write = u8_writer; 833ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 834ca632f55SGrant Likely chip->n_bytes = 2; 835ca632f55SGrant Likely chip->read = u16_reader; 836ca632f55SGrant Likely chip->write = u16_writer; 837ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 838ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 839ca632f55SGrant Likely chip->n_bytes = 4; 840ca632f55SGrant Likely chip->read = u32_reader; 841ca632f55SGrant Likely chip->write = u32_writer; 842ca632f55SGrant Likely } else { 843ca632f55SGrant Likely dev_err(&spi->dev, "invalid wordsize\n"); 844ca632f55SGrant Likely return -ENODEV; 845ca632f55SGrant Likely } 846ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 847ca632f55SGrant Likely 848ca632f55SGrant Likely spi_set_ctldata(spi, chip); 849ca632f55SGrant Likely 850ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 851ca632f55SGrant Likely return 0; 852ca632f55SGrant Likely 853ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 854ca632f55SGrant Likely } 855ca632f55SGrant Likely 856ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 857ca632f55SGrant Likely { 858ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 859ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 860ca632f55SGrant Likely 861ca632f55SGrant Likely if (!chip) 862ca632f55SGrant Likely return; 863ca632f55SGrant Likely 864ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 865ca632f55SGrant Likely gpio_free(chip->gpio_cs); 866ca632f55SGrant Likely 867ca632f55SGrant Likely kfree(chip); 868ca632f55SGrant Likely } 869ca632f55SGrant Likely 870fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 871ca632f55SGrant Likely { 872ca632f55SGrant Likely struct device *dev = &pdev->dev; 873ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 874ca632f55SGrant Likely struct spi_master *master; 875ca632f55SGrant Likely struct driver_data *drv_data; 876ca632f55SGrant Likely struct ssp_device *ssp; 877ca632f55SGrant Likely int status; 878ca632f55SGrant Likely 879851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 880851bacf5SMika Westerberg if (!platform_info) { 881851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 882851bacf5SMika Westerberg return -ENODEV; 883851bacf5SMika Westerberg } 884ca632f55SGrant Likely 885ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 886851bacf5SMika Westerberg if (!ssp) 887851bacf5SMika Westerberg ssp = &platform_info->ssp; 888851bacf5SMika Westerberg 889851bacf5SMika Westerberg if (!ssp->mmio_base) { 890851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 891ca632f55SGrant Likely return -ENODEV; 892ca632f55SGrant Likely } 893ca632f55SGrant Likely 894ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 895ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 896ca632f55SGrant Likely if (!master) { 897ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 898ca632f55SGrant Likely pxa_ssp_free(ssp); 899ca632f55SGrant Likely return -ENOMEM; 900ca632f55SGrant Likely } 901ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 902ca632f55SGrant Likely drv_data->master = master; 903ca632f55SGrant Likely drv_data->master_info = platform_info; 904ca632f55SGrant Likely drv_data->pdev = pdev; 905ca632f55SGrant Likely drv_data->ssp = ssp; 906ca632f55SGrant Likely 907ca632f55SGrant Likely master->dev.parent = &pdev->dev; 908ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 909ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 910ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 911ca632f55SGrant Likely 912851bacf5SMika Westerberg master->bus_num = ssp->port_id; 913ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 914ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 915ca632f55SGrant Likely master->cleanup = cleanup; 916ca632f55SGrant Likely master->setup = setup; 9177f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 918ca632f55SGrant Likely 919ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 9202b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 921ca632f55SGrant Likely 922ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 923ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 924ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 925ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 926ca632f55SGrant Likely drv_data->dma_cr1 = 0; 927ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 928ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 929ca632f55SGrant Likely } else { 930ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 931*5928808eSMika Westerberg drv_data->dma_cr1 = DEFAULT_DMA_CR1; 932ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 933ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 934ca632f55SGrant Likely } 935ca632f55SGrant Likely 936ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 937ca632f55SGrant Likely drv_data); 938ca632f55SGrant Likely if (status < 0) { 939ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 940ca632f55SGrant Likely goto out_error_master_alloc; 941ca632f55SGrant Likely } 942ca632f55SGrant Likely 943ca632f55SGrant Likely /* Setup DMA if requested */ 944ca632f55SGrant Likely drv_data->tx_channel = -1; 945ca632f55SGrant Likely drv_data->rx_channel = -1; 946ca632f55SGrant Likely if (platform_info->enable_dma) { 947cd7bed00SMika Westerberg status = pxa2xx_spi_dma_setup(drv_data); 948cd7bed00SMika Westerberg if (status) { 949cd7bed00SMika Westerberg dev_warn(dev, "failed to setup DMA, using PIO\n"); 950cd7bed00SMika Westerberg platform_info->enable_dma = false; 951ca632f55SGrant Likely } 952ca632f55SGrant Likely } 953ca632f55SGrant Likely 954ca632f55SGrant Likely /* Enable SOC clock */ 9553343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 9563343b7a6SMika Westerberg 9573343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 958ca632f55SGrant Likely 959ca632f55SGrant Likely /* Load default SSP configuration */ 960ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 961ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 962ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 963ca632f55SGrant Likely drv_data->ioaddr); 964ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 965ca632f55SGrant Likely | SSCR0_Motorola 966ca632f55SGrant Likely | SSCR0_DataSize(8), 967ca632f55SGrant Likely drv_data->ioaddr); 968ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 969ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 970ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 971ca632f55SGrant Likely 9727f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 9737f86bde9SMika Westerberg (unsigned long)drv_data); 974ca632f55SGrant Likely 975ca632f55SGrant Likely /* Register with the SPI framework */ 976ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 977ca632f55SGrant Likely status = spi_register_master(master); 978ca632f55SGrant Likely if (status != 0) { 979ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 9807f86bde9SMika Westerberg goto out_error_clock_enabled; 981ca632f55SGrant Likely } 982ca632f55SGrant Likely 983ca632f55SGrant Likely return status; 984ca632f55SGrant Likely 985ca632f55SGrant Likely out_error_clock_enabled: 9863343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 987cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 988ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 989ca632f55SGrant Likely 990ca632f55SGrant Likely out_error_master_alloc: 991ca632f55SGrant Likely spi_master_put(master); 992ca632f55SGrant Likely pxa_ssp_free(ssp); 993ca632f55SGrant Likely return status; 994ca632f55SGrant Likely } 995ca632f55SGrant Likely 996ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 997ca632f55SGrant Likely { 998ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 999ca632f55SGrant Likely struct ssp_device *ssp; 1000ca632f55SGrant Likely 1001ca632f55SGrant Likely if (!drv_data) 1002ca632f55SGrant Likely return 0; 1003ca632f55SGrant Likely ssp = drv_data->ssp; 1004ca632f55SGrant Likely 1005ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1006ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 10073343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1008ca632f55SGrant Likely 1009ca632f55SGrant Likely /* Release DMA */ 1010cd7bed00SMika Westerberg if (drv_data->master_info->enable_dma) 1011cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1012ca632f55SGrant Likely 1013ca632f55SGrant Likely /* Release IRQ */ 1014ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely /* Release SSP */ 1017ca632f55SGrant Likely pxa_ssp_free(ssp); 1018ca632f55SGrant Likely 1019ca632f55SGrant Likely /* Disconnect from the SPI framework */ 1020ca632f55SGrant Likely spi_unregister_master(drv_data->master); 1021ca632f55SGrant Likely 1022ca632f55SGrant Likely /* Prevent double remove */ 1023ca632f55SGrant Likely platform_set_drvdata(pdev, NULL); 1024ca632f55SGrant Likely 1025ca632f55SGrant Likely return 0; 1026ca632f55SGrant Likely } 1027ca632f55SGrant Likely 1028ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1029ca632f55SGrant Likely { 1030ca632f55SGrant Likely int status = 0; 1031ca632f55SGrant Likely 1032ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1033ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1034ca632f55SGrant Likely } 1035ca632f55SGrant Likely 1036ca632f55SGrant Likely #ifdef CONFIG_PM 1037ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1038ca632f55SGrant Likely { 1039ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1040ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1041ca632f55SGrant Likely int status = 0; 1042ca632f55SGrant Likely 10437f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1044ca632f55SGrant Likely if (status != 0) 1045ca632f55SGrant Likely return status; 1046ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 10473343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1048ca632f55SGrant Likely 1049ca632f55SGrant Likely return 0; 1050ca632f55SGrant Likely } 1051ca632f55SGrant Likely 1052ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1053ca632f55SGrant Likely { 1054ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1055ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1056ca632f55SGrant Likely int status = 0; 1057ca632f55SGrant Likely 1058cd7bed00SMika Westerberg pxa2xx_spi_dma_resume(drv_data); 1059ca632f55SGrant Likely 1060ca632f55SGrant Likely /* Enable the SSP clock */ 10613343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1062ca632f55SGrant Likely 1063ca632f55SGrant Likely /* Start the queue running */ 10647f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1065ca632f55SGrant Likely if (status != 0) { 1066ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1067ca632f55SGrant Likely return status; 1068ca632f55SGrant Likely } 1069ca632f55SGrant Likely 1070ca632f55SGrant Likely return 0; 1071ca632f55SGrant Likely } 1072ca632f55SGrant Likely 1073ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1074ca632f55SGrant Likely .suspend = pxa2xx_spi_suspend, 1075ca632f55SGrant Likely .resume = pxa2xx_spi_resume, 1076ca632f55SGrant Likely }; 1077ca632f55SGrant Likely #endif 1078ca632f55SGrant Likely 1079ca632f55SGrant Likely static struct platform_driver driver = { 1080ca632f55SGrant Likely .driver = { 1081ca632f55SGrant Likely .name = "pxa2xx-spi", 1082ca632f55SGrant Likely .owner = THIS_MODULE, 1083ca632f55SGrant Likely #ifdef CONFIG_PM 1084ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1085ca632f55SGrant Likely #endif 1086ca632f55SGrant Likely }, 1087ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1088ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1089ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1090ca632f55SGrant Likely }; 1091ca632f55SGrant Likely 1092ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1093ca632f55SGrant Likely { 1094ca632f55SGrant Likely return platform_driver_register(&driver); 1095ca632f55SGrant Likely } 1096ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1097ca632f55SGrant Likely 1098ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1099ca632f55SGrant Likely { 1100ca632f55SGrant Likely platform_driver_unregister(&driver); 1101ca632f55SGrant Likely } 1102ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1103