1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 5ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 6ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 7ca632f55SGrant Likely * (at your option) any later version. 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 10ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 11ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12ca632f55SGrant Likely * GNU General Public License for more details. 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 15ca632f55SGrant Likely * along with this program; if not, write to the Free Software 16ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17ca632f55SGrant Likely */ 18ca632f55SGrant Likely 19ca632f55SGrant Likely #include <linux/init.h> 20ca632f55SGrant Likely #include <linux/module.h> 21ca632f55SGrant Likely #include <linux/device.h> 22ca632f55SGrant Likely #include <linux/ioport.h> 23ca632f55SGrant Likely #include <linux/errno.h> 24ca632f55SGrant Likely #include <linux/interrupt.h> 25ca632f55SGrant Likely #include <linux/platform_device.h> 26ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 27ca632f55SGrant Likely #include <linux/dma-mapping.h> 28ca632f55SGrant Likely #include <linux/spi/spi.h> 29ca632f55SGrant Likely #include <linux/workqueue.h> 30ca632f55SGrant Likely #include <linux/delay.h> 31ca632f55SGrant Likely #include <linux/gpio.h> 32ca632f55SGrant Likely #include <linux/slab.h> 33*3343b7a6SMika Westerberg #include <linux/clk.h> 34ca632f55SGrant Likely 35ca632f55SGrant Likely #include <asm/io.h> 36ca632f55SGrant Likely #include <asm/irq.h> 37ca632f55SGrant Likely #include <asm/delay.h> 38ca632f55SGrant Likely 39ca632f55SGrant Likely 40ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 41ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 42ca632f55SGrant Likely MODULE_LICENSE("GPL"); 43ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 44ca632f55SGrant Likely 45ca632f55SGrant Likely #define MAX_BUSES 3 46ca632f55SGrant Likely 47ca632f55SGrant Likely #define TIMOUT_DFLT 1000 48ca632f55SGrant Likely 49ca632f55SGrant Likely #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) 50ca632f55SGrant Likely #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) 512b9b84f4SMika Westerberg #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT) 52ca632f55SGrant Likely #define MAX_DMA_LEN 8191 53ca632f55SGrant Likely #define DMA_ALIGNMENT 8 54ca632f55SGrant Likely 55ca632f55SGrant Likely /* 56ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 57ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 58ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 59ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 60ca632f55SGrant Likely * service and interrupt enables 61ca632f55SGrant Likely */ 62ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 63ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 64ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 65ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 66ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 67ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 68ca632f55SGrant Likely 69ca632f55SGrant Likely #define DEFINE_SSP_REG(reg, off) \ 70ca632f55SGrant Likely static inline u32 read_##reg(void const __iomem *p) \ 71ca632f55SGrant Likely { return __raw_readl(p + (off)); } \ 72ca632f55SGrant Likely \ 73ca632f55SGrant Likely static inline void write_##reg(u32 v, void __iomem *p) \ 74ca632f55SGrant Likely { __raw_writel(v, p + (off)); } 75ca632f55SGrant Likely 76ca632f55SGrant Likely DEFINE_SSP_REG(SSCR0, 0x00) 77ca632f55SGrant Likely DEFINE_SSP_REG(SSCR1, 0x04) 78ca632f55SGrant Likely DEFINE_SSP_REG(SSSR, 0x08) 79ca632f55SGrant Likely DEFINE_SSP_REG(SSITR, 0x0c) 80ca632f55SGrant Likely DEFINE_SSP_REG(SSDR, 0x10) 81ca632f55SGrant Likely DEFINE_SSP_REG(SSTO, 0x28) 82ca632f55SGrant Likely DEFINE_SSP_REG(SSPSP, 0x2c) 83ca632f55SGrant Likely 84ca632f55SGrant Likely #define START_STATE ((void*)0) 85ca632f55SGrant Likely #define RUNNING_STATE ((void*)1) 86ca632f55SGrant Likely #define DONE_STATE ((void*)2) 87ca632f55SGrant Likely #define ERROR_STATE ((void*)-1) 88ca632f55SGrant Likely 89ca632f55SGrant Likely struct driver_data { 90ca632f55SGrant Likely /* Driver model hookup */ 91ca632f55SGrant Likely struct platform_device *pdev; 92ca632f55SGrant Likely 93ca632f55SGrant Likely /* SSP Info */ 94ca632f55SGrant Likely struct ssp_device *ssp; 95ca632f55SGrant Likely 96ca632f55SGrant Likely /* SPI framework hookup */ 97ca632f55SGrant Likely enum pxa_ssp_type ssp_type; 98ca632f55SGrant Likely struct spi_master *master; 99ca632f55SGrant Likely 100ca632f55SGrant Likely /* PXA hookup */ 101ca632f55SGrant Likely struct pxa2xx_spi_master *master_info; 102ca632f55SGrant Likely 103ca632f55SGrant Likely /* DMA setup stuff */ 104ca632f55SGrant Likely int rx_channel; 105ca632f55SGrant Likely int tx_channel; 106ca632f55SGrant Likely u32 *null_dma_buf; 107ca632f55SGrant Likely 108ca632f55SGrant Likely /* SSP register addresses */ 109ca632f55SGrant Likely void __iomem *ioaddr; 110ca632f55SGrant Likely u32 ssdr_physical; 111ca632f55SGrant Likely 112ca632f55SGrant Likely /* SSP masks*/ 113ca632f55SGrant Likely u32 dma_cr1; 114ca632f55SGrant Likely u32 int_cr1; 115ca632f55SGrant Likely u32 clear_sr; 116ca632f55SGrant Likely u32 mask_sr; 117ca632f55SGrant Likely 118*3343b7a6SMika Westerberg /* Maximun clock rate */ 119*3343b7a6SMika Westerberg unsigned long max_clk_rate; 120*3343b7a6SMika Westerberg 121ca632f55SGrant Likely /* Message Transfer pump */ 122ca632f55SGrant Likely struct tasklet_struct pump_transfers; 123ca632f55SGrant Likely 124ca632f55SGrant Likely /* Current message transfer state info */ 125ca632f55SGrant Likely struct spi_message* cur_msg; 126ca632f55SGrant Likely struct spi_transfer* cur_transfer; 127ca632f55SGrant Likely struct chip_data *cur_chip; 128ca632f55SGrant Likely size_t len; 129ca632f55SGrant Likely void *tx; 130ca632f55SGrant Likely void *tx_end; 131ca632f55SGrant Likely void *rx; 132ca632f55SGrant Likely void *rx_end; 133ca632f55SGrant Likely int dma_mapped; 134ca632f55SGrant Likely dma_addr_t rx_dma; 135ca632f55SGrant Likely dma_addr_t tx_dma; 136ca632f55SGrant Likely size_t rx_map_len; 137ca632f55SGrant Likely size_t tx_map_len; 138ca632f55SGrant Likely u8 n_bytes; 139ca632f55SGrant Likely u32 dma_width; 140ca632f55SGrant Likely int (*write)(struct driver_data *drv_data); 141ca632f55SGrant Likely int (*read)(struct driver_data *drv_data); 142ca632f55SGrant Likely irqreturn_t (*transfer_handler)(struct driver_data *drv_data); 143ca632f55SGrant Likely void (*cs_control)(u32 command); 144ca632f55SGrant Likely }; 145ca632f55SGrant Likely 146ca632f55SGrant Likely struct chip_data { 147ca632f55SGrant Likely u32 cr0; 148ca632f55SGrant Likely u32 cr1; 149ca632f55SGrant Likely u32 psp; 150ca632f55SGrant Likely u32 timeout; 151ca632f55SGrant Likely u8 n_bytes; 152ca632f55SGrant Likely u32 dma_width; 153ca632f55SGrant Likely u32 dma_burst_size; 154ca632f55SGrant Likely u32 threshold; 155ca632f55SGrant Likely u32 dma_threshold; 156ca632f55SGrant Likely u8 enable_dma; 157ca632f55SGrant Likely u8 bits_per_word; 158ca632f55SGrant Likely u32 speed_hz; 159ca632f55SGrant Likely union { 160ca632f55SGrant Likely int gpio_cs; 161ca632f55SGrant Likely unsigned int frm; 162ca632f55SGrant Likely }; 163ca632f55SGrant Likely int gpio_cs_inverted; 164ca632f55SGrant Likely int (*write)(struct driver_data *drv_data); 165ca632f55SGrant Likely int (*read)(struct driver_data *drv_data); 166ca632f55SGrant Likely void (*cs_control)(u32 command); 167ca632f55SGrant Likely }; 168ca632f55SGrant Likely 169ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 170ca632f55SGrant Likely { 171ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 172ca632f55SGrant Likely 173ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 174ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 175ca632f55SGrant Likely return; 176ca632f55SGrant Likely } 177ca632f55SGrant Likely 178ca632f55SGrant Likely if (chip->cs_control) { 179ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 180ca632f55SGrant Likely return; 181ca632f55SGrant Likely } 182ca632f55SGrant Likely 183ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 184ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 185ca632f55SGrant Likely } 186ca632f55SGrant Likely 187ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 188ca632f55SGrant Likely { 189ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 190ca632f55SGrant Likely 191ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 192ca632f55SGrant Likely return; 193ca632f55SGrant Likely 194ca632f55SGrant Likely if (chip->cs_control) { 195ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 196ca632f55SGrant Likely return; 197ca632f55SGrant Likely } 198ca632f55SGrant Likely 199ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 200ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 201ca632f55SGrant Likely } 202ca632f55SGrant Likely 203ca632f55SGrant Likely static void write_SSSR_CS(struct driver_data *drv_data, u32 val) 204ca632f55SGrant Likely { 205ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 206ca632f55SGrant Likely 207ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 208ca632f55SGrant Likely val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; 209ca632f55SGrant Likely 210ca632f55SGrant Likely write_SSSR(val, reg); 211ca632f55SGrant Likely } 212ca632f55SGrant Likely 213ca632f55SGrant Likely static int pxa25x_ssp_comp(struct driver_data *drv_data) 214ca632f55SGrant Likely { 215ca632f55SGrant Likely if (drv_data->ssp_type == PXA25x_SSP) 216ca632f55SGrant Likely return 1; 217ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 218ca632f55SGrant Likely return 1; 219ca632f55SGrant Likely return 0; 220ca632f55SGrant Likely } 221ca632f55SGrant Likely 222ca632f55SGrant Likely static int flush(struct driver_data *drv_data) 223ca632f55SGrant Likely { 224ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 225ca632f55SGrant Likely 226ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 227ca632f55SGrant Likely 228ca632f55SGrant Likely do { 229ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 230ca632f55SGrant Likely read_SSDR(reg); 231ca632f55SGrant Likely } 232ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 233ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 234ca632f55SGrant Likely 235ca632f55SGrant Likely return limit; 236ca632f55SGrant Likely } 237ca632f55SGrant Likely 238ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 239ca632f55SGrant Likely { 240ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 241ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 242ca632f55SGrant Likely 243ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 244ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 245ca632f55SGrant Likely return 0; 246ca632f55SGrant Likely 247ca632f55SGrant Likely write_SSDR(0, reg); 248ca632f55SGrant Likely drv_data->tx += n_bytes; 249ca632f55SGrant Likely 250ca632f55SGrant Likely return 1; 251ca632f55SGrant Likely } 252ca632f55SGrant Likely 253ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 254ca632f55SGrant Likely { 255ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 256ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 257ca632f55SGrant Likely 258ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 259ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 260ca632f55SGrant Likely read_SSDR(reg); 261ca632f55SGrant Likely drv_data->rx += n_bytes; 262ca632f55SGrant Likely } 263ca632f55SGrant Likely 264ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 265ca632f55SGrant Likely } 266ca632f55SGrant Likely 267ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 268ca632f55SGrant Likely { 269ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 270ca632f55SGrant Likely 271ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 272ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 273ca632f55SGrant Likely return 0; 274ca632f55SGrant Likely 275ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 276ca632f55SGrant Likely ++drv_data->tx; 277ca632f55SGrant Likely 278ca632f55SGrant Likely return 1; 279ca632f55SGrant Likely } 280ca632f55SGrant Likely 281ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 282ca632f55SGrant Likely { 283ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 284ca632f55SGrant Likely 285ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 286ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 287ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 288ca632f55SGrant Likely ++drv_data->rx; 289ca632f55SGrant Likely } 290ca632f55SGrant Likely 291ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 292ca632f55SGrant Likely } 293ca632f55SGrant Likely 294ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 295ca632f55SGrant Likely { 296ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 297ca632f55SGrant Likely 298ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 299ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 300ca632f55SGrant Likely return 0; 301ca632f55SGrant Likely 302ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 303ca632f55SGrant Likely drv_data->tx += 2; 304ca632f55SGrant Likely 305ca632f55SGrant Likely return 1; 306ca632f55SGrant Likely } 307ca632f55SGrant Likely 308ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 309ca632f55SGrant Likely { 310ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 311ca632f55SGrant Likely 312ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 313ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 314ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 315ca632f55SGrant Likely drv_data->rx += 2; 316ca632f55SGrant Likely } 317ca632f55SGrant Likely 318ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 319ca632f55SGrant Likely } 320ca632f55SGrant Likely 321ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 322ca632f55SGrant Likely { 323ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 324ca632f55SGrant Likely 325ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 326ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 327ca632f55SGrant Likely return 0; 328ca632f55SGrant Likely 329ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 330ca632f55SGrant Likely drv_data->tx += 4; 331ca632f55SGrant Likely 332ca632f55SGrant Likely return 1; 333ca632f55SGrant Likely } 334ca632f55SGrant Likely 335ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 336ca632f55SGrant Likely { 337ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 338ca632f55SGrant Likely 339ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 340ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 341ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 342ca632f55SGrant Likely drv_data->rx += 4; 343ca632f55SGrant Likely } 344ca632f55SGrant Likely 345ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 346ca632f55SGrant Likely } 347ca632f55SGrant Likely 348ca632f55SGrant Likely static void *next_transfer(struct driver_data *drv_data) 349ca632f55SGrant Likely { 350ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 351ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 352ca632f55SGrant Likely 353ca632f55SGrant Likely /* Move to next transfer */ 354ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 355ca632f55SGrant Likely drv_data->cur_transfer = 356ca632f55SGrant Likely list_entry(trans->transfer_list.next, 357ca632f55SGrant Likely struct spi_transfer, 358ca632f55SGrant Likely transfer_list); 359ca632f55SGrant Likely return RUNNING_STATE; 360ca632f55SGrant Likely } else 361ca632f55SGrant Likely return DONE_STATE; 362ca632f55SGrant Likely } 363ca632f55SGrant Likely 364ca632f55SGrant Likely static int map_dma_buffers(struct driver_data *drv_data) 365ca632f55SGrant Likely { 366ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 367ca632f55SGrant Likely struct device *dev = &msg->spi->dev; 368ca632f55SGrant Likely 369ca632f55SGrant Likely if (!drv_data->cur_chip->enable_dma) 370ca632f55SGrant Likely return 0; 371ca632f55SGrant Likely 372ca632f55SGrant Likely if (msg->is_dma_mapped) 373ca632f55SGrant Likely return drv_data->rx_dma && drv_data->tx_dma; 374ca632f55SGrant Likely 375ca632f55SGrant Likely if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) 376ca632f55SGrant Likely return 0; 377ca632f55SGrant Likely 378ca632f55SGrant Likely /* Modify setup if rx buffer is null */ 379ca632f55SGrant Likely if (drv_data->rx == NULL) { 380ca632f55SGrant Likely *drv_data->null_dma_buf = 0; 381ca632f55SGrant Likely drv_data->rx = drv_data->null_dma_buf; 382ca632f55SGrant Likely drv_data->rx_map_len = 4; 383ca632f55SGrant Likely } else 384ca632f55SGrant Likely drv_data->rx_map_len = drv_data->len; 385ca632f55SGrant Likely 386ca632f55SGrant Likely 387ca632f55SGrant Likely /* Modify setup if tx buffer is null */ 388ca632f55SGrant Likely if (drv_data->tx == NULL) { 389ca632f55SGrant Likely *drv_data->null_dma_buf = 0; 390ca632f55SGrant Likely drv_data->tx = drv_data->null_dma_buf; 391ca632f55SGrant Likely drv_data->tx_map_len = 4; 392ca632f55SGrant Likely } else 393ca632f55SGrant Likely drv_data->tx_map_len = drv_data->len; 394ca632f55SGrant Likely 395ca632f55SGrant Likely /* Stream map the tx buffer. Always do DMA_TO_DEVICE first 396ca632f55SGrant Likely * so we flush the cache *before* invalidating it, in case 397ca632f55SGrant Likely * the tx and rx buffers overlap. 398ca632f55SGrant Likely */ 399ca632f55SGrant Likely drv_data->tx_dma = dma_map_single(dev, drv_data->tx, 400ca632f55SGrant Likely drv_data->tx_map_len, DMA_TO_DEVICE); 401ca632f55SGrant Likely if (dma_mapping_error(dev, drv_data->tx_dma)) 402ca632f55SGrant Likely return 0; 403ca632f55SGrant Likely 404ca632f55SGrant Likely /* Stream map the rx buffer */ 405ca632f55SGrant Likely drv_data->rx_dma = dma_map_single(dev, drv_data->rx, 406ca632f55SGrant Likely drv_data->rx_map_len, DMA_FROM_DEVICE); 407ca632f55SGrant Likely if (dma_mapping_error(dev, drv_data->rx_dma)) { 408ca632f55SGrant Likely dma_unmap_single(dev, drv_data->tx_dma, 409ca632f55SGrant Likely drv_data->tx_map_len, DMA_TO_DEVICE); 410ca632f55SGrant Likely return 0; 411ca632f55SGrant Likely } 412ca632f55SGrant Likely 413ca632f55SGrant Likely return 1; 414ca632f55SGrant Likely } 415ca632f55SGrant Likely 416ca632f55SGrant Likely static void unmap_dma_buffers(struct driver_data *drv_data) 417ca632f55SGrant Likely { 418ca632f55SGrant Likely struct device *dev; 419ca632f55SGrant Likely 420ca632f55SGrant Likely if (!drv_data->dma_mapped) 421ca632f55SGrant Likely return; 422ca632f55SGrant Likely 423ca632f55SGrant Likely if (!drv_data->cur_msg->is_dma_mapped) { 424ca632f55SGrant Likely dev = &drv_data->cur_msg->spi->dev; 425ca632f55SGrant Likely dma_unmap_single(dev, drv_data->rx_dma, 426ca632f55SGrant Likely drv_data->rx_map_len, DMA_FROM_DEVICE); 427ca632f55SGrant Likely dma_unmap_single(dev, drv_data->tx_dma, 428ca632f55SGrant Likely drv_data->tx_map_len, DMA_TO_DEVICE); 429ca632f55SGrant Likely } 430ca632f55SGrant Likely 431ca632f55SGrant Likely drv_data->dma_mapped = 0; 432ca632f55SGrant Likely } 433ca632f55SGrant Likely 434ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 435ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 436ca632f55SGrant Likely { 437ca632f55SGrant Likely struct spi_transfer* last_transfer; 438ca632f55SGrant Likely struct spi_message *msg; 439ca632f55SGrant Likely 440ca632f55SGrant Likely msg = drv_data->cur_msg; 441ca632f55SGrant Likely drv_data->cur_msg = NULL; 442ca632f55SGrant Likely drv_data->cur_transfer = NULL; 443ca632f55SGrant Likely 444ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 445ca632f55SGrant Likely struct spi_transfer, 446ca632f55SGrant Likely transfer_list); 447ca632f55SGrant Likely 448ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 449ca632f55SGrant Likely if (last_transfer->delay_usecs) 450ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 451ca632f55SGrant Likely 452ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 453ca632f55SGrant Likely * a message with an error, or next message is for another chip 454ca632f55SGrant Likely */ 455ca632f55SGrant Likely if (!last_transfer->cs_change) 456ca632f55SGrant Likely cs_deassert(drv_data); 457ca632f55SGrant Likely else { 458ca632f55SGrant Likely struct spi_message *next_msg; 459ca632f55SGrant Likely 460ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 461ca632f55SGrant Likely * the next message is for the same chip. Don't waste 462ca632f55SGrant Likely * time with the following tests unless this was hinted. 463ca632f55SGrant Likely * 464ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 465ca632f55SGrant Likely * after calling msg->complete (below) the driver that 466ca632f55SGrant Likely * sent the current message could be unloaded, which 467ca632f55SGrant Likely * could invalidate the cs_control() callback... 468ca632f55SGrant Likely */ 469ca632f55SGrant Likely 470ca632f55SGrant Likely /* get a pointer to the next message, if any */ 4717f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 472ca632f55SGrant Likely 473ca632f55SGrant Likely /* see if the next and current messages point 474ca632f55SGrant Likely * to the same chip 475ca632f55SGrant Likely */ 476ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 477ca632f55SGrant Likely next_msg = NULL; 478ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 479ca632f55SGrant Likely cs_deassert(drv_data); 480ca632f55SGrant Likely } 481ca632f55SGrant Likely 4827f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 483ca632f55SGrant Likely drv_data->cur_chip = NULL; 484ca632f55SGrant Likely } 485ca632f55SGrant Likely 486ca632f55SGrant Likely static int wait_ssp_rx_stall(void const __iomem *ioaddr) 487ca632f55SGrant Likely { 488ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 489ca632f55SGrant Likely 490ca632f55SGrant Likely while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) 491ca632f55SGrant Likely cpu_relax(); 492ca632f55SGrant Likely 493ca632f55SGrant Likely return limit; 494ca632f55SGrant Likely } 495ca632f55SGrant Likely 496ca632f55SGrant Likely static int wait_dma_channel_stop(int channel) 497ca632f55SGrant Likely { 498ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 499ca632f55SGrant Likely 500ca632f55SGrant Likely while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) 501ca632f55SGrant Likely cpu_relax(); 502ca632f55SGrant Likely 503ca632f55SGrant Likely return limit; 504ca632f55SGrant Likely } 505ca632f55SGrant Likely 506ca632f55SGrant Likely static void dma_error_stop(struct driver_data *drv_data, const char *msg) 507ca632f55SGrant Likely { 508ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 509ca632f55SGrant Likely 510ca632f55SGrant Likely /* Stop and reset */ 511ca632f55SGrant Likely DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 512ca632f55SGrant Likely DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 513ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 514ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 515ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 516ca632f55SGrant Likely write_SSTO(0, reg); 517ca632f55SGrant Likely flush(drv_data); 518ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 519ca632f55SGrant Likely 520ca632f55SGrant Likely unmap_dma_buffers(drv_data); 521ca632f55SGrant Likely 522ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 523ca632f55SGrant Likely 524ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 525ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 526ca632f55SGrant Likely } 527ca632f55SGrant Likely 528ca632f55SGrant Likely static void dma_transfer_complete(struct driver_data *drv_data) 529ca632f55SGrant Likely { 530ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 531ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 532ca632f55SGrant Likely 533ca632f55SGrant Likely /* Clear and disable interrupts on SSP and DMA channels*/ 534ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 535ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 536ca632f55SGrant Likely DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 537ca632f55SGrant Likely DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 538ca632f55SGrant Likely 539ca632f55SGrant Likely if (wait_dma_channel_stop(drv_data->rx_channel) == 0) 540ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 541ca632f55SGrant Likely "dma_handler: dma rx channel stop failed\n"); 542ca632f55SGrant Likely 543ca632f55SGrant Likely if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) 544ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 545ca632f55SGrant Likely "dma_transfer: ssp rx stall failed\n"); 546ca632f55SGrant Likely 547ca632f55SGrant Likely unmap_dma_buffers(drv_data); 548ca632f55SGrant Likely 549ca632f55SGrant Likely /* update the buffer pointer for the amount completed in dma */ 550ca632f55SGrant Likely drv_data->rx += drv_data->len - 551ca632f55SGrant Likely (DCMD(drv_data->rx_channel) & DCMD_LENGTH); 552ca632f55SGrant Likely 553ca632f55SGrant Likely /* read trailing data from fifo, it does not matter how many 554ca632f55SGrant Likely * bytes are in the fifo just read until buffer is full 555ca632f55SGrant Likely * or fifo is empty, which ever occurs first */ 556ca632f55SGrant Likely drv_data->read(drv_data); 557ca632f55SGrant Likely 558ca632f55SGrant Likely /* return count of what was actually read */ 559ca632f55SGrant Likely msg->actual_length += drv_data->len - 560ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 561ca632f55SGrant Likely 562ca632f55SGrant Likely /* Transfer delays and chip select release are 563ca632f55SGrant Likely * handled in pump_transfers or giveback 564ca632f55SGrant Likely */ 565ca632f55SGrant Likely 566ca632f55SGrant Likely /* Move to next transfer */ 567ca632f55SGrant Likely msg->state = next_transfer(drv_data); 568ca632f55SGrant Likely 569ca632f55SGrant Likely /* Schedule transfer tasklet */ 570ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 571ca632f55SGrant Likely } 572ca632f55SGrant Likely 573ca632f55SGrant Likely static void dma_handler(int channel, void *data) 574ca632f55SGrant Likely { 575ca632f55SGrant Likely struct driver_data *drv_data = data; 576ca632f55SGrant Likely u32 irq_status = DCSR(channel) & DMA_INT_MASK; 577ca632f55SGrant Likely 578ca632f55SGrant Likely if (irq_status & DCSR_BUSERR) { 579ca632f55SGrant Likely 580ca632f55SGrant Likely if (channel == drv_data->tx_channel) 581ca632f55SGrant Likely dma_error_stop(drv_data, 582ca632f55SGrant Likely "dma_handler: " 583ca632f55SGrant Likely "bad bus address on tx channel"); 584ca632f55SGrant Likely else 585ca632f55SGrant Likely dma_error_stop(drv_data, 586ca632f55SGrant Likely "dma_handler: " 587ca632f55SGrant Likely "bad bus address on rx channel"); 588ca632f55SGrant Likely return; 589ca632f55SGrant Likely } 590ca632f55SGrant Likely 591ca632f55SGrant Likely /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ 592ca632f55SGrant Likely if ((channel == drv_data->tx_channel) 593ca632f55SGrant Likely && (irq_status & DCSR_ENDINTR) 594ca632f55SGrant Likely && (drv_data->ssp_type == PXA25x_SSP)) { 595ca632f55SGrant Likely 596ca632f55SGrant Likely /* Wait for rx to stall */ 597ca632f55SGrant Likely if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) 598ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 599ca632f55SGrant Likely "dma_handler: ssp rx stall failed\n"); 600ca632f55SGrant Likely 601ca632f55SGrant Likely /* finish this transfer, start the next */ 602ca632f55SGrant Likely dma_transfer_complete(drv_data); 603ca632f55SGrant Likely } 604ca632f55SGrant Likely } 605ca632f55SGrant Likely 606ca632f55SGrant Likely static irqreturn_t dma_transfer(struct driver_data *drv_data) 607ca632f55SGrant Likely { 608ca632f55SGrant Likely u32 irq_status; 609ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 610ca632f55SGrant Likely 611ca632f55SGrant Likely irq_status = read_SSSR(reg) & drv_data->mask_sr; 612ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 613ca632f55SGrant Likely dma_error_stop(drv_data, "dma_transfer: fifo overrun"); 614ca632f55SGrant Likely return IRQ_HANDLED; 615ca632f55SGrant Likely } 616ca632f55SGrant Likely 617ca632f55SGrant Likely /* Check for false positive timeout */ 618ca632f55SGrant Likely if ((irq_status & SSSR_TINT) 619ca632f55SGrant Likely && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { 620ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 621ca632f55SGrant Likely return IRQ_HANDLED; 622ca632f55SGrant Likely } 623ca632f55SGrant Likely 624ca632f55SGrant Likely if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { 625ca632f55SGrant Likely 626ca632f55SGrant Likely /* Clear and disable timeout interrupt, do the rest in 627ca632f55SGrant Likely * dma_transfer_complete */ 628ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 629ca632f55SGrant Likely write_SSTO(0, reg); 630ca632f55SGrant Likely 631ca632f55SGrant Likely /* finish this transfer, start the next */ 632ca632f55SGrant Likely dma_transfer_complete(drv_data); 633ca632f55SGrant Likely 634ca632f55SGrant Likely return IRQ_HANDLED; 635ca632f55SGrant Likely } 636ca632f55SGrant Likely 637ca632f55SGrant Likely /* Opps problem detected */ 638ca632f55SGrant Likely return IRQ_NONE; 639ca632f55SGrant Likely } 640ca632f55SGrant Likely 641ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 642ca632f55SGrant Likely { 643ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 644ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 645ca632f55SGrant Likely u32 sccr1_reg; 646ca632f55SGrant Likely 647ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 648ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 649ca632f55SGrant Likely sccr1_reg |= chip->threshold; 650ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 651ca632f55SGrant Likely } 652ca632f55SGrant Likely 653ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 654ca632f55SGrant Likely { 655ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 656ca632f55SGrant Likely 657ca632f55SGrant Likely /* Stop and reset SSP */ 658ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 659ca632f55SGrant Likely reset_sccr1(drv_data); 660ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 661ca632f55SGrant Likely write_SSTO(0, reg); 662ca632f55SGrant Likely flush(drv_data); 663ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 664ca632f55SGrant Likely 665ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 666ca632f55SGrant Likely 667ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 668ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 669ca632f55SGrant Likely } 670ca632f55SGrant Likely 671ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 672ca632f55SGrant Likely { 673ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 674ca632f55SGrant Likely 675ca632f55SGrant Likely /* Stop SSP */ 676ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 677ca632f55SGrant Likely reset_sccr1(drv_data); 678ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 679ca632f55SGrant Likely write_SSTO(0, reg); 680ca632f55SGrant Likely 681ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 682ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 683ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 684ca632f55SGrant Likely 685ca632f55SGrant Likely /* Transfer delays and chip select release are 686ca632f55SGrant Likely * handled in pump_transfers or giveback 687ca632f55SGrant Likely */ 688ca632f55SGrant Likely 689ca632f55SGrant Likely /* Move to next transfer */ 690ca632f55SGrant Likely drv_data->cur_msg->state = next_transfer(drv_data); 691ca632f55SGrant Likely 692ca632f55SGrant Likely /* Schedule transfer tasklet */ 693ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 694ca632f55SGrant Likely } 695ca632f55SGrant Likely 696ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 697ca632f55SGrant Likely { 698ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 699ca632f55SGrant Likely 700ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 701ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 702ca632f55SGrant Likely 703ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 704ca632f55SGrant Likely 705ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 706ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 707ca632f55SGrant Likely return IRQ_HANDLED; 708ca632f55SGrant Likely } 709ca632f55SGrant Likely 710ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 711ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 712ca632f55SGrant Likely if (drv_data->read(drv_data)) { 713ca632f55SGrant Likely int_transfer_complete(drv_data); 714ca632f55SGrant Likely return IRQ_HANDLED; 715ca632f55SGrant Likely } 716ca632f55SGrant Likely } 717ca632f55SGrant Likely 718ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 719ca632f55SGrant Likely do { 720ca632f55SGrant Likely if (drv_data->read(drv_data)) { 721ca632f55SGrant Likely int_transfer_complete(drv_data); 722ca632f55SGrant Likely return IRQ_HANDLED; 723ca632f55SGrant Likely } 724ca632f55SGrant Likely } while (drv_data->write(drv_data)); 725ca632f55SGrant Likely 726ca632f55SGrant Likely if (drv_data->read(drv_data)) { 727ca632f55SGrant Likely int_transfer_complete(drv_data); 728ca632f55SGrant Likely return IRQ_HANDLED; 729ca632f55SGrant Likely } 730ca632f55SGrant Likely 731ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 732ca632f55SGrant Likely u32 bytes_left; 733ca632f55SGrant Likely u32 sccr1_reg; 734ca632f55SGrant Likely 735ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 736ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 737ca632f55SGrant Likely 738ca632f55SGrant Likely /* 739ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 740ca632f55SGrant Likely * remaining RX bytes. 741ca632f55SGrant Likely */ 742ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 743ca632f55SGrant Likely 744ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 745ca632f55SGrant Likely 746ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 747ca632f55SGrant Likely switch (drv_data->n_bytes) { 748ca632f55SGrant Likely case 4: 749ca632f55SGrant Likely bytes_left >>= 1; 750ca632f55SGrant Likely case 2: 751ca632f55SGrant Likely bytes_left >>= 1; 752ca632f55SGrant Likely } 753ca632f55SGrant Likely 754ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 755ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 756ca632f55SGrant Likely 757ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 758ca632f55SGrant Likely } 759ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 760ca632f55SGrant Likely } 761ca632f55SGrant Likely 762ca632f55SGrant Likely /* We did something */ 763ca632f55SGrant Likely return IRQ_HANDLED; 764ca632f55SGrant Likely } 765ca632f55SGrant Likely 766ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 767ca632f55SGrant Likely { 768ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 769ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 770ca632f55SGrant Likely u32 sccr1_reg = read_SSCR1(reg); 771ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 772ca632f55SGrant Likely u32 status; 773ca632f55SGrant Likely 774ca632f55SGrant Likely status = read_SSSR(reg); 775ca632f55SGrant Likely 776ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 777ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 778ca632f55SGrant Likely mask &= ~SSSR_TFS; 779ca632f55SGrant Likely 780ca632f55SGrant Likely if (!(status & mask)) 781ca632f55SGrant Likely return IRQ_NONE; 782ca632f55SGrant Likely 783ca632f55SGrant Likely if (!drv_data->cur_msg) { 784ca632f55SGrant Likely 785ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 786ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 787ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 788ca632f55SGrant Likely write_SSTO(0, reg); 789ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 790ca632f55SGrant Likely 791ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "bad message state " 792ca632f55SGrant Likely "in interrupt handler\n"); 793ca632f55SGrant Likely 794ca632f55SGrant Likely /* Never fail */ 795ca632f55SGrant Likely return IRQ_HANDLED; 796ca632f55SGrant Likely } 797ca632f55SGrant Likely 798ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 799ca632f55SGrant Likely } 800ca632f55SGrant Likely 801ca632f55SGrant Likely static int set_dma_burst_and_threshold(struct chip_data *chip, 802ca632f55SGrant Likely struct spi_device *spi, 803ca632f55SGrant Likely u8 bits_per_word, u32 *burst_code, 804ca632f55SGrant Likely u32 *threshold) 805ca632f55SGrant Likely { 806ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = 807ca632f55SGrant Likely (struct pxa2xx_spi_chip *)spi->controller_data; 808ca632f55SGrant Likely int bytes_per_word; 809ca632f55SGrant Likely int burst_bytes; 810ca632f55SGrant Likely int thresh_words; 811ca632f55SGrant Likely int req_burst_size; 812ca632f55SGrant Likely int retval = 0; 813ca632f55SGrant Likely 814ca632f55SGrant Likely /* Set the threshold (in registers) to equal the same amount of data 815ca632f55SGrant Likely * as represented by burst size (in bytes). The computation below 816ca632f55SGrant Likely * is (burst_size rounded up to nearest 8 byte, word or long word) 817ca632f55SGrant Likely * divided by (bytes/register); the tx threshold is the inverse of 818ca632f55SGrant Likely * the rx, so that there will always be enough data in the rx fifo 819ca632f55SGrant Likely * to satisfy a burst, and there will always be enough space in the 820ca632f55SGrant Likely * tx fifo to accept a burst (a tx burst will overwrite the fifo if 821ca632f55SGrant Likely * there is not enough space), there must always remain enough empty 822ca632f55SGrant Likely * space in the rx fifo for any data loaded to the tx fifo. 823ca632f55SGrant Likely * Whenever burst_size (in bytes) equals bits/word, the fifo threshold 824ca632f55SGrant Likely * will be 8, or half the fifo; 825ca632f55SGrant Likely * The threshold can only be set to 2, 4 or 8, but not 16, because 826ca632f55SGrant Likely * to burst 16 to the tx fifo, the fifo would have to be empty; 827ca632f55SGrant Likely * however, the minimum fifo trigger level is 1, and the tx will 828ca632f55SGrant Likely * request service when the fifo is at this level, with only 15 spaces. 829ca632f55SGrant Likely */ 830ca632f55SGrant Likely 831ca632f55SGrant Likely /* find bytes/word */ 832ca632f55SGrant Likely if (bits_per_word <= 8) 833ca632f55SGrant Likely bytes_per_word = 1; 834ca632f55SGrant Likely else if (bits_per_word <= 16) 835ca632f55SGrant Likely bytes_per_word = 2; 836ca632f55SGrant Likely else 837ca632f55SGrant Likely bytes_per_word = 4; 838ca632f55SGrant Likely 839ca632f55SGrant Likely /* use struct pxa2xx_spi_chip->dma_burst_size if available */ 840ca632f55SGrant Likely if (chip_info) 841ca632f55SGrant Likely req_burst_size = chip_info->dma_burst_size; 842ca632f55SGrant Likely else { 843ca632f55SGrant Likely switch (chip->dma_burst_size) { 844ca632f55SGrant Likely default: 845ca632f55SGrant Likely /* if the default burst size is not set, 846ca632f55SGrant Likely * do it now */ 847ca632f55SGrant Likely chip->dma_burst_size = DCMD_BURST8; 848ca632f55SGrant Likely case DCMD_BURST8: 849ca632f55SGrant Likely req_burst_size = 8; 850ca632f55SGrant Likely break; 851ca632f55SGrant Likely case DCMD_BURST16: 852ca632f55SGrant Likely req_burst_size = 16; 853ca632f55SGrant Likely break; 854ca632f55SGrant Likely case DCMD_BURST32: 855ca632f55SGrant Likely req_burst_size = 32; 856ca632f55SGrant Likely break; 857ca632f55SGrant Likely } 858ca632f55SGrant Likely } 859ca632f55SGrant Likely if (req_burst_size <= 8) { 860ca632f55SGrant Likely *burst_code = DCMD_BURST8; 861ca632f55SGrant Likely burst_bytes = 8; 862ca632f55SGrant Likely } else if (req_burst_size <= 16) { 863ca632f55SGrant Likely if (bytes_per_word == 1) { 864ca632f55SGrant Likely /* don't burst more than 1/2 the fifo */ 865ca632f55SGrant Likely *burst_code = DCMD_BURST8; 866ca632f55SGrant Likely burst_bytes = 8; 867ca632f55SGrant Likely retval = 1; 868ca632f55SGrant Likely } else { 869ca632f55SGrant Likely *burst_code = DCMD_BURST16; 870ca632f55SGrant Likely burst_bytes = 16; 871ca632f55SGrant Likely } 872ca632f55SGrant Likely } else { 873ca632f55SGrant Likely if (bytes_per_word == 1) { 874ca632f55SGrant Likely /* don't burst more than 1/2 the fifo */ 875ca632f55SGrant Likely *burst_code = DCMD_BURST8; 876ca632f55SGrant Likely burst_bytes = 8; 877ca632f55SGrant Likely retval = 1; 878ca632f55SGrant Likely } else if (bytes_per_word == 2) { 879ca632f55SGrant Likely /* don't burst more than 1/2 the fifo */ 880ca632f55SGrant Likely *burst_code = DCMD_BURST16; 881ca632f55SGrant Likely burst_bytes = 16; 882ca632f55SGrant Likely retval = 1; 883ca632f55SGrant Likely } else { 884ca632f55SGrant Likely *burst_code = DCMD_BURST32; 885ca632f55SGrant Likely burst_bytes = 32; 886ca632f55SGrant Likely } 887ca632f55SGrant Likely } 888ca632f55SGrant Likely 889ca632f55SGrant Likely thresh_words = burst_bytes / bytes_per_word; 890ca632f55SGrant Likely 891ca632f55SGrant Likely /* thresh_words will be between 2 and 8 */ 892ca632f55SGrant Likely *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) 893ca632f55SGrant Likely | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); 894ca632f55SGrant Likely 895ca632f55SGrant Likely return retval; 896ca632f55SGrant Likely } 897ca632f55SGrant Likely 898*3343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 899ca632f55SGrant Likely { 900*3343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 901*3343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 902*3343b7a6SMika Westerberg 903*3343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 904ca632f55SGrant Likely 905ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 906ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 907ca632f55SGrant Likely else 908ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 909ca632f55SGrant Likely } 910ca632f55SGrant Likely 911ca632f55SGrant Likely static void pump_transfers(unsigned long data) 912ca632f55SGrant Likely { 913ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 914ca632f55SGrant Likely struct spi_message *message = NULL; 915ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 916ca632f55SGrant Likely struct spi_transfer *previous = NULL; 917ca632f55SGrant Likely struct chip_data *chip = NULL; 918ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 919ca632f55SGrant Likely u32 clk_div = 0; 920ca632f55SGrant Likely u8 bits = 0; 921ca632f55SGrant Likely u32 speed = 0; 922ca632f55SGrant Likely u32 cr0; 923ca632f55SGrant Likely u32 cr1; 924ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 925ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 926ca632f55SGrant Likely 927ca632f55SGrant Likely /* Get current state information */ 928ca632f55SGrant Likely message = drv_data->cur_msg; 929ca632f55SGrant Likely transfer = drv_data->cur_transfer; 930ca632f55SGrant Likely chip = drv_data->cur_chip; 931ca632f55SGrant Likely 932ca632f55SGrant Likely /* Handle for abort */ 933ca632f55SGrant Likely if (message->state == ERROR_STATE) { 934ca632f55SGrant Likely message->status = -EIO; 935ca632f55SGrant Likely giveback(drv_data); 936ca632f55SGrant Likely return; 937ca632f55SGrant Likely } 938ca632f55SGrant Likely 939ca632f55SGrant Likely /* Handle end of message */ 940ca632f55SGrant Likely if (message->state == DONE_STATE) { 941ca632f55SGrant Likely message->status = 0; 942ca632f55SGrant Likely giveback(drv_data); 943ca632f55SGrant Likely return; 944ca632f55SGrant Likely } 945ca632f55SGrant Likely 946ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 947ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 948ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 949ca632f55SGrant Likely struct spi_transfer, 950ca632f55SGrant Likely transfer_list); 951ca632f55SGrant Likely if (previous->delay_usecs) 952ca632f55SGrant Likely udelay(previous->delay_usecs); 953ca632f55SGrant Likely 954ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 955ca632f55SGrant Likely if (previous->cs_change) 956ca632f55SGrant Likely cs_deassert(drv_data); 957ca632f55SGrant Likely } 958ca632f55SGrant Likely 959ca632f55SGrant Likely /* Check for transfers that need multiple DMA segments */ 960ca632f55SGrant Likely if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 961ca632f55SGrant Likely 962ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 963ca632f55SGrant Likely if (message->is_dma_mapped 964ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 965ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 966ca632f55SGrant Likely "pump_transfers: mapped transfer length " 967ca632f55SGrant Likely "of %u is greater than %d\n", 968ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 969ca632f55SGrant Likely message->status = -EINVAL; 970ca632f55SGrant Likely giveback(drv_data); 971ca632f55SGrant Likely return; 972ca632f55SGrant Likely } 973ca632f55SGrant Likely 974ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 975ca632f55SGrant Likely if (printk_ratelimit()) 976ca632f55SGrant Likely dev_warn(&message->spi->dev, "pump_transfers: " 977ca632f55SGrant Likely "DMA disabled for transfer length %ld " 978ca632f55SGrant Likely "greater than %d\n", 979ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 980ca632f55SGrant Likely } 981ca632f55SGrant Likely 982ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 983ca632f55SGrant Likely if (flush(drv_data) == 0) { 984ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 985ca632f55SGrant Likely message->status = -EIO; 986ca632f55SGrant Likely giveback(drv_data); 987ca632f55SGrant Likely return; 988ca632f55SGrant Likely } 989ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 990ca632f55SGrant Likely drv_data->dma_width = chip->dma_width; 991ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 992ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 993ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 994ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 995ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 996ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 997ca632f55SGrant Likely drv_data->len = transfer->len & DCMD_LENGTH; 998ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 999ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 1000ca632f55SGrant Likely 1001ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 1002ca632f55SGrant Likely cr0 = chip->cr0; 1003ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 1004ca632f55SGrant Likely 1005ca632f55SGrant Likely bits = chip->bits_per_word; 1006ca632f55SGrant Likely speed = chip->speed_hz; 1007ca632f55SGrant Likely 1008ca632f55SGrant Likely if (transfer->speed_hz) 1009ca632f55SGrant Likely speed = transfer->speed_hz; 1010ca632f55SGrant Likely 1011ca632f55SGrant Likely if (transfer->bits_per_word) 1012ca632f55SGrant Likely bits = transfer->bits_per_word; 1013ca632f55SGrant Likely 1014*3343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, speed); 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely if (bits <= 8) { 1017ca632f55SGrant Likely drv_data->n_bytes = 1; 1018ca632f55SGrant Likely drv_data->dma_width = DCMD_WIDTH1; 1019ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 1020ca632f55SGrant Likely u8_reader : null_reader; 1021ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 1022ca632f55SGrant Likely u8_writer : null_writer; 1023ca632f55SGrant Likely } else if (bits <= 16) { 1024ca632f55SGrant Likely drv_data->n_bytes = 2; 1025ca632f55SGrant Likely drv_data->dma_width = DCMD_WIDTH2; 1026ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 1027ca632f55SGrant Likely u16_reader : null_reader; 1028ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 1029ca632f55SGrant Likely u16_writer : null_writer; 1030ca632f55SGrant Likely } else if (bits <= 32) { 1031ca632f55SGrant Likely drv_data->n_bytes = 4; 1032ca632f55SGrant Likely drv_data->dma_width = DCMD_WIDTH4; 1033ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 1034ca632f55SGrant Likely u32_reader : null_reader; 1035ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 1036ca632f55SGrant Likely u32_writer : null_writer; 1037ca632f55SGrant Likely } 1038ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 1039ca632f55SGrant Likely * thresholds and burst also */ 1040ca632f55SGrant Likely if (chip->enable_dma) { 1041ca632f55SGrant Likely if (set_dma_burst_and_threshold(chip, message->spi, 1042ca632f55SGrant Likely bits, &dma_burst, 1043ca632f55SGrant Likely &dma_thresh)) 1044ca632f55SGrant Likely if (printk_ratelimit()) 1045ca632f55SGrant Likely dev_warn(&message->spi->dev, 1046ca632f55SGrant Likely "pump_transfers: " 1047ca632f55SGrant Likely "DMA burst size reduced to " 1048ca632f55SGrant Likely "match bits_per_word\n"); 1049ca632f55SGrant Likely } 1050ca632f55SGrant Likely 1051ca632f55SGrant Likely cr0 = clk_div 1052ca632f55SGrant Likely | SSCR0_Motorola 1053ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 1054ca632f55SGrant Likely | SSCR0_SSE 1055ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 1056ca632f55SGrant Likely } 1057ca632f55SGrant Likely 1058ca632f55SGrant Likely message->state = RUNNING_STATE; 1059ca632f55SGrant Likely 1060ca632f55SGrant Likely /* Try to map dma buffer and do a dma transfer if successful, but 1061ca632f55SGrant Likely * only if the length is non-zero and less than MAX_DMA_LEN. 1062ca632f55SGrant Likely * 1063ca632f55SGrant Likely * Zero-length non-descriptor DMA is illegal on PXA2xx; force use 1064ca632f55SGrant Likely * of PIO instead. Care is needed above because the transfer may 1065ca632f55SGrant Likely * have have been passed with buffers that are already dma mapped. 1066ca632f55SGrant Likely * A zero-length transfer in PIO mode will not try to write/read 1067ca632f55SGrant Likely * to/from the buffers 1068ca632f55SGrant Likely * 1069ca632f55SGrant Likely * REVISIT large transfers are exactly where we most want to be 1070ca632f55SGrant Likely * using DMA. If this happens much, split those transfers into 1071ca632f55SGrant Likely * multiple DMA segments rather than forcing PIO. 1072ca632f55SGrant Likely */ 1073ca632f55SGrant Likely drv_data->dma_mapped = 0; 1074ca632f55SGrant Likely if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) 1075ca632f55SGrant Likely drv_data->dma_mapped = map_dma_buffers(drv_data); 1076ca632f55SGrant Likely if (drv_data->dma_mapped) { 1077ca632f55SGrant Likely 1078ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 1079ca632f55SGrant Likely drv_data->transfer_handler = dma_transfer; 1080ca632f55SGrant Likely 1081ca632f55SGrant Likely /* Setup rx DMA Channel */ 1082ca632f55SGrant Likely DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 1083ca632f55SGrant Likely DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; 1084ca632f55SGrant Likely DTADR(drv_data->rx_channel) = drv_data->rx_dma; 1085ca632f55SGrant Likely if (drv_data->rx == drv_data->null_dma_buf) 1086ca632f55SGrant Likely /* No target address increment */ 1087ca632f55SGrant Likely DCMD(drv_data->rx_channel) = DCMD_FLOWSRC 1088ca632f55SGrant Likely | drv_data->dma_width 1089ca632f55SGrant Likely | dma_burst 1090ca632f55SGrant Likely | drv_data->len; 1091ca632f55SGrant Likely else 1092ca632f55SGrant Likely DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR 1093ca632f55SGrant Likely | DCMD_FLOWSRC 1094ca632f55SGrant Likely | drv_data->dma_width 1095ca632f55SGrant Likely | dma_burst 1096ca632f55SGrant Likely | drv_data->len; 1097ca632f55SGrant Likely 1098ca632f55SGrant Likely /* Setup tx DMA Channel */ 1099ca632f55SGrant Likely DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 1100ca632f55SGrant Likely DSADR(drv_data->tx_channel) = drv_data->tx_dma; 1101ca632f55SGrant Likely DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; 1102ca632f55SGrant Likely if (drv_data->tx == drv_data->null_dma_buf) 1103ca632f55SGrant Likely /* No source address increment */ 1104ca632f55SGrant Likely DCMD(drv_data->tx_channel) = DCMD_FLOWTRG 1105ca632f55SGrant Likely | drv_data->dma_width 1106ca632f55SGrant Likely | dma_burst 1107ca632f55SGrant Likely | drv_data->len; 1108ca632f55SGrant Likely else 1109ca632f55SGrant Likely DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR 1110ca632f55SGrant Likely | DCMD_FLOWTRG 1111ca632f55SGrant Likely | drv_data->dma_width 1112ca632f55SGrant Likely | dma_burst 1113ca632f55SGrant Likely | drv_data->len; 1114ca632f55SGrant Likely 1115ca632f55SGrant Likely /* Enable dma end irqs on SSP to detect end of transfer */ 1116ca632f55SGrant Likely if (drv_data->ssp_type == PXA25x_SSP) 1117ca632f55SGrant Likely DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; 1118ca632f55SGrant Likely 1119ca632f55SGrant Likely /* Clear status and start DMA engine */ 1120ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1121ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 1122ca632f55SGrant Likely DCSR(drv_data->rx_channel) |= DCSR_RUN; 1123ca632f55SGrant Likely DCSR(drv_data->tx_channel) |= DCSR_RUN; 1124ca632f55SGrant Likely } else { 1125ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 1126ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 1127ca632f55SGrant Likely 1128ca632f55SGrant Likely /* Clear status */ 1129ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1130ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 1131ca632f55SGrant Likely } 1132ca632f55SGrant Likely 1133ca632f55SGrant Likely /* see if we need to reload the config registers */ 1134ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 1135ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 1136ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 1137ca632f55SGrant Likely 1138ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 1139ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 1140ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1141ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 1142ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 1143ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 1144ca632f55SGrant Likely /* restart the SSP */ 1145ca632f55SGrant Likely write_SSCR0(cr0, reg); 1146ca632f55SGrant Likely 1147ca632f55SGrant Likely } else { 1148ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1149ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 1150ca632f55SGrant Likely } 1151ca632f55SGrant Likely 1152ca632f55SGrant Likely cs_assert(drv_data); 1153ca632f55SGrant Likely 1154ca632f55SGrant Likely /* after chip select, release the data by enabling service 1155ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 1156ca632f55SGrant Likely write_SSCR1(cr1, reg); 1157ca632f55SGrant Likely } 1158ca632f55SGrant Likely 11597f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 11607f86bde9SMika Westerberg struct spi_message *msg) 1161ca632f55SGrant Likely { 11627f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 1163ca632f55SGrant Likely 11647f86bde9SMika Westerberg drv_data->cur_msg = msg; 1165ca632f55SGrant Likely /* Initial message state*/ 1166ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 1167ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 1168ca632f55SGrant Likely struct spi_transfer, 1169ca632f55SGrant Likely transfer_list); 1170ca632f55SGrant Likely 1171ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 1172ca632f55SGrant Likely * chip configuration */ 1173ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 1174ca632f55SGrant Likely 1175ca632f55SGrant Likely /* Mark as busy and launch transfers */ 1176ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 1177ca632f55SGrant Likely return 0; 1178ca632f55SGrant Likely } 1179ca632f55SGrant Likely 1180ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1181ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 1182ca632f55SGrant Likely { 1183ca632f55SGrant Likely int err = 0; 1184ca632f55SGrant Likely 1185ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 1186ca632f55SGrant Likely return 0; 1187ca632f55SGrant Likely 1188ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 1189ca632f55SGrant Likely * different chip_info, release previously requested GPIO 1190ca632f55SGrant Likely */ 1191ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 1192ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1193ca632f55SGrant Likely 1194ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 1195ca632f55SGrant Likely if (chip_info->cs_control) { 1196ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1197ca632f55SGrant Likely return 0; 1198ca632f55SGrant Likely } 1199ca632f55SGrant Likely 1200ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 1201ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1202ca632f55SGrant Likely if (err) { 1203ca632f55SGrant Likely dev_err(&spi->dev, "failed to request chip select " 1204ca632f55SGrant Likely "GPIO%d\n", chip_info->gpio_cs); 1205ca632f55SGrant Likely return err; 1206ca632f55SGrant Likely } 1207ca632f55SGrant Likely 1208ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 1209ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1210ca632f55SGrant Likely 1211ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 1212ca632f55SGrant Likely !chip->gpio_cs_inverted); 1213ca632f55SGrant Likely } 1214ca632f55SGrant Likely 1215ca632f55SGrant Likely return err; 1216ca632f55SGrant Likely } 1217ca632f55SGrant Likely 1218ca632f55SGrant Likely static int setup(struct spi_device *spi) 1219ca632f55SGrant Likely { 1220ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 1221ca632f55SGrant Likely struct chip_data *chip; 1222ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1223ca632f55SGrant Likely unsigned int clk_div; 1224ca632f55SGrant Likely uint tx_thres = TX_THRESH_DFLT; 1225ca632f55SGrant Likely uint rx_thres = RX_THRESH_DFLT; 1226ca632f55SGrant Likely 1227ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data) 1228ca632f55SGrant Likely && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { 1229ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 1230ca632f55SGrant Likely "b/w not 4-32 for type non-PXA25x_SSP\n", 1231ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 1232ca632f55SGrant Likely return -EINVAL; 1233ca632f55SGrant Likely } else if (pxa25x_ssp_comp(drv_data) 1234ca632f55SGrant Likely && (spi->bits_per_word < 4 1235ca632f55SGrant Likely || spi->bits_per_word > 16)) { 1236ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 1237ca632f55SGrant Likely "b/w not 4-16 for type PXA25x_SSP\n", 1238ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 1239ca632f55SGrant Likely return -EINVAL; 1240ca632f55SGrant Likely } 1241ca632f55SGrant Likely 1242ca632f55SGrant Likely /* Only alloc on first setup */ 1243ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1244ca632f55SGrant Likely if (!chip) { 1245ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1246ca632f55SGrant Likely if (!chip) { 1247ca632f55SGrant Likely dev_err(&spi->dev, 1248ca632f55SGrant Likely "failed setup: can't allocate chip data\n"); 1249ca632f55SGrant Likely return -ENOMEM; 1250ca632f55SGrant Likely } 1251ca632f55SGrant Likely 1252ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 1253ca632f55SGrant Likely if (spi->chip_select > 4) { 1254ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: " 1255ca632f55SGrant Likely "cs number must not be > 4.\n"); 1256ca632f55SGrant Likely kfree(chip); 1257ca632f55SGrant Likely return -EINVAL; 1258ca632f55SGrant Likely } 1259ca632f55SGrant Likely 1260ca632f55SGrant Likely chip->frm = spi->chip_select; 1261ca632f55SGrant Likely } else 1262ca632f55SGrant Likely chip->gpio_cs = -1; 1263ca632f55SGrant Likely chip->enable_dma = 0; 1264ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 1265ca632f55SGrant Likely chip->dma_burst_size = drv_data->master_info->enable_dma ? 1266ca632f55SGrant Likely DCMD_BURST8 : 0; 1267ca632f55SGrant Likely } 1268ca632f55SGrant Likely 1269ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 1270ca632f55SGrant Likely * if chip_info exists, use it */ 1271ca632f55SGrant Likely chip_info = spi->controller_data; 1272ca632f55SGrant Likely 1273ca632f55SGrant Likely /* chip_info isn't always needed */ 1274ca632f55SGrant Likely chip->cr1 = 0; 1275ca632f55SGrant Likely if (chip_info) { 1276ca632f55SGrant Likely if (chip_info->timeout) 1277ca632f55SGrant Likely chip->timeout = chip_info->timeout; 1278ca632f55SGrant Likely if (chip_info->tx_threshold) 1279ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 1280ca632f55SGrant Likely if (chip_info->rx_threshold) 1281ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 1282ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 1283ca632f55SGrant Likely chip->dma_threshold = 0; 1284ca632f55SGrant Likely if (chip_info->enable_loopback) 1285ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 1286ca632f55SGrant Likely } 1287ca632f55SGrant Likely 1288ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1289ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1290ca632f55SGrant Likely 1291ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 1292ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 1293ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 1294ca632f55SGrant Likely if (chip->enable_dma) { 1295ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 1296ca632f55SGrant Likely if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, 1297ca632f55SGrant Likely &chip->dma_burst_size, 1298ca632f55SGrant Likely &chip->dma_threshold)) { 1299ca632f55SGrant Likely dev_warn(&spi->dev, "in setup: DMA burst size reduced " 1300ca632f55SGrant Likely "to match bits_per_word\n"); 1301ca632f55SGrant Likely } 1302ca632f55SGrant Likely } 1303ca632f55SGrant Likely 1304*3343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 1305ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 1306ca632f55SGrant Likely 1307ca632f55SGrant Likely chip->cr0 = clk_div 1308ca632f55SGrant Likely | SSCR0_Motorola 1309ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 1310ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 1311ca632f55SGrant Likely | SSCR0_SSE 1312ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 1313ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1314ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1315ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1316ca632f55SGrant Likely 1317ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1318ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1319ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1320*3343b7a6SMika Westerberg drv_data->max_clk_rate 1321ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 1322ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 1323ca632f55SGrant Likely else 1324ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1325*3343b7a6SMika Westerberg drv_data->max_clk_rate / 2 1326ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1327ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 1328ca632f55SGrant Likely 1329ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 1330ca632f55SGrant Likely chip->n_bytes = 1; 1331ca632f55SGrant Likely chip->dma_width = DCMD_WIDTH1; 1332ca632f55SGrant Likely chip->read = u8_reader; 1333ca632f55SGrant Likely chip->write = u8_writer; 1334ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 1335ca632f55SGrant Likely chip->n_bytes = 2; 1336ca632f55SGrant Likely chip->dma_width = DCMD_WIDTH2; 1337ca632f55SGrant Likely chip->read = u16_reader; 1338ca632f55SGrant Likely chip->write = u16_writer; 1339ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 1340ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 1341ca632f55SGrant Likely chip->n_bytes = 4; 1342ca632f55SGrant Likely chip->dma_width = DCMD_WIDTH4; 1343ca632f55SGrant Likely chip->read = u32_reader; 1344ca632f55SGrant Likely chip->write = u32_writer; 1345ca632f55SGrant Likely } else { 1346ca632f55SGrant Likely dev_err(&spi->dev, "invalid wordsize\n"); 1347ca632f55SGrant Likely return -ENODEV; 1348ca632f55SGrant Likely } 1349ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 1350ca632f55SGrant Likely 1351ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1352ca632f55SGrant Likely 1353ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 1354ca632f55SGrant Likely return 0; 1355ca632f55SGrant Likely 1356ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 1357ca632f55SGrant Likely } 1358ca632f55SGrant Likely 1359ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 1360ca632f55SGrant Likely { 1361ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1362ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1363ca632f55SGrant Likely 1364ca632f55SGrant Likely if (!chip) 1365ca632f55SGrant Likely return; 1366ca632f55SGrant Likely 1367ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1368ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1369ca632f55SGrant Likely 1370ca632f55SGrant Likely kfree(chip); 1371ca632f55SGrant Likely } 1372ca632f55SGrant Likely 1373fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 1374ca632f55SGrant Likely { 1375ca632f55SGrant Likely struct device *dev = &pdev->dev; 1376ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 1377ca632f55SGrant Likely struct spi_master *master; 1378ca632f55SGrant Likely struct driver_data *drv_data; 1379ca632f55SGrant Likely struct ssp_device *ssp; 1380ca632f55SGrant Likely int status; 1381ca632f55SGrant Likely 1382851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 1383851bacf5SMika Westerberg if (!platform_info) { 1384851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 1385851bacf5SMika Westerberg return -ENODEV; 1386851bacf5SMika Westerberg } 1387ca632f55SGrant Likely 1388ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 1389851bacf5SMika Westerberg if (!ssp) 1390851bacf5SMika Westerberg ssp = &platform_info->ssp; 1391851bacf5SMika Westerberg 1392851bacf5SMika Westerberg if (!ssp->mmio_base) { 1393851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 1394ca632f55SGrant Likely return -ENODEV; 1395ca632f55SGrant Likely } 1396ca632f55SGrant Likely 1397ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 1398ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1399ca632f55SGrant Likely if (!master) { 1400ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1401ca632f55SGrant Likely pxa_ssp_free(ssp); 1402ca632f55SGrant Likely return -ENOMEM; 1403ca632f55SGrant Likely } 1404ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 1405ca632f55SGrant Likely drv_data->master = master; 1406ca632f55SGrant Likely drv_data->master_info = platform_info; 1407ca632f55SGrant Likely drv_data->pdev = pdev; 1408ca632f55SGrant Likely drv_data->ssp = ssp; 1409ca632f55SGrant Likely 1410ca632f55SGrant Likely master->dev.parent = &pdev->dev; 1411ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 1412ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1413ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1414ca632f55SGrant Likely 1415851bacf5SMika Westerberg master->bus_num = ssp->port_id; 1416ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 1417ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 1418ca632f55SGrant Likely master->cleanup = cleanup; 1419ca632f55SGrant Likely master->setup = setup; 14207f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 1421ca632f55SGrant Likely 1422ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 14232b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1424ca632f55SGrant Likely 1425ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 1426ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 1427ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 1428ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1429ca632f55SGrant Likely drv_data->dma_cr1 = 0; 1430ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 1431ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1432ca632f55SGrant Likely } else { 1433ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1434ca632f55SGrant Likely drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; 1435ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1436ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1437ca632f55SGrant Likely } 1438ca632f55SGrant Likely 1439ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1440ca632f55SGrant Likely drv_data); 1441ca632f55SGrant Likely if (status < 0) { 1442ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1443ca632f55SGrant Likely goto out_error_master_alloc; 1444ca632f55SGrant Likely } 1445ca632f55SGrant Likely 1446ca632f55SGrant Likely /* Setup DMA if requested */ 1447ca632f55SGrant Likely drv_data->tx_channel = -1; 1448ca632f55SGrant Likely drv_data->rx_channel = -1; 1449ca632f55SGrant Likely if (platform_info->enable_dma) { 1450ca632f55SGrant Likely 1451ca632f55SGrant Likely /* Get two DMA channels (rx and tx) */ 1452ca632f55SGrant Likely drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", 1453ca632f55SGrant Likely DMA_PRIO_HIGH, 1454ca632f55SGrant Likely dma_handler, 1455ca632f55SGrant Likely drv_data); 1456ca632f55SGrant Likely if (drv_data->rx_channel < 0) { 1457ca632f55SGrant Likely dev_err(dev, "problem (%d) requesting rx channel\n", 1458ca632f55SGrant Likely drv_data->rx_channel); 1459ca632f55SGrant Likely status = -ENODEV; 1460ca632f55SGrant Likely goto out_error_irq_alloc; 1461ca632f55SGrant Likely } 1462ca632f55SGrant Likely drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", 1463ca632f55SGrant Likely DMA_PRIO_MEDIUM, 1464ca632f55SGrant Likely dma_handler, 1465ca632f55SGrant Likely drv_data); 1466ca632f55SGrant Likely if (drv_data->tx_channel < 0) { 1467ca632f55SGrant Likely dev_err(dev, "problem (%d) requesting tx channel\n", 1468ca632f55SGrant Likely drv_data->tx_channel); 1469ca632f55SGrant Likely status = -ENODEV; 1470ca632f55SGrant Likely goto out_error_dma_alloc; 1471ca632f55SGrant Likely } 1472ca632f55SGrant Likely 1473ca632f55SGrant Likely DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; 1474ca632f55SGrant Likely DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; 1475ca632f55SGrant Likely } 1476ca632f55SGrant Likely 1477ca632f55SGrant Likely /* Enable SOC clock */ 1478*3343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1479*3343b7a6SMika Westerberg 1480*3343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1481ca632f55SGrant Likely 1482ca632f55SGrant Likely /* Load default SSP configuration */ 1483ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1484ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1485ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 1486ca632f55SGrant Likely drv_data->ioaddr); 1487ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 1488ca632f55SGrant Likely | SSCR0_Motorola 1489ca632f55SGrant Likely | SSCR0_DataSize(8), 1490ca632f55SGrant Likely drv_data->ioaddr); 1491ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1492ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 1493ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 1494ca632f55SGrant Likely 14957f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 14967f86bde9SMika Westerberg (unsigned long)drv_data); 1497ca632f55SGrant Likely 1498ca632f55SGrant Likely /* Register with the SPI framework */ 1499ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1500ca632f55SGrant Likely status = spi_register_master(master); 1501ca632f55SGrant Likely if (status != 0) { 1502ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 15037f86bde9SMika Westerberg goto out_error_clock_enabled; 1504ca632f55SGrant Likely } 1505ca632f55SGrant Likely 1506ca632f55SGrant Likely return status; 1507ca632f55SGrant Likely 1508ca632f55SGrant Likely out_error_clock_enabled: 1509*3343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1510ca632f55SGrant Likely 1511ca632f55SGrant Likely out_error_dma_alloc: 1512ca632f55SGrant Likely if (drv_data->tx_channel != -1) 1513ca632f55SGrant Likely pxa_free_dma(drv_data->tx_channel); 1514ca632f55SGrant Likely if (drv_data->rx_channel != -1) 1515ca632f55SGrant Likely pxa_free_dma(drv_data->rx_channel); 1516ca632f55SGrant Likely 1517ca632f55SGrant Likely out_error_irq_alloc: 1518ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1519ca632f55SGrant Likely 1520ca632f55SGrant Likely out_error_master_alloc: 1521ca632f55SGrant Likely spi_master_put(master); 1522ca632f55SGrant Likely pxa_ssp_free(ssp); 1523ca632f55SGrant Likely return status; 1524ca632f55SGrant Likely } 1525ca632f55SGrant Likely 1526ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1527ca632f55SGrant Likely { 1528ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1529ca632f55SGrant Likely struct ssp_device *ssp; 1530ca632f55SGrant Likely 1531ca632f55SGrant Likely if (!drv_data) 1532ca632f55SGrant Likely return 0; 1533ca632f55SGrant Likely ssp = drv_data->ssp; 1534ca632f55SGrant Likely 1535ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1536ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1537*3343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1538ca632f55SGrant Likely 1539ca632f55SGrant Likely /* Release DMA */ 1540ca632f55SGrant Likely if (drv_data->master_info->enable_dma) { 1541ca632f55SGrant Likely DRCMR(ssp->drcmr_rx) = 0; 1542ca632f55SGrant Likely DRCMR(ssp->drcmr_tx) = 0; 1543ca632f55SGrant Likely pxa_free_dma(drv_data->tx_channel); 1544ca632f55SGrant Likely pxa_free_dma(drv_data->rx_channel); 1545ca632f55SGrant Likely } 1546ca632f55SGrant Likely 1547ca632f55SGrant Likely /* Release IRQ */ 1548ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1549ca632f55SGrant Likely 1550ca632f55SGrant Likely /* Release SSP */ 1551ca632f55SGrant Likely pxa_ssp_free(ssp); 1552ca632f55SGrant Likely 1553ca632f55SGrant Likely /* Disconnect from the SPI framework */ 1554ca632f55SGrant Likely spi_unregister_master(drv_data->master); 1555ca632f55SGrant Likely 1556ca632f55SGrant Likely /* Prevent double remove */ 1557ca632f55SGrant Likely platform_set_drvdata(pdev, NULL); 1558ca632f55SGrant Likely 1559ca632f55SGrant Likely return 0; 1560ca632f55SGrant Likely } 1561ca632f55SGrant Likely 1562ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1563ca632f55SGrant Likely { 1564ca632f55SGrant Likely int status = 0; 1565ca632f55SGrant Likely 1566ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1567ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1568ca632f55SGrant Likely } 1569ca632f55SGrant Likely 1570ca632f55SGrant Likely #ifdef CONFIG_PM 1571ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1572ca632f55SGrant Likely { 1573ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1574ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1575ca632f55SGrant Likely int status = 0; 1576ca632f55SGrant Likely 15777f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1578ca632f55SGrant Likely if (status != 0) 1579ca632f55SGrant Likely return status; 1580ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1581*3343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1582ca632f55SGrant Likely 1583ca632f55SGrant Likely return 0; 1584ca632f55SGrant Likely } 1585ca632f55SGrant Likely 1586ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1587ca632f55SGrant Likely { 1588ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1589ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1590ca632f55SGrant Likely int status = 0; 1591ca632f55SGrant Likely 1592ca632f55SGrant Likely if (drv_data->rx_channel != -1) 1593ca632f55SGrant Likely DRCMR(drv_data->ssp->drcmr_rx) = 1594ca632f55SGrant Likely DRCMR_MAPVLD | drv_data->rx_channel; 1595ca632f55SGrant Likely if (drv_data->tx_channel != -1) 1596ca632f55SGrant Likely DRCMR(drv_data->ssp->drcmr_tx) = 1597ca632f55SGrant Likely DRCMR_MAPVLD | drv_data->tx_channel; 1598ca632f55SGrant Likely 1599ca632f55SGrant Likely /* Enable the SSP clock */ 1600*3343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1601ca632f55SGrant Likely 1602ca632f55SGrant Likely /* Start the queue running */ 16037f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1604ca632f55SGrant Likely if (status != 0) { 1605ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1606ca632f55SGrant Likely return status; 1607ca632f55SGrant Likely } 1608ca632f55SGrant Likely 1609ca632f55SGrant Likely return 0; 1610ca632f55SGrant Likely } 1611ca632f55SGrant Likely 1612ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1613ca632f55SGrant Likely .suspend = pxa2xx_spi_suspend, 1614ca632f55SGrant Likely .resume = pxa2xx_spi_resume, 1615ca632f55SGrant Likely }; 1616ca632f55SGrant Likely #endif 1617ca632f55SGrant Likely 1618ca632f55SGrant Likely static struct platform_driver driver = { 1619ca632f55SGrant Likely .driver = { 1620ca632f55SGrant Likely .name = "pxa2xx-spi", 1621ca632f55SGrant Likely .owner = THIS_MODULE, 1622ca632f55SGrant Likely #ifdef CONFIG_PM 1623ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1624ca632f55SGrant Likely #endif 1625ca632f55SGrant Likely }, 1626ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1627ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1628ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1629ca632f55SGrant Likely }; 1630ca632f55SGrant Likely 1631ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1632ca632f55SGrant Likely { 1633ca632f55SGrant Likely return platform_driver_register(&driver); 1634ca632f55SGrant Likely } 1635ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1636ca632f55SGrant Likely 1637ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1638ca632f55SGrant Likely { 1639ca632f55SGrant Likely platform_driver_unregister(&driver); 1640ca632f55SGrant Likely } 1641ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1642