1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3a0d2642eSMika Westerberg * Copyright (C) 2013, Intel Corporation 4ca632f55SGrant Likely * 5ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 6ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 7ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 8ca632f55SGrant Likely * (at your option) any later version. 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 11ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 12ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ca632f55SGrant Likely * GNU General Public License for more details. 14ca632f55SGrant Likely * 15ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 16ca632f55SGrant Likely * along with this program; if not, write to the Free Software 17ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18ca632f55SGrant Likely */ 19ca632f55SGrant Likely 20ca632f55SGrant Likely #include <linux/init.h> 21ca632f55SGrant Likely #include <linux/module.h> 22ca632f55SGrant Likely #include <linux/device.h> 23ca632f55SGrant Likely #include <linux/ioport.h> 24ca632f55SGrant Likely #include <linux/errno.h> 25cbfd6a21SSachin Kamat #include <linux/err.h> 26ca632f55SGrant Likely #include <linux/interrupt.h> 27ca632f55SGrant Likely #include <linux/platform_device.h> 28ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 29ca632f55SGrant Likely #include <linux/spi/spi.h> 30ca632f55SGrant Likely #include <linux/workqueue.h> 31ca632f55SGrant Likely #include <linux/delay.h> 32ca632f55SGrant Likely #include <linux/gpio.h> 33ca632f55SGrant Likely #include <linux/slab.h> 343343b7a6SMika Westerberg #include <linux/clk.h> 357d94a505SMika Westerberg #include <linux/pm_runtime.h> 36a3496855SMika Westerberg #include <linux/acpi.h> 37ca632f55SGrant Likely 38ca632f55SGrant Likely #include <asm/io.h> 39ca632f55SGrant Likely #include <asm/irq.h> 40ca632f55SGrant Likely #include <asm/delay.h> 41ca632f55SGrant Likely 42cd7bed00SMika Westerberg #include "spi-pxa2xx.h" 43ca632f55SGrant Likely 44ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 45ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 46ca632f55SGrant Likely MODULE_LICENSE("GPL"); 47ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 48ca632f55SGrant Likely 49ca632f55SGrant Likely #define MAX_BUSES 3 50ca632f55SGrant Likely 51ca632f55SGrant Likely #define TIMOUT_DFLT 1000 52ca632f55SGrant Likely 53ca632f55SGrant Likely /* 54ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 55ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 56ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 57ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 58ca632f55SGrant Likely * service and interrupt enables 59ca632f55SGrant Likely */ 60ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 61ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 62ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 63ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 64ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 65ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 66ca632f55SGrant Likely 67a0d2642eSMika Westerberg #define LPSS_RX_THRESH_DFLT 64 68a0d2642eSMika Westerberg #define LPSS_TX_LOTHRESH_DFLT 160 69a0d2642eSMika Westerberg #define LPSS_TX_HITHRESH_DFLT 224 70a0d2642eSMika Westerberg 71a0d2642eSMika Westerberg /* Offset from drv_data->lpss_base */ 721de70612SMika Westerberg #define GENERAL_REG 0x08 731de70612SMika Westerberg #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 740054e28dSMika Westerberg #define SSP_REG 0x0c 75a0d2642eSMika Westerberg #define SPI_CS_CONTROL 0x18 76a0d2642eSMika Westerberg #define SPI_CS_CONTROL_SW_MODE BIT(0) 77a0d2642eSMika Westerberg #define SPI_CS_CONTROL_CS_HIGH BIT(1) 78a0d2642eSMika Westerberg 79a0d2642eSMika Westerberg static bool is_lpss_ssp(const struct driver_data *drv_data) 80a0d2642eSMika Westerberg { 81a0d2642eSMika Westerberg return drv_data->ssp_type == LPSS_SSP; 82a0d2642eSMika Westerberg } 83a0d2642eSMika Westerberg 84a0d2642eSMika Westerberg /* 85a0d2642eSMika Westerberg * Read and write LPSS SSP private registers. Caller must first check that 86a0d2642eSMika Westerberg * is_lpss_ssp() returns true before these can be called. 87a0d2642eSMika Westerberg */ 88a0d2642eSMika Westerberg static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 89a0d2642eSMika Westerberg { 90a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 91a0d2642eSMika Westerberg return readl(drv_data->lpss_base + offset); 92a0d2642eSMika Westerberg } 93a0d2642eSMika Westerberg 94a0d2642eSMika Westerberg static void __lpss_ssp_write_priv(struct driver_data *drv_data, 95a0d2642eSMika Westerberg unsigned offset, u32 value) 96a0d2642eSMika Westerberg { 97a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 98a0d2642eSMika Westerberg writel(value, drv_data->lpss_base + offset); 99a0d2642eSMika Westerberg } 100a0d2642eSMika Westerberg 101a0d2642eSMika Westerberg /* 102a0d2642eSMika Westerberg * lpss_ssp_setup - perform LPSS SSP specific setup 103a0d2642eSMika Westerberg * @drv_data: pointer to the driver private data 104a0d2642eSMika Westerberg * 105a0d2642eSMika Westerberg * Perform LPSS SSP specific setup. This function must be called first if 106a0d2642eSMika Westerberg * one is going to use LPSS SSP private registers. 107a0d2642eSMika Westerberg */ 108a0d2642eSMika Westerberg static void lpss_ssp_setup(struct driver_data *drv_data) 109a0d2642eSMika Westerberg { 110a0d2642eSMika Westerberg unsigned offset = 0x400; 111a0d2642eSMika Westerberg u32 value, orig; 112a0d2642eSMika Westerberg 113a0d2642eSMika Westerberg if (!is_lpss_ssp(drv_data)) 114a0d2642eSMika Westerberg return; 115a0d2642eSMika Westerberg 116a0d2642eSMika Westerberg /* 117a0d2642eSMika Westerberg * Perform auto-detection of the LPSS SSP private registers. They 118a0d2642eSMika Westerberg * can be either at 1k or 2k offset from the base address. 119a0d2642eSMika Westerberg */ 120a0d2642eSMika Westerberg orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 121a0d2642eSMika Westerberg 122a0d2642eSMika Westerberg value = orig | SPI_CS_CONTROL_SW_MODE; 123a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 124a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 125a0d2642eSMika Westerberg if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { 126a0d2642eSMika Westerberg offset = 0x800; 127a0d2642eSMika Westerberg goto detection_done; 128a0d2642eSMika Westerberg } 129a0d2642eSMika Westerberg 130a0d2642eSMika Westerberg value &= ~SPI_CS_CONTROL_SW_MODE; 131a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 132a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 133a0d2642eSMika Westerberg if (value != orig) { 134a0d2642eSMika Westerberg offset = 0x800; 135a0d2642eSMika Westerberg goto detection_done; 136a0d2642eSMika Westerberg } 137a0d2642eSMika Westerberg 138a0d2642eSMika Westerberg detection_done: 139a0d2642eSMika Westerberg /* Now set the LPSS base */ 140a0d2642eSMika Westerberg drv_data->lpss_base = drv_data->ioaddr + offset; 141a0d2642eSMika Westerberg 142a0d2642eSMika Westerberg /* Enable software chip select control */ 143a0d2642eSMika Westerberg value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 144a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 1450054e28dSMika Westerberg 1460054e28dSMika Westerberg /* Enable multiblock DMA transfers */ 1471de70612SMika Westerberg if (drv_data->master_info->enable_dma) { 1480054e28dSMika Westerberg __lpss_ssp_write_priv(drv_data, SSP_REG, 1); 1491de70612SMika Westerberg 1501de70612SMika Westerberg value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); 1511de70612SMika Westerberg value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; 1521de70612SMika Westerberg __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); 1531de70612SMika Westerberg } 154a0d2642eSMika Westerberg } 155a0d2642eSMika Westerberg 156a0d2642eSMika Westerberg static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 157a0d2642eSMika Westerberg { 158a0d2642eSMika Westerberg u32 value; 159a0d2642eSMika Westerberg 160a0d2642eSMika Westerberg if (!is_lpss_ssp(drv_data)) 161a0d2642eSMika Westerberg return; 162a0d2642eSMika Westerberg 163a0d2642eSMika Westerberg value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 164a0d2642eSMika Westerberg if (enable) 165a0d2642eSMika Westerberg value &= ~SPI_CS_CONTROL_CS_HIGH; 166a0d2642eSMika Westerberg else 167a0d2642eSMika Westerberg value |= SPI_CS_CONTROL_CS_HIGH; 168a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 169a0d2642eSMika Westerberg } 170a0d2642eSMika Westerberg 171ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 172ca632f55SGrant Likely { 173ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 174ca632f55SGrant Likely 175ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 176ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 177ca632f55SGrant Likely return; 178ca632f55SGrant Likely } 179ca632f55SGrant Likely 180ca632f55SGrant Likely if (chip->cs_control) { 181ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 182ca632f55SGrant Likely return; 183ca632f55SGrant Likely } 184ca632f55SGrant Likely 185a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 186ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 187a0d2642eSMika Westerberg return; 188a0d2642eSMika Westerberg } 189a0d2642eSMika Westerberg 190a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, true); 191ca632f55SGrant Likely } 192ca632f55SGrant Likely 193ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 194ca632f55SGrant Likely { 195ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 196ca632f55SGrant Likely 197ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 198ca632f55SGrant Likely return; 199ca632f55SGrant Likely 200ca632f55SGrant Likely if (chip->cs_control) { 201ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 202ca632f55SGrant Likely return; 203ca632f55SGrant Likely } 204ca632f55SGrant Likely 205a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 206ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 207a0d2642eSMika Westerberg return; 208a0d2642eSMika Westerberg } 209a0d2642eSMika Westerberg 210a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, false); 211ca632f55SGrant Likely } 212ca632f55SGrant Likely 213cd7bed00SMika Westerberg int pxa2xx_spi_flush(struct driver_data *drv_data) 214ca632f55SGrant Likely { 215ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 216ca632f55SGrant Likely 217ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 218ca632f55SGrant Likely 219ca632f55SGrant Likely do { 220ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 221ca632f55SGrant Likely read_SSDR(reg); 222ca632f55SGrant Likely } 223ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 224ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 225ca632f55SGrant Likely 226ca632f55SGrant Likely return limit; 227ca632f55SGrant Likely } 228ca632f55SGrant Likely 229ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 230ca632f55SGrant Likely { 231ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 232ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 233ca632f55SGrant Likely 234ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 235ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 236ca632f55SGrant Likely return 0; 237ca632f55SGrant Likely 238ca632f55SGrant Likely write_SSDR(0, reg); 239ca632f55SGrant Likely drv_data->tx += n_bytes; 240ca632f55SGrant Likely 241ca632f55SGrant Likely return 1; 242ca632f55SGrant Likely } 243ca632f55SGrant Likely 244ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 245ca632f55SGrant Likely { 246ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 247ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 248ca632f55SGrant Likely 249ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 250ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 251ca632f55SGrant Likely read_SSDR(reg); 252ca632f55SGrant Likely drv_data->rx += n_bytes; 253ca632f55SGrant Likely } 254ca632f55SGrant Likely 255ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 256ca632f55SGrant Likely } 257ca632f55SGrant Likely 258ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 259ca632f55SGrant Likely { 260ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 261ca632f55SGrant Likely 262ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 263ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 264ca632f55SGrant Likely return 0; 265ca632f55SGrant Likely 266ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 267ca632f55SGrant Likely ++drv_data->tx; 268ca632f55SGrant Likely 269ca632f55SGrant Likely return 1; 270ca632f55SGrant Likely } 271ca632f55SGrant Likely 272ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 273ca632f55SGrant Likely { 274ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 275ca632f55SGrant Likely 276ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 277ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 278ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 279ca632f55SGrant Likely ++drv_data->rx; 280ca632f55SGrant Likely } 281ca632f55SGrant Likely 282ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 283ca632f55SGrant Likely } 284ca632f55SGrant Likely 285ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 286ca632f55SGrant Likely { 287ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 288ca632f55SGrant Likely 289ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 290ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 291ca632f55SGrant Likely return 0; 292ca632f55SGrant Likely 293ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 294ca632f55SGrant Likely drv_data->tx += 2; 295ca632f55SGrant Likely 296ca632f55SGrant Likely return 1; 297ca632f55SGrant Likely } 298ca632f55SGrant Likely 299ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 300ca632f55SGrant Likely { 301ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 302ca632f55SGrant Likely 303ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 304ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 305ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 306ca632f55SGrant Likely drv_data->rx += 2; 307ca632f55SGrant Likely } 308ca632f55SGrant Likely 309ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 310ca632f55SGrant Likely } 311ca632f55SGrant Likely 312ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 313ca632f55SGrant Likely { 314ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 315ca632f55SGrant Likely 316ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 317ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 318ca632f55SGrant Likely return 0; 319ca632f55SGrant Likely 320ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 321ca632f55SGrant Likely drv_data->tx += 4; 322ca632f55SGrant Likely 323ca632f55SGrant Likely return 1; 324ca632f55SGrant Likely } 325ca632f55SGrant Likely 326ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 327ca632f55SGrant Likely { 328ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 329ca632f55SGrant Likely 330ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 331ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 332ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 333ca632f55SGrant Likely drv_data->rx += 4; 334ca632f55SGrant Likely } 335ca632f55SGrant Likely 336ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 337ca632f55SGrant Likely } 338ca632f55SGrant Likely 339cd7bed00SMika Westerberg void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 340ca632f55SGrant Likely { 341ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 342ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 343ca632f55SGrant Likely 344ca632f55SGrant Likely /* Move to next transfer */ 345ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 346ca632f55SGrant Likely drv_data->cur_transfer = 347ca632f55SGrant Likely list_entry(trans->transfer_list.next, 348ca632f55SGrant Likely struct spi_transfer, 349ca632f55SGrant Likely transfer_list); 350ca632f55SGrant Likely return RUNNING_STATE; 351ca632f55SGrant Likely } else 352ca632f55SGrant Likely return DONE_STATE; 353ca632f55SGrant Likely } 354ca632f55SGrant Likely 355ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 356ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 357ca632f55SGrant Likely { 358ca632f55SGrant Likely struct spi_transfer* last_transfer; 359ca632f55SGrant Likely struct spi_message *msg; 360ca632f55SGrant Likely 361ca632f55SGrant Likely msg = drv_data->cur_msg; 362ca632f55SGrant Likely drv_data->cur_msg = NULL; 363ca632f55SGrant Likely drv_data->cur_transfer = NULL; 364ca632f55SGrant Likely 365*23e2c2aaSAxel Lin last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 366ca632f55SGrant Likely transfer_list); 367ca632f55SGrant Likely 368ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 369ca632f55SGrant Likely if (last_transfer->delay_usecs) 370ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 371ca632f55SGrant Likely 372ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 373ca632f55SGrant Likely * a message with an error, or next message is for another chip 374ca632f55SGrant Likely */ 375ca632f55SGrant Likely if (!last_transfer->cs_change) 376ca632f55SGrant Likely cs_deassert(drv_data); 377ca632f55SGrant Likely else { 378ca632f55SGrant Likely struct spi_message *next_msg; 379ca632f55SGrant Likely 380ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 381ca632f55SGrant Likely * the next message is for the same chip. Don't waste 382ca632f55SGrant Likely * time with the following tests unless this was hinted. 383ca632f55SGrant Likely * 384ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 385ca632f55SGrant Likely * after calling msg->complete (below) the driver that 386ca632f55SGrant Likely * sent the current message could be unloaded, which 387ca632f55SGrant Likely * could invalidate the cs_control() callback... 388ca632f55SGrant Likely */ 389ca632f55SGrant Likely 390ca632f55SGrant Likely /* get a pointer to the next message, if any */ 3917f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 392ca632f55SGrant Likely 393ca632f55SGrant Likely /* see if the next and current messages point 394ca632f55SGrant Likely * to the same chip 395ca632f55SGrant Likely */ 396ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 397ca632f55SGrant Likely next_msg = NULL; 398ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 399ca632f55SGrant Likely cs_deassert(drv_data); 400ca632f55SGrant Likely } 401ca632f55SGrant Likely 4027f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 403ca632f55SGrant Likely drv_data->cur_chip = NULL; 404ca632f55SGrant Likely } 405ca632f55SGrant Likely 406ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 407ca632f55SGrant Likely { 408ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 409ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 410ca632f55SGrant Likely u32 sccr1_reg; 411ca632f55SGrant Likely 412ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 413ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 414ca632f55SGrant Likely sccr1_reg |= chip->threshold; 415ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 416ca632f55SGrant Likely } 417ca632f55SGrant Likely 418ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 419ca632f55SGrant Likely { 420ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 421ca632f55SGrant Likely 422ca632f55SGrant Likely /* Stop and reset SSP */ 423ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 424ca632f55SGrant Likely reset_sccr1(drv_data); 425ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 426ca632f55SGrant Likely write_SSTO(0, reg); 427cd7bed00SMika Westerberg pxa2xx_spi_flush(drv_data); 428ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 429ca632f55SGrant Likely 430ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 431ca632f55SGrant Likely 432ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 433ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 434ca632f55SGrant Likely } 435ca632f55SGrant Likely 436ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 437ca632f55SGrant Likely { 438ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 439ca632f55SGrant Likely 440ca632f55SGrant Likely /* Stop SSP */ 441ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 442ca632f55SGrant Likely reset_sccr1(drv_data); 443ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 444ca632f55SGrant Likely write_SSTO(0, reg); 445ca632f55SGrant Likely 446ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 447ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 448ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 449ca632f55SGrant Likely 450ca632f55SGrant Likely /* Transfer delays and chip select release are 451ca632f55SGrant Likely * handled in pump_transfers or giveback 452ca632f55SGrant Likely */ 453ca632f55SGrant Likely 454ca632f55SGrant Likely /* Move to next transfer */ 455cd7bed00SMika Westerberg drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 456ca632f55SGrant Likely 457ca632f55SGrant Likely /* Schedule transfer tasklet */ 458ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 459ca632f55SGrant Likely } 460ca632f55SGrant Likely 461ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 462ca632f55SGrant Likely { 463ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 464ca632f55SGrant Likely 465ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 466ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 467ca632f55SGrant Likely 468ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 469ca632f55SGrant Likely 470ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 471ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 472ca632f55SGrant Likely return IRQ_HANDLED; 473ca632f55SGrant Likely } 474ca632f55SGrant Likely 475ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 476ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 477ca632f55SGrant Likely if (drv_data->read(drv_data)) { 478ca632f55SGrant Likely int_transfer_complete(drv_data); 479ca632f55SGrant Likely return IRQ_HANDLED; 480ca632f55SGrant Likely } 481ca632f55SGrant Likely } 482ca632f55SGrant Likely 483ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 484ca632f55SGrant Likely do { 485ca632f55SGrant Likely if (drv_data->read(drv_data)) { 486ca632f55SGrant Likely int_transfer_complete(drv_data); 487ca632f55SGrant Likely return IRQ_HANDLED; 488ca632f55SGrant Likely } 489ca632f55SGrant Likely } while (drv_data->write(drv_data)); 490ca632f55SGrant Likely 491ca632f55SGrant Likely if (drv_data->read(drv_data)) { 492ca632f55SGrant Likely int_transfer_complete(drv_data); 493ca632f55SGrant Likely return IRQ_HANDLED; 494ca632f55SGrant Likely } 495ca632f55SGrant Likely 496ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 497ca632f55SGrant Likely u32 bytes_left; 498ca632f55SGrant Likely u32 sccr1_reg; 499ca632f55SGrant Likely 500ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 501ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 502ca632f55SGrant Likely 503ca632f55SGrant Likely /* 504ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 505ca632f55SGrant Likely * remaining RX bytes. 506ca632f55SGrant Likely */ 507ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 508ca632f55SGrant Likely 509ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 510ca632f55SGrant Likely 511ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 512ca632f55SGrant Likely switch (drv_data->n_bytes) { 513ca632f55SGrant Likely case 4: 514ca632f55SGrant Likely bytes_left >>= 1; 515ca632f55SGrant Likely case 2: 516ca632f55SGrant Likely bytes_left >>= 1; 517ca632f55SGrant Likely } 518ca632f55SGrant Likely 519ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 520ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 521ca632f55SGrant Likely 522ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 523ca632f55SGrant Likely } 524ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 525ca632f55SGrant Likely } 526ca632f55SGrant Likely 527ca632f55SGrant Likely /* We did something */ 528ca632f55SGrant Likely return IRQ_HANDLED; 529ca632f55SGrant Likely } 530ca632f55SGrant Likely 531ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 532ca632f55SGrant Likely { 533ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 534ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 5357d94a505SMika Westerberg u32 sccr1_reg; 536ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 537ca632f55SGrant Likely u32 status; 538ca632f55SGrant Likely 5397d94a505SMika Westerberg /* 5407d94a505SMika Westerberg * The IRQ might be shared with other peripherals so we must first 5417d94a505SMika Westerberg * check that are we RPM suspended or not. If we are we assume that 5427d94a505SMika Westerberg * the IRQ was not for us (we shouldn't be RPM suspended when the 5437d94a505SMika Westerberg * interrupt is enabled). 5447d94a505SMika Westerberg */ 5457d94a505SMika Westerberg if (pm_runtime_suspended(&drv_data->pdev->dev)) 5467d94a505SMika Westerberg return IRQ_NONE; 5477d94a505SMika Westerberg 548269e4a41SMika Westerberg /* 549269e4a41SMika Westerberg * If the device is not yet in RPM suspended state and we get an 550269e4a41SMika Westerberg * interrupt that is meant for another device, check if status bits 551269e4a41SMika Westerberg * are all set to one. That means that the device is already 552269e4a41SMika Westerberg * powered off. 553269e4a41SMika Westerberg */ 554ca632f55SGrant Likely status = read_SSSR(reg); 555269e4a41SMika Westerberg if (status == ~0) 556269e4a41SMika Westerberg return IRQ_NONE; 557269e4a41SMika Westerberg 558269e4a41SMika Westerberg sccr1_reg = read_SSCR1(reg); 559ca632f55SGrant Likely 560ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 561ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 562ca632f55SGrant Likely mask &= ~SSSR_TFS; 563ca632f55SGrant Likely 564ca632f55SGrant Likely if (!(status & mask)) 565ca632f55SGrant Likely return IRQ_NONE; 566ca632f55SGrant Likely 567ca632f55SGrant Likely if (!drv_data->cur_msg) { 568ca632f55SGrant Likely 569ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 570ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 571ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 572ca632f55SGrant Likely write_SSTO(0, reg); 573ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 574ca632f55SGrant Likely 575f6bd03a7SJarkko Nikula dev_err(&drv_data->pdev->dev, 576f6bd03a7SJarkko Nikula "bad message state in interrupt handler\n"); 577ca632f55SGrant Likely 578ca632f55SGrant Likely /* Never fail */ 579ca632f55SGrant Likely return IRQ_HANDLED; 580ca632f55SGrant Likely } 581ca632f55SGrant Likely 582ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 583ca632f55SGrant Likely } 584ca632f55SGrant Likely 5853343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 586ca632f55SGrant Likely { 5873343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 5883343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 5893343b7a6SMika Westerberg 5903343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 591ca632f55SGrant Likely 592ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 593ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 594ca632f55SGrant Likely else 595ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 596ca632f55SGrant Likely } 597ca632f55SGrant Likely 598ca632f55SGrant Likely static void pump_transfers(unsigned long data) 599ca632f55SGrant Likely { 600ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 601ca632f55SGrant Likely struct spi_message *message = NULL; 602ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 603ca632f55SGrant Likely struct spi_transfer *previous = NULL; 604ca632f55SGrant Likely struct chip_data *chip = NULL; 605ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 606ca632f55SGrant Likely u32 clk_div = 0; 607ca632f55SGrant Likely u8 bits = 0; 608ca632f55SGrant Likely u32 speed = 0; 609ca632f55SGrant Likely u32 cr0; 610ca632f55SGrant Likely u32 cr1; 611ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 612ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 613ca632f55SGrant Likely 614ca632f55SGrant Likely /* Get current state information */ 615ca632f55SGrant Likely message = drv_data->cur_msg; 616ca632f55SGrant Likely transfer = drv_data->cur_transfer; 617ca632f55SGrant Likely chip = drv_data->cur_chip; 618ca632f55SGrant Likely 619ca632f55SGrant Likely /* Handle for abort */ 620ca632f55SGrant Likely if (message->state == ERROR_STATE) { 621ca632f55SGrant Likely message->status = -EIO; 622ca632f55SGrant Likely giveback(drv_data); 623ca632f55SGrant Likely return; 624ca632f55SGrant Likely } 625ca632f55SGrant Likely 626ca632f55SGrant Likely /* Handle end of message */ 627ca632f55SGrant Likely if (message->state == DONE_STATE) { 628ca632f55SGrant Likely message->status = 0; 629ca632f55SGrant Likely giveback(drv_data); 630ca632f55SGrant Likely return; 631ca632f55SGrant Likely } 632ca632f55SGrant Likely 633ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 634ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 635ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 636ca632f55SGrant Likely struct spi_transfer, 637ca632f55SGrant Likely transfer_list); 638ca632f55SGrant Likely if (previous->delay_usecs) 639ca632f55SGrant Likely udelay(previous->delay_usecs); 640ca632f55SGrant Likely 641ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 642ca632f55SGrant Likely if (previous->cs_change) 643ca632f55SGrant Likely cs_deassert(drv_data); 644ca632f55SGrant Likely } 645ca632f55SGrant Likely 646cd7bed00SMika Westerberg /* Check if we can DMA this transfer */ 647cd7bed00SMika Westerberg if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 648ca632f55SGrant Likely 649ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 650ca632f55SGrant Likely if (message->is_dma_mapped 651ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 652ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 653f6bd03a7SJarkko Nikula "pump_transfers: mapped transfer length of " 654f6bd03a7SJarkko Nikula "%u is greater than %d\n", 655ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 656ca632f55SGrant Likely message->status = -EINVAL; 657ca632f55SGrant Likely giveback(drv_data); 658ca632f55SGrant Likely return; 659ca632f55SGrant Likely } 660ca632f55SGrant Likely 661ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 662f6bd03a7SJarkko Nikula dev_warn_ratelimited(&message->spi->dev, 663f6bd03a7SJarkko Nikula "pump_transfers: DMA disabled for transfer length %ld " 664ca632f55SGrant Likely "greater than %d\n", 665ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 666ca632f55SGrant Likely } 667ca632f55SGrant Likely 668ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 669cd7bed00SMika Westerberg if (pxa2xx_spi_flush(drv_data) == 0) { 670ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 671ca632f55SGrant Likely message->status = -EIO; 672ca632f55SGrant Likely giveback(drv_data); 673ca632f55SGrant Likely return; 674ca632f55SGrant Likely } 675ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 676ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 677ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 678ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 679ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 680ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 681ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 682cd7bed00SMika Westerberg drv_data->len = transfer->len; 683ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 684ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 685ca632f55SGrant Likely 686ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 687ca632f55SGrant Likely cr0 = chip->cr0; 688ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 689ca632f55SGrant Likely 690ca632f55SGrant Likely bits = chip->bits_per_word; 691ca632f55SGrant Likely speed = chip->speed_hz; 692ca632f55SGrant Likely 693ca632f55SGrant Likely if (transfer->speed_hz) 694ca632f55SGrant Likely speed = transfer->speed_hz; 695ca632f55SGrant Likely 696ca632f55SGrant Likely if (transfer->bits_per_word) 697ca632f55SGrant Likely bits = transfer->bits_per_word; 698ca632f55SGrant Likely 6993343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, speed); 700ca632f55SGrant Likely 701ca632f55SGrant Likely if (bits <= 8) { 702ca632f55SGrant Likely drv_data->n_bytes = 1; 703ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 704ca632f55SGrant Likely u8_reader : null_reader; 705ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 706ca632f55SGrant Likely u8_writer : null_writer; 707ca632f55SGrant Likely } else if (bits <= 16) { 708ca632f55SGrant Likely drv_data->n_bytes = 2; 709ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 710ca632f55SGrant Likely u16_reader : null_reader; 711ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 712ca632f55SGrant Likely u16_writer : null_writer; 713ca632f55SGrant Likely } else if (bits <= 32) { 714ca632f55SGrant Likely drv_data->n_bytes = 4; 715ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 716ca632f55SGrant Likely u32_reader : null_reader; 717ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 718ca632f55SGrant Likely u32_writer : null_writer; 719ca632f55SGrant Likely } 720ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 721ca632f55SGrant Likely * thresholds and burst also */ 722ca632f55SGrant Likely if (chip->enable_dma) { 723cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 724cd7bed00SMika Westerberg message->spi, 725ca632f55SGrant Likely bits, &dma_burst, 726ca632f55SGrant Likely &dma_thresh)) 727f6bd03a7SJarkko Nikula dev_warn_ratelimited(&message->spi->dev, 728f6bd03a7SJarkko Nikula "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 729ca632f55SGrant Likely } 730ca632f55SGrant Likely 731ca632f55SGrant Likely cr0 = clk_div 732ca632f55SGrant Likely | SSCR0_Motorola 733ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 734ca632f55SGrant Likely | SSCR0_SSE 735ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 736ca632f55SGrant Likely } 737ca632f55SGrant Likely 738ca632f55SGrant Likely message->state = RUNNING_STATE; 739ca632f55SGrant Likely 740ca632f55SGrant Likely drv_data->dma_mapped = 0; 741cd7bed00SMika Westerberg if (pxa2xx_spi_dma_is_possible(drv_data->len)) 742cd7bed00SMika Westerberg drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 743ca632f55SGrant Likely if (drv_data->dma_mapped) { 744ca632f55SGrant Likely 745ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 746cd7bed00SMika Westerberg drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 747ca632f55SGrant Likely 748cd7bed00SMika Westerberg pxa2xx_spi_dma_prepare(drv_data, dma_burst); 749ca632f55SGrant Likely 750ca632f55SGrant Likely /* Clear status and start DMA engine */ 751ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 752ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 753cd7bed00SMika Westerberg 754cd7bed00SMika Westerberg pxa2xx_spi_dma_start(drv_data); 755ca632f55SGrant Likely } else { 756ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 757ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 758ca632f55SGrant Likely 759ca632f55SGrant Likely /* Clear status */ 760ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 761ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 762ca632f55SGrant Likely } 763ca632f55SGrant Likely 764a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 765a0d2642eSMika Westerberg if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) 766a0d2642eSMika Westerberg write_SSIRF(chip->lpss_rx_threshold, reg); 767a0d2642eSMika Westerberg if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) 768a0d2642eSMika Westerberg write_SSITF(chip->lpss_tx_threshold, reg); 769a0d2642eSMika Westerberg } 770a0d2642eSMika Westerberg 771ca632f55SGrant Likely /* see if we need to reload the config registers */ 772ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 773ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 774ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 775ca632f55SGrant Likely 776ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 777ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 778ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 779ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 780ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 781ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 782ca632f55SGrant Likely /* restart the SSP */ 783ca632f55SGrant Likely write_SSCR0(cr0, reg); 784ca632f55SGrant Likely 785ca632f55SGrant Likely } else { 786ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 787ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 788ca632f55SGrant Likely } 789ca632f55SGrant Likely 790ca632f55SGrant Likely cs_assert(drv_data); 791ca632f55SGrant Likely 792ca632f55SGrant Likely /* after chip select, release the data by enabling service 793ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 794ca632f55SGrant Likely write_SSCR1(cr1, reg); 795ca632f55SGrant Likely } 796ca632f55SGrant Likely 7977f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 7987f86bde9SMika Westerberg struct spi_message *msg) 799ca632f55SGrant Likely { 8007f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 801ca632f55SGrant Likely 8027f86bde9SMika Westerberg drv_data->cur_msg = msg; 803ca632f55SGrant Likely /* Initial message state*/ 804ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 805ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 806ca632f55SGrant Likely struct spi_transfer, 807ca632f55SGrant Likely transfer_list); 808ca632f55SGrant Likely 809ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 810ca632f55SGrant Likely * chip configuration */ 811ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 812ca632f55SGrant Likely 813ca632f55SGrant Likely /* Mark as busy and launch transfers */ 814ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 815ca632f55SGrant Likely return 0; 816ca632f55SGrant Likely } 817ca632f55SGrant Likely 8187d94a505SMika Westerberg static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 8197d94a505SMika Westerberg { 8207d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 8217d94a505SMika Westerberg 8227d94a505SMika Westerberg /* Disable the SSP now */ 8237d94a505SMika Westerberg write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, 8247d94a505SMika Westerberg drv_data->ioaddr); 8257d94a505SMika Westerberg 8267d94a505SMika Westerberg return 0; 8277d94a505SMika Westerberg } 8287d94a505SMika Westerberg 829ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 830ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 831ca632f55SGrant Likely { 832ca632f55SGrant Likely int err = 0; 833ca632f55SGrant Likely 834ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 835ca632f55SGrant Likely return 0; 836ca632f55SGrant Likely 837ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 838ca632f55SGrant Likely * different chip_info, release previously requested GPIO 839ca632f55SGrant Likely */ 840ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 841ca632f55SGrant Likely gpio_free(chip->gpio_cs); 842ca632f55SGrant Likely 843ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 844ca632f55SGrant Likely if (chip_info->cs_control) { 845ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 846ca632f55SGrant Likely return 0; 847ca632f55SGrant Likely } 848ca632f55SGrant Likely 849ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 850ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 851ca632f55SGrant Likely if (err) { 852f6bd03a7SJarkko Nikula dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 853f6bd03a7SJarkko Nikula chip_info->gpio_cs); 854ca632f55SGrant Likely return err; 855ca632f55SGrant Likely } 856ca632f55SGrant Likely 857ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 858ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 859ca632f55SGrant Likely 860ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 861ca632f55SGrant Likely !chip->gpio_cs_inverted); 862ca632f55SGrant Likely } 863ca632f55SGrant Likely 864ca632f55SGrant Likely return err; 865ca632f55SGrant Likely } 866ca632f55SGrant Likely 867ca632f55SGrant Likely static int setup(struct spi_device *spi) 868ca632f55SGrant Likely { 869ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 870ca632f55SGrant Likely struct chip_data *chip; 871ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 872ca632f55SGrant Likely unsigned int clk_div; 873a0d2642eSMika Westerberg uint tx_thres, tx_hi_thres, rx_thres; 874a0d2642eSMika Westerberg 875a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 876a0d2642eSMika Westerberg tx_thres = LPSS_TX_LOTHRESH_DFLT; 877a0d2642eSMika Westerberg tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 878a0d2642eSMika Westerberg rx_thres = LPSS_RX_THRESH_DFLT; 879a0d2642eSMika Westerberg } else { 880a0d2642eSMika Westerberg tx_thres = TX_THRESH_DFLT; 881a0d2642eSMika Westerberg tx_hi_thres = 0; 882a0d2642eSMika Westerberg rx_thres = RX_THRESH_DFLT; 883a0d2642eSMika Westerberg } 884ca632f55SGrant Likely 885ca632f55SGrant Likely /* Only alloc on first setup */ 886ca632f55SGrant Likely chip = spi_get_ctldata(spi); 887ca632f55SGrant Likely if (!chip) { 888ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 889ca632f55SGrant Likely if (!chip) { 890ca632f55SGrant Likely dev_err(&spi->dev, 891ca632f55SGrant Likely "failed setup: can't allocate chip data\n"); 892ca632f55SGrant Likely return -ENOMEM; 893ca632f55SGrant Likely } 894ca632f55SGrant Likely 895ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 896ca632f55SGrant Likely if (spi->chip_select > 4) { 897f6bd03a7SJarkko Nikula dev_err(&spi->dev, 898f6bd03a7SJarkko Nikula "failed setup: cs number must not be > 4.\n"); 899ca632f55SGrant Likely kfree(chip); 900ca632f55SGrant Likely return -EINVAL; 901ca632f55SGrant Likely } 902ca632f55SGrant Likely 903ca632f55SGrant Likely chip->frm = spi->chip_select; 904ca632f55SGrant Likely } else 905ca632f55SGrant Likely chip->gpio_cs = -1; 906ca632f55SGrant Likely chip->enable_dma = 0; 907ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 908ca632f55SGrant Likely } 909ca632f55SGrant Likely 910ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 911ca632f55SGrant Likely * if chip_info exists, use it */ 912ca632f55SGrant Likely chip_info = spi->controller_data; 913ca632f55SGrant Likely 914ca632f55SGrant Likely /* chip_info isn't always needed */ 915ca632f55SGrant Likely chip->cr1 = 0; 916ca632f55SGrant Likely if (chip_info) { 917ca632f55SGrant Likely if (chip_info->timeout) 918ca632f55SGrant Likely chip->timeout = chip_info->timeout; 919ca632f55SGrant Likely if (chip_info->tx_threshold) 920ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 921a0d2642eSMika Westerberg if (chip_info->tx_hi_threshold) 922a0d2642eSMika Westerberg tx_hi_thres = chip_info->tx_hi_threshold; 923ca632f55SGrant Likely if (chip_info->rx_threshold) 924ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 925ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 926ca632f55SGrant Likely chip->dma_threshold = 0; 927ca632f55SGrant Likely if (chip_info->enable_loopback) 928ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 929a3496855SMika Westerberg } else if (ACPI_HANDLE(&spi->dev)) { 930a3496855SMika Westerberg /* 931a3496855SMika Westerberg * Slave devices enumerated from ACPI namespace don't 932a3496855SMika Westerberg * usually have chip_info but we still might want to use 933a3496855SMika Westerberg * DMA with them. 934a3496855SMika Westerberg */ 935a3496855SMika Westerberg chip->enable_dma = drv_data->master_info->enable_dma; 936ca632f55SGrant Likely } 937ca632f55SGrant Likely 938ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 939ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 940ca632f55SGrant Likely 941a0d2642eSMika Westerberg chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 942a0d2642eSMika Westerberg chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 943a0d2642eSMika Westerberg | SSITF_TxHiThresh(tx_hi_thres); 944a0d2642eSMika Westerberg 945ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 946ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 947ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 948ca632f55SGrant Likely if (chip->enable_dma) { 949ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 950cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 951cd7bed00SMika Westerberg spi->bits_per_word, 952ca632f55SGrant Likely &chip->dma_burst_size, 953ca632f55SGrant Likely &chip->dma_threshold)) { 954f6bd03a7SJarkko Nikula dev_warn(&spi->dev, 955f6bd03a7SJarkko Nikula "in setup: DMA burst size reduced to match bits_per_word\n"); 956ca632f55SGrant Likely } 957ca632f55SGrant Likely } 958ca632f55SGrant Likely 9593343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 960ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 961ca632f55SGrant Likely 962ca632f55SGrant Likely chip->cr0 = clk_div 963ca632f55SGrant Likely | SSCR0_Motorola 964ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 965ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 966ca632f55SGrant Likely | SSCR0_SSE 967ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 968ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 969ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 970ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 971ca632f55SGrant Likely 972b833172fSMika Westerberg if (spi->mode & SPI_LOOP) 973b833172fSMika Westerberg chip->cr1 |= SSCR1_LBM; 974b833172fSMika Westerberg 975ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 976ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 977ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 9783343b7a6SMika Westerberg drv_data->max_clk_rate 979ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 980ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 981ca632f55SGrant Likely else 982ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 9833343b7a6SMika Westerberg drv_data->max_clk_rate / 2 984ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 985ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 986ca632f55SGrant Likely 987ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 988ca632f55SGrant Likely chip->n_bytes = 1; 989ca632f55SGrant Likely chip->read = u8_reader; 990ca632f55SGrant Likely chip->write = u8_writer; 991ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 992ca632f55SGrant Likely chip->n_bytes = 2; 993ca632f55SGrant Likely chip->read = u16_reader; 994ca632f55SGrant Likely chip->write = u16_writer; 995ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 996ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 997ca632f55SGrant Likely chip->n_bytes = 4; 998ca632f55SGrant Likely chip->read = u32_reader; 999ca632f55SGrant Likely chip->write = u32_writer; 1000ca632f55SGrant Likely } 1001ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 1002ca632f55SGrant Likely 1003ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1004ca632f55SGrant Likely 1005ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 1006ca632f55SGrant Likely return 0; 1007ca632f55SGrant Likely 1008ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 1009ca632f55SGrant Likely } 1010ca632f55SGrant Likely 1011ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 1012ca632f55SGrant Likely { 1013ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1014ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely if (!chip) 1017ca632f55SGrant Likely return; 1018ca632f55SGrant Likely 1019ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1020ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1021ca632f55SGrant Likely 1022ca632f55SGrant Likely kfree(chip); 1023ca632f55SGrant Likely } 1024ca632f55SGrant Likely 1025a3496855SMika Westerberg #ifdef CONFIG_ACPI 1026a3496855SMika Westerberg static struct pxa2xx_spi_master * 1027a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1028a3496855SMika Westerberg { 1029a3496855SMika Westerberg struct pxa2xx_spi_master *pdata; 1030a3496855SMika Westerberg struct acpi_device *adev; 1031a3496855SMika Westerberg struct ssp_device *ssp; 1032a3496855SMika Westerberg struct resource *res; 1033a3496855SMika Westerberg int devid; 1034a3496855SMika Westerberg 1035a3496855SMika Westerberg if (!ACPI_HANDLE(&pdev->dev) || 1036a3496855SMika Westerberg acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1037a3496855SMika Westerberg return NULL; 1038a3496855SMika Westerberg 1039cc0ee987SMika Westerberg pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1040a3496855SMika Westerberg if (!pdata) { 1041a3496855SMika Westerberg dev_err(&pdev->dev, 1042a3496855SMika Westerberg "failed to allocate memory for platform data\n"); 1043a3496855SMika Westerberg return NULL; 1044a3496855SMika Westerberg } 1045a3496855SMika Westerberg 1046a3496855SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1047a3496855SMika Westerberg if (!res) 1048a3496855SMika Westerberg return NULL; 1049a3496855SMika Westerberg 1050a3496855SMika Westerberg ssp = &pdata->ssp; 1051a3496855SMika Westerberg 1052a3496855SMika Westerberg ssp->phys_base = res->start; 1053cbfd6a21SSachin Kamat ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1054cbfd6a21SSachin Kamat if (IS_ERR(ssp->mmio_base)) 10556dc81f6fSMika Westerberg return NULL; 1056a3496855SMika Westerberg 1057a3496855SMika Westerberg ssp->clk = devm_clk_get(&pdev->dev, NULL); 1058a3496855SMika Westerberg ssp->irq = platform_get_irq(pdev, 0); 1059a3496855SMika Westerberg ssp->type = LPSS_SSP; 1060a3496855SMika Westerberg ssp->pdev = pdev; 1061a3496855SMika Westerberg 1062a3496855SMika Westerberg ssp->port_id = -1; 1063a3496855SMika Westerberg if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1064a3496855SMika Westerberg ssp->port_id = devid; 1065a3496855SMika Westerberg 1066a3496855SMika Westerberg pdata->num_chipselect = 1; 1067cddb339bSMika Westerberg pdata->enable_dma = true; 1068483c3191SMika Westerberg pdata->tx_chan_id = -1; 1069483c3191SMika Westerberg pdata->rx_chan_id = -1; 1070a3496855SMika Westerberg 1071a3496855SMika Westerberg return pdata; 1072a3496855SMika Westerberg } 1073a3496855SMika Westerberg 1074a3496855SMika Westerberg static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1075a3496855SMika Westerberg { "INT33C0", 0 }, 1076a3496855SMika Westerberg { "INT33C1", 0 }, 107754acbd96SMika Westerberg { "INT3430", 0 }, 107854acbd96SMika Westerberg { "INT3431", 0 }, 10794b30f2a1SMika Westerberg { "80860F0E", 0 }, 1080a3496855SMika Westerberg { }, 1081a3496855SMika Westerberg }; 1082a3496855SMika Westerberg MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1083a3496855SMika Westerberg #else 1084a3496855SMika Westerberg static inline struct pxa2xx_spi_master * 1085a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1086a3496855SMika Westerberg { 1087a3496855SMika Westerberg return NULL; 1088a3496855SMika Westerberg } 1089a3496855SMika Westerberg #endif 1090a3496855SMika Westerberg 1091fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 1092ca632f55SGrant Likely { 1093ca632f55SGrant Likely struct device *dev = &pdev->dev; 1094ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 1095ca632f55SGrant Likely struct spi_master *master; 1096ca632f55SGrant Likely struct driver_data *drv_data; 1097ca632f55SGrant Likely struct ssp_device *ssp; 1098ca632f55SGrant Likely int status; 1099ca632f55SGrant Likely 1100851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 1101851bacf5SMika Westerberg if (!platform_info) { 1102a3496855SMika Westerberg platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1103a3496855SMika Westerberg if (!platform_info) { 1104851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 1105851bacf5SMika Westerberg return -ENODEV; 1106851bacf5SMika Westerberg } 1107a3496855SMika Westerberg } 1108ca632f55SGrant Likely 1109ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 1110851bacf5SMika Westerberg if (!ssp) 1111851bacf5SMika Westerberg ssp = &platform_info->ssp; 1112851bacf5SMika Westerberg 1113851bacf5SMika Westerberg if (!ssp->mmio_base) { 1114851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 1115ca632f55SGrant Likely return -ENODEV; 1116ca632f55SGrant Likely } 1117ca632f55SGrant Likely 1118ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 1119ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1120ca632f55SGrant Likely if (!master) { 1121ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1122ca632f55SGrant Likely pxa_ssp_free(ssp); 1123ca632f55SGrant Likely return -ENOMEM; 1124ca632f55SGrant Likely } 1125ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 1126ca632f55SGrant Likely drv_data->master = master; 1127ca632f55SGrant Likely drv_data->master_info = platform_info; 1128ca632f55SGrant Likely drv_data->pdev = pdev; 1129ca632f55SGrant Likely drv_data->ssp = ssp; 1130ca632f55SGrant Likely 1131ca632f55SGrant Likely master->dev.parent = &pdev->dev; 1132ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 1133ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1134b833172fSMika Westerberg master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1135ca632f55SGrant Likely 1136851bacf5SMika Westerberg master->bus_num = ssp->port_id; 1137ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 1138ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 1139ca632f55SGrant Likely master->cleanup = cleanup; 1140ca632f55SGrant Likely master->setup = setup; 11417f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 11427d94a505SMika Westerberg master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 11437dd62787SMark Brown master->auto_runtime_pm = true; 1144ca632f55SGrant Likely 1145ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 11462b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1147ca632f55SGrant Likely 1148ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 1149ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 1150ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 115124778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1152ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1153ca632f55SGrant Likely drv_data->dma_cr1 = 0; 1154ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 1155ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1156ca632f55SGrant Likely } else { 115724778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1158ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 11595928808eSMika Westerberg drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1160ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1161ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1162ca632f55SGrant Likely } 1163ca632f55SGrant Likely 1164ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1165ca632f55SGrant Likely drv_data); 1166ca632f55SGrant Likely if (status < 0) { 1167ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1168ca632f55SGrant Likely goto out_error_master_alloc; 1169ca632f55SGrant Likely } 1170ca632f55SGrant Likely 1171ca632f55SGrant Likely /* Setup DMA if requested */ 1172ca632f55SGrant Likely drv_data->tx_channel = -1; 1173ca632f55SGrant Likely drv_data->rx_channel = -1; 1174ca632f55SGrant Likely if (platform_info->enable_dma) { 1175cd7bed00SMika Westerberg status = pxa2xx_spi_dma_setup(drv_data); 1176cd7bed00SMika Westerberg if (status) { 1177cddb339bSMika Westerberg dev_dbg(dev, "no DMA channels available, using PIO\n"); 1178cd7bed00SMika Westerberg platform_info->enable_dma = false; 1179ca632f55SGrant Likely } 1180ca632f55SGrant Likely } 1181ca632f55SGrant Likely 1182ca632f55SGrant Likely /* Enable SOC clock */ 11833343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 11843343b7a6SMika Westerberg 11853343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1186ca632f55SGrant Likely 1187ca632f55SGrant Likely /* Load default SSP configuration */ 1188ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1189ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1190ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 1191ca632f55SGrant Likely drv_data->ioaddr); 1192ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 1193ca632f55SGrant Likely | SSCR0_Motorola 1194ca632f55SGrant Likely | SSCR0_DataSize(8), 1195ca632f55SGrant Likely drv_data->ioaddr); 1196ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1197ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 1198ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 1199ca632f55SGrant Likely 1200a0d2642eSMika Westerberg lpss_ssp_setup(drv_data); 1201a0d2642eSMika Westerberg 12027f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 12037f86bde9SMika Westerberg (unsigned long)drv_data); 1204ca632f55SGrant Likely 1205ca632f55SGrant Likely /* Register with the SPI framework */ 1206ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1207a807fcd0SJingoo Han status = devm_spi_register_master(&pdev->dev, master); 1208ca632f55SGrant Likely if (status != 0) { 1209ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 12107f86bde9SMika Westerberg goto out_error_clock_enabled; 1211ca632f55SGrant Likely } 1212ca632f55SGrant Likely 12137d94a505SMika Westerberg pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 12147d94a505SMika Westerberg pm_runtime_use_autosuspend(&pdev->dev); 12157d94a505SMika Westerberg pm_runtime_set_active(&pdev->dev); 12167d94a505SMika Westerberg pm_runtime_enable(&pdev->dev); 12177d94a505SMika Westerberg 1218ca632f55SGrant Likely return status; 1219ca632f55SGrant Likely 1220ca632f55SGrant Likely out_error_clock_enabled: 12213343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1222cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1223ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1224ca632f55SGrant Likely 1225ca632f55SGrant Likely out_error_master_alloc: 1226ca632f55SGrant Likely spi_master_put(master); 1227ca632f55SGrant Likely pxa_ssp_free(ssp); 1228ca632f55SGrant Likely return status; 1229ca632f55SGrant Likely } 1230ca632f55SGrant Likely 1231ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1232ca632f55SGrant Likely { 1233ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1234ca632f55SGrant Likely struct ssp_device *ssp; 1235ca632f55SGrant Likely 1236ca632f55SGrant Likely if (!drv_data) 1237ca632f55SGrant Likely return 0; 1238ca632f55SGrant Likely ssp = drv_data->ssp; 1239ca632f55SGrant Likely 12407d94a505SMika Westerberg pm_runtime_get_sync(&pdev->dev); 12417d94a505SMika Westerberg 1242ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1243ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 12443343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1245ca632f55SGrant Likely 1246ca632f55SGrant Likely /* Release DMA */ 1247cd7bed00SMika Westerberg if (drv_data->master_info->enable_dma) 1248cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1249ca632f55SGrant Likely 12507d94a505SMika Westerberg pm_runtime_put_noidle(&pdev->dev); 12517d94a505SMika Westerberg pm_runtime_disable(&pdev->dev); 12527d94a505SMika Westerberg 1253ca632f55SGrant Likely /* Release IRQ */ 1254ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1255ca632f55SGrant Likely 1256ca632f55SGrant Likely /* Release SSP */ 1257ca632f55SGrant Likely pxa_ssp_free(ssp); 1258ca632f55SGrant Likely 1259ca632f55SGrant Likely return 0; 1260ca632f55SGrant Likely } 1261ca632f55SGrant Likely 1262ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1263ca632f55SGrant Likely { 1264ca632f55SGrant Likely int status = 0; 1265ca632f55SGrant Likely 1266ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1267ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1268ca632f55SGrant Likely } 1269ca632f55SGrant Likely 1270382cebb0SMika Westerberg #ifdef CONFIG_PM_SLEEP 1271ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1272ca632f55SGrant Likely { 1273ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1274ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1275ca632f55SGrant Likely int status = 0; 1276ca632f55SGrant Likely 12777f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1278ca632f55SGrant Likely if (status != 0) 1279ca632f55SGrant Likely return status; 1280ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 12813343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1282ca632f55SGrant Likely 1283ca632f55SGrant Likely return 0; 1284ca632f55SGrant Likely } 1285ca632f55SGrant Likely 1286ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1287ca632f55SGrant Likely { 1288ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1289ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1290ca632f55SGrant Likely int status = 0; 1291ca632f55SGrant Likely 1292cd7bed00SMika Westerberg pxa2xx_spi_dma_resume(drv_data); 1293ca632f55SGrant Likely 1294ca632f55SGrant Likely /* Enable the SSP clock */ 12953343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1296ca632f55SGrant Likely 1297c50325f7SChew, Chiau Ee /* Restore LPSS private register bits */ 1298c50325f7SChew, Chiau Ee lpss_ssp_setup(drv_data); 1299c50325f7SChew, Chiau Ee 1300ca632f55SGrant Likely /* Start the queue running */ 13017f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1302ca632f55SGrant Likely if (status != 0) { 1303ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1304ca632f55SGrant Likely return status; 1305ca632f55SGrant Likely } 1306ca632f55SGrant Likely 1307ca632f55SGrant Likely return 0; 1308ca632f55SGrant Likely } 13097d94a505SMika Westerberg #endif 13107d94a505SMika Westerberg 13117d94a505SMika Westerberg #ifdef CONFIG_PM_RUNTIME 13127d94a505SMika Westerberg static int pxa2xx_spi_runtime_suspend(struct device *dev) 13137d94a505SMika Westerberg { 13147d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 13157d94a505SMika Westerberg 13167d94a505SMika Westerberg clk_disable_unprepare(drv_data->ssp->clk); 13177d94a505SMika Westerberg return 0; 13187d94a505SMika Westerberg } 13197d94a505SMika Westerberg 13207d94a505SMika Westerberg static int pxa2xx_spi_runtime_resume(struct device *dev) 13217d94a505SMika Westerberg { 13227d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 13237d94a505SMika Westerberg 13247d94a505SMika Westerberg clk_prepare_enable(drv_data->ssp->clk); 13257d94a505SMika Westerberg return 0; 13267d94a505SMika Westerberg } 13277d94a505SMika Westerberg #endif 1328ca632f55SGrant Likely 1329ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 13307d94a505SMika Westerberg SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 13317d94a505SMika Westerberg SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 13327d94a505SMika Westerberg pxa2xx_spi_runtime_resume, NULL) 1333ca632f55SGrant Likely }; 1334ca632f55SGrant Likely 1335ca632f55SGrant Likely static struct platform_driver driver = { 1336ca632f55SGrant Likely .driver = { 1337ca632f55SGrant Likely .name = "pxa2xx-spi", 1338ca632f55SGrant Likely .owner = THIS_MODULE, 1339ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1340a3496855SMika Westerberg .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1341ca632f55SGrant Likely }, 1342ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1343ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1344ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1345ca632f55SGrant Likely }; 1346ca632f55SGrant Likely 1347ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1348ca632f55SGrant Likely { 1349ca632f55SGrant Likely return platform_driver_register(&driver); 1350ca632f55SGrant Likely } 1351ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1352ca632f55SGrant Likely 1353ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1354ca632f55SGrant Likely { 1355ca632f55SGrant Likely platform_driver_unregister(&driver); 1356ca632f55SGrant Likely } 1357ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1358