1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3a0d2642eSMika Westerberg * Copyright (C) 2013, Intel Corporation 4ca632f55SGrant Likely * 5ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 6ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 7ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 8ca632f55SGrant Likely * (at your option) any later version. 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 11ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 12ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ca632f55SGrant Likely * GNU General Public License for more details. 14ca632f55SGrant Likely */ 15ca632f55SGrant Likely 16ca632f55SGrant Likely #include <linux/init.h> 17ca632f55SGrant Likely #include <linux/module.h> 18ca632f55SGrant Likely #include <linux/device.h> 19ca632f55SGrant Likely #include <linux/ioport.h> 20ca632f55SGrant Likely #include <linux/errno.h> 21cbfd6a21SSachin Kamat #include <linux/err.h> 22ca632f55SGrant Likely #include <linux/interrupt.h> 23ca632f55SGrant Likely #include <linux/platform_device.h> 24ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 25ca632f55SGrant Likely #include <linux/spi/spi.h> 26ca632f55SGrant Likely #include <linux/delay.h> 27ca632f55SGrant Likely #include <linux/gpio.h> 28ca632f55SGrant Likely #include <linux/slab.h> 293343b7a6SMika Westerberg #include <linux/clk.h> 307d94a505SMika Westerberg #include <linux/pm_runtime.h> 31a3496855SMika Westerberg #include <linux/acpi.h> 32ca632f55SGrant Likely 33cd7bed00SMika Westerberg #include "spi-pxa2xx.h" 34ca632f55SGrant Likely 35ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 36ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 37ca632f55SGrant Likely MODULE_LICENSE("GPL"); 38ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 39ca632f55SGrant Likely 40ca632f55SGrant Likely #define TIMOUT_DFLT 1000 41ca632f55SGrant Likely 42ca632f55SGrant Likely /* 43ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 44ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 45ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 46ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 47ca632f55SGrant Likely * service and interrupt enables 48ca632f55SGrant Likely */ 49ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 50ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 51ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 52ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 53ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 54ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 55ca632f55SGrant Likely 56e5262d05SWeike Chen #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 57e5262d05SWeike Chen | QUARK_X1000_SSCR1_EFWR \ 58e5262d05SWeike Chen | QUARK_X1000_SSCR1_RFT \ 59e5262d05SWeike Chen | QUARK_X1000_SSCR1_TFT \ 60e5262d05SWeike Chen | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 61e5262d05SWeike Chen 62a0d2642eSMika Westerberg #define LPSS_RX_THRESH_DFLT 64 63a0d2642eSMika Westerberg #define LPSS_TX_LOTHRESH_DFLT 160 64a0d2642eSMika Westerberg #define LPSS_TX_HITHRESH_DFLT 224 65a0d2642eSMika Westerberg 66e5262d05SWeike Chen struct quark_spi_rate { 67e5262d05SWeike Chen u32 bitrate; 68e5262d05SWeike Chen u32 dds_clk_rate; 69e5262d05SWeike Chen u32 clk_div; 70e5262d05SWeike Chen }; 71e5262d05SWeike Chen 72e5262d05SWeike Chen /* 73e5262d05SWeike Chen * 'rate', 'dds', 'clk_div' lookup table, which is defined in 74e5262d05SWeike Chen * the Quark SPI datasheet. 75e5262d05SWeike Chen */ 76e5262d05SWeike Chen static const struct quark_spi_rate quark_spi_rate_table[] = { 77e5262d05SWeike Chen /* bitrate, dds_clk_rate, clk_div */ 78e5262d05SWeike Chen {50000000, 0x800000, 0}, 79e5262d05SWeike Chen {40000000, 0x666666, 0}, 80e5262d05SWeike Chen {25000000, 0x400000, 0}, 81e5262d05SWeike Chen {20000000, 0x666666, 1}, 82e5262d05SWeike Chen {16667000, 0x800000, 2}, 83e5262d05SWeike Chen {13333000, 0x666666, 2}, 84e5262d05SWeike Chen {12500000, 0x200000, 0}, 85e5262d05SWeike Chen {10000000, 0x800000, 4}, 86e5262d05SWeike Chen {8000000, 0x666666, 4}, 87e5262d05SWeike Chen {6250000, 0x400000, 3}, 88e5262d05SWeike Chen {5000000, 0x400000, 4}, 89e5262d05SWeike Chen {4000000, 0x666666, 9}, 90e5262d05SWeike Chen {3125000, 0x80000, 0}, 91e5262d05SWeike Chen {2500000, 0x400000, 9}, 92e5262d05SWeike Chen {2000000, 0x666666, 19}, 93e5262d05SWeike Chen {1563000, 0x40000, 0}, 94e5262d05SWeike Chen {1250000, 0x200000, 9}, 95e5262d05SWeike Chen {1000000, 0x400000, 24}, 96e5262d05SWeike Chen {800000, 0x666666, 49}, 97e5262d05SWeike Chen {781250, 0x20000, 0}, 98e5262d05SWeike Chen {625000, 0x200000, 19}, 99e5262d05SWeike Chen {500000, 0x400000, 49}, 100e5262d05SWeike Chen {400000, 0x666666, 99}, 101e5262d05SWeike Chen {390625, 0x10000, 0}, 102e5262d05SWeike Chen {250000, 0x400000, 99}, 103e5262d05SWeike Chen {200000, 0x666666, 199}, 104e5262d05SWeike Chen {195313, 0x8000, 0}, 105e5262d05SWeike Chen {125000, 0x100000, 49}, 106e5262d05SWeike Chen {100000, 0x200000, 124}, 107e5262d05SWeike Chen {50000, 0x100000, 124}, 108e5262d05SWeike Chen {25000, 0x80000, 124}, 109e5262d05SWeike Chen {10016, 0x20000, 77}, 110e5262d05SWeike Chen {5040, 0x20000, 154}, 111e5262d05SWeike Chen {1002, 0x8000, 194}, 112e5262d05SWeike Chen }; 113e5262d05SWeike Chen 114a0d2642eSMika Westerberg /* Offset from drv_data->lpss_base */ 1151de70612SMika Westerberg #define GENERAL_REG 0x08 1161de70612SMika Westerberg #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 1170054e28dSMika Westerberg #define SSP_REG 0x0c 118a0d2642eSMika Westerberg #define SPI_CS_CONTROL 0x18 119a0d2642eSMika Westerberg #define SPI_CS_CONTROL_SW_MODE BIT(0) 120a0d2642eSMika Westerberg #define SPI_CS_CONTROL_CS_HIGH BIT(1) 121a0d2642eSMika Westerberg 122a0d2642eSMika Westerberg static bool is_lpss_ssp(const struct driver_data *drv_data) 123a0d2642eSMika Westerberg { 124a0d2642eSMika Westerberg return drv_data->ssp_type == LPSS_SSP; 125a0d2642eSMika Westerberg } 126a0d2642eSMika Westerberg 127e5262d05SWeike Chen static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 128e5262d05SWeike Chen { 129e5262d05SWeike Chen return drv_data->ssp_type == QUARK_X1000_SSP; 130e5262d05SWeike Chen } 131e5262d05SWeike Chen 1324fdb2424SWeike Chen static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 1334fdb2424SWeike Chen { 1344fdb2424SWeike Chen switch (drv_data->ssp_type) { 135e5262d05SWeike Chen case QUARK_X1000_SSP: 136e5262d05SWeike Chen return QUARK_X1000_SSCR1_CHANGE_MASK; 1374fdb2424SWeike Chen default: 1384fdb2424SWeike Chen return SSCR1_CHANGE_MASK; 1394fdb2424SWeike Chen } 1404fdb2424SWeike Chen } 1414fdb2424SWeike Chen 1424fdb2424SWeike Chen static u32 1434fdb2424SWeike Chen pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 1444fdb2424SWeike Chen { 1454fdb2424SWeike Chen switch (drv_data->ssp_type) { 146e5262d05SWeike Chen case QUARK_X1000_SSP: 147e5262d05SWeike Chen return RX_THRESH_QUARK_X1000_DFLT; 1484fdb2424SWeike Chen default: 1494fdb2424SWeike Chen return RX_THRESH_DFLT; 1504fdb2424SWeike Chen } 1514fdb2424SWeike Chen } 1524fdb2424SWeike Chen 1534fdb2424SWeike Chen static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 1544fdb2424SWeike Chen { 1554fdb2424SWeike Chen u32 mask; 1564fdb2424SWeike Chen 1574fdb2424SWeike Chen switch (drv_data->ssp_type) { 158e5262d05SWeike Chen case QUARK_X1000_SSP: 159e5262d05SWeike Chen mask = QUARK_X1000_SSSR_TFL_MASK; 160e5262d05SWeike Chen break; 1614fdb2424SWeike Chen default: 1624fdb2424SWeike Chen mask = SSSR_TFL_MASK; 1634fdb2424SWeike Chen break; 1644fdb2424SWeike Chen } 1654fdb2424SWeike Chen 166c039dd27SJarkko Nikula return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 1674fdb2424SWeike Chen } 1684fdb2424SWeike Chen 1694fdb2424SWeike Chen static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 1704fdb2424SWeike Chen u32 *sccr1_reg) 1714fdb2424SWeike Chen { 1724fdb2424SWeike Chen u32 mask; 1734fdb2424SWeike Chen 1744fdb2424SWeike Chen switch (drv_data->ssp_type) { 175e5262d05SWeike Chen case QUARK_X1000_SSP: 176e5262d05SWeike Chen mask = QUARK_X1000_SSCR1_RFT; 177e5262d05SWeike Chen break; 1784fdb2424SWeike Chen default: 1794fdb2424SWeike Chen mask = SSCR1_RFT; 1804fdb2424SWeike Chen break; 1814fdb2424SWeike Chen } 1824fdb2424SWeike Chen *sccr1_reg &= ~mask; 1834fdb2424SWeike Chen } 1844fdb2424SWeike Chen 1854fdb2424SWeike Chen static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 1864fdb2424SWeike Chen u32 *sccr1_reg, u32 threshold) 1874fdb2424SWeike Chen { 1884fdb2424SWeike Chen switch (drv_data->ssp_type) { 189e5262d05SWeike Chen case QUARK_X1000_SSP: 190e5262d05SWeike Chen *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 191e5262d05SWeike Chen break; 1924fdb2424SWeike Chen default: 1934fdb2424SWeike Chen *sccr1_reg |= SSCR1_RxTresh(threshold); 1944fdb2424SWeike Chen break; 1954fdb2424SWeike Chen } 1964fdb2424SWeike Chen } 1974fdb2424SWeike Chen 1984fdb2424SWeike Chen static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 1994fdb2424SWeike Chen u32 clk_div, u8 bits) 2004fdb2424SWeike Chen { 2014fdb2424SWeike Chen switch (drv_data->ssp_type) { 202e5262d05SWeike Chen case QUARK_X1000_SSP: 203e5262d05SWeike Chen return clk_div 204e5262d05SWeike Chen | QUARK_X1000_SSCR0_Motorola 205e5262d05SWeike Chen | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 206e5262d05SWeike Chen | SSCR0_SSE; 2074fdb2424SWeike Chen default: 2084fdb2424SWeike Chen return clk_div 2094fdb2424SWeike Chen | SSCR0_Motorola 2104fdb2424SWeike Chen | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 2114fdb2424SWeike Chen | SSCR0_SSE 2124fdb2424SWeike Chen | (bits > 16 ? SSCR0_EDSS : 0); 2134fdb2424SWeike Chen } 2144fdb2424SWeike Chen } 2154fdb2424SWeike Chen 216a0d2642eSMika Westerberg /* 217a0d2642eSMika Westerberg * Read and write LPSS SSP private registers. Caller must first check that 218a0d2642eSMika Westerberg * is_lpss_ssp() returns true before these can be called. 219a0d2642eSMika Westerberg */ 220a0d2642eSMika Westerberg static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 221a0d2642eSMika Westerberg { 222a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 223a0d2642eSMika Westerberg return readl(drv_data->lpss_base + offset); 224a0d2642eSMika Westerberg } 225a0d2642eSMika Westerberg 226a0d2642eSMika Westerberg static void __lpss_ssp_write_priv(struct driver_data *drv_data, 227a0d2642eSMika Westerberg unsigned offset, u32 value) 228a0d2642eSMika Westerberg { 229a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 230a0d2642eSMika Westerberg writel(value, drv_data->lpss_base + offset); 231a0d2642eSMika Westerberg } 232a0d2642eSMika Westerberg 233a0d2642eSMika Westerberg /* 234a0d2642eSMika Westerberg * lpss_ssp_setup - perform LPSS SSP specific setup 235a0d2642eSMika Westerberg * @drv_data: pointer to the driver private data 236a0d2642eSMika Westerberg * 237a0d2642eSMika Westerberg * Perform LPSS SSP specific setup. This function must be called first if 238a0d2642eSMika Westerberg * one is going to use LPSS SSP private registers. 239a0d2642eSMika Westerberg */ 240a0d2642eSMika Westerberg static void lpss_ssp_setup(struct driver_data *drv_data) 241a0d2642eSMika Westerberg { 242a0d2642eSMika Westerberg unsigned offset = 0x400; 243a0d2642eSMika Westerberg u32 value, orig; 244a0d2642eSMika Westerberg 245a0d2642eSMika Westerberg /* 246a0d2642eSMika Westerberg * Perform auto-detection of the LPSS SSP private registers. They 247a0d2642eSMika Westerberg * can be either at 1k or 2k offset from the base address. 248a0d2642eSMika Westerberg */ 249a0d2642eSMika Westerberg orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 250a0d2642eSMika Westerberg 251e61f487fSChew, Chiau Ee /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ 252a0d2642eSMika Westerberg value = orig | SPI_CS_CONTROL_SW_MODE; 253a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 254a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 255a0d2642eSMika Westerberg if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { 256a0d2642eSMika Westerberg offset = 0x800; 257a0d2642eSMika Westerberg goto detection_done; 258a0d2642eSMika Westerberg } 259a0d2642eSMika Westerberg 260e61f487fSChew, Chiau Ee orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 261e61f487fSChew, Chiau Ee 262e61f487fSChew, Chiau Ee /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ 263e61f487fSChew, Chiau Ee value = orig & ~SPI_CS_CONTROL_SW_MODE; 264a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 265a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 266e61f487fSChew, Chiau Ee if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { 267a0d2642eSMika Westerberg offset = 0x800; 268a0d2642eSMika Westerberg goto detection_done; 269a0d2642eSMika Westerberg } 270a0d2642eSMika Westerberg 271a0d2642eSMika Westerberg detection_done: 272a0d2642eSMika Westerberg /* Now set the LPSS base */ 273a0d2642eSMika Westerberg drv_data->lpss_base = drv_data->ioaddr + offset; 274a0d2642eSMika Westerberg 275a0d2642eSMika Westerberg /* Enable software chip select control */ 276a0d2642eSMika Westerberg value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 277a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 2780054e28dSMika Westerberg 2790054e28dSMika Westerberg /* Enable multiblock DMA transfers */ 2801de70612SMika Westerberg if (drv_data->master_info->enable_dma) { 2810054e28dSMika Westerberg __lpss_ssp_write_priv(drv_data, SSP_REG, 1); 2821de70612SMika Westerberg 2831de70612SMika Westerberg value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); 2841de70612SMika Westerberg value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; 2851de70612SMika Westerberg __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); 2861de70612SMika Westerberg } 287a0d2642eSMika Westerberg } 288a0d2642eSMika Westerberg 289a0d2642eSMika Westerberg static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 290a0d2642eSMika Westerberg { 291a0d2642eSMika Westerberg u32 value; 292a0d2642eSMika Westerberg 293a0d2642eSMika Westerberg value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 294a0d2642eSMika Westerberg if (enable) 295a0d2642eSMika Westerberg value &= ~SPI_CS_CONTROL_CS_HIGH; 296a0d2642eSMika Westerberg else 297a0d2642eSMika Westerberg value |= SPI_CS_CONTROL_CS_HIGH; 298a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 299a0d2642eSMika Westerberg } 300a0d2642eSMika Westerberg 301ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 302ca632f55SGrant Likely { 303ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 304ca632f55SGrant Likely 305ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 306c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); 307ca632f55SGrant Likely return; 308ca632f55SGrant Likely } 309ca632f55SGrant Likely 310ca632f55SGrant Likely if (chip->cs_control) { 311ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 312ca632f55SGrant Likely return; 313ca632f55SGrant Likely } 314ca632f55SGrant Likely 315a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 316ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 317a0d2642eSMika Westerberg return; 318a0d2642eSMika Westerberg } 319a0d2642eSMika Westerberg 3207566bcc7SJarkko Nikula if (is_lpss_ssp(drv_data)) 321a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, true); 322ca632f55SGrant Likely } 323ca632f55SGrant Likely 324ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 325ca632f55SGrant Likely { 326ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 327ca632f55SGrant Likely 328ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 329ca632f55SGrant Likely return; 330ca632f55SGrant Likely 331ca632f55SGrant Likely if (chip->cs_control) { 332ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 333ca632f55SGrant Likely return; 334ca632f55SGrant Likely } 335ca632f55SGrant Likely 336a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 337ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 338a0d2642eSMika Westerberg return; 339a0d2642eSMika Westerberg } 340a0d2642eSMika Westerberg 3417566bcc7SJarkko Nikula if (is_lpss_ssp(drv_data)) 342a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, false); 343ca632f55SGrant Likely } 344ca632f55SGrant Likely 345cd7bed00SMika Westerberg int pxa2xx_spi_flush(struct driver_data *drv_data) 346ca632f55SGrant Likely { 347ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 348ca632f55SGrant Likely 349ca632f55SGrant Likely do { 350c039dd27SJarkko Nikula while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 351c039dd27SJarkko Nikula pxa2xx_spi_read(drv_data, SSDR); 352c039dd27SJarkko Nikula } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 353ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 354ca632f55SGrant Likely 355ca632f55SGrant Likely return limit; 356ca632f55SGrant Likely } 357ca632f55SGrant Likely 358ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 359ca632f55SGrant Likely { 360ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 361ca632f55SGrant Likely 3624fdb2424SWeike Chen if (pxa2xx_spi_txfifo_full(drv_data) 363ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 364ca632f55SGrant Likely return 0; 365ca632f55SGrant Likely 366c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSDR, 0); 367ca632f55SGrant Likely drv_data->tx += n_bytes; 368ca632f55SGrant Likely 369ca632f55SGrant Likely return 1; 370ca632f55SGrant Likely } 371ca632f55SGrant Likely 372ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 373ca632f55SGrant Likely { 374ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 375ca632f55SGrant Likely 376c039dd27SJarkko Nikula while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 377ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 378c039dd27SJarkko Nikula pxa2xx_spi_read(drv_data, SSDR); 379ca632f55SGrant Likely drv_data->rx += n_bytes; 380ca632f55SGrant Likely } 381ca632f55SGrant Likely 382ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 383ca632f55SGrant Likely } 384ca632f55SGrant Likely 385ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 386ca632f55SGrant Likely { 3874fdb2424SWeike Chen if (pxa2xx_spi_txfifo_full(drv_data) 388ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 389ca632f55SGrant Likely return 0; 390ca632f55SGrant Likely 391c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 392ca632f55SGrant Likely ++drv_data->tx; 393ca632f55SGrant Likely 394ca632f55SGrant Likely return 1; 395ca632f55SGrant Likely } 396ca632f55SGrant Likely 397ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 398ca632f55SGrant Likely { 399c039dd27SJarkko Nikula while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 400ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 401c039dd27SJarkko Nikula *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 402ca632f55SGrant Likely ++drv_data->rx; 403ca632f55SGrant Likely } 404ca632f55SGrant Likely 405ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 406ca632f55SGrant Likely } 407ca632f55SGrant Likely 408ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 409ca632f55SGrant Likely { 4104fdb2424SWeike Chen if (pxa2xx_spi_txfifo_full(drv_data) 411ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 412ca632f55SGrant Likely return 0; 413ca632f55SGrant Likely 414c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 415ca632f55SGrant Likely drv_data->tx += 2; 416ca632f55SGrant Likely 417ca632f55SGrant Likely return 1; 418ca632f55SGrant Likely } 419ca632f55SGrant Likely 420ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 421ca632f55SGrant Likely { 422c039dd27SJarkko Nikula while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 423ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 424c039dd27SJarkko Nikula *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 425ca632f55SGrant Likely drv_data->rx += 2; 426ca632f55SGrant Likely } 427ca632f55SGrant Likely 428ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 429ca632f55SGrant Likely } 430ca632f55SGrant Likely 431ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 432ca632f55SGrant Likely { 4334fdb2424SWeike Chen if (pxa2xx_spi_txfifo_full(drv_data) 434ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 435ca632f55SGrant Likely return 0; 436ca632f55SGrant Likely 437c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 438ca632f55SGrant Likely drv_data->tx += 4; 439ca632f55SGrant Likely 440ca632f55SGrant Likely return 1; 441ca632f55SGrant Likely } 442ca632f55SGrant Likely 443ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 444ca632f55SGrant Likely { 445c039dd27SJarkko Nikula while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 446ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 447c039dd27SJarkko Nikula *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 448ca632f55SGrant Likely drv_data->rx += 4; 449ca632f55SGrant Likely } 450ca632f55SGrant Likely 451ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 452ca632f55SGrant Likely } 453ca632f55SGrant Likely 454cd7bed00SMika Westerberg void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 455ca632f55SGrant Likely { 456ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 457ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 458ca632f55SGrant Likely 459ca632f55SGrant Likely /* Move to next transfer */ 460ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 461ca632f55SGrant Likely drv_data->cur_transfer = 462ca632f55SGrant Likely list_entry(trans->transfer_list.next, 463ca632f55SGrant Likely struct spi_transfer, 464ca632f55SGrant Likely transfer_list); 465ca632f55SGrant Likely return RUNNING_STATE; 466ca632f55SGrant Likely } else 467ca632f55SGrant Likely return DONE_STATE; 468ca632f55SGrant Likely } 469ca632f55SGrant Likely 470ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 471ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 472ca632f55SGrant Likely { 473ca632f55SGrant Likely struct spi_transfer* last_transfer; 474ca632f55SGrant Likely struct spi_message *msg; 475ca632f55SGrant Likely 476ca632f55SGrant Likely msg = drv_data->cur_msg; 477ca632f55SGrant Likely drv_data->cur_msg = NULL; 478ca632f55SGrant Likely drv_data->cur_transfer = NULL; 479ca632f55SGrant Likely 48023e2c2aaSAxel Lin last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 481ca632f55SGrant Likely transfer_list); 482ca632f55SGrant Likely 483ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 484ca632f55SGrant Likely if (last_transfer->delay_usecs) 485ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 486ca632f55SGrant Likely 487ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 488ca632f55SGrant Likely * a message with an error, or next message is for another chip 489ca632f55SGrant Likely */ 490ca632f55SGrant Likely if (!last_transfer->cs_change) 491ca632f55SGrant Likely cs_deassert(drv_data); 492ca632f55SGrant Likely else { 493ca632f55SGrant Likely struct spi_message *next_msg; 494ca632f55SGrant Likely 495ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 496ca632f55SGrant Likely * the next message is for the same chip. Don't waste 497ca632f55SGrant Likely * time with the following tests unless this was hinted. 498ca632f55SGrant Likely * 499ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 500ca632f55SGrant Likely * after calling msg->complete (below) the driver that 501ca632f55SGrant Likely * sent the current message could be unloaded, which 502ca632f55SGrant Likely * could invalidate the cs_control() callback... 503ca632f55SGrant Likely */ 504ca632f55SGrant Likely 505ca632f55SGrant Likely /* get a pointer to the next message, if any */ 5067f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 507ca632f55SGrant Likely 508ca632f55SGrant Likely /* see if the next and current messages point 509ca632f55SGrant Likely * to the same chip 510ca632f55SGrant Likely */ 511ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 512ca632f55SGrant Likely next_msg = NULL; 513ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 514ca632f55SGrant Likely cs_deassert(drv_data); 515ca632f55SGrant Likely } 516ca632f55SGrant Likely 517ca632f55SGrant Likely drv_data->cur_chip = NULL; 518c957e8f0SMika Westerberg spi_finalize_current_message(drv_data->master); 519ca632f55SGrant Likely } 520ca632f55SGrant Likely 521ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 522ca632f55SGrant Likely { 523ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 524ca632f55SGrant Likely u32 sccr1_reg; 525ca632f55SGrant Likely 526c039dd27SJarkko Nikula sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 527ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 528ca632f55SGrant Likely sccr1_reg |= chip->threshold; 529c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 530ca632f55SGrant Likely } 531ca632f55SGrant Likely 532ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 533ca632f55SGrant Likely { 534ca632f55SGrant Likely /* Stop and reset SSP */ 535ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 536ca632f55SGrant Likely reset_sccr1(drv_data); 537ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 538c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSTO, 0); 539cd7bed00SMika Westerberg pxa2xx_spi_flush(drv_data); 540c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 541c039dd27SJarkko Nikula pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 542ca632f55SGrant Likely 543ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 544ca632f55SGrant Likely 545ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 546ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 547ca632f55SGrant Likely } 548ca632f55SGrant Likely 549ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 550ca632f55SGrant Likely { 551ca632f55SGrant Likely /* Stop SSP */ 552ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 553ca632f55SGrant Likely reset_sccr1(drv_data); 554ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 555c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSTO, 0); 556ca632f55SGrant Likely 557ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 558ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 559ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 560ca632f55SGrant Likely 561ca632f55SGrant Likely /* Transfer delays and chip select release are 562ca632f55SGrant Likely * handled in pump_transfers or giveback 563ca632f55SGrant Likely */ 564ca632f55SGrant Likely 565ca632f55SGrant Likely /* Move to next transfer */ 566cd7bed00SMika Westerberg drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 567ca632f55SGrant Likely 568ca632f55SGrant Likely /* Schedule transfer tasklet */ 569ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 570ca632f55SGrant Likely } 571ca632f55SGrant Likely 572ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 573ca632f55SGrant Likely { 574c039dd27SJarkko Nikula u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 575ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 576ca632f55SGrant Likely 577c039dd27SJarkko Nikula u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 578ca632f55SGrant Likely 579ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 580ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 581ca632f55SGrant Likely return IRQ_HANDLED; 582ca632f55SGrant Likely } 583ca632f55SGrant Likely 584ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 585c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 586ca632f55SGrant Likely if (drv_data->read(drv_data)) { 587ca632f55SGrant Likely int_transfer_complete(drv_data); 588ca632f55SGrant Likely return IRQ_HANDLED; 589ca632f55SGrant Likely } 590ca632f55SGrant Likely } 591ca632f55SGrant Likely 592ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 593ca632f55SGrant Likely do { 594ca632f55SGrant Likely if (drv_data->read(drv_data)) { 595ca632f55SGrant Likely int_transfer_complete(drv_data); 596ca632f55SGrant Likely return IRQ_HANDLED; 597ca632f55SGrant Likely } 598ca632f55SGrant Likely } while (drv_data->write(drv_data)); 599ca632f55SGrant Likely 600ca632f55SGrant Likely if (drv_data->read(drv_data)) { 601ca632f55SGrant Likely int_transfer_complete(drv_data); 602ca632f55SGrant Likely return IRQ_HANDLED; 603ca632f55SGrant Likely } 604ca632f55SGrant Likely 605ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 606ca632f55SGrant Likely u32 bytes_left; 607ca632f55SGrant Likely u32 sccr1_reg; 608ca632f55SGrant Likely 609c039dd27SJarkko Nikula sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 610ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 611ca632f55SGrant Likely 612ca632f55SGrant Likely /* 613ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 614ca632f55SGrant Likely * remaining RX bytes. 615ca632f55SGrant Likely */ 616ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 6174fdb2424SWeike Chen u32 rx_thre; 618ca632f55SGrant Likely 6194fdb2424SWeike Chen pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 620ca632f55SGrant Likely 621ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 622ca632f55SGrant Likely switch (drv_data->n_bytes) { 623ca632f55SGrant Likely case 4: 624ca632f55SGrant Likely bytes_left >>= 1; 625ca632f55SGrant Likely case 2: 626ca632f55SGrant Likely bytes_left >>= 1; 627ca632f55SGrant Likely } 628ca632f55SGrant Likely 6294fdb2424SWeike Chen rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 6304fdb2424SWeike Chen if (rx_thre > bytes_left) 6314fdb2424SWeike Chen rx_thre = bytes_left; 632ca632f55SGrant Likely 6334fdb2424SWeike Chen pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 634ca632f55SGrant Likely } 635c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 636ca632f55SGrant Likely } 637ca632f55SGrant Likely 638ca632f55SGrant Likely /* We did something */ 639ca632f55SGrant Likely return IRQ_HANDLED; 640ca632f55SGrant Likely } 641ca632f55SGrant Likely 642ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 643ca632f55SGrant Likely { 644ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 6457d94a505SMika Westerberg u32 sccr1_reg; 646ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 647ca632f55SGrant Likely u32 status; 648ca632f55SGrant Likely 6497d94a505SMika Westerberg /* 6507d94a505SMika Westerberg * The IRQ might be shared with other peripherals so we must first 6517d94a505SMika Westerberg * check that are we RPM suspended or not. If we are we assume that 6527d94a505SMika Westerberg * the IRQ was not for us (we shouldn't be RPM suspended when the 6537d94a505SMika Westerberg * interrupt is enabled). 6547d94a505SMika Westerberg */ 6557d94a505SMika Westerberg if (pm_runtime_suspended(&drv_data->pdev->dev)) 6567d94a505SMika Westerberg return IRQ_NONE; 6577d94a505SMika Westerberg 658269e4a41SMika Westerberg /* 659269e4a41SMika Westerberg * If the device is not yet in RPM suspended state and we get an 660269e4a41SMika Westerberg * interrupt that is meant for another device, check if status bits 661269e4a41SMika Westerberg * are all set to one. That means that the device is already 662269e4a41SMika Westerberg * powered off. 663269e4a41SMika Westerberg */ 664c039dd27SJarkko Nikula status = pxa2xx_spi_read(drv_data, SSSR); 665269e4a41SMika Westerberg if (status == ~0) 666269e4a41SMika Westerberg return IRQ_NONE; 667269e4a41SMika Westerberg 668c039dd27SJarkko Nikula sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 669ca632f55SGrant Likely 670ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 671ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 672ca632f55SGrant Likely mask &= ~SSSR_TFS; 673ca632f55SGrant Likely 674ca632f55SGrant Likely if (!(status & mask)) 675ca632f55SGrant Likely return IRQ_NONE; 676ca632f55SGrant Likely 677ca632f55SGrant Likely if (!drv_data->cur_msg) { 678ca632f55SGrant Likely 679c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 680c039dd27SJarkko Nikula pxa2xx_spi_read(drv_data, SSCR0) 681c039dd27SJarkko Nikula & ~SSCR0_SSE); 682c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, 683c039dd27SJarkko Nikula pxa2xx_spi_read(drv_data, SSCR1) 684c039dd27SJarkko Nikula & ~drv_data->int_cr1); 685ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 686c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSTO, 0); 687ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 688ca632f55SGrant Likely 689f6bd03a7SJarkko Nikula dev_err(&drv_data->pdev->dev, 690f6bd03a7SJarkko Nikula "bad message state in interrupt handler\n"); 691ca632f55SGrant Likely 692ca632f55SGrant Likely /* Never fail */ 693ca632f55SGrant Likely return IRQ_HANDLED; 694ca632f55SGrant Likely } 695ca632f55SGrant Likely 696ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 697ca632f55SGrant Likely } 698ca632f55SGrant Likely 699e5262d05SWeike Chen /* 700e5262d05SWeike Chen * The Quark SPI data sheet gives a table, and for the given 'rate', 701e5262d05SWeike Chen * the 'dds' and 'clk_div' can be found in the table. 702e5262d05SWeike Chen */ 703e5262d05SWeike Chen static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div) 704e5262d05SWeike Chen { 705e5262d05SWeike Chen unsigned int i; 706e5262d05SWeike Chen 707e5262d05SWeike Chen for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) { 708e5262d05SWeike Chen if (rate >= quark_spi_rate_table[i].bitrate) { 709e5262d05SWeike Chen *dds = quark_spi_rate_table[i].dds_clk_rate; 710e5262d05SWeike Chen *clk_div = quark_spi_rate_table[i].clk_div; 711e5262d05SWeike Chen return quark_spi_rate_table[i].bitrate; 712e5262d05SWeike Chen } 713e5262d05SWeike Chen } 714e5262d05SWeike Chen 715e5262d05SWeike Chen *dds = quark_spi_rate_table[i-1].dds_clk_rate; 716e5262d05SWeike Chen *clk_div = quark_spi_rate_table[i-1].clk_div; 717e5262d05SWeike Chen 718e5262d05SWeike Chen return quark_spi_rate_table[i-1].bitrate; 719e5262d05SWeike Chen } 720e5262d05SWeike Chen 7213343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 722ca632f55SGrant Likely { 7233343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 7243343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 7253343b7a6SMika Westerberg 7263343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 727ca632f55SGrant Likely 728ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 729*025ffe88SAndy Shevchenko return (ssp_clk / (2 * rate) - 1) & 0xff; 730ca632f55SGrant Likely else 731*025ffe88SAndy Shevchenko return (ssp_clk / rate - 1) & 0xfff; 732ca632f55SGrant Likely } 733ca632f55SGrant Likely 734e5262d05SWeike Chen static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 735e5262d05SWeike Chen struct chip_data *chip, int rate) 736e5262d05SWeike Chen { 737*025ffe88SAndy Shevchenko unsigned int clk_div; 738e5262d05SWeike Chen 739e5262d05SWeike Chen switch (drv_data->ssp_type) { 740e5262d05SWeike Chen case QUARK_X1000_SSP: 741e5262d05SWeike Chen quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div); 742e5262d05SWeike Chen default: 743*025ffe88SAndy Shevchenko clk_div = ssp_get_clk_div(drv_data, rate); 744e5262d05SWeike Chen } 745*025ffe88SAndy Shevchenko return clk_div << 8; 746e5262d05SWeike Chen } 747e5262d05SWeike Chen 748ca632f55SGrant Likely static void pump_transfers(unsigned long data) 749ca632f55SGrant Likely { 750ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 751ca632f55SGrant Likely struct spi_message *message = NULL; 752ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 753ca632f55SGrant Likely struct spi_transfer *previous = NULL; 754ca632f55SGrant Likely struct chip_data *chip = NULL; 755ca632f55SGrant Likely u32 clk_div = 0; 756ca632f55SGrant Likely u8 bits = 0; 757ca632f55SGrant Likely u32 speed = 0; 758ca632f55SGrant Likely u32 cr0; 759ca632f55SGrant Likely u32 cr1; 760ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 761ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 7624fdb2424SWeike Chen u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 763ca632f55SGrant Likely 764ca632f55SGrant Likely /* Get current state information */ 765ca632f55SGrant Likely message = drv_data->cur_msg; 766ca632f55SGrant Likely transfer = drv_data->cur_transfer; 767ca632f55SGrant Likely chip = drv_data->cur_chip; 768ca632f55SGrant Likely 769ca632f55SGrant Likely /* Handle for abort */ 770ca632f55SGrant Likely if (message->state == ERROR_STATE) { 771ca632f55SGrant Likely message->status = -EIO; 772ca632f55SGrant Likely giveback(drv_data); 773ca632f55SGrant Likely return; 774ca632f55SGrant Likely } 775ca632f55SGrant Likely 776ca632f55SGrant Likely /* Handle end of message */ 777ca632f55SGrant Likely if (message->state == DONE_STATE) { 778ca632f55SGrant Likely message->status = 0; 779ca632f55SGrant Likely giveback(drv_data); 780ca632f55SGrant Likely return; 781ca632f55SGrant Likely } 782ca632f55SGrant Likely 783ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 784ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 785ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 786ca632f55SGrant Likely struct spi_transfer, 787ca632f55SGrant Likely transfer_list); 788ca632f55SGrant Likely if (previous->delay_usecs) 789ca632f55SGrant Likely udelay(previous->delay_usecs); 790ca632f55SGrant Likely 791ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 792ca632f55SGrant Likely if (previous->cs_change) 793ca632f55SGrant Likely cs_deassert(drv_data); 794ca632f55SGrant Likely } 795ca632f55SGrant Likely 796cd7bed00SMika Westerberg /* Check if we can DMA this transfer */ 797cd7bed00SMika Westerberg if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 798ca632f55SGrant Likely 799ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 800ca632f55SGrant Likely if (message->is_dma_mapped 801ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 802ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 803f6bd03a7SJarkko Nikula "pump_transfers: mapped transfer length of " 804f6bd03a7SJarkko Nikula "%u is greater than %d\n", 805ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 806ca632f55SGrant Likely message->status = -EINVAL; 807ca632f55SGrant Likely giveback(drv_data); 808ca632f55SGrant Likely return; 809ca632f55SGrant Likely } 810ca632f55SGrant Likely 811ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 812f6bd03a7SJarkko Nikula dev_warn_ratelimited(&message->spi->dev, 813f6bd03a7SJarkko Nikula "pump_transfers: DMA disabled for transfer length %ld " 814ca632f55SGrant Likely "greater than %d\n", 815ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 816ca632f55SGrant Likely } 817ca632f55SGrant Likely 818ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 819cd7bed00SMika Westerberg if (pxa2xx_spi_flush(drv_data) == 0) { 820ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 821ca632f55SGrant Likely message->status = -EIO; 822ca632f55SGrant Likely giveback(drv_data); 823ca632f55SGrant Likely return; 824ca632f55SGrant Likely } 825ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 826ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 827ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 828ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 829ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 830ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 831ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 832cd7bed00SMika Westerberg drv_data->len = transfer->len; 833ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 834ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 835ca632f55SGrant Likely 836ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 837ca632f55SGrant Likely cr0 = chip->cr0; 838ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 839ca632f55SGrant Likely 840ca632f55SGrant Likely bits = chip->bits_per_word; 841ca632f55SGrant Likely speed = chip->speed_hz; 842ca632f55SGrant Likely 843ca632f55SGrant Likely if (transfer->speed_hz) 844ca632f55SGrant Likely speed = transfer->speed_hz; 845ca632f55SGrant Likely 846ca632f55SGrant Likely if (transfer->bits_per_word) 847ca632f55SGrant Likely bits = transfer->bits_per_word; 848ca632f55SGrant Likely 849e5262d05SWeike Chen clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); 850ca632f55SGrant Likely 851ca632f55SGrant Likely if (bits <= 8) { 852ca632f55SGrant Likely drv_data->n_bytes = 1; 853ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 854ca632f55SGrant Likely u8_reader : null_reader; 855ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 856ca632f55SGrant Likely u8_writer : null_writer; 857ca632f55SGrant Likely } else if (bits <= 16) { 858ca632f55SGrant Likely drv_data->n_bytes = 2; 859ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 860ca632f55SGrant Likely u16_reader : null_reader; 861ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 862ca632f55SGrant Likely u16_writer : null_writer; 863ca632f55SGrant Likely } else if (bits <= 32) { 864ca632f55SGrant Likely drv_data->n_bytes = 4; 865ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 866ca632f55SGrant Likely u32_reader : null_reader; 867ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 868ca632f55SGrant Likely u32_writer : null_writer; 869ca632f55SGrant Likely } 870ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 871ca632f55SGrant Likely * thresholds and burst also */ 872ca632f55SGrant Likely if (chip->enable_dma) { 873cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 874cd7bed00SMika Westerberg message->spi, 875ca632f55SGrant Likely bits, &dma_burst, 876ca632f55SGrant Likely &dma_thresh)) 877f6bd03a7SJarkko Nikula dev_warn_ratelimited(&message->spi->dev, 878f6bd03a7SJarkko Nikula "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 879ca632f55SGrant Likely } 880ca632f55SGrant Likely 8814fdb2424SWeike Chen cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 882ca632f55SGrant Likely } 883ca632f55SGrant Likely 884ca632f55SGrant Likely message->state = RUNNING_STATE; 885ca632f55SGrant Likely 886ca632f55SGrant Likely drv_data->dma_mapped = 0; 887cd7bed00SMika Westerberg if (pxa2xx_spi_dma_is_possible(drv_data->len)) 888cd7bed00SMika Westerberg drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 889ca632f55SGrant Likely if (drv_data->dma_mapped) { 890ca632f55SGrant Likely 891ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 892cd7bed00SMika Westerberg drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 893ca632f55SGrant Likely 894cd7bed00SMika Westerberg pxa2xx_spi_dma_prepare(drv_data, dma_burst); 895ca632f55SGrant Likely 896ca632f55SGrant Likely /* Clear status and start DMA engine */ 897ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 898c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 899cd7bed00SMika Westerberg 900cd7bed00SMika Westerberg pxa2xx_spi_dma_start(drv_data); 901ca632f55SGrant Likely } else { 902ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 903ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 904ca632f55SGrant Likely 905ca632f55SGrant Likely /* Clear status */ 906ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 907ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 908ca632f55SGrant Likely } 909ca632f55SGrant Likely 910a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 911c039dd27SJarkko Nikula if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 912c039dd27SJarkko Nikula != chip->lpss_rx_threshold) 913c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSIRF, 914c039dd27SJarkko Nikula chip->lpss_rx_threshold); 915c039dd27SJarkko Nikula if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 916c039dd27SJarkko Nikula != chip->lpss_tx_threshold) 917c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSITF, 918c039dd27SJarkko Nikula chip->lpss_tx_threshold); 919a0d2642eSMika Westerberg } 920a0d2642eSMika Westerberg 921e5262d05SWeike Chen if (is_quark_x1000_ssp(drv_data) && 922c039dd27SJarkko Nikula (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 923c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 924e5262d05SWeike Chen 925ca632f55SGrant Likely /* see if we need to reload the config registers */ 926c039dd27SJarkko Nikula if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 927c039dd27SJarkko Nikula || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 928c039dd27SJarkko Nikula != (cr1 & change_mask)) { 929ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 930c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 931ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 932c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 933ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 934c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 935ca632f55SGrant Likely /* restart the SSP */ 936c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, cr0); 937ca632f55SGrant Likely 938ca632f55SGrant Likely } else { 939ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 940c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 941ca632f55SGrant Likely } 942ca632f55SGrant Likely 943ca632f55SGrant Likely cs_assert(drv_data); 944ca632f55SGrant Likely 945ca632f55SGrant Likely /* after chip select, release the data by enabling service 946ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 947c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, cr1); 948ca632f55SGrant Likely } 949ca632f55SGrant Likely 9507f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 9517f86bde9SMika Westerberg struct spi_message *msg) 952ca632f55SGrant Likely { 9537f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 954ca632f55SGrant Likely 9557f86bde9SMika Westerberg drv_data->cur_msg = msg; 956ca632f55SGrant Likely /* Initial message state*/ 957ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 958ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 959ca632f55SGrant Likely struct spi_transfer, 960ca632f55SGrant Likely transfer_list); 961ca632f55SGrant Likely 962ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 963ca632f55SGrant Likely * chip configuration */ 964ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 965ca632f55SGrant Likely 966ca632f55SGrant Likely /* Mark as busy and launch transfers */ 967ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 968ca632f55SGrant Likely return 0; 969ca632f55SGrant Likely } 970ca632f55SGrant Likely 9717d94a505SMika Westerberg static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 9727d94a505SMika Westerberg { 9737d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 9747d94a505SMika Westerberg 9757d94a505SMika Westerberg /* Disable the SSP now */ 976c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 977c039dd27SJarkko Nikula pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 9787d94a505SMika Westerberg 9797d94a505SMika Westerberg return 0; 9807d94a505SMika Westerberg } 9817d94a505SMika Westerberg 982ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 983ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 984ca632f55SGrant Likely { 985ca632f55SGrant Likely int err = 0; 986ca632f55SGrant Likely 987ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 988ca632f55SGrant Likely return 0; 989ca632f55SGrant Likely 990ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 991ca632f55SGrant Likely * different chip_info, release previously requested GPIO 992ca632f55SGrant Likely */ 993ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 994ca632f55SGrant Likely gpio_free(chip->gpio_cs); 995ca632f55SGrant Likely 996ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 997ca632f55SGrant Likely if (chip_info->cs_control) { 998ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 999ca632f55SGrant Likely return 0; 1000ca632f55SGrant Likely } 1001ca632f55SGrant Likely 1002ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 1003ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1004ca632f55SGrant Likely if (err) { 1005f6bd03a7SJarkko Nikula dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1006f6bd03a7SJarkko Nikula chip_info->gpio_cs); 1007ca632f55SGrant Likely return err; 1008ca632f55SGrant Likely } 1009ca632f55SGrant Likely 1010ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 1011ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1012ca632f55SGrant Likely 1013ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 1014ca632f55SGrant Likely !chip->gpio_cs_inverted); 1015ca632f55SGrant Likely } 1016ca632f55SGrant Likely 1017ca632f55SGrant Likely return err; 1018ca632f55SGrant Likely } 1019ca632f55SGrant Likely 1020ca632f55SGrant Likely static int setup(struct spi_device *spi) 1021ca632f55SGrant Likely { 1022ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 1023ca632f55SGrant Likely struct chip_data *chip; 1024ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1025ca632f55SGrant Likely unsigned int clk_div; 1026a0d2642eSMika Westerberg uint tx_thres, tx_hi_thres, rx_thres; 1027a0d2642eSMika Westerberg 1028e5262d05SWeike Chen switch (drv_data->ssp_type) { 1029e5262d05SWeike Chen case QUARK_X1000_SSP: 1030e5262d05SWeike Chen tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1031e5262d05SWeike Chen tx_hi_thres = 0; 1032e5262d05SWeike Chen rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1033e5262d05SWeike Chen break; 1034e5262d05SWeike Chen case LPSS_SSP: 1035a0d2642eSMika Westerberg tx_thres = LPSS_TX_LOTHRESH_DFLT; 1036a0d2642eSMika Westerberg tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 1037a0d2642eSMika Westerberg rx_thres = LPSS_RX_THRESH_DFLT; 1038e5262d05SWeike Chen break; 1039e5262d05SWeike Chen default: 1040a0d2642eSMika Westerberg tx_thres = TX_THRESH_DFLT; 1041a0d2642eSMika Westerberg tx_hi_thres = 0; 1042a0d2642eSMika Westerberg rx_thres = RX_THRESH_DFLT; 1043e5262d05SWeike Chen break; 1044a0d2642eSMika Westerberg } 1045ca632f55SGrant Likely 1046ca632f55SGrant Likely /* Only alloc on first setup */ 1047ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1048ca632f55SGrant Likely if (!chip) { 1049ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 10509deae459SJingoo Han if (!chip) 1051ca632f55SGrant Likely return -ENOMEM; 1052ca632f55SGrant Likely 1053ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 1054ca632f55SGrant Likely if (spi->chip_select > 4) { 1055f6bd03a7SJarkko Nikula dev_err(&spi->dev, 1056f6bd03a7SJarkko Nikula "failed setup: cs number must not be > 4.\n"); 1057ca632f55SGrant Likely kfree(chip); 1058ca632f55SGrant Likely return -EINVAL; 1059ca632f55SGrant Likely } 1060ca632f55SGrant Likely 1061ca632f55SGrant Likely chip->frm = spi->chip_select; 1062ca632f55SGrant Likely } else 1063ca632f55SGrant Likely chip->gpio_cs = -1; 1064ca632f55SGrant Likely chip->enable_dma = 0; 1065ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 1066ca632f55SGrant Likely } 1067ca632f55SGrant Likely 1068ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 1069ca632f55SGrant Likely * if chip_info exists, use it */ 1070ca632f55SGrant Likely chip_info = spi->controller_data; 1071ca632f55SGrant Likely 1072ca632f55SGrant Likely /* chip_info isn't always needed */ 1073ca632f55SGrant Likely chip->cr1 = 0; 1074ca632f55SGrant Likely if (chip_info) { 1075ca632f55SGrant Likely if (chip_info->timeout) 1076ca632f55SGrant Likely chip->timeout = chip_info->timeout; 1077ca632f55SGrant Likely if (chip_info->tx_threshold) 1078ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 1079a0d2642eSMika Westerberg if (chip_info->tx_hi_threshold) 1080a0d2642eSMika Westerberg tx_hi_thres = chip_info->tx_hi_threshold; 1081ca632f55SGrant Likely if (chip_info->rx_threshold) 1082ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 1083ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 1084ca632f55SGrant Likely chip->dma_threshold = 0; 1085ca632f55SGrant Likely if (chip_info->enable_loopback) 1086ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 1087a3496855SMika Westerberg } else if (ACPI_HANDLE(&spi->dev)) { 1088a3496855SMika Westerberg /* 1089a3496855SMika Westerberg * Slave devices enumerated from ACPI namespace don't 1090a3496855SMika Westerberg * usually have chip_info but we still might want to use 1091a3496855SMika Westerberg * DMA with them. 1092a3496855SMika Westerberg */ 1093a3496855SMika Westerberg chip->enable_dma = drv_data->master_info->enable_dma; 1094ca632f55SGrant Likely } 1095ca632f55SGrant Likely 1096a0d2642eSMika Westerberg chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1097a0d2642eSMika Westerberg chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1098a0d2642eSMika Westerberg | SSITF_TxHiThresh(tx_hi_thres); 1099a0d2642eSMika Westerberg 1100ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 1101ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 1102ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 1103ca632f55SGrant Likely if (chip->enable_dma) { 1104ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 1105cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1106cd7bed00SMika Westerberg spi->bits_per_word, 1107ca632f55SGrant Likely &chip->dma_burst_size, 1108ca632f55SGrant Likely &chip->dma_threshold)) { 1109f6bd03a7SJarkko Nikula dev_warn(&spi->dev, 1110f6bd03a7SJarkko Nikula "in setup: DMA burst size reduced to match bits_per_word\n"); 1111ca632f55SGrant Likely } 1112ca632f55SGrant Likely } 1113ca632f55SGrant Likely 1114e5262d05SWeike Chen clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); 1115ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 1116ca632f55SGrant Likely 11174fdb2424SWeike Chen chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, 11184fdb2424SWeike Chen spi->bits_per_word); 1119e5262d05SWeike Chen switch (drv_data->ssp_type) { 1120e5262d05SWeike Chen case QUARK_X1000_SSP: 1121e5262d05SWeike Chen chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1122e5262d05SWeike Chen & QUARK_X1000_SSCR1_RFT) 1123e5262d05SWeike Chen | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1124e5262d05SWeike Chen & QUARK_X1000_SSCR1_TFT); 1125e5262d05SWeike Chen break; 1126e5262d05SWeike Chen default: 1127e5262d05SWeike Chen chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1128e5262d05SWeike Chen (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1129e5262d05SWeike Chen break; 1130e5262d05SWeike Chen } 1131e5262d05SWeike Chen 1132ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1133ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1134ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1135ca632f55SGrant Likely 1136b833172fSMika Westerberg if (spi->mode & SPI_LOOP) 1137b833172fSMika Westerberg chip->cr1 |= SSCR1_LBM; 1138b833172fSMika Westerberg 1139ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1140ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1141ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 11423343b7a6SMika Westerberg drv_data->max_clk_rate 1143ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 1144ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 1145ca632f55SGrant Likely else 1146ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 11473343b7a6SMika Westerberg drv_data->max_clk_rate / 2 1148ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1149ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 1150ca632f55SGrant Likely 1151ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 1152ca632f55SGrant Likely chip->n_bytes = 1; 1153ca632f55SGrant Likely chip->read = u8_reader; 1154ca632f55SGrant Likely chip->write = u8_writer; 1155ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 1156ca632f55SGrant Likely chip->n_bytes = 2; 1157ca632f55SGrant Likely chip->read = u16_reader; 1158ca632f55SGrant Likely chip->write = u16_writer; 1159ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 1160e5262d05SWeike Chen if (!is_quark_x1000_ssp(drv_data)) 1161ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 1162ca632f55SGrant Likely chip->n_bytes = 4; 1163ca632f55SGrant Likely chip->read = u32_reader; 1164ca632f55SGrant Likely chip->write = u32_writer; 1165ca632f55SGrant Likely } 1166ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 1167ca632f55SGrant Likely 1168ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1169ca632f55SGrant Likely 1170ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 1171ca632f55SGrant Likely return 0; 1172ca632f55SGrant Likely 1173ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 1174ca632f55SGrant Likely } 1175ca632f55SGrant Likely 1176ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 1177ca632f55SGrant Likely { 1178ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1179ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1180ca632f55SGrant Likely 1181ca632f55SGrant Likely if (!chip) 1182ca632f55SGrant Likely return; 1183ca632f55SGrant Likely 1184ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1185ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1186ca632f55SGrant Likely 1187ca632f55SGrant Likely kfree(chip); 1188ca632f55SGrant Likely } 1189ca632f55SGrant Likely 1190a3496855SMika Westerberg #ifdef CONFIG_ACPI 1191a3496855SMika Westerberg static struct pxa2xx_spi_master * 1192a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1193a3496855SMika Westerberg { 1194a3496855SMika Westerberg struct pxa2xx_spi_master *pdata; 1195a3496855SMika Westerberg struct acpi_device *adev; 1196a3496855SMika Westerberg struct ssp_device *ssp; 1197a3496855SMika Westerberg struct resource *res; 1198a3496855SMika Westerberg int devid; 1199a3496855SMika Westerberg 1200a3496855SMika Westerberg if (!ACPI_HANDLE(&pdev->dev) || 1201a3496855SMika Westerberg acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1202a3496855SMika Westerberg return NULL; 1203a3496855SMika Westerberg 1204cc0ee987SMika Westerberg pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 12059deae459SJingoo Han if (!pdata) 1206a3496855SMika Westerberg return NULL; 1207a3496855SMika Westerberg 1208a3496855SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1209a3496855SMika Westerberg if (!res) 1210a3496855SMika Westerberg return NULL; 1211a3496855SMika Westerberg 1212a3496855SMika Westerberg ssp = &pdata->ssp; 1213a3496855SMika Westerberg 1214a3496855SMika Westerberg ssp->phys_base = res->start; 1215cbfd6a21SSachin Kamat ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1216cbfd6a21SSachin Kamat if (IS_ERR(ssp->mmio_base)) 12176dc81f6fSMika Westerberg return NULL; 1218a3496855SMika Westerberg 1219a3496855SMika Westerberg ssp->clk = devm_clk_get(&pdev->dev, NULL); 1220a3496855SMika Westerberg ssp->irq = platform_get_irq(pdev, 0); 1221a3496855SMika Westerberg ssp->type = LPSS_SSP; 1222a3496855SMika Westerberg ssp->pdev = pdev; 1223a3496855SMika Westerberg 1224a3496855SMika Westerberg ssp->port_id = -1; 1225a3496855SMika Westerberg if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1226a3496855SMika Westerberg ssp->port_id = devid; 1227a3496855SMika Westerberg 1228a3496855SMika Westerberg pdata->num_chipselect = 1; 1229cddb339bSMika Westerberg pdata->enable_dma = true; 1230a3496855SMika Westerberg 1231a3496855SMika Westerberg return pdata; 1232a3496855SMika Westerberg } 1233a3496855SMika Westerberg 1234a3496855SMika Westerberg static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1235a3496855SMika Westerberg { "INT33C0", 0 }, 1236a3496855SMika Westerberg { "INT33C1", 0 }, 123754acbd96SMika Westerberg { "INT3430", 0 }, 123854acbd96SMika Westerberg { "INT3431", 0 }, 12394b30f2a1SMika Westerberg { "80860F0E", 0 }, 1240aca26364SAlan Cox { "8086228E", 0 }, 1241a3496855SMika Westerberg { }, 1242a3496855SMika Westerberg }; 1243a3496855SMika Westerberg MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1244a3496855SMika Westerberg #else 1245a3496855SMika Westerberg static inline struct pxa2xx_spi_master * 1246a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1247a3496855SMika Westerberg { 1248a3496855SMika Westerberg return NULL; 1249a3496855SMika Westerberg } 1250a3496855SMika Westerberg #endif 1251a3496855SMika Westerberg 1252fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 1253ca632f55SGrant Likely { 1254ca632f55SGrant Likely struct device *dev = &pdev->dev; 1255ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 1256ca632f55SGrant Likely struct spi_master *master; 1257ca632f55SGrant Likely struct driver_data *drv_data; 1258ca632f55SGrant Likely struct ssp_device *ssp; 1259ca632f55SGrant Likely int status; 1260c039dd27SJarkko Nikula u32 tmp; 1261ca632f55SGrant Likely 1262851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 1263851bacf5SMika Westerberg if (!platform_info) { 1264a3496855SMika Westerberg platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1265a3496855SMika Westerberg if (!platform_info) { 1266851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 1267851bacf5SMika Westerberg return -ENODEV; 1268851bacf5SMika Westerberg } 1269a3496855SMika Westerberg } 1270ca632f55SGrant Likely 1271ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 1272851bacf5SMika Westerberg if (!ssp) 1273851bacf5SMika Westerberg ssp = &platform_info->ssp; 1274851bacf5SMika Westerberg 1275851bacf5SMika Westerberg if (!ssp->mmio_base) { 1276851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 1277ca632f55SGrant Likely return -ENODEV; 1278ca632f55SGrant Likely } 1279ca632f55SGrant Likely 1280ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 1281ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1282ca632f55SGrant Likely if (!master) { 1283ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1284ca632f55SGrant Likely pxa_ssp_free(ssp); 1285ca632f55SGrant Likely return -ENOMEM; 1286ca632f55SGrant Likely } 1287ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 1288ca632f55SGrant Likely drv_data->master = master; 1289ca632f55SGrant Likely drv_data->master_info = platform_info; 1290ca632f55SGrant Likely drv_data->pdev = pdev; 1291ca632f55SGrant Likely drv_data->ssp = ssp; 1292ca632f55SGrant Likely 1293ca632f55SGrant Likely master->dev.parent = &pdev->dev; 1294ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 1295ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1296b833172fSMika Westerberg master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1297ca632f55SGrant Likely 1298851bacf5SMika Westerberg master->bus_num = ssp->port_id; 1299ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 1300ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 1301ca632f55SGrant Likely master->cleanup = cleanup; 1302ca632f55SGrant Likely master->setup = setup; 13037f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 13047d94a505SMika Westerberg master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 13057dd62787SMark Brown master->auto_runtime_pm = true; 1306ca632f55SGrant Likely 1307ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 13082b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1309ca632f55SGrant Likely 1310ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 1311ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 1312ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 1313e5262d05SWeike Chen switch (drv_data->ssp_type) { 1314e5262d05SWeike Chen case QUARK_X1000_SSP: 1315e5262d05SWeike Chen master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1316e5262d05SWeike Chen break; 1317e5262d05SWeike Chen default: 131824778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1319e5262d05SWeike Chen break; 1320e5262d05SWeike Chen } 1321e5262d05SWeike Chen 1322ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1323ca632f55SGrant Likely drv_data->dma_cr1 = 0; 1324ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 1325ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1326ca632f55SGrant Likely } else { 132724778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1328ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 13295928808eSMika Westerberg drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1330ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1331ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1332ca632f55SGrant Likely } 1333ca632f55SGrant Likely 1334ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1335ca632f55SGrant Likely drv_data); 1336ca632f55SGrant Likely if (status < 0) { 1337ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1338ca632f55SGrant Likely goto out_error_master_alloc; 1339ca632f55SGrant Likely } 1340ca632f55SGrant Likely 1341ca632f55SGrant Likely /* Setup DMA if requested */ 1342ca632f55SGrant Likely drv_data->tx_channel = -1; 1343ca632f55SGrant Likely drv_data->rx_channel = -1; 1344ca632f55SGrant Likely if (platform_info->enable_dma) { 1345cd7bed00SMika Westerberg status = pxa2xx_spi_dma_setup(drv_data); 1346cd7bed00SMika Westerberg if (status) { 1347cddb339bSMika Westerberg dev_dbg(dev, "no DMA channels available, using PIO\n"); 1348cd7bed00SMika Westerberg platform_info->enable_dma = false; 1349ca632f55SGrant Likely } 1350ca632f55SGrant Likely } 1351ca632f55SGrant Likely 1352ca632f55SGrant Likely /* Enable SOC clock */ 13533343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 13543343b7a6SMika Westerberg 13553343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1356ca632f55SGrant Likely 1357ca632f55SGrant Likely /* Load default SSP configuration */ 1358c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 0); 1359e5262d05SWeike Chen switch (drv_data->ssp_type) { 1360e5262d05SWeike Chen case QUARK_X1000_SSP: 1361c039dd27SJarkko Nikula tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) 1362c039dd27SJarkko Nikula | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1363c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, tmp); 1364e5262d05SWeike Chen 1365e5262d05SWeike Chen /* using the Motorola SPI protocol and use 8 bit frame */ 1366c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 1367c039dd27SJarkko Nikula QUARK_X1000_SSCR0_Motorola 1368c039dd27SJarkko Nikula | QUARK_X1000_SSCR0_DataSize(8)); 1369e5262d05SWeike Chen break; 1370e5262d05SWeike Chen default: 1371c039dd27SJarkko Nikula tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1372c039dd27SJarkko Nikula SSCR1_TxTresh(TX_THRESH_DFLT); 1373c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR1, tmp); 1374c039dd27SJarkko Nikula tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1375c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, tmp); 1376e5262d05SWeike Chen break; 1377e5262d05SWeike Chen } 1378e5262d05SWeike Chen 1379ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1380c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSTO, 0); 1381e5262d05SWeike Chen 1382e5262d05SWeike Chen if (!is_quark_x1000_ssp(drv_data)) 1383c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSPSP, 0); 1384ca632f55SGrant Likely 13857566bcc7SJarkko Nikula if (is_lpss_ssp(drv_data)) 1386a0d2642eSMika Westerberg lpss_ssp_setup(drv_data); 1387a0d2642eSMika Westerberg 13887f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 13897f86bde9SMika Westerberg (unsigned long)drv_data); 1390ca632f55SGrant Likely 1391836d1a22SAntonio Ospite pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1392836d1a22SAntonio Ospite pm_runtime_use_autosuspend(&pdev->dev); 1393836d1a22SAntonio Ospite pm_runtime_set_active(&pdev->dev); 1394836d1a22SAntonio Ospite pm_runtime_enable(&pdev->dev); 1395836d1a22SAntonio Ospite 1396ca632f55SGrant Likely /* Register with the SPI framework */ 1397ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1398a807fcd0SJingoo Han status = devm_spi_register_master(&pdev->dev, master); 1399ca632f55SGrant Likely if (status != 0) { 1400ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 14017f86bde9SMika Westerberg goto out_error_clock_enabled; 1402ca632f55SGrant Likely } 1403ca632f55SGrant Likely 1404ca632f55SGrant Likely return status; 1405ca632f55SGrant Likely 1406ca632f55SGrant Likely out_error_clock_enabled: 14073343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1408cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1409ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1410ca632f55SGrant Likely 1411ca632f55SGrant Likely out_error_master_alloc: 1412ca632f55SGrant Likely spi_master_put(master); 1413ca632f55SGrant Likely pxa_ssp_free(ssp); 1414ca632f55SGrant Likely return status; 1415ca632f55SGrant Likely } 1416ca632f55SGrant Likely 1417ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1418ca632f55SGrant Likely { 1419ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1420ca632f55SGrant Likely struct ssp_device *ssp; 1421ca632f55SGrant Likely 1422ca632f55SGrant Likely if (!drv_data) 1423ca632f55SGrant Likely return 0; 1424ca632f55SGrant Likely ssp = drv_data->ssp; 1425ca632f55SGrant Likely 14267d94a505SMika Westerberg pm_runtime_get_sync(&pdev->dev); 14277d94a505SMika Westerberg 1428ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1429c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 0); 14303343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1431ca632f55SGrant Likely 1432ca632f55SGrant Likely /* Release DMA */ 1433cd7bed00SMika Westerberg if (drv_data->master_info->enable_dma) 1434cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1435ca632f55SGrant Likely 14367d94a505SMika Westerberg pm_runtime_put_noidle(&pdev->dev); 14377d94a505SMika Westerberg pm_runtime_disable(&pdev->dev); 14387d94a505SMika Westerberg 1439ca632f55SGrant Likely /* Release IRQ */ 1440ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1441ca632f55SGrant Likely 1442ca632f55SGrant Likely /* Release SSP */ 1443ca632f55SGrant Likely pxa_ssp_free(ssp); 1444ca632f55SGrant Likely 1445ca632f55SGrant Likely return 0; 1446ca632f55SGrant Likely } 1447ca632f55SGrant Likely 1448ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1449ca632f55SGrant Likely { 1450ca632f55SGrant Likely int status = 0; 1451ca632f55SGrant Likely 1452ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1453ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1454ca632f55SGrant Likely } 1455ca632f55SGrant Likely 1456382cebb0SMika Westerberg #ifdef CONFIG_PM_SLEEP 1457ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1458ca632f55SGrant Likely { 1459ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1460ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1461ca632f55SGrant Likely int status = 0; 1462ca632f55SGrant Likely 14637f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1464ca632f55SGrant Likely if (status != 0) 1465ca632f55SGrant Likely return status; 1466c039dd27SJarkko Nikula pxa2xx_spi_write(drv_data, SSCR0, 0); 14672b9375b9SDmitry Eremin-Solenikov 14682b9375b9SDmitry Eremin-Solenikov if (!pm_runtime_suspended(dev)) 14693343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1470ca632f55SGrant Likely 1471ca632f55SGrant Likely return 0; 1472ca632f55SGrant Likely } 1473ca632f55SGrant Likely 1474ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1475ca632f55SGrant Likely { 1476ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1477ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1478ca632f55SGrant Likely int status = 0; 1479ca632f55SGrant Likely 1480cd7bed00SMika Westerberg pxa2xx_spi_dma_resume(drv_data); 1481ca632f55SGrant Likely 1482ca632f55SGrant Likely /* Enable the SSP clock */ 14832b9375b9SDmitry Eremin-Solenikov if (!pm_runtime_suspended(dev)) 14843343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1485ca632f55SGrant Likely 1486c50325f7SChew, Chiau Ee /* Restore LPSS private register bits */ 148748421adfSJarkko Nikula if (is_lpss_ssp(drv_data)) 1488c50325f7SChew, Chiau Ee lpss_ssp_setup(drv_data); 1489c50325f7SChew, Chiau Ee 1490ca632f55SGrant Likely /* Start the queue running */ 14917f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1492ca632f55SGrant Likely if (status != 0) { 1493ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1494ca632f55SGrant Likely return status; 1495ca632f55SGrant Likely } 1496ca632f55SGrant Likely 1497ca632f55SGrant Likely return 0; 1498ca632f55SGrant Likely } 14997d94a505SMika Westerberg #endif 15007d94a505SMika Westerberg 1501ec833050SRafael J. Wysocki #ifdef CONFIG_PM 15027d94a505SMika Westerberg static int pxa2xx_spi_runtime_suspend(struct device *dev) 15037d94a505SMika Westerberg { 15047d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 15057d94a505SMika Westerberg 15067d94a505SMika Westerberg clk_disable_unprepare(drv_data->ssp->clk); 15077d94a505SMika Westerberg return 0; 15087d94a505SMika Westerberg } 15097d94a505SMika Westerberg 15107d94a505SMika Westerberg static int pxa2xx_spi_runtime_resume(struct device *dev) 15117d94a505SMika Westerberg { 15127d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 15137d94a505SMika Westerberg 15147d94a505SMika Westerberg clk_prepare_enable(drv_data->ssp->clk); 15157d94a505SMika Westerberg return 0; 15167d94a505SMika Westerberg } 15177d94a505SMika Westerberg #endif 1518ca632f55SGrant Likely 1519ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 15207d94a505SMika Westerberg SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 15217d94a505SMika Westerberg SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 15227d94a505SMika Westerberg pxa2xx_spi_runtime_resume, NULL) 1523ca632f55SGrant Likely }; 1524ca632f55SGrant Likely 1525ca632f55SGrant Likely static struct platform_driver driver = { 1526ca632f55SGrant Likely .driver = { 1527ca632f55SGrant Likely .name = "pxa2xx-spi", 1528ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1529a3496855SMika Westerberg .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1530ca632f55SGrant Likely }, 1531ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1532ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1533ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1534ca632f55SGrant Likely }; 1535ca632f55SGrant Likely 1536ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1537ca632f55SGrant Likely { 1538ca632f55SGrant Likely return platform_driver_register(&driver); 1539ca632f55SGrant Likely } 1540ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1541ca632f55SGrant Likely 1542ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1543ca632f55SGrant Likely { 1544ca632f55SGrant Likely platform_driver_unregister(&driver); 1545ca632f55SGrant Likely } 1546ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1547