1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3a0d2642eSMika Westerberg * Copyright (C) 2013, Intel Corporation 4ca632f55SGrant Likely * 5ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 6ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 7ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 8ca632f55SGrant Likely * (at your option) any later version. 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 11ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 12ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ca632f55SGrant Likely * GNU General Public License for more details. 14ca632f55SGrant Likely * 15ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 16ca632f55SGrant Likely * along with this program; if not, write to the Free Software 17ca632f55SGrant Likely * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18ca632f55SGrant Likely */ 19ca632f55SGrant Likely 20ca632f55SGrant Likely #include <linux/init.h> 21ca632f55SGrant Likely #include <linux/module.h> 22ca632f55SGrant Likely #include <linux/device.h> 23ca632f55SGrant Likely #include <linux/ioport.h> 24ca632f55SGrant Likely #include <linux/errno.h> 25ca632f55SGrant Likely #include <linux/interrupt.h> 26ca632f55SGrant Likely #include <linux/platform_device.h> 27ca632f55SGrant Likely #include <linux/spi/pxa2xx_spi.h> 28ca632f55SGrant Likely #include <linux/spi/spi.h> 29ca632f55SGrant Likely #include <linux/workqueue.h> 30ca632f55SGrant Likely #include <linux/delay.h> 31ca632f55SGrant Likely #include <linux/gpio.h> 32ca632f55SGrant Likely #include <linux/slab.h> 333343b7a6SMika Westerberg #include <linux/clk.h> 347d94a505SMika Westerberg #include <linux/pm_runtime.h> 35a3496855SMika Westerberg #include <linux/acpi.h> 36ca632f55SGrant Likely 37ca632f55SGrant Likely #include <asm/io.h> 38ca632f55SGrant Likely #include <asm/irq.h> 39ca632f55SGrant Likely #include <asm/delay.h> 40ca632f55SGrant Likely 41cd7bed00SMika Westerberg #include "spi-pxa2xx.h" 42ca632f55SGrant Likely 43ca632f55SGrant Likely MODULE_AUTHOR("Stephen Street"); 44ca632f55SGrant Likely MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 45ca632f55SGrant Likely MODULE_LICENSE("GPL"); 46ca632f55SGrant Likely MODULE_ALIAS("platform:pxa2xx-spi"); 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define MAX_BUSES 3 49ca632f55SGrant Likely 50ca632f55SGrant Likely #define TIMOUT_DFLT 1000 51ca632f55SGrant Likely 52ca632f55SGrant Likely /* 53ca632f55SGrant Likely * for testing SSCR1 changes that require SSP restart, basically 54ca632f55SGrant Likely * everything except the service and interrupt enables, the pxa270 developer 55ca632f55SGrant Likely * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 56ca632f55SGrant Likely * list, but the PXA255 dev man says all bits without really meaning the 57ca632f55SGrant Likely * service and interrupt enables 58ca632f55SGrant Likely */ 59ca632f55SGrant Likely #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 60ca632f55SGrant Likely | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 61ca632f55SGrant Likely | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 62ca632f55SGrant Likely | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 63ca632f55SGrant Likely | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 64ca632f55SGrant Likely | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 65ca632f55SGrant Likely 66a0d2642eSMika Westerberg #define LPSS_RX_THRESH_DFLT 64 67a0d2642eSMika Westerberg #define LPSS_TX_LOTHRESH_DFLT 160 68a0d2642eSMika Westerberg #define LPSS_TX_HITHRESH_DFLT 224 69a0d2642eSMika Westerberg 70a0d2642eSMika Westerberg /* Offset from drv_data->lpss_base */ 71*0054e28dSMika Westerberg #define SSP_REG 0x0c 72a0d2642eSMika Westerberg #define SPI_CS_CONTROL 0x18 73a0d2642eSMika Westerberg #define SPI_CS_CONTROL_SW_MODE BIT(0) 74a0d2642eSMika Westerberg #define SPI_CS_CONTROL_CS_HIGH BIT(1) 75a0d2642eSMika Westerberg 76a0d2642eSMika Westerberg static bool is_lpss_ssp(const struct driver_data *drv_data) 77a0d2642eSMika Westerberg { 78a0d2642eSMika Westerberg return drv_data->ssp_type == LPSS_SSP; 79a0d2642eSMika Westerberg } 80a0d2642eSMika Westerberg 81a0d2642eSMika Westerberg /* 82a0d2642eSMika Westerberg * Read and write LPSS SSP private registers. Caller must first check that 83a0d2642eSMika Westerberg * is_lpss_ssp() returns true before these can be called. 84a0d2642eSMika Westerberg */ 85a0d2642eSMika Westerberg static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 86a0d2642eSMika Westerberg { 87a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 88a0d2642eSMika Westerberg return readl(drv_data->lpss_base + offset); 89a0d2642eSMika Westerberg } 90a0d2642eSMika Westerberg 91a0d2642eSMika Westerberg static void __lpss_ssp_write_priv(struct driver_data *drv_data, 92a0d2642eSMika Westerberg unsigned offset, u32 value) 93a0d2642eSMika Westerberg { 94a0d2642eSMika Westerberg WARN_ON(!drv_data->lpss_base); 95a0d2642eSMika Westerberg writel(value, drv_data->lpss_base + offset); 96a0d2642eSMika Westerberg } 97a0d2642eSMika Westerberg 98a0d2642eSMika Westerberg /* 99a0d2642eSMika Westerberg * lpss_ssp_setup - perform LPSS SSP specific setup 100a0d2642eSMika Westerberg * @drv_data: pointer to the driver private data 101a0d2642eSMika Westerberg * 102a0d2642eSMika Westerberg * Perform LPSS SSP specific setup. This function must be called first if 103a0d2642eSMika Westerberg * one is going to use LPSS SSP private registers. 104a0d2642eSMika Westerberg */ 105a0d2642eSMika Westerberg static void lpss_ssp_setup(struct driver_data *drv_data) 106a0d2642eSMika Westerberg { 107a0d2642eSMika Westerberg unsigned offset = 0x400; 108a0d2642eSMika Westerberg u32 value, orig; 109a0d2642eSMika Westerberg 110a0d2642eSMika Westerberg if (!is_lpss_ssp(drv_data)) 111a0d2642eSMika Westerberg return; 112a0d2642eSMika Westerberg 113a0d2642eSMika Westerberg /* 114a0d2642eSMika Westerberg * Perform auto-detection of the LPSS SSP private registers. They 115a0d2642eSMika Westerberg * can be either at 1k or 2k offset from the base address. 116a0d2642eSMika Westerberg */ 117a0d2642eSMika Westerberg orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 118a0d2642eSMika Westerberg 119a0d2642eSMika Westerberg value = orig | SPI_CS_CONTROL_SW_MODE; 120a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 121a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 122a0d2642eSMika Westerberg if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { 123a0d2642eSMika Westerberg offset = 0x800; 124a0d2642eSMika Westerberg goto detection_done; 125a0d2642eSMika Westerberg } 126a0d2642eSMika Westerberg 127a0d2642eSMika Westerberg value &= ~SPI_CS_CONTROL_SW_MODE; 128a0d2642eSMika Westerberg writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 129a0d2642eSMika Westerberg value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 130a0d2642eSMika Westerberg if (value != orig) { 131a0d2642eSMika Westerberg offset = 0x800; 132a0d2642eSMika Westerberg goto detection_done; 133a0d2642eSMika Westerberg } 134a0d2642eSMika Westerberg 135a0d2642eSMika Westerberg detection_done: 136a0d2642eSMika Westerberg /* Now set the LPSS base */ 137a0d2642eSMika Westerberg drv_data->lpss_base = drv_data->ioaddr + offset; 138a0d2642eSMika Westerberg 139a0d2642eSMika Westerberg /* Enable software chip select control */ 140a0d2642eSMika Westerberg value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 141a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 142*0054e28dSMika Westerberg 143*0054e28dSMika Westerberg /* Enable multiblock DMA transfers */ 144*0054e28dSMika Westerberg if (drv_data->master_info->enable_dma) 145*0054e28dSMika Westerberg __lpss_ssp_write_priv(drv_data, SSP_REG, 1); 146a0d2642eSMika Westerberg } 147a0d2642eSMika Westerberg 148a0d2642eSMika Westerberg static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 149a0d2642eSMika Westerberg { 150a0d2642eSMika Westerberg u32 value; 151a0d2642eSMika Westerberg 152a0d2642eSMika Westerberg if (!is_lpss_ssp(drv_data)) 153a0d2642eSMika Westerberg return; 154a0d2642eSMika Westerberg 155a0d2642eSMika Westerberg value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 156a0d2642eSMika Westerberg if (enable) 157a0d2642eSMika Westerberg value &= ~SPI_CS_CONTROL_CS_HIGH; 158a0d2642eSMika Westerberg else 159a0d2642eSMika Westerberg value |= SPI_CS_CONTROL_CS_HIGH; 160a0d2642eSMika Westerberg __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 161a0d2642eSMika Westerberg } 162a0d2642eSMika Westerberg 163ca632f55SGrant Likely static void cs_assert(struct driver_data *drv_data) 164ca632f55SGrant Likely { 165ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 166ca632f55SGrant Likely 167ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 168ca632f55SGrant Likely write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 169ca632f55SGrant Likely return; 170ca632f55SGrant Likely } 171ca632f55SGrant Likely 172ca632f55SGrant Likely if (chip->cs_control) { 173ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_ASSERT); 174ca632f55SGrant Likely return; 175ca632f55SGrant Likely } 176ca632f55SGrant Likely 177a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 178ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 179a0d2642eSMika Westerberg return; 180a0d2642eSMika Westerberg } 181a0d2642eSMika Westerberg 182a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, true); 183ca632f55SGrant Likely } 184ca632f55SGrant Likely 185ca632f55SGrant Likely static void cs_deassert(struct driver_data *drv_data) 186ca632f55SGrant Likely { 187ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 188ca632f55SGrant Likely 189ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 190ca632f55SGrant Likely return; 191ca632f55SGrant Likely 192ca632f55SGrant Likely if (chip->cs_control) { 193ca632f55SGrant Likely chip->cs_control(PXA2XX_CS_DEASSERT); 194ca632f55SGrant Likely return; 195ca632f55SGrant Likely } 196ca632f55SGrant Likely 197a0d2642eSMika Westerberg if (gpio_is_valid(chip->gpio_cs)) { 198ca632f55SGrant Likely gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 199a0d2642eSMika Westerberg return; 200a0d2642eSMika Westerberg } 201a0d2642eSMika Westerberg 202a0d2642eSMika Westerberg lpss_ssp_cs_control(drv_data, false); 203ca632f55SGrant Likely } 204ca632f55SGrant Likely 205cd7bed00SMika Westerberg int pxa2xx_spi_flush(struct driver_data *drv_data) 206ca632f55SGrant Likely { 207ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 208ca632f55SGrant Likely 209ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 210ca632f55SGrant Likely 211ca632f55SGrant Likely do { 212ca632f55SGrant Likely while (read_SSSR(reg) & SSSR_RNE) { 213ca632f55SGrant Likely read_SSDR(reg); 214ca632f55SGrant Likely } 215ca632f55SGrant Likely } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 216ca632f55SGrant Likely write_SSSR_CS(drv_data, SSSR_ROR); 217ca632f55SGrant Likely 218ca632f55SGrant Likely return limit; 219ca632f55SGrant Likely } 220ca632f55SGrant Likely 221ca632f55SGrant Likely static int null_writer(struct driver_data *drv_data) 222ca632f55SGrant Likely { 223ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 224ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 225ca632f55SGrant Likely 226ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 227ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 228ca632f55SGrant Likely return 0; 229ca632f55SGrant Likely 230ca632f55SGrant Likely write_SSDR(0, reg); 231ca632f55SGrant Likely drv_data->tx += n_bytes; 232ca632f55SGrant Likely 233ca632f55SGrant Likely return 1; 234ca632f55SGrant Likely } 235ca632f55SGrant Likely 236ca632f55SGrant Likely static int null_reader(struct driver_data *drv_data) 237ca632f55SGrant Likely { 238ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 239ca632f55SGrant Likely u8 n_bytes = drv_data->n_bytes; 240ca632f55SGrant Likely 241ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 242ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 243ca632f55SGrant Likely read_SSDR(reg); 244ca632f55SGrant Likely drv_data->rx += n_bytes; 245ca632f55SGrant Likely } 246ca632f55SGrant Likely 247ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 248ca632f55SGrant Likely } 249ca632f55SGrant Likely 250ca632f55SGrant Likely static int u8_writer(struct driver_data *drv_data) 251ca632f55SGrant Likely { 252ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 253ca632f55SGrant Likely 254ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 255ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 256ca632f55SGrant Likely return 0; 257ca632f55SGrant Likely 258ca632f55SGrant Likely write_SSDR(*(u8 *)(drv_data->tx), reg); 259ca632f55SGrant Likely ++drv_data->tx; 260ca632f55SGrant Likely 261ca632f55SGrant Likely return 1; 262ca632f55SGrant Likely } 263ca632f55SGrant Likely 264ca632f55SGrant Likely static int u8_reader(struct driver_data *drv_data) 265ca632f55SGrant Likely { 266ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 267ca632f55SGrant Likely 268ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 269ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 270ca632f55SGrant Likely *(u8 *)(drv_data->rx) = read_SSDR(reg); 271ca632f55SGrant Likely ++drv_data->rx; 272ca632f55SGrant Likely } 273ca632f55SGrant Likely 274ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 275ca632f55SGrant Likely } 276ca632f55SGrant Likely 277ca632f55SGrant Likely static int u16_writer(struct driver_data *drv_data) 278ca632f55SGrant Likely { 279ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 280ca632f55SGrant Likely 281ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 282ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 283ca632f55SGrant Likely return 0; 284ca632f55SGrant Likely 285ca632f55SGrant Likely write_SSDR(*(u16 *)(drv_data->tx), reg); 286ca632f55SGrant Likely drv_data->tx += 2; 287ca632f55SGrant Likely 288ca632f55SGrant Likely return 1; 289ca632f55SGrant Likely } 290ca632f55SGrant Likely 291ca632f55SGrant Likely static int u16_reader(struct driver_data *drv_data) 292ca632f55SGrant Likely { 293ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 294ca632f55SGrant Likely 295ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 296ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 297ca632f55SGrant Likely *(u16 *)(drv_data->rx) = read_SSDR(reg); 298ca632f55SGrant Likely drv_data->rx += 2; 299ca632f55SGrant Likely } 300ca632f55SGrant Likely 301ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 302ca632f55SGrant Likely } 303ca632f55SGrant Likely 304ca632f55SGrant Likely static int u32_writer(struct driver_data *drv_data) 305ca632f55SGrant Likely { 306ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 307ca632f55SGrant Likely 308ca632f55SGrant Likely if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 309ca632f55SGrant Likely || (drv_data->tx == drv_data->tx_end)) 310ca632f55SGrant Likely return 0; 311ca632f55SGrant Likely 312ca632f55SGrant Likely write_SSDR(*(u32 *)(drv_data->tx), reg); 313ca632f55SGrant Likely drv_data->tx += 4; 314ca632f55SGrant Likely 315ca632f55SGrant Likely return 1; 316ca632f55SGrant Likely } 317ca632f55SGrant Likely 318ca632f55SGrant Likely static int u32_reader(struct driver_data *drv_data) 319ca632f55SGrant Likely { 320ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 321ca632f55SGrant Likely 322ca632f55SGrant Likely while ((read_SSSR(reg) & SSSR_RNE) 323ca632f55SGrant Likely && (drv_data->rx < drv_data->rx_end)) { 324ca632f55SGrant Likely *(u32 *)(drv_data->rx) = read_SSDR(reg); 325ca632f55SGrant Likely drv_data->rx += 4; 326ca632f55SGrant Likely } 327ca632f55SGrant Likely 328ca632f55SGrant Likely return drv_data->rx == drv_data->rx_end; 329ca632f55SGrant Likely } 330ca632f55SGrant Likely 331cd7bed00SMika Westerberg void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 332ca632f55SGrant Likely { 333ca632f55SGrant Likely struct spi_message *msg = drv_data->cur_msg; 334ca632f55SGrant Likely struct spi_transfer *trans = drv_data->cur_transfer; 335ca632f55SGrant Likely 336ca632f55SGrant Likely /* Move to next transfer */ 337ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 338ca632f55SGrant Likely drv_data->cur_transfer = 339ca632f55SGrant Likely list_entry(trans->transfer_list.next, 340ca632f55SGrant Likely struct spi_transfer, 341ca632f55SGrant Likely transfer_list); 342ca632f55SGrant Likely return RUNNING_STATE; 343ca632f55SGrant Likely } else 344ca632f55SGrant Likely return DONE_STATE; 345ca632f55SGrant Likely } 346ca632f55SGrant Likely 347ca632f55SGrant Likely /* caller already set message->status; dma and pio irqs are blocked */ 348ca632f55SGrant Likely static void giveback(struct driver_data *drv_data) 349ca632f55SGrant Likely { 350ca632f55SGrant Likely struct spi_transfer* last_transfer; 351ca632f55SGrant Likely struct spi_message *msg; 352ca632f55SGrant Likely 353ca632f55SGrant Likely msg = drv_data->cur_msg; 354ca632f55SGrant Likely drv_data->cur_msg = NULL; 355ca632f55SGrant Likely drv_data->cur_transfer = NULL; 356ca632f55SGrant Likely 357ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 358ca632f55SGrant Likely struct spi_transfer, 359ca632f55SGrant Likely transfer_list); 360ca632f55SGrant Likely 361ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 362ca632f55SGrant Likely if (last_transfer->delay_usecs) 363ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 364ca632f55SGrant Likely 365ca632f55SGrant Likely /* Drop chip select UNLESS cs_change is true or we are returning 366ca632f55SGrant Likely * a message with an error, or next message is for another chip 367ca632f55SGrant Likely */ 368ca632f55SGrant Likely if (!last_transfer->cs_change) 369ca632f55SGrant Likely cs_deassert(drv_data); 370ca632f55SGrant Likely else { 371ca632f55SGrant Likely struct spi_message *next_msg; 372ca632f55SGrant Likely 373ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 374ca632f55SGrant Likely * the next message is for the same chip. Don't waste 375ca632f55SGrant Likely * time with the following tests unless this was hinted. 376ca632f55SGrant Likely * 377ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 378ca632f55SGrant Likely * after calling msg->complete (below) the driver that 379ca632f55SGrant Likely * sent the current message could be unloaded, which 380ca632f55SGrant Likely * could invalidate the cs_control() callback... 381ca632f55SGrant Likely */ 382ca632f55SGrant Likely 383ca632f55SGrant Likely /* get a pointer to the next message, if any */ 3847f86bde9SMika Westerberg next_msg = spi_get_next_queued_message(drv_data->master); 385ca632f55SGrant Likely 386ca632f55SGrant Likely /* see if the next and current messages point 387ca632f55SGrant Likely * to the same chip 388ca632f55SGrant Likely */ 389ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 390ca632f55SGrant Likely next_msg = NULL; 391ca632f55SGrant Likely if (!next_msg || msg->state == ERROR_STATE) 392ca632f55SGrant Likely cs_deassert(drv_data); 393ca632f55SGrant Likely } 394ca632f55SGrant Likely 3957f86bde9SMika Westerberg spi_finalize_current_message(drv_data->master); 396ca632f55SGrant Likely drv_data->cur_chip = NULL; 397ca632f55SGrant Likely } 398ca632f55SGrant Likely 399ca632f55SGrant Likely static void reset_sccr1(struct driver_data *drv_data) 400ca632f55SGrant Likely { 401ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 402ca632f55SGrant Likely struct chip_data *chip = drv_data->cur_chip; 403ca632f55SGrant Likely u32 sccr1_reg; 404ca632f55SGrant Likely 405ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 406ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 407ca632f55SGrant Likely sccr1_reg |= chip->threshold; 408ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 409ca632f55SGrant Likely } 410ca632f55SGrant Likely 411ca632f55SGrant Likely static void int_error_stop(struct driver_data *drv_data, const char* msg) 412ca632f55SGrant Likely { 413ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 414ca632f55SGrant Likely 415ca632f55SGrant Likely /* Stop and reset SSP */ 416ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 417ca632f55SGrant Likely reset_sccr1(drv_data); 418ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 419ca632f55SGrant Likely write_SSTO(0, reg); 420cd7bed00SMika Westerberg pxa2xx_spi_flush(drv_data); 421ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 422ca632f55SGrant Likely 423ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "%s\n", msg); 424ca632f55SGrant Likely 425ca632f55SGrant Likely drv_data->cur_msg->state = ERROR_STATE; 426ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 427ca632f55SGrant Likely } 428ca632f55SGrant Likely 429ca632f55SGrant Likely static void int_transfer_complete(struct driver_data *drv_data) 430ca632f55SGrant Likely { 431ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 432ca632f55SGrant Likely 433ca632f55SGrant Likely /* Stop SSP */ 434ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 435ca632f55SGrant Likely reset_sccr1(drv_data); 436ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 437ca632f55SGrant Likely write_SSTO(0, reg); 438ca632f55SGrant Likely 439ca632f55SGrant Likely /* Update total byte transferred return count actual bytes read */ 440ca632f55SGrant Likely drv_data->cur_msg->actual_length += drv_data->len - 441ca632f55SGrant Likely (drv_data->rx_end - drv_data->rx); 442ca632f55SGrant Likely 443ca632f55SGrant Likely /* Transfer delays and chip select release are 444ca632f55SGrant Likely * handled in pump_transfers or giveback 445ca632f55SGrant Likely */ 446ca632f55SGrant Likely 447ca632f55SGrant Likely /* Move to next transfer */ 448cd7bed00SMika Westerberg drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 449ca632f55SGrant Likely 450ca632f55SGrant Likely /* Schedule transfer tasklet */ 451ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 452ca632f55SGrant Likely } 453ca632f55SGrant Likely 454ca632f55SGrant Likely static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 455ca632f55SGrant Likely { 456ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 457ca632f55SGrant Likely 458ca632f55SGrant Likely u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 459ca632f55SGrant Likely drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 460ca632f55SGrant Likely 461ca632f55SGrant Likely u32 irq_status = read_SSSR(reg) & irq_mask; 462ca632f55SGrant Likely 463ca632f55SGrant Likely if (irq_status & SSSR_ROR) { 464ca632f55SGrant Likely int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 465ca632f55SGrant Likely return IRQ_HANDLED; 466ca632f55SGrant Likely } 467ca632f55SGrant Likely 468ca632f55SGrant Likely if (irq_status & SSSR_TINT) { 469ca632f55SGrant Likely write_SSSR(SSSR_TINT, reg); 470ca632f55SGrant Likely if (drv_data->read(drv_data)) { 471ca632f55SGrant Likely int_transfer_complete(drv_data); 472ca632f55SGrant Likely return IRQ_HANDLED; 473ca632f55SGrant Likely } 474ca632f55SGrant Likely } 475ca632f55SGrant Likely 476ca632f55SGrant Likely /* Drain rx fifo, Fill tx fifo and prevent overruns */ 477ca632f55SGrant Likely do { 478ca632f55SGrant Likely if (drv_data->read(drv_data)) { 479ca632f55SGrant Likely int_transfer_complete(drv_data); 480ca632f55SGrant Likely return IRQ_HANDLED; 481ca632f55SGrant Likely } 482ca632f55SGrant Likely } while (drv_data->write(drv_data)); 483ca632f55SGrant Likely 484ca632f55SGrant Likely if (drv_data->read(drv_data)) { 485ca632f55SGrant Likely int_transfer_complete(drv_data); 486ca632f55SGrant Likely return IRQ_HANDLED; 487ca632f55SGrant Likely } 488ca632f55SGrant Likely 489ca632f55SGrant Likely if (drv_data->tx == drv_data->tx_end) { 490ca632f55SGrant Likely u32 bytes_left; 491ca632f55SGrant Likely u32 sccr1_reg; 492ca632f55SGrant Likely 493ca632f55SGrant Likely sccr1_reg = read_SSCR1(reg); 494ca632f55SGrant Likely sccr1_reg &= ~SSCR1_TIE; 495ca632f55SGrant Likely 496ca632f55SGrant Likely /* 497ca632f55SGrant Likely * PXA25x_SSP has no timeout, set up rx threshould for the 498ca632f55SGrant Likely * remaining RX bytes. 499ca632f55SGrant Likely */ 500ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 501ca632f55SGrant Likely 502ca632f55SGrant Likely sccr1_reg &= ~SSCR1_RFT; 503ca632f55SGrant Likely 504ca632f55SGrant Likely bytes_left = drv_data->rx_end - drv_data->rx; 505ca632f55SGrant Likely switch (drv_data->n_bytes) { 506ca632f55SGrant Likely case 4: 507ca632f55SGrant Likely bytes_left >>= 1; 508ca632f55SGrant Likely case 2: 509ca632f55SGrant Likely bytes_left >>= 1; 510ca632f55SGrant Likely } 511ca632f55SGrant Likely 512ca632f55SGrant Likely if (bytes_left > RX_THRESH_DFLT) 513ca632f55SGrant Likely bytes_left = RX_THRESH_DFLT; 514ca632f55SGrant Likely 515ca632f55SGrant Likely sccr1_reg |= SSCR1_RxTresh(bytes_left); 516ca632f55SGrant Likely } 517ca632f55SGrant Likely write_SSCR1(sccr1_reg, reg); 518ca632f55SGrant Likely } 519ca632f55SGrant Likely 520ca632f55SGrant Likely /* We did something */ 521ca632f55SGrant Likely return IRQ_HANDLED; 522ca632f55SGrant Likely } 523ca632f55SGrant Likely 524ca632f55SGrant Likely static irqreturn_t ssp_int(int irq, void *dev_id) 525ca632f55SGrant Likely { 526ca632f55SGrant Likely struct driver_data *drv_data = dev_id; 527ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 5287d94a505SMika Westerberg u32 sccr1_reg; 529ca632f55SGrant Likely u32 mask = drv_data->mask_sr; 530ca632f55SGrant Likely u32 status; 531ca632f55SGrant Likely 5327d94a505SMika Westerberg /* 5337d94a505SMika Westerberg * The IRQ might be shared with other peripherals so we must first 5347d94a505SMika Westerberg * check that are we RPM suspended or not. If we are we assume that 5357d94a505SMika Westerberg * the IRQ was not for us (we shouldn't be RPM suspended when the 5367d94a505SMika Westerberg * interrupt is enabled). 5377d94a505SMika Westerberg */ 5387d94a505SMika Westerberg if (pm_runtime_suspended(&drv_data->pdev->dev)) 5397d94a505SMika Westerberg return IRQ_NONE; 5407d94a505SMika Westerberg 5417d94a505SMika Westerberg sccr1_reg = read_SSCR1(reg); 542ca632f55SGrant Likely status = read_SSSR(reg); 543ca632f55SGrant Likely 544ca632f55SGrant Likely /* Ignore possible writes if we don't need to write */ 545ca632f55SGrant Likely if (!(sccr1_reg & SSCR1_TIE)) 546ca632f55SGrant Likely mask &= ~SSSR_TFS; 547ca632f55SGrant Likely 548ca632f55SGrant Likely if (!(status & mask)) 549ca632f55SGrant Likely return IRQ_NONE; 550ca632f55SGrant Likely 551ca632f55SGrant Likely if (!drv_data->cur_msg) { 552ca632f55SGrant Likely 553ca632f55SGrant Likely write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 554ca632f55SGrant Likely write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 555ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 556ca632f55SGrant Likely write_SSTO(0, reg); 557ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 558ca632f55SGrant Likely 559ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "bad message state " 560ca632f55SGrant Likely "in interrupt handler\n"); 561ca632f55SGrant Likely 562ca632f55SGrant Likely /* Never fail */ 563ca632f55SGrant Likely return IRQ_HANDLED; 564ca632f55SGrant Likely } 565ca632f55SGrant Likely 566ca632f55SGrant Likely return drv_data->transfer_handler(drv_data); 567ca632f55SGrant Likely } 568ca632f55SGrant Likely 5693343b7a6SMika Westerberg static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 570ca632f55SGrant Likely { 5713343b7a6SMika Westerberg unsigned long ssp_clk = drv_data->max_clk_rate; 5723343b7a6SMika Westerberg const struct ssp_device *ssp = drv_data->ssp; 5733343b7a6SMika Westerberg 5743343b7a6SMika Westerberg rate = min_t(int, ssp_clk, rate); 575ca632f55SGrant Likely 576ca632f55SGrant Likely if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 577ca632f55SGrant Likely return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 578ca632f55SGrant Likely else 579ca632f55SGrant Likely return ((ssp_clk / rate - 1) & 0xfff) << 8; 580ca632f55SGrant Likely } 581ca632f55SGrant Likely 582ca632f55SGrant Likely static void pump_transfers(unsigned long data) 583ca632f55SGrant Likely { 584ca632f55SGrant Likely struct driver_data *drv_data = (struct driver_data *)data; 585ca632f55SGrant Likely struct spi_message *message = NULL; 586ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 587ca632f55SGrant Likely struct spi_transfer *previous = NULL; 588ca632f55SGrant Likely struct chip_data *chip = NULL; 589ca632f55SGrant Likely void __iomem *reg = drv_data->ioaddr; 590ca632f55SGrant Likely u32 clk_div = 0; 591ca632f55SGrant Likely u8 bits = 0; 592ca632f55SGrant Likely u32 speed = 0; 593ca632f55SGrant Likely u32 cr0; 594ca632f55SGrant Likely u32 cr1; 595ca632f55SGrant Likely u32 dma_thresh = drv_data->cur_chip->dma_threshold; 596ca632f55SGrant Likely u32 dma_burst = drv_data->cur_chip->dma_burst_size; 597ca632f55SGrant Likely 598ca632f55SGrant Likely /* Get current state information */ 599ca632f55SGrant Likely message = drv_data->cur_msg; 600ca632f55SGrant Likely transfer = drv_data->cur_transfer; 601ca632f55SGrant Likely chip = drv_data->cur_chip; 602ca632f55SGrant Likely 603ca632f55SGrant Likely /* Handle for abort */ 604ca632f55SGrant Likely if (message->state == ERROR_STATE) { 605ca632f55SGrant Likely message->status = -EIO; 606ca632f55SGrant Likely giveback(drv_data); 607ca632f55SGrant Likely return; 608ca632f55SGrant Likely } 609ca632f55SGrant Likely 610ca632f55SGrant Likely /* Handle end of message */ 611ca632f55SGrant Likely if (message->state == DONE_STATE) { 612ca632f55SGrant Likely message->status = 0; 613ca632f55SGrant Likely giveback(drv_data); 614ca632f55SGrant Likely return; 615ca632f55SGrant Likely } 616ca632f55SGrant Likely 617ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 618ca632f55SGrant Likely if (message->state == RUNNING_STATE) { 619ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 620ca632f55SGrant Likely struct spi_transfer, 621ca632f55SGrant Likely transfer_list); 622ca632f55SGrant Likely if (previous->delay_usecs) 623ca632f55SGrant Likely udelay(previous->delay_usecs); 624ca632f55SGrant Likely 625ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 626ca632f55SGrant Likely if (previous->cs_change) 627ca632f55SGrant Likely cs_deassert(drv_data); 628ca632f55SGrant Likely } 629ca632f55SGrant Likely 630cd7bed00SMika Westerberg /* Check if we can DMA this transfer */ 631cd7bed00SMika Westerberg if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 632ca632f55SGrant Likely 633ca632f55SGrant Likely /* reject already-mapped transfers; PIO won't always work */ 634ca632f55SGrant Likely if (message->is_dma_mapped 635ca632f55SGrant Likely || transfer->rx_dma || transfer->tx_dma) { 636ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, 637ca632f55SGrant Likely "pump_transfers: mapped transfer length " 638ca632f55SGrant Likely "of %u is greater than %d\n", 639ca632f55SGrant Likely transfer->len, MAX_DMA_LEN); 640ca632f55SGrant Likely message->status = -EINVAL; 641ca632f55SGrant Likely giveback(drv_data); 642ca632f55SGrant Likely return; 643ca632f55SGrant Likely } 644ca632f55SGrant Likely 645ca632f55SGrant Likely /* warn ... we force this to PIO mode */ 646ca632f55SGrant Likely if (printk_ratelimit()) 647ca632f55SGrant Likely dev_warn(&message->spi->dev, "pump_transfers: " 648ca632f55SGrant Likely "DMA disabled for transfer length %ld " 649ca632f55SGrant Likely "greater than %d\n", 650ca632f55SGrant Likely (long)drv_data->len, MAX_DMA_LEN); 651ca632f55SGrant Likely } 652ca632f55SGrant Likely 653ca632f55SGrant Likely /* Setup the transfer state based on the type of transfer */ 654cd7bed00SMika Westerberg if (pxa2xx_spi_flush(drv_data) == 0) { 655ca632f55SGrant Likely dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 656ca632f55SGrant Likely message->status = -EIO; 657ca632f55SGrant Likely giveback(drv_data); 658ca632f55SGrant Likely return; 659ca632f55SGrant Likely } 660ca632f55SGrant Likely drv_data->n_bytes = chip->n_bytes; 661ca632f55SGrant Likely drv_data->tx = (void *)transfer->tx_buf; 662ca632f55SGrant Likely drv_data->tx_end = drv_data->tx + transfer->len; 663ca632f55SGrant Likely drv_data->rx = transfer->rx_buf; 664ca632f55SGrant Likely drv_data->rx_end = drv_data->rx + transfer->len; 665ca632f55SGrant Likely drv_data->rx_dma = transfer->rx_dma; 666ca632f55SGrant Likely drv_data->tx_dma = transfer->tx_dma; 667cd7bed00SMika Westerberg drv_data->len = transfer->len; 668ca632f55SGrant Likely drv_data->write = drv_data->tx ? chip->write : null_writer; 669ca632f55SGrant Likely drv_data->read = drv_data->rx ? chip->read : null_reader; 670ca632f55SGrant Likely 671ca632f55SGrant Likely /* Change speed and bit per word on a per transfer */ 672ca632f55SGrant Likely cr0 = chip->cr0; 673ca632f55SGrant Likely if (transfer->speed_hz || transfer->bits_per_word) { 674ca632f55SGrant Likely 675ca632f55SGrant Likely bits = chip->bits_per_word; 676ca632f55SGrant Likely speed = chip->speed_hz; 677ca632f55SGrant Likely 678ca632f55SGrant Likely if (transfer->speed_hz) 679ca632f55SGrant Likely speed = transfer->speed_hz; 680ca632f55SGrant Likely 681ca632f55SGrant Likely if (transfer->bits_per_word) 682ca632f55SGrant Likely bits = transfer->bits_per_word; 683ca632f55SGrant Likely 6843343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, speed); 685ca632f55SGrant Likely 686ca632f55SGrant Likely if (bits <= 8) { 687ca632f55SGrant Likely drv_data->n_bytes = 1; 688ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 689ca632f55SGrant Likely u8_reader : null_reader; 690ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 691ca632f55SGrant Likely u8_writer : null_writer; 692ca632f55SGrant Likely } else if (bits <= 16) { 693ca632f55SGrant Likely drv_data->n_bytes = 2; 694ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 695ca632f55SGrant Likely u16_reader : null_reader; 696ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 697ca632f55SGrant Likely u16_writer : null_writer; 698ca632f55SGrant Likely } else if (bits <= 32) { 699ca632f55SGrant Likely drv_data->n_bytes = 4; 700ca632f55SGrant Likely drv_data->read = drv_data->read != null_reader ? 701ca632f55SGrant Likely u32_reader : null_reader; 702ca632f55SGrant Likely drv_data->write = drv_data->write != null_writer ? 703ca632f55SGrant Likely u32_writer : null_writer; 704ca632f55SGrant Likely } 705ca632f55SGrant Likely /* if bits/word is changed in dma mode, then must check the 706ca632f55SGrant Likely * thresholds and burst also */ 707ca632f55SGrant Likely if (chip->enable_dma) { 708cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 709cd7bed00SMika Westerberg message->spi, 710ca632f55SGrant Likely bits, &dma_burst, 711ca632f55SGrant Likely &dma_thresh)) 712ca632f55SGrant Likely if (printk_ratelimit()) 713ca632f55SGrant Likely dev_warn(&message->spi->dev, 714ca632f55SGrant Likely "pump_transfers: " 715ca632f55SGrant Likely "DMA burst size reduced to " 716ca632f55SGrant Likely "match bits_per_word\n"); 717ca632f55SGrant Likely } 718ca632f55SGrant Likely 719ca632f55SGrant Likely cr0 = clk_div 720ca632f55SGrant Likely | SSCR0_Motorola 721ca632f55SGrant Likely | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 722ca632f55SGrant Likely | SSCR0_SSE 723ca632f55SGrant Likely | (bits > 16 ? SSCR0_EDSS : 0); 724ca632f55SGrant Likely } 725ca632f55SGrant Likely 726ca632f55SGrant Likely message->state = RUNNING_STATE; 727ca632f55SGrant Likely 728ca632f55SGrant Likely drv_data->dma_mapped = 0; 729cd7bed00SMika Westerberg if (pxa2xx_spi_dma_is_possible(drv_data->len)) 730cd7bed00SMika Westerberg drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 731ca632f55SGrant Likely if (drv_data->dma_mapped) { 732ca632f55SGrant Likely 733ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 734cd7bed00SMika Westerberg drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 735ca632f55SGrant Likely 736cd7bed00SMika Westerberg pxa2xx_spi_dma_prepare(drv_data, dma_burst); 737ca632f55SGrant Likely 738ca632f55SGrant Likely /* Clear status and start DMA engine */ 739ca632f55SGrant Likely cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 740ca632f55SGrant Likely write_SSSR(drv_data->clear_sr, reg); 741cd7bed00SMika Westerberg 742cd7bed00SMika Westerberg pxa2xx_spi_dma_start(drv_data); 743ca632f55SGrant Likely } else { 744ca632f55SGrant Likely /* Ensure we have the correct interrupt handler */ 745ca632f55SGrant Likely drv_data->transfer_handler = interrupt_transfer; 746ca632f55SGrant Likely 747ca632f55SGrant Likely /* Clear status */ 748ca632f55SGrant Likely cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 749ca632f55SGrant Likely write_SSSR_CS(drv_data, drv_data->clear_sr); 750ca632f55SGrant Likely } 751ca632f55SGrant Likely 752a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 753a0d2642eSMika Westerberg if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) 754a0d2642eSMika Westerberg write_SSIRF(chip->lpss_rx_threshold, reg); 755a0d2642eSMika Westerberg if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) 756a0d2642eSMika Westerberg write_SSITF(chip->lpss_tx_threshold, reg); 757a0d2642eSMika Westerberg } 758a0d2642eSMika Westerberg 759ca632f55SGrant Likely /* see if we need to reload the config registers */ 760ca632f55SGrant Likely if ((read_SSCR0(reg) != cr0) 761ca632f55SGrant Likely || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 762ca632f55SGrant Likely (cr1 & SSCR1_CHANGE_MASK)) { 763ca632f55SGrant Likely 764ca632f55SGrant Likely /* stop the SSP, and update the other bits */ 765ca632f55SGrant Likely write_SSCR0(cr0 & ~SSCR0_SSE, reg); 766ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 767ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 768ca632f55SGrant Likely /* first set CR1 without interrupt and service enables */ 769ca632f55SGrant Likely write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 770ca632f55SGrant Likely /* restart the SSP */ 771ca632f55SGrant Likely write_SSCR0(cr0, reg); 772ca632f55SGrant Likely 773ca632f55SGrant Likely } else { 774ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 775ca632f55SGrant Likely write_SSTO(chip->timeout, reg); 776ca632f55SGrant Likely } 777ca632f55SGrant Likely 778ca632f55SGrant Likely cs_assert(drv_data); 779ca632f55SGrant Likely 780ca632f55SGrant Likely /* after chip select, release the data by enabling service 781ca632f55SGrant Likely * requests and interrupts, without changing any mode bits */ 782ca632f55SGrant Likely write_SSCR1(cr1, reg); 783ca632f55SGrant Likely } 784ca632f55SGrant Likely 7857f86bde9SMika Westerberg static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 7867f86bde9SMika Westerberg struct spi_message *msg) 787ca632f55SGrant Likely { 7887f86bde9SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 789ca632f55SGrant Likely 7907f86bde9SMika Westerberg drv_data->cur_msg = msg; 791ca632f55SGrant Likely /* Initial message state*/ 792ca632f55SGrant Likely drv_data->cur_msg->state = START_STATE; 793ca632f55SGrant Likely drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 794ca632f55SGrant Likely struct spi_transfer, 795ca632f55SGrant Likely transfer_list); 796ca632f55SGrant Likely 797ca632f55SGrant Likely /* prepare to setup the SSP, in pump_transfers, using the per 798ca632f55SGrant Likely * chip configuration */ 799ca632f55SGrant Likely drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 800ca632f55SGrant Likely 801ca632f55SGrant Likely /* Mark as busy and launch transfers */ 802ca632f55SGrant Likely tasklet_schedule(&drv_data->pump_transfers); 803ca632f55SGrant Likely return 0; 804ca632f55SGrant Likely } 805ca632f55SGrant Likely 8067d94a505SMika Westerberg static int pxa2xx_spi_prepare_transfer(struct spi_master *master) 8077d94a505SMika Westerberg { 8087d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 8097d94a505SMika Westerberg 8107d94a505SMika Westerberg pm_runtime_get_sync(&drv_data->pdev->dev); 8117d94a505SMika Westerberg return 0; 8127d94a505SMika Westerberg } 8137d94a505SMika Westerberg 8147d94a505SMika Westerberg static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 8157d94a505SMika Westerberg { 8167d94a505SMika Westerberg struct driver_data *drv_data = spi_master_get_devdata(master); 8177d94a505SMika Westerberg 8187d94a505SMika Westerberg /* Disable the SSP now */ 8197d94a505SMika Westerberg write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, 8207d94a505SMika Westerberg drv_data->ioaddr); 8217d94a505SMika Westerberg 8227d94a505SMika Westerberg pm_runtime_mark_last_busy(&drv_data->pdev->dev); 8237d94a505SMika Westerberg pm_runtime_put_autosuspend(&drv_data->pdev->dev); 8247d94a505SMika Westerberg return 0; 8257d94a505SMika Westerberg } 8267d94a505SMika Westerberg 827ca632f55SGrant Likely static int setup_cs(struct spi_device *spi, struct chip_data *chip, 828ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info) 829ca632f55SGrant Likely { 830ca632f55SGrant Likely int err = 0; 831ca632f55SGrant Likely 832ca632f55SGrant Likely if (chip == NULL || chip_info == NULL) 833ca632f55SGrant Likely return 0; 834ca632f55SGrant Likely 835ca632f55SGrant Likely /* NOTE: setup() can be called multiple times, possibly with 836ca632f55SGrant Likely * different chip_info, release previously requested GPIO 837ca632f55SGrant Likely */ 838ca632f55SGrant Likely if (gpio_is_valid(chip->gpio_cs)) 839ca632f55SGrant Likely gpio_free(chip->gpio_cs); 840ca632f55SGrant Likely 841ca632f55SGrant Likely /* If (*cs_control) is provided, ignore GPIO chip select */ 842ca632f55SGrant Likely if (chip_info->cs_control) { 843ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 844ca632f55SGrant Likely return 0; 845ca632f55SGrant Likely } 846ca632f55SGrant Likely 847ca632f55SGrant Likely if (gpio_is_valid(chip_info->gpio_cs)) { 848ca632f55SGrant Likely err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 849ca632f55SGrant Likely if (err) { 850ca632f55SGrant Likely dev_err(&spi->dev, "failed to request chip select " 851ca632f55SGrant Likely "GPIO%d\n", chip_info->gpio_cs); 852ca632f55SGrant Likely return err; 853ca632f55SGrant Likely } 854ca632f55SGrant Likely 855ca632f55SGrant Likely chip->gpio_cs = chip_info->gpio_cs; 856ca632f55SGrant Likely chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 857ca632f55SGrant Likely 858ca632f55SGrant Likely err = gpio_direction_output(chip->gpio_cs, 859ca632f55SGrant Likely !chip->gpio_cs_inverted); 860ca632f55SGrant Likely } 861ca632f55SGrant Likely 862ca632f55SGrant Likely return err; 863ca632f55SGrant Likely } 864ca632f55SGrant Likely 865ca632f55SGrant Likely static int setup(struct spi_device *spi) 866ca632f55SGrant Likely { 867ca632f55SGrant Likely struct pxa2xx_spi_chip *chip_info = NULL; 868ca632f55SGrant Likely struct chip_data *chip; 869ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 870ca632f55SGrant Likely unsigned int clk_div; 871a0d2642eSMika Westerberg uint tx_thres, tx_hi_thres, rx_thres; 872a0d2642eSMika Westerberg 873a0d2642eSMika Westerberg if (is_lpss_ssp(drv_data)) { 874a0d2642eSMika Westerberg tx_thres = LPSS_TX_LOTHRESH_DFLT; 875a0d2642eSMika Westerberg tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 876a0d2642eSMika Westerberg rx_thres = LPSS_RX_THRESH_DFLT; 877a0d2642eSMika Westerberg } else { 878a0d2642eSMika Westerberg tx_thres = TX_THRESH_DFLT; 879a0d2642eSMika Westerberg tx_hi_thres = 0; 880a0d2642eSMika Westerberg rx_thres = RX_THRESH_DFLT; 881a0d2642eSMika Westerberg } 882ca632f55SGrant Likely 883ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data) 884ca632f55SGrant Likely && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { 885ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 886ca632f55SGrant Likely "b/w not 4-32 for type non-PXA25x_SSP\n", 887ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 888ca632f55SGrant Likely return -EINVAL; 889ca632f55SGrant Likely } else if (pxa25x_ssp_comp(drv_data) 890ca632f55SGrant Likely && (spi->bits_per_word < 4 891ca632f55SGrant Likely || spi->bits_per_word > 16)) { 892ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " 893ca632f55SGrant Likely "b/w not 4-16 for type PXA25x_SSP\n", 894ca632f55SGrant Likely drv_data->ssp_type, spi->bits_per_word); 895ca632f55SGrant Likely return -EINVAL; 896ca632f55SGrant Likely } 897ca632f55SGrant Likely 898ca632f55SGrant Likely /* Only alloc on first setup */ 899ca632f55SGrant Likely chip = spi_get_ctldata(spi); 900ca632f55SGrant Likely if (!chip) { 901ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 902ca632f55SGrant Likely if (!chip) { 903ca632f55SGrant Likely dev_err(&spi->dev, 904ca632f55SGrant Likely "failed setup: can't allocate chip data\n"); 905ca632f55SGrant Likely return -ENOMEM; 906ca632f55SGrant Likely } 907ca632f55SGrant Likely 908ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) { 909ca632f55SGrant Likely if (spi->chip_select > 4) { 910ca632f55SGrant Likely dev_err(&spi->dev, "failed setup: " 911ca632f55SGrant Likely "cs number must not be > 4.\n"); 912ca632f55SGrant Likely kfree(chip); 913ca632f55SGrant Likely return -EINVAL; 914ca632f55SGrant Likely } 915ca632f55SGrant Likely 916ca632f55SGrant Likely chip->frm = spi->chip_select; 917ca632f55SGrant Likely } else 918ca632f55SGrant Likely chip->gpio_cs = -1; 919ca632f55SGrant Likely chip->enable_dma = 0; 920ca632f55SGrant Likely chip->timeout = TIMOUT_DFLT; 921ca632f55SGrant Likely } 922ca632f55SGrant Likely 923ca632f55SGrant Likely /* protocol drivers may change the chip settings, so... 924ca632f55SGrant Likely * if chip_info exists, use it */ 925ca632f55SGrant Likely chip_info = spi->controller_data; 926ca632f55SGrant Likely 927ca632f55SGrant Likely /* chip_info isn't always needed */ 928ca632f55SGrant Likely chip->cr1 = 0; 929ca632f55SGrant Likely if (chip_info) { 930ca632f55SGrant Likely if (chip_info->timeout) 931ca632f55SGrant Likely chip->timeout = chip_info->timeout; 932ca632f55SGrant Likely if (chip_info->tx_threshold) 933ca632f55SGrant Likely tx_thres = chip_info->tx_threshold; 934a0d2642eSMika Westerberg if (chip_info->tx_hi_threshold) 935a0d2642eSMika Westerberg tx_hi_thres = chip_info->tx_hi_threshold; 936ca632f55SGrant Likely if (chip_info->rx_threshold) 937ca632f55SGrant Likely rx_thres = chip_info->rx_threshold; 938ca632f55SGrant Likely chip->enable_dma = drv_data->master_info->enable_dma; 939ca632f55SGrant Likely chip->dma_threshold = 0; 940ca632f55SGrant Likely if (chip_info->enable_loopback) 941ca632f55SGrant Likely chip->cr1 = SSCR1_LBM; 942a3496855SMika Westerberg } else if (ACPI_HANDLE(&spi->dev)) { 943a3496855SMika Westerberg /* 944a3496855SMika Westerberg * Slave devices enumerated from ACPI namespace don't 945a3496855SMika Westerberg * usually have chip_info but we still might want to use 946a3496855SMika Westerberg * DMA with them. 947a3496855SMika Westerberg */ 948a3496855SMika Westerberg chip->enable_dma = drv_data->master_info->enable_dma; 949ca632f55SGrant Likely } 950ca632f55SGrant Likely 951ca632f55SGrant Likely chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 952ca632f55SGrant Likely (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 953ca632f55SGrant Likely 954a0d2642eSMika Westerberg chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 955a0d2642eSMika Westerberg chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 956a0d2642eSMika Westerberg | SSITF_TxHiThresh(tx_hi_thres); 957a0d2642eSMika Westerberg 958ca632f55SGrant Likely /* set dma burst and threshold outside of chip_info path so that if 959ca632f55SGrant Likely * chip_info goes away after setting chip->enable_dma, the 960ca632f55SGrant Likely * burst and threshold can still respond to changes in bits_per_word */ 961ca632f55SGrant Likely if (chip->enable_dma) { 962ca632f55SGrant Likely /* set up legal burst and threshold for dma */ 963cd7bed00SMika Westerberg if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 964cd7bed00SMika Westerberg spi->bits_per_word, 965ca632f55SGrant Likely &chip->dma_burst_size, 966ca632f55SGrant Likely &chip->dma_threshold)) { 967ca632f55SGrant Likely dev_warn(&spi->dev, "in setup: DMA burst size reduced " 968ca632f55SGrant Likely "to match bits_per_word\n"); 969ca632f55SGrant Likely } 970ca632f55SGrant Likely } 971ca632f55SGrant Likely 9723343b7a6SMika Westerberg clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 973ca632f55SGrant Likely chip->speed_hz = spi->max_speed_hz; 974ca632f55SGrant Likely 975ca632f55SGrant Likely chip->cr0 = clk_div 976ca632f55SGrant Likely | SSCR0_Motorola 977ca632f55SGrant Likely | SSCR0_DataSize(spi->bits_per_word > 16 ? 978ca632f55SGrant Likely spi->bits_per_word - 16 : spi->bits_per_word) 979ca632f55SGrant Likely | SSCR0_SSE 980ca632f55SGrant Likely | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 981ca632f55SGrant Likely chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 982ca632f55SGrant Likely chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 983ca632f55SGrant Likely | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 984ca632f55SGrant Likely 985b833172fSMika Westerberg if (spi->mode & SPI_LOOP) 986b833172fSMika Westerberg chip->cr1 |= SSCR1_LBM; 987b833172fSMika Westerberg 988ca632f55SGrant Likely /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 989ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 990ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 9913343b7a6SMika Westerberg drv_data->max_clk_rate 992ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 993ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 994ca632f55SGrant Likely else 995ca632f55SGrant Likely dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 9963343b7a6SMika Westerberg drv_data->max_clk_rate / 2 997ca632f55SGrant Likely / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 998ca632f55SGrant Likely chip->enable_dma ? "DMA" : "PIO"); 999ca632f55SGrant Likely 1000ca632f55SGrant Likely if (spi->bits_per_word <= 8) { 1001ca632f55SGrant Likely chip->n_bytes = 1; 1002ca632f55SGrant Likely chip->read = u8_reader; 1003ca632f55SGrant Likely chip->write = u8_writer; 1004ca632f55SGrant Likely } else if (spi->bits_per_word <= 16) { 1005ca632f55SGrant Likely chip->n_bytes = 2; 1006ca632f55SGrant Likely chip->read = u16_reader; 1007ca632f55SGrant Likely chip->write = u16_writer; 1008ca632f55SGrant Likely } else if (spi->bits_per_word <= 32) { 1009ca632f55SGrant Likely chip->cr0 |= SSCR0_EDSS; 1010ca632f55SGrant Likely chip->n_bytes = 4; 1011ca632f55SGrant Likely chip->read = u32_reader; 1012ca632f55SGrant Likely chip->write = u32_writer; 1013ca632f55SGrant Likely } else { 1014ca632f55SGrant Likely dev_err(&spi->dev, "invalid wordsize\n"); 1015ca632f55SGrant Likely return -ENODEV; 1016ca632f55SGrant Likely } 1017ca632f55SGrant Likely chip->bits_per_word = spi->bits_per_word; 1018ca632f55SGrant Likely 1019ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1020ca632f55SGrant Likely 1021ca632f55SGrant Likely if (drv_data->ssp_type == CE4100_SSP) 1022ca632f55SGrant Likely return 0; 1023ca632f55SGrant Likely 1024ca632f55SGrant Likely return setup_cs(spi, chip, chip_info); 1025ca632f55SGrant Likely } 1026ca632f55SGrant Likely 1027ca632f55SGrant Likely static void cleanup(struct spi_device *spi) 1028ca632f55SGrant Likely { 1029ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1030ca632f55SGrant Likely struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1031ca632f55SGrant Likely 1032ca632f55SGrant Likely if (!chip) 1033ca632f55SGrant Likely return; 1034ca632f55SGrant Likely 1035ca632f55SGrant Likely if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1036ca632f55SGrant Likely gpio_free(chip->gpio_cs); 1037ca632f55SGrant Likely 1038ca632f55SGrant Likely kfree(chip); 1039ca632f55SGrant Likely } 1040ca632f55SGrant Likely 1041a3496855SMika Westerberg #ifdef CONFIG_ACPI 1042a3496855SMika Westerberg static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data) 1043a3496855SMika Westerberg { 1044a3496855SMika Westerberg struct pxa2xx_spi_master *pdata = data; 1045a3496855SMika Westerberg 1046a3496855SMika Westerberg if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) { 1047a3496855SMika Westerberg const struct acpi_resource_fixed_dma *dma; 1048a3496855SMika Westerberg 1049a3496855SMika Westerberg dma = &res->data.fixed_dma; 1050a3496855SMika Westerberg if (pdata->tx_slave_id < 0) { 1051a3496855SMika Westerberg pdata->tx_slave_id = dma->request_lines; 1052a3496855SMika Westerberg pdata->tx_chan_id = dma->channels; 1053a3496855SMika Westerberg } else if (pdata->rx_slave_id < 0) { 1054a3496855SMika Westerberg pdata->rx_slave_id = dma->request_lines; 1055a3496855SMika Westerberg pdata->rx_chan_id = dma->channels; 1056a3496855SMika Westerberg } 1057a3496855SMika Westerberg } 1058a3496855SMika Westerberg 1059a3496855SMika Westerberg /* Tell the ACPI core to skip this resource */ 1060a3496855SMika Westerberg return 1; 1061a3496855SMika Westerberg } 1062a3496855SMika Westerberg 1063a3496855SMika Westerberg static struct pxa2xx_spi_master * 1064a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1065a3496855SMika Westerberg { 1066a3496855SMika Westerberg struct pxa2xx_spi_master *pdata; 1067a3496855SMika Westerberg struct list_head resource_list; 1068a3496855SMika Westerberg struct acpi_device *adev; 1069a3496855SMika Westerberg struct ssp_device *ssp; 1070a3496855SMika Westerberg struct resource *res; 1071a3496855SMika Westerberg int devid; 1072a3496855SMika Westerberg 1073a3496855SMika Westerberg if (!ACPI_HANDLE(&pdev->dev) || 1074a3496855SMika Westerberg acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1075a3496855SMika Westerberg return NULL; 1076a3496855SMika Westerberg 1077a3496855SMika Westerberg pdata = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); 1078a3496855SMika Westerberg if (!pdata) { 1079a3496855SMika Westerberg dev_err(&pdev->dev, 1080a3496855SMika Westerberg "failed to allocate memory for platform data\n"); 1081a3496855SMika Westerberg return NULL; 1082a3496855SMika Westerberg } 1083a3496855SMika Westerberg 1084a3496855SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1085a3496855SMika Westerberg if (!res) 1086a3496855SMika Westerberg return NULL; 1087a3496855SMika Westerberg 1088a3496855SMika Westerberg ssp = &pdata->ssp; 1089a3496855SMika Westerberg 1090a3496855SMika Westerberg ssp->phys_base = res->start; 1091a3496855SMika Westerberg ssp->mmio_base = devm_request_and_ioremap(&pdev->dev, res); 1092a3496855SMika Westerberg if (!ssp->mmio_base) { 1093a3496855SMika Westerberg dev_err(&pdev->dev, "failed to ioremap mmio_base\n"); 1094a3496855SMika Westerberg return NULL; 1095a3496855SMika Westerberg } 1096a3496855SMika Westerberg 1097a3496855SMika Westerberg ssp->clk = devm_clk_get(&pdev->dev, NULL); 1098a3496855SMika Westerberg ssp->irq = platform_get_irq(pdev, 0); 1099a3496855SMika Westerberg ssp->type = LPSS_SSP; 1100a3496855SMika Westerberg ssp->pdev = pdev; 1101a3496855SMika Westerberg 1102a3496855SMika Westerberg ssp->port_id = -1; 1103a3496855SMika Westerberg if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1104a3496855SMika Westerberg ssp->port_id = devid; 1105a3496855SMika Westerberg 1106a3496855SMika Westerberg pdata->num_chipselect = 1; 1107a3496855SMika Westerberg pdata->rx_slave_id = -1; 1108a3496855SMika Westerberg pdata->tx_slave_id = -1; 1109a3496855SMika Westerberg 1110a3496855SMika Westerberg INIT_LIST_HEAD(&resource_list); 1111a3496855SMika Westerberg acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma, 1112a3496855SMika Westerberg pdata); 1113a3496855SMika Westerberg acpi_dev_free_resource_list(&resource_list); 1114a3496855SMika Westerberg 1115a3496855SMika Westerberg pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0; 1116a3496855SMika Westerberg 1117a3496855SMika Westerberg return pdata; 1118a3496855SMika Westerberg } 1119a3496855SMika Westerberg 1120a3496855SMika Westerberg static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1121a3496855SMika Westerberg { "INT33C0", 0 }, 1122a3496855SMika Westerberg { "INT33C1", 0 }, 1123a3496855SMika Westerberg { }, 1124a3496855SMika Westerberg }; 1125a3496855SMika Westerberg MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1126a3496855SMika Westerberg #else 1127a3496855SMika Westerberg static inline struct pxa2xx_spi_master * 1128a3496855SMika Westerberg pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1129a3496855SMika Westerberg { 1130a3496855SMika Westerberg return NULL; 1131a3496855SMika Westerberg } 1132a3496855SMika Westerberg #endif 1133a3496855SMika Westerberg 1134fd4a319bSGrant Likely static int pxa2xx_spi_probe(struct platform_device *pdev) 1135ca632f55SGrant Likely { 1136ca632f55SGrant Likely struct device *dev = &pdev->dev; 1137ca632f55SGrant Likely struct pxa2xx_spi_master *platform_info; 1138ca632f55SGrant Likely struct spi_master *master; 1139ca632f55SGrant Likely struct driver_data *drv_data; 1140ca632f55SGrant Likely struct ssp_device *ssp; 1141ca632f55SGrant Likely int status; 1142ca632f55SGrant Likely 1143851bacf5SMika Westerberg platform_info = dev_get_platdata(dev); 1144851bacf5SMika Westerberg if (!platform_info) { 1145a3496855SMika Westerberg platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1146a3496855SMika Westerberg if (!platform_info) { 1147851bacf5SMika Westerberg dev_err(&pdev->dev, "missing platform data\n"); 1148851bacf5SMika Westerberg return -ENODEV; 1149851bacf5SMika Westerberg } 1150a3496855SMika Westerberg } 1151ca632f55SGrant Likely 1152ca632f55SGrant Likely ssp = pxa_ssp_request(pdev->id, pdev->name); 1153851bacf5SMika Westerberg if (!ssp) 1154851bacf5SMika Westerberg ssp = &platform_info->ssp; 1155851bacf5SMika Westerberg 1156851bacf5SMika Westerberg if (!ssp->mmio_base) { 1157851bacf5SMika Westerberg dev_err(&pdev->dev, "failed to get ssp\n"); 1158ca632f55SGrant Likely return -ENODEV; 1159ca632f55SGrant Likely } 1160ca632f55SGrant Likely 1161ca632f55SGrant Likely /* Allocate master with space for drv_data and null dma buffer */ 1162ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1163ca632f55SGrant Likely if (!master) { 1164ca632f55SGrant Likely dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1165ca632f55SGrant Likely pxa_ssp_free(ssp); 1166ca632f55SGrant Likely return -ENOMEM; 1167ca632f55SGrant Likely } 1168ca632f55SGrant Likely drv_data = spi_master_get_devdata(master); 1169ca632f55SGrant Likely drv_data->master = master; 1170ca632f55SGrant Likely drv_data->master_info = platform_info; 1171ca632f55SGrant Likely drv_data->pdev = pdev; 1172ca632f55SGrant Likely drv_data->ssp = ssp; 1173ca632f55SGrant Likely 1174ca632f55SGrant Likely master->dev.parent = &pdev->dev; 1175ca632f55SGrant Likely master->dev.of_node = pdev->dev.of_node; 1176a3496855SMika Westerberg ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev)); 1177ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1178b833172fSMika Westerberg master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1179ca632f55SGrant Likely 1180851bacf5SMika Westerberg master->bus_num = ssp->port_id; 1181ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 1182ca632f55SGrant Likely master->dma_alignment = DMA_ALIGNMENT; 1183ca632f55SGrant Likely master->cleanup = cleanup; 1184ca632f55SGrant Likely master->setup = setup; 11857f86bde9SMika Westerberg master->transfer_one_message = pxa2xx_spi_transfer_one_message; 11867d94a505SMika Westerberg master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; 11877d94a505SMika Westerberg master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1188ca632f55SGrant Likely 1189ca632f55SGrant Likely drv_data->ssp_type = ssp->type; 11902b9b84f4SMika Westerberg drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1191ca632f55SGrant Likely 1192ca632f55SGrant Likely drv_data->ioaddr = ssp->mmio_base; 1193ca632f55SGrant Likely drv_data->ssdr_physical = ssp->phys_base + SSDR; 1194ca632f55SGrant Likely if (pxa25x_ssp_comp(drv_data)) { 1195ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1196ca632f55SGrant Likely drv_data->dma_cr1 = 0; 1197ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR; 1198ca632f55SGrant Likely drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1199ca632f55SGrant Likely } else { 1200ca632f55SGrant Likely drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 12015928808eSMika Westerberg drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1202ca632f55SGrant Likely drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1203ca632f55SGrant Likely drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1204ca632f55SGrant Likely } 1205ca632f55SGrant Likely 1206ca632f55SGrant Likely status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1207ca632f55SGrant Likely drv_data); 1208ca632f55SGrant Likely if (status < 0) { 1209ca632f55SGrant Likely dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1210ca632f55SGrant Likely goto out_error_master_alloc; 1211ca632f55SGrant Likely } 1212ca632f55SGrant Likely 1213ca632f55SGrant Likely /* Setup DMA if requested */ 1214ca632f55SGrant Likely drv_data->tx_channel = -1; 1215ca632f55SGrant Likely drv_data->rx_channel = -1; 1216ca632f55SGrant Likely if (platform_info->enable_dma) { 1217cd7bed00SMika Westerberg status = pxa2xx_spi_dma_setup(drv_data); 1218cd7bed00SMika Westerberg if (status) { 1219cd7bed00SMika Westerberg dev_warn(dev, "failed to setup DMA, using PIO\n"); 1220cd7bed00SMika Westerberg platform_info->enable_dma = false; 1221ca632f55SGrant Likely } 1222ca632f55SGrant Likely } 1223ca632f55SGrant Likely 1224ca632f55SGrant Likely /* Enable SOC clock */ 12253343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 12263343b7a6SMika Westerberg 12273343b7a6SMika Westerberg drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1228ca632f55SGrant Likely 1229ca632f55SGrant Likely /* Load default SSP configuration */ 1230ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 1231ca632f55SGrant Likely write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1232ca632f55SGrant Likely SSCR1_TxTresh(TX_THRESH_DFLT), 1233ca632f55SGrant Likely drv_data->ioaddr); 1234ca632f55SGrant Likely write_SSCR0(SSCR0_SCR(2) 1235ca632f55SGrant Likely | SSCR0_Motorola 1236ca632f55SGrant Likely | SSCR0_DataSize(8), 1237ca632f55SGrant Likely drv_data->ioaddr); 1238ca632f55SGrant Likely if (!pxa25x_ssp_comp(drv_data)) 1239ca632f55SGrant Likely write_SSTO(0, drv_data->ioaddr); 1240ca632f55SGrant Likely write_SSPSP(0, drv_data->ioaddr); 1241ca632f55SGrant Likely 1242a0d2642eSMika Westerberg lpss_ssp_setup(drv_data); 1243a0d2642eSMika Westerberg 12447f86bde9SMika Westerberg tasklet_init(&drv_data->pump_transfers, pump_transfers, 12457f86bde9SMika Westerberg (unsigned long)drv_data); 1246ca632f55SGrant Likely 1247ca632f55SGrant Likely /* Register with the SPI framework */ 1248ca632f55SGrant Likely platform_set_drvdata(pdev, drv_data); 1249ca632f55SGrant Likely status = spi_register_master(master); 1250ca632f55SGrant Likely if (status != 0) { 1251ca632f55SGrant Likely dev_err(&pdev->dev, "problem registering spi master\n"); 12527f86bde9SMika Westerberg goto out_error_clock_enabled; 1253ca632f55SGrant Likely } 1254ca632f55SGrant Likely 12557d94a505SMika Westerberg pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 12567d94a505SMika Westerberg pm_runtime_use_autosuspend(&pdev->dev); 12577d94a505SMika Westerberg pm_runtime_set_active(&pdev->dev); 12587d94a505SMika Westerberg pm_runtime_enable(&pdev->dev); 12597d94a505SMika Westerberg 1260ca632f55SGrant Likely return status; 1261ca632f55SGrant Likely 1262ca632f55SGrant Likely out_error_clock_enabled: 12633343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1264cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1265ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1266ca632f55SGrant Likely 1267ca632f55SGrant Likely out_error_master_alloc: 1268ca632f55SGrant Likely spi_master_put(master); 1269ca632f55SGrant Likely pxa_ssp_free(ssp); 1270ca632f55SGrant Likely return status; 1271ca632f55SGrant Likely } 1272ca632f55SGrant Likely 1273ca632f55SGrant Likely static int pxa2xx_spi_remove(struct platform_device *pdev) 1274ca632f55SGrant Likely { 1275ca632f55SGrant Likely struct driver_data *drv_data = platform_get_drvdata(pdev); 1276ca632f55SGrant Likely struct ssp_device *ssp; 1277ca632f55SGrant Likely 1278ca632f55SGrant Likely if (!drv_data) 1279ca632f55SGrant Likely return 0; 1280ca632f55SGrant Likely ssp = drv_data->ssp; 1281ca632f55SGrant Likely 12827d94a505SMika Westerberg pm_runtime_get_sync(&pdev->dev); 12837d94a505SMika Westerberg 1284ca632f55SGrant Likely /* Disable the SSP at the peripheral and SOC level */ 1285ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 12863343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1287ca632f55SGrant Likely 1288ca632f55SGrant Likely /* Release DMA */ 1289cd7bed00SMika Westerberg if (drv_data->master_info->enable_dma) 1290cd7bed00SMika Westerberg pxa2xx_spi_dma_release(drv_data); 1291ca632f55SGrant Likely 12927d94a505SMika Westerberg pm_runtime_put_noidle(&pdev->dev); 12937d94a505SMika Westerberg pm_runtime_disable(&pdev->dev); 12947d94a505SMika Westerberg 1295ca632f55SGrant Likely /* Release IRQ */ 1296ca632f55SGrant Likely free_irq(ssp->irq, drv_data); 1297ca632f55SGrant Likely 1298ca632f55SGrant Likely /* Release SSP */ 1299ca632f55SGrant Likely pxa_ssp_free(ssp); 1300ca632f55SGrant Likely 1301ca632f55SGrant Likely /* Disconnect from the SPI framework */ 1302ca632f55SGrant Likely spi_unregister_master(drv_data->master); 1303ca632f55SGrant Likely 1304ca632f55SGrant Likely /* Prevent double remove */ 1305ca632f55SGrant Likely platform_set_drvdata(pdev, NULL); 1306ca632f55SGrant Likely 1307ca632f55SGrant Likely return 0; 1308ca632f55SGrant Likely } 1309ca632f55SGrant Likely 1310ca632f55SGrant Likely static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1311ca632f55SGrant Likely { 1312ca632f55SGrant Likely int status = 0; 1313ca632f55SGrant Likely 1314ca632f55SGrant Likely if ((status = pxa2xx_spi_remove(pdev)) != 0) 1315ca632f55SGrant Likely dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1316ca632f55SGrant Likely } 1317ca632f55SGrant Likely 1318ca632f55SGrant Likely #ifdef CONFIG_PM 1319ca632f55SGrant Likely static int pxa2xx_spi_suspend(struct device *dev) 1320ca632f55SGrant Likely { 1321ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1322ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1323ca632f55SGrant Likely int status = 0; 1324ca632f55SGrant Likely 13257f86bde9SMika Westerberg status = spi_master_suspend(drv_data->master); 1326ca632f55SGrant Likely if (status != 0) 1327ca632f55SGrant Likely return status; 1328ca632f55SGrant Likely write_SSCR0(0, drv_data->ioaddr); 13293343b7a6SMika Westerberg clk_disable_unprepare(ssp->clk); 1330ca632f55SGrant Likely 1331ca632f55SGrant Likely return 0; 1332ca632f55SGrant Likely } 1333ca632f55SGrant Likely 1334ca632f55SGrant Likely static int pxa2xx_spi_resume(struct device *dev) 1335ca632f55SGrant Likely { 1336ca632f55SGrant Likely struct driver_data *drv_data = dev_get_drvdata(dev); 1337ca632f55SGrant Likely struct ssp_device *ssp = drv_data->ssp; 1338ca632f55SGrant Likely int status = 0; 1339ca632f55SGrant Likely 1340cd7bed00SMika Westerberg pxa2xx_spi_dma_resume(drv_data); 1341ca632f55SGrant Likely 1342ca632f55SGrant Likely /* Enable the SSP clock */ 13433343b7a6SMika Westerberg clk_prepare_enable(ssp->clk); 1344ca632f55SGrant Likely 1345ca632f55SGrant Likely /* Start the queue running */ 13467f86bde9SMika Westerberg status = spi_master_resume(drv_data->master); 1347ca632f55SGrant Likely if (status != 0) { 1348ca632f55SGrant Likely dev_err(dev, "problem starting queue (%d)\n", status); 1349ca632f55SGrant Likely return status; 1350ca632f55SGrant Likely } 1351ca632f55SGrant Likely 1352ca632f55SGrant Likely return 0; 1353ca632f55SGrant Likely } 13547d94a505SMika Westerberg #endif 13557d94a505SMika Westerberg 13567d94a505SMika Westerberg #ifdef CONFIG_PM_RUNTIME 13577d94a505SMika Westerberg static int pxa2xx_spi_runtime_suspend(struct device *dev) 13587d94a505SMika Westerberg { 13597d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 13607d94a505SMika Westerberg 13617d94a505SMika Westerberg clk_disable_unprepare(drv_data->ssp->clk); 13627d94a505SMika Westerberg return 0; 13637d94a505SMika Westerberg } 13647d94a505SMika Westerberg 13657d94a505SMika Westerberg static int pxa2xx_spi_runtime_resume(struct device *dev) 13667d94a505SMika Westerberg { 13677d94a505SMika Westerberg struct driver_data *drv_data = dev_get_drvdata(dev); 13687d94a505SMika Westerberg 13697d94a505SMika Westerberg clk_prepare_enable(drv_data->ssp->clk); 13707d94a505SMika Westerberg return 0; 13717d94a505SMika Westerberg } 13727d94a505SMika Westerberg #endif 1373ca632f55SGrant Likely 1374ca632f55SGrant Likely static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 13757d94a505SMika Westerberg SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 13767d94a505SMika Westerberg SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 13777d94a505SMika Westerberg pxa2xx_spi_runtime_resume, NULL) 1378ca632f55SGrant Likely }; 1379ca632f55SGrant Likely 1380ca632f55SGrant Likely static struct platform_driver driver = { 1381ca632f55SGrant Likely .driver = { 1382ca632f55SGrant Likely .name = "pxa2xx-spi", 1383ca632f55SGrant Likely .owner = THIS_MODULE, 1384ca632f55SGrant Likely .pm = &pxa2xx_spi_pm_ops, 1385a3496855SMika Westerberg .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1386ca632f55SGrant Likely }, 1387ca632f55SGrant Likely .probe = pxa2xx_spi_probe, 1388ca632f55SGrant Likely .remove = pxa2xx_spi_remove, 1389ca632f55SGrant Likely .shutdown = pxa2xx_spi_shutdown, 1390ca632f55SGrant Likely }; 1391ca632f55SGrant Likely 1392ca632f55SGrant Likely static int __init pxa2xx_spi_init(void) 1393ca632f55SGrant Likely { 1394ca632f55SGrant Likely return platform_driver_register(&driver); 1395ca632f55SGrant Likely } 1396ca632f55SGrant Likely subsys_initcall(pxa2xx_spi_init); 1397ca632f55SGrant Likely 1398ca632f55SGrant Likely static void __exit pxa2xx_spi_exit(void) 1399ca632f55SGrant Likely { 1400ca632f55SGrant Likely platform_driver_unregister(&driver); 1401ca632f55SGrant Likely } 1402ca632f55SGrant Likely module_exit(pxa2xx_spi_exit); 1403