1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2ca632f55SGrant Likely /*
3ca632f55SGrant Likely * SPI_PPC4XX SPI controller driver.
4ca632f55SGrant Likely *
5ca632f55SGrant Likely * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
6ca632f55SGrant Likely * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
7ca632f55SGrant Likely * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
8ca632f55SGrant Likely *
9ca632f55SGrant Likely * Based in part on drivers/spi/spi_s3c24xx.c
10ca632f55SGrant Likely *
11ca632f55SGrant Likely * Copyright (c) 2006 Ben Dooks
12ca632f55SGrant Likely * Copyright (c) 2006 Simtec Electronics
13ca632f55SGrant Likely * Ben Dooks <ben@simtec.co.uk>
14ca632f55SGrant Likely */
15ca632f55SGrant Likely
16ca632f55SGrant Likely /*
17ca632f55SGrant Likely * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18ca632f55SGrant Likely * generate an interrupt to the CPU. This can cause high CPU utilization.
19ca632f55SGrant Likely * This driver allows platforms to reduce the interrupt load on the CPU
20ca632f55SGrant Likely * during SPI transfers by setting max_speed_hz via the device tree.
21ca632f55SGrant Likely */
22ca632f55SGrant Likely
23ca632f55SGrant Likely #include <linux/module.h>
24ca632f55SGrant Likely #include <linux/sched.h>
25ca632f55SGrant Likely #include <linux/slab.h>
26ca632f55SGrant Likely #include <linux/errno.h>
27ca632f55SGrant Likely #include <linux/wait.h>
28c11eede6SRob Herring #include <linux/of_address.h>
29ca632f55SGrant Likely #include <linux/of_platform.h>
30ca632f55SGrant Likely #include <linux/interrupt.h>
31ca632f55SGrant Likely #include <linux/delay.h>
32ca632f55SGrant Likely
33ca632f55SGrant Likely #include <linux/spi/spi.h>
34ca632f55SGrant Likely #include <linux/spi/spi_bitbang.h>
35ca632f55SGrant Likely
3666fe7403SJay Fang #include <linux/io.h>
37ca632f55SGrant Likely #include <asm/dcr.h>
38ca632f55SGrant Likely #include <asm/dcr-regs.h>
39ca632f55SGrant Likely
40ca632f55SGrant Likely /* bits in mode register - bit 0 is MSb */
41ca632f55SGrant Likely
42ca632f55SGrant Likely /*
43ca632f55SGrant Likely * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
44ca632f55SGrant Likely * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
45ca632f55SGrant Likely * Note: This is the inverse of CPHA.
46ca632f55SGrant Likely */
47ca632f55SGrant Likely #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
48ca632f55SGrant Likely
49ca632f55SGrant Likely /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
50ca632f55SGrant Likely #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
51ca632f55SGrant Likely
52ca632f55SGrant Likely /*
53ca632f55SGrant Likely * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
54ca632f55SGrant Likely * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
55ca632f55SGrant Likely * Note: This is identical to SPI_LSB_FIRST.
56ca632f55SGrant Likely */
57ca632f55SGrant Likely #define SPI_PPC4XX_MODE_RD (0x80 >> 5)
58ca632f55SGrant Likely
59ca632f55SGrant Likely /*
60ca632f55SGrant Likely * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
61ca632f55SGrant Likely * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
62ca632f55SGrant Likely * Note: This is identical to CPOL.
63ca632f55SGrant Likely */
64ca632f55SGrant Likely #define SPI_PPC4XX_MODE_CI (0x80 >> 6)
65ca632f55SGrant Likely
66ca632f55SGrant Likely /*
67ca632f55SGrant Likely * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
68ca632f55SGrant Likely * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
69ca632f55SGrant Likely */
70ca632f55SGrant Likely #define SPI_PPC4XX_MODE_IL (0x80 >> 7)
71ca632f55SGrant Likely
72ca632f55SGrant Likely /* bits in control register */
73ca632f55SGrant Likely /* starts a transfer when set */
74ca632f55SGrant Likely #define SPI_PPC4XX_CR_STR (0x80 >> 7)
75ca632f55SGrant Likely
76ca632f55SGrant Likely /* bits in status register */
77ca632f55SGrant Likely /* port is busy with a transfer */
78ca632f55SGrant Likely #define SPI_PPC4XX_SR_BSY (0x80 >> 6)
79ca632f55SGrant Likely /* RxD ready */
80ca632f55SGrant Likely #define SPI_PPC4XX_SR_RBR (0x80 >> 7)
81ca632f55SGrant Likely
82ca632f55SGrant Likely /* clock settings (SCP and CI) for various SPI modes */
83ca632f55SGrant Likely #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
84ca632f55SGrant Likely #define SPI_CLK_MODE1 (0 | 0)
85ca632f55SGrant Likely #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
86ca632f55SGrant Likely #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
87ca632f55SGrant Likely
88ca632f55SGrant Likely #define DRIVER_NAME "spi_ppc4xx_of"
89ca632f55SGrant Likely
90ca632f55SGrant Likely struct spi_ppc4xx_regs {
91ca632f55SGrant Likely u8 mode;
92ca632f55SGrant Likely u8 rxd;
93ca632f55SGrant Likely u8 txd;
94ca632f55SGrant Likely u8 cr;
95ca632f55SGrant Likely u8 sr;
96ca632f55SGrant Likely u8 dummy;
97ca632f55SGrant Likely /*
98ca632f55SGrant Likely * Clock divisor modulus register
99886db6acSMasanari Iida * This uses the following formula:
100ca632f55SGrant Likely * SCPClkOut = OPBCLK/(4(CDM + 1))
101ca632f55SGrant Likely * or
102ca632f55SGrant Likely * CDM = (OPBCLK/4*SCPClkOut) - 1
103ca632f55SGrant Likely * bit 0 is the MSb!
104ca632f55SGrant Likely */
105ca632f55SGrant Likely u8 cdm;
106ca632f55SGrant Likely };
107ca632f55SGrant Likely
108ca632f55SGrant Likely /* SPI Controller driver's private data. */
109ca632f55SGrant Likely struct ppc4xx_spi {
110ca632f55SGrant Likely /* bitbang has to be first */
111ca632f55SGrant Likely struct spi_bitbang bitbang;
112ca632f55SGrant Likely struct completion done;
113ca632f55SGrant Likely
114ca632f55SGrant Likely u64 mapbase;
115ca632f55SGrant Likely u64 mapsize;
116ca632f55SGrant Likely int irqnum;
117ca632f55SGrant Likely /* need this to set the SPI clock */
118ca632f55SGrant Likely unsigned int opb_freq;
119ca632f55SGrant Likely
120ca632f55SGrant Likely /* for transfers */
121ca632f55SGrant Likely int len;
122ca632f55SGrant Likely int count;
123ca632f55SGrant Likely /* data buffers */
124ca632f55SGrant Likely const unsigned char *tx;
125ca632f55SGrant Likely unsigned char *rx;
126ca632f55SGrant Likely
127ca632f55SGrant Likely struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
12871345830SYang Yingliang struct spi_controller *host;
129ca632f55SGrant Likely struct device *dev;
130ca632f55SGrant Likely };
131ca632f55SGrant Likely
132ca632f55SGrant Likely /* need this so we can set the clock in the chipselect routine */
133ca632f55SGrant Likely struct spi_ppc4xx_cs {
134ca632f55SGrant Likely u8 mode;
135ca632f55SGrant Likely };
136ca632f55SGrant Likely
spi_ppc4xx_txrx(struct spi_device * spi,struct spi_transfer * t)137ca632f55SGrant Likely static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
138ca632f55SGrant Likely {
139ca632f55SGrant Likely struct ppc4xx_spi *hw;
140ca632f55SGrant Likely u8 data;
141ca632f55SGrant Likely
142ca632f55SGrant Likely dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
143ca632f55SGrant Likely t->tx_buf, t->rx_buf, t->len);
144ca632f55SGrant Likely
14571345830SYang Yingliang hw = spi_controller_get_devdata(spi->controller);
146ca632f55SGrant Likely
147ca632f55SGrant Likely hw->tx = t->tx_buf;
148ca632f55SGrant Likely hw->rx = t->rx_buf;
149ca632f55SGrant Likely hw->len = t->len;
150ca632f55SGrant Likely hw->count = 0;
151ca632f55SGrant Likely
152ca632f55SGrant Likely /* send the first byte */
153ca632f55SGrant Likely data = hw->tx ? hw->tx[0] : 0;
154ca632f55SGrant Likely out_8(&hw->regs->txd, data);
155ca632f55SGrant Likely out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
156ca632f55SGrant Likely wait_for_completion(&hw->done);
157ca632f55SGrant Likely
158ca632f55SGrant Likely return hw->count;
159ca632f55SGrant Likely }
160ca632f55SGrant Likely
spi_ppc4xx_setupxfer(struct spi_device * spi,struct spi_transfer * t)161ca632f55SGrant Likely static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
162ca632f55SGrant Likely {
16371345830SYang Yingliang struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller);
164ca632f55SGrant Likely struct spi_ppc4xx_cs *cs = spi->controller_state;
165ca632f55SGrant Likely int scr;
166ca632f55SGrant Likely u8 cdm = 0;
167ca632f55SGrant Likely u32 speed;
168ca632f55SGrant Likely
169ca632f55SGrant Likely /* Start with the generic configuration for this device. */
170ca632f55SGrant Likely speed = spi->max_speed_hz;
171ca632f55SGrant Likely
172ca632f55SGrant Likely /*
173ca632f55SGrant Likely * Modify the configuration if the transfer overrides it. Do not allow
174ca632f55SGrant Likely * the transfer to overwrite the generic configuration with zeros.
175ca632f55SGrant Likely */
176ca632f55SGrant Likely if (t) {
177ca632f55SGrant Likely if (t->speed_hz)
178ca632f55SGrant Likely speed = min(t->speed_hz, spi->max_speed_hz);
179ca632f55SGrant Likely }
180ca632f55SGrant Likely
181ca632f55SGrant Likely if (!speed || (speed > spi->max_speed_hz)) {
182ca632f55SGrant Likely dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
183ca632f55SGrant Likely return -EINVAL;
184ca632f55SGrant Likely }
185ca632f55SGrant Likely
186886db6acSMasanari Iida /* Write new configuration */
187ca632f55SGrant Likely out_8(&hw->regs->mode, cs->mode);
188ca632f55SGrant Likely
189ca632f55SGrant Likely /* Set the clock */
190ca632f55SGrant Likely /* opb_freq was already divided by 4 */
191ca632f55SGrant Likely scr = (hw->opb_freq / speed) - 1;
192ca632f55SGrant Likely if (scr > 0)
193ca632f55SGrant Likely cdm = min(scr, 0xff);
194ca632f55SGrant Likely
195ca632f55SGrant Likely dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
196ca632f55SGrant Likely
197ca632f55SGrant Likely if (in_8(&hw->regs->cdm) != cdm)
198ca632f55SGrant Likely out_8(&hw->regs->cdm, cdm);
199ca632f55SGrant Likely
200c15f6ed3SNicolas Boichat mutex_lock(&hw->bitbang.lock);
201ca632f55SGrant Likely if (!hw->bitbang.busy) {
202ca632f55SGrant Likely hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
203ca632f55SGrant Likely /* Need to ndelay here? */
204ca632f55SGrant Likely }
205c15f6ed3SNicolas Boichat mutex_unlock(&hw->bitbang.lock);
206ca632f55SGrant Likely
207ca632f55SGrant Likely return 0;
208ca632f55SGrant Likely }
209ca632f55SGrant Likely
spi_ppc4xx_setup(struct spi_device * spi)210ca632f55SGrant Likely static int spi_ppc4xx_setup(struct spi_device *spi)
211ca632f55SGrant Likely {
212ca632f55SGrant Likely struct spi_ppc4xx_cs *cs = spi->controller_state;
213ca632f55SGrant Likely
214ca632f55SGrant Likely if (!spi->max_speed_hz) {
215ca632f55SGrant Likely dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
216ca632f55SGrant Likely return -EINVAL;
217ca632f55SGrant Likely }
218ca632f55SGrant Likely
219ca632f55SGrant Likely if (cs == NULL) {
22007c74f84SZhiqi Song cs = kzalloc(sizeof(*cs), GFP_KERNEL);
221ca632f55SGrant Likely if (!cs)
222ca632f55SGrant Likely return -ENOMEM;
223ca632f55SGrant Likely spi->controller_state = cs;
224ca632f55SGrant Likely }
225ca632f55SGrant Likely
226ca632f55SGrant Likely /*
227ca632f55SGrant Likely * We set all bits of the SPI0_MODE register, so,
228ca632f55SGrant Likely * no need to read-modify-write
229ca632f55SGrant Likely */
230ca632f55SGrant Likely cs->mode = SPI_PPC4XX_MODE_SPE;
231ca632f55SGrant Likely
2324ccf0557SAndy Shevchenko switch (spi->mode & SPI_MODE_X_MASK) {
233ca632f55SGrant Likely case SPI_MODE_0:
234ca632f55SGrant Likely cs->mode |= SPI_CLK_MODE0;
235ca632f55SGrant Likely break;
236ca632f55SGrant Likely case SPI_MODE_1:
237ca632f55SGrant Likely cs->mode |= SPI_CLK_MODE1;
238ca632f55SGrant Likely break;
239ca632f55SGrant Likely case SPI_MODE_2:
240ca632f55SGrant Likely cs->mode |= SPI_CLK_MODE2;
241ca632f55SGrant Likely break;
242ca632f55SGrant Likely case SPI_MODE_3:
243ca632f55SGrant Likely cs->mode |= SPI_CLK_MODE3;
244ca632f55SGrant Likely break;
245ca632f55SGrant Likely }
246ca632f55SGrant Likely
247ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST)
248ca632f55SGrant Likely cs->mode |= SPI_PPC4XX_MODE_RD;
249ca632f55SGrant Likely
250ca632f55SGrant Likely return 0;
251ca632f55SGrant Likely }
252ca632f55SGrant Likely
spi_ppc4xx_int(int irq,void * dev_id)253ca632f55SGrant Likely static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
254ca632f55SGrant Likely {
255ca632f55SGrant Likely struct ppc4xx_spi *hw;
256ca632f55SGrant Likely u8 status;
257ca632f55SGrant Likely u8 data;
258ca632f55SGrant Likely unsigned int count;
259ca632f55SGrant Likely
260ca632f55SGrant Likely hw = (struct ppc4xx_spi *)dev_id;
261ca632f55SGrant Likely
262ca632f55SGrant Likely status = in_8(&hw->regs->sr);
263ca632f55SGrant Likely if (!status)
264ca632f55SGrant Likely return IRQ_NONE;
265ca632f55SGrant Likely
266ca632f55SGrant Likely /*
267ca632f55SGrant Likely * BSY de-asserts one cycle after the transfer is complete. The
268ca632f55SGrant Likely * interrupt is asserted after the transfer is complete. The exact
269ca632f55SGrant Likely * relationship is not documented, hence this code.
270ca632f55SGrant Likely */
271ca632f55SGrant Likely
272ca632f55SGrant Likely if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
273ca632f55SGrant Likely u8 lstatus;
274ca632f55SGrant Likely int cnt = 0;
275ca632f55SGrant Likely
276ca632f55SGrant Likely dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
277ca632f55SGrant Likely do {
278ca632f55SGrant Likely ndelay(10);
279ca632f55SGrant Likely lstatus = in_8(&hw->regs->sr);
280ca632f55SGrant Likely } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
281ca632f55SGrant Likely
282ca632f55SGrant Likely if (cnt >= 100) {
283ca632f55SGrant Likely dev_err(hw->dev, "busywait: too many loops!\n");
284ca632f55SGrant Likely complete(&hw->done);
285ca632f55SGrant Likely return IRQ_HANDLED;
286ca632f55SGrant Likely } else {
287ca632f55SGrant Likely /* status is always 1 (RBR) here */
288ca632f55SGrant Likely status = in_8(&hw->regs->sr);
289ca632f55SGrant Likely dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
290ca632f55SGrant Likely }
291ca632f55SGrant Likely }
292ca632f55SGrant Likely
293ca632f55SGrant Likely count = hw->count;
294ca632f55SGrant Likely hw->count++;
295ca632f55SGrant Likely
296ca632f55SGrant Likely /* RBR triggered this interrupt. Therefore, data must be ready. */
297ca632f55SGrant Likely data = in_8(&hw->regs->rxd);
298ca632f55SGrant Likely if (hw->rx)
299ca632f55SGrant Likely hw->rx[count] = data;
300ca632f55SGrant Likely
301ca632f55SGrant Likely count++;
302ca632f55SGrant Likely
303ca632f55SGrant Likely if (count < hw->len) {
304ca632f55SGrant Likely data = hw->tx ? hw->tx[count] : 0;
305ca632f55SGrant Likely out_8(&hw->regs->txd, data);
306ca632f55SGrant Likely out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
307ca632f55SGrant Likely } else {
308ca632f55SGrant Likely complete(&hw->done);
309ca632f55SGrant Likely }
310ca632f55SGrant Likely
311ca632f55SGrant Likely return IRQ_HANDLED;
312ca632f55SGrant Likely }
313ca632f55SGrant Likely
spi_ppc4xx_cleanup(struct spi_device * spi)314ca632f55SGrant Likely static void spi_ppc4xx_cleanup(struct spi_device *spi)
315ca632f55SGrant Likely {
316ca632f55SGrant Likely kfree(spi->controller_state);
317ca632f55SGrant Likely }
318ca632f55SGrant Likely
spi_ppc4xx_enable(struct ppc4xx_spi * hw)319ca632f55SGrant Likely static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
320ca632f55SGrant Likely {
321ca632f55SGrant Likely /*
322ca632f55SGrant Likely * On all 4xx PPC's the SPI bus is shared/multiplexed with
323db56d030SJay Fang * the 2nd I2C bus. We need to enable the SPI bus before
324ca632f55SGrant Likely * using it.
325ca632f55SGrant Likely */
326ca632f55SGrant Likely
327ca632f55SGrant Likely /* need to clear bit 14 to enable SPC */
328ca632f55SGrant Likely dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
329ca632f55SGrant Likely }
330ca632f55SGrant Likely
331ca632f55SGrant Likely /*
332ca632f55SGrant Likely * platform_device layer stuff...
333ca632f55SGrant Likely */
spi_ppc4xx_of_probe(struct platform_device * op)3342deff8d6SGrant Likely static int spi_ppc4xx_of_probe(struct platform_device *op)
335ca632f55SGrant Likely {
336ca632f55SGrant Likely struct ppc4xx_spi *hw;
33771345830SYang Yingliang struct spi_controller *host;
338ca632f55SGrant Likely struct spi_bitbang *bbp;
339ca632f55SGrant Likely struct resource resource;
340ca632f55SGrant Likely struct device_node *np = op->dev.of_node;
341ca632f55SGrant Likely struct device *dev = &op->dev;
342ca632f55SGrant Likely struct device_node *opbnp;
343ca632f55SGrant Likely int ret;
344ca632f55SGrant Likely const unsigned int *clk;
345ca632f55SGrant Likely
34671345830SYang Yingliang host = spi_alloc_host(dev, sizeof(*hw));
34771345830SYang Yingliang if (host == NULL)
348ca632f55SGrant Likely return -ENOMEM;
34971345830SYang Yingliang host->dev.of_node = np;
35071345830SYang Yingliang platform_set_drvdata(op, host);
35171345830SYang Yingliang hw = spi_controller_get_devdata(host);
35271345830SYang Yingliang hw->host = host;
353ca632f55SGrant Likely hw->dev = dev;
354ca632f55SGrant Likely
355ca632f55SGrant Likely init_completion(&hw->done);
356ca632f55SGrant Likely
357ca632f55SGrant Likely /* Setup the state for the bitbang driver */
358ca632f55SGrant Likely bbp = &hw->bitbang;
35971345830SYang Yingliang bbp->master = hw->host;
360ca632f55SGrant Likely bbp->setup_transfer = spi_ppc4xx_setupxfer;
361ca632f55SGrant Likely bbp->txrx_bufs = spi_ppc4xx_txrx;
362ca632f55SGrant Likely bbp->use_dma = 0;
363ca632f55SGrant Likely bbp->master->setup = spi_ppc4xx_setup;
364ca632f55SGrant Likely bbp->master->cleanup = spi_ppc4xx_cleanup;
36524778be2SStephen Warren bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
36647267732SLinus Walleij bbp->master->use_gpio_descriptors = true;
36747267732SLinus Walleij /*
36847267732SLinus Walleij * The SPI core will count the number of GPIO descriptors to figure
36947267732SLinus Walleij * out the number of chip selects available on the platform.
37047267732SLinus Walleij */
37147267732SLinus Walleij bbp->master->num_chipselect = 0;
372ca632f55SGrant Likely
373ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */
374ca632f55SGrant Likely bbp->master->mode_bits =
375ca632f55SGrant Likely SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
376ca632f55SGrant Likely
377ca632f55SGrant Likely /* Get the clock for the OPB */
378ca632f55SGrant Likely opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
379ca632f55SGrant Likely if (opbnp == NULL) {
380ca632f55SGrant Likely dev_err(dev, "OPB: cannot find node\n");
381ca632f55SGrant Likely ret = -ENODEV;
38271345830SYang Yingliang goto free_host;
383ca632f55SGrant Likely }
384ca632f55SGrant Likely /* Get the clock (Hz) for the OPB */
385ca632f55SGrant Likely clk = of_get_property(opbnp, "clock-frequency", NULL);
386ca632f55SGrant Likely if (clk == NULL) {
387ca632f55SGrant Likely dev_err(dev, "OPB: no clock-frequency property set\n");
388ca632f55SGrant Likely of_node_put(opbnp);
389ca632f55SGrant Likely ret = -ENODEV;
39071345830SYang Yingliang goto free_host;
391ca632f55SGrant Likely }
392ca632f55SGrant Likely hw->opb_freq = *clk;
393ca632f55SGrant Likely hw->opb_freq >>= 2;
394ca632f55SGrant Likely of_node_put(opbnp);
395ca632f55SGrant Likely
396ca632f55SGrant Likely ret = of_address_to_resource(np, 0, &resource);
397ca632f55SGrant Likely if (ret) {
398ca632f55SGrant Likely dev_err(dev, "error while parsing device node resource\n");
39971345830SYang Yingliang goto free_host;
400ca632f55SGrant Likely }
401ca632f55SGrant Likely hw->mapbase = resource.start;
4028e2943c0SJoe Perches hw->mapsize = resource_size(&resource);
403ca632f55SGrant Likely
404ca632f55SGrant Likely /* Sanity check */
405ca632f55SGrant Likely if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
406ca632f55SGrant Likely dev_err(dev, "too small to map registers\n");
407ca632f55SGrant Likely ret = -EINVAL;
40871345830SYang Yingliang goto free_host;
409ca632f55SGrant Likely }
410ca632f55SGrant Likely
411ca632f55SGrant Likely /* Request IRQ */
412*3bf127bcSAndy Shevchenko ret = platform_get_irq(op, 0);
413*3bf127bcSAndy Shevchenko if (ret < 0)
4141b08f7b5SMa Ke goto free_host;
415*3bf127bcSAndy Shevchenko hw->irqnum = ret;
4161b08f7b5SMa Ke
417ca632f55SGrant Likely ret = request_irq(hw->irqnum, spi_ppc4xx_int,
41838ada214SYong Zhang 0, "spi_ppc4xx_of", (void *)hw);
419ca632f55SGrant Likely if (ret) {
420ca632f55SGrant Likely dev_err(dev, "unable to allocate interrupt\n");
42171345830SYang Yingliang goto free_host;
422ca632f55SGrant Likely }
423ca632f55SGrant Likely
424ca632f55SGrant Likely if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
425ca632f55SGrant Likely dev_err(dev, "resource unavailable\n");
426ca632f55SGrant Likely ret = -EBUSY;
427ca632f55SGrant Likely goto request_mem_error;
428ca632f55SGrant Likely }
429ca632f55SGrant Likely
430ca632f55SGrant Likely hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
431ca632f55SGrant Likely
432ca632f55SGrant Likely if (!hw->regs) {
433ca632f55SGrant Likely dev_err(dev, "unable to memory map registers\n");
434ca632f55SGrant Likely ret = -ENXIO;
435ca632f55SGrant Likely goto map_io_error;
436ca632f55SGrant Likely }
437ca632f55SGrant Likely
438ca632f55SGrant Likely spi_ppc4xx_enable(hw);
439ca632f55SGrant Likely
440ca632f55SGrant Likely /* Finally register our spi controller */
441ca632f55SGrant Likely dev->dma_mask = 0;
442ca632f55SGrant Likely ret = spi_bitbang_start(bbp);
443ca632f55SGrant Likely if (ret) {
44471345830SYang Yingliang dev_err(dev, "failed to register SPI host\n");
445ca632f55SGrant Likely goto unmap_regs;
446ca632f55SGrant Likely }
447ca632f55SGrant Likely
448ca632f55SGrant Likely dev_info(dev, "driver initialized\n");
449ca632f55SGrant Likely
450ca632f55SGrant Likely return 0;
451ca632f55SGrant Likely
452ca632f55SGrant Likely unmap_regs:
453ca632f55SGrant Likely iounmap(hw->regs);
454ca632f55SGrant Likely map_io_error:
455ca632f55SGrant Likely release_mem_region(hw->mapbase, hw->mapsize);
456ca632f55SGrant Likely request_mem_error:
457ca632f55SGrant Likely free_irq(hw->irqnum, hw);
45871345830SYang Yingliang free_host:
45971345830SYang Yingliang spi_controller_put(host);
460ca632f55SGrant Likely
461ca632f55SGrant Likely dev_err(dev, "initialization failed\n");
462ca632f55SGrant Likely return ret;
463ca632f55SGrant Likely }
464ca632f55SGrant Likely
spi_ppc4xx_of_remove(struct platform_device * op)465224d9437SUwe Kleine-König static void spi_ppc4xx_of_remove(struct platform_device *op)
466ca632f55SGrant Likely {
46771345830SYang Yingliang struct spi_controller *host = platform_get_drvdata(op);
46871345830SYang Yingliang struct ppc4xx_spi *hw = spi_controller_get_devdata(host);
469ca632f55SGrant Likely
470ca632f55SGrant Likely spi_bitbang_stop(&hw->bitbang);
471ca632f55SGrant Likely release_mem_region(hw->mapbase, hw->mapsize);
472ca632f55SGrant Likely free_irq(hw->irqnum, hw);
473ca632f55SGrant Likely iounmap(hw->regs);
47471345830SYang Yingliang spi_controller_put(host);
475ca632f55SGrant Likely }
476ca632f55SGrant Likely
477ca632f55SGrant Likely static const struct of_device_id spi_ppc4xx_of_match[] = {
478ca632f55SGrant Likely { .compatible = "ibm,ppc4xx-spi", },
479ca632f55SGrant Likely {},
480ca632f55SGrant Likely };
481ca632f55SGrant Likely
482ca632f55SGrant Likely MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
483ca632f55SGrant Likely
484ca632f55SGrant Likely static struct platform_driver spi_ppc4xx_of_driver = {
485ca632f55SGrant Likely .probe = spi_ppc4xx_of_probe,
486224d9437SUwe Kleine-König .remove_new = spi_ppc4xx_of_remove,
487ca632f55SGrant Likely .driver = {
488ca632f55SGrant Likely .name = DRIVER_NAME,
489ca632f55SGrant Likely .of_match_table = spi_ppc4xx_of_match,
490ca632f55SGrant Likely },
491ca632f55SGrant Likely };
492940ab889SGrant Likely module_platform_driver(spi_ppc4xx_of_driver);
493ca632f55SGrant Likely
494ca632f55SGrant Likely MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
495ca632f55SGrant Likely MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
496ca632f55SGrant Likely MODULE_LICENSE("GPL");
497