1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2008-2009 ST-Ericsson AB 5ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6ca632f55SGrant Likely * 7ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * Initial version inspired by: 10ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11ca632f55SGrant Likely * Initial adoption to PL022 by: 12ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 15ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 16ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 17ca632f55SGrant Likely * (at your option) any later version. 18ca632f55SGrant Likely * 19ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 20ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 21ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22ca632f55SGrant Likely * GNU General Public License for more details. 23ca632f55SGrant Likely */ 24ca632f55SGrant Likely 25ca632f55SGrant Likely #include <linux/init.h> 26ca632f55SGrant Likely #include <linux/module.h> 27ca632f55SGrant Likely #include <linux/device.h> 28ca632f55SGrant Likely #include <linux/ioport.h> 29ca632f55SGrant Likely #include <linux/errno.h> 30ca632f55SGrant Likely #include <linux/interrupt.h> 31ca632f55SGrant Likely #include <linux/spi/spi.h> 32ca632f55SGrant Likely #include <linux/delay.h> 33ca632f55SGrant Likely #include <linux/clk.h> 34ca632f55SGrant Likely #include <linux/err.h> 35ca632f55SGrant Likely #include <linux/amba/bus.h> 36ca632f55SGrant Likely #include <linux/amba/pl022.h> 37ca632f55SGrant Likely #include <linux/io.h> 38ca632f55SGrant Likely #include <linux/slab.h> 39ca632f55SGrant Likely #include <linux/dmaengine.h> 40ca632f55SGrant Likely #include <linux/dma-mapping.h> 41ca632f55SGrant Likely #include <linux/scatterlist.h> 42bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 43ca632f55SGrant Likely 44ca632f55SGrant Likely /* 45ca632f55SGrant Likely * This macro is used to define some register default values. 46ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 47ca632f55SGrant Likely * val shifted sb steps to the left. 48ca632f55SGrant Likely */ 49ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 50ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 51ca632f55SGrant Likely 52ca632f55SGrant Likely /* 53ca632f55SGrant Likely * This macro is also used to define some default values. 54ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 55ca632f55SGrant Likely * the result with mask. 56ca632f55SGrant Likely */ 57ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 58ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 59ca632f55SGrant Likely 60ca632f55SGrant Likely #define DRIVE_TX 0 61ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 62ca632f55SGrant Likely 63ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 64ca632f55SGrant Likely #define QUEUE_DMA 1 65ca632f55SGrant Likely 66ca632f55SGrant Likely #define RX_TRANSFER 1 67ca632f55SGrant Likely #define TX_TRANSFER 2 68ca632f55SGrant Likely 69ca632f55SGrant Likely /* 70ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 71ca632f55SGrant Likely */ 72ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 73ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 74ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 75ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 76ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 77ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 78ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 79ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 80ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 81ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 82ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 83ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 84ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 85ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 86ca632f55SGrant Likely 87ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 88ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 89ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 90ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 91ca632f55SGrant Likely 92ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 93ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 94ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 95ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 96ca632f55SGrant Likely 97ca632f55SGrant Likely /* 98ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 99ca632f55SGrant Likely */ 100ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 101ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 102ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 103ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 104ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 105ca632f55SGrant Likely 106ca632f55SGrant Likely /* 107ca632f55SGrant Likely * The ST version of this block moves som bits 108ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 109ca632f55SGrant Likely */ 110ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 111ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 112ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 113ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 114ca632f55SGrant Likely 115ca632f55SGrant Likely /* 116ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 117ca632f55SGrant Likely */ 118ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 119ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 120ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 121ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 122ca632f55SGrant Likely 123ca632f55SGrant Likely /* 124ca632f55SGrant Likely * The ST version of this block adds some bits 125ca632f55SGrant Likely * in SSP_CR1 126ca632f55SGrant Likely */ 127ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 128ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 129ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 130ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 131ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 132ca632f55SGrant Likely /* This one is only in the PL023 variant */ 133ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 134ca632f55SGrant Likely 135ca632f55SGrant Likely /* 136ca632f55SGrant Likely * SSP Status Register - SSP_SR 137ca632f55SGrant Likely */ 138ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 139ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 140ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 141ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 142ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 143ca632f55SGrant Likely 144ca632f55SGrant Likely /* 145ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 146ca632f55SGrant Likely */ 147ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 148ca632f55SGrant Likely 149ca632f55SGrant Likely /* 150ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 151ca632f55SGrant Likely */ 152ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 153ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 154ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 155ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 156ca632f55SGrant Likely 157ca632f55SGrant Likely /* 158ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 159ca632f55SGrant Likely */ 160ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 161ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 162ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 163ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 164ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 165ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 166ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 167ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 168ca632f55SGrant Likely 169ca632f55SGrant Likely /* 170ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 171ca632f55SGrant Likely */ 172ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 173ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 174ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 175ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 176ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 177ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 178ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 179ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 180ca632f55SGrant Likely 181ca632f55SGrant Likely /* 182ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 183ca632f55SGrant Likely */ 184ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 185ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 186ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 187ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 188ca632f55SGrant Likely 189ca632f55SGrant Likely /* 190ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 191ca632f55SGrant Likely */ 192ca632f55SGrant Likely /* Receive DMA Enable bit */ 193ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 194ca632f55SGrant Likely /* Transmit DMA Enable bit */ 195ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 196ca632f55SGrant Likely 197ca632f55SGrant Likely /* 198ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 199ca632f55SGrant Likely */ 200ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 201ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 202ca632f55SGrant Likely 203ca632f55SGrant Likely /* 204ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 205ca632f55SGrant Likely */ 206ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 207ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 208ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 209ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 210ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 211ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 212ca632f55SGrant Likely 213ca632f55SGrant Likely /* 214ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 215ca632f55SGrant Likely */ 216ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 217ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 218ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 219ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 220ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 221ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 222ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 223ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 224ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 225ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 226ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 227ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 228ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 229ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 230ca632f55SGrant Likely 231ca632f55SGrant Likely /* 232ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 233ca632f55SGrant Likely */ 234ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 235ca632f55SGrant Likely 236ca632f55SGrant Likely /* 237ca632f55SGrant Likely * Message State 238ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 239ca632f55SGrant Likely * hold a single state value, that's why all this 240ca632f55SGrant Likely * (void *) casting is done here. 241ca632f55SGrant Likely */ 242ca632f55SGrant Likely #define STATE_START ((void *) 0) 243ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 244ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 245ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 246ca632f55SGrant Likely 247ca632f55SGrant Likely /* 248ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 249ca632f55SGrant Likely */ 250ca632f55SGrant Likely #define SSP_DISABLED (0) 251ca632f55SGrant Likely #define SSP_ENABLED (1) 252ca632f55SGrant Likely 253ca632f55SGrant Likely /* 254ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 255ca632f55SGrant Likely */ 256ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 257ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 258ca632f55SGrant Likely 259ca632f55SGrant Likely /* 260ca632f55SGrant Likely * SSP Clock Defaults 261ca632f55SGrant Likely */ 262ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 263ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 264ca632f55SGrant Likely 265ca632f55SGrant Likely /* 266ca632f55SGrant Likely * SSP Clock Parameter ranges 267ca632f55SGrant Likely */ 268ca632f55SGrant Likely #define CPSDVR_MIN 0x02 269ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 270ca632f55SGrant Likely #define SCR_MIN 0x00 271ca632f55SGrant Likely #define SCR_MAX 0xFF 272ca632f55SGrant Likely 273ca632f55SGrant Likely /* 274ca632f55SGrant Likely * SSP Interrupt related Macros 275ca632f55SGrant Likely */ 276ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 277ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 278ca632f55SGrant Likely #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 279ca632f55SGrant Likely 280ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 281ca632f55SGrant Likely 282ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 283ca632f55SGrant Likely 284ca632f55SGrant Likely /* 285ca632f55SGrant Likely * The type of reading going on on this chip 286ca632f55SGrant Likely */ 287ca632f55SGrant Likely enum ssp_reading { 288ca632f55SGrant Likely READING_NULL, 289ca632f55SGrant Likely READING_U8, 290ca632f55SGrant Likely READING_U16, 291ca632f55SGrant Likely READING_U32 292ca632f55SGrant Likely }; 293ca632f55SGrant Likely 294ca632f55SGrant Likely /** 295ca632f55SGrant Likely * The type of writing going on on this chip 296ca632f55SGrant Likely */ 297ca632f55SGrant Likely enum ssp_writing { 298ca632f55SGrant Likely WRITING_NULL, 299ca632f55SGrant Likely WRITING_U8, 300ca632f55SGrant Likely WRITING_U16, 301ca632f55SGrant Likely WRITING_U32 302ca632f55SGrant Likely }; 303ca632f55SGrant Likely 304ca632f55SGrant Likely /** 305ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 306ca632f55SGrant Likely * for PL022 derivates 307ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 308ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 309ca632f55SGrant Likely * @unidir: supports unidirection transfers 310ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 311ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 312ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 313ca632f55SGrant Likely */ 314ca632f55SGrant Likely struct vendor_data { 315ca632f55SGrant Likely int fifodepth; 316ca632f55SGrant Likely int max_bpw; 317ca632f55SGrant Likely bool unidir; 318ca632f55SGrant Likely bool extended_cr; 319ca632f55SGrant Likely bool pl023; 320ca632f55SGrant Likely bool loopback; 321ca632f55SGrant Likely }; 322ca632f55SGrant Likely 323ca632f55SGrant Likely /** 324ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 325ca632f55SGrant Likely * @adev: AMBA device model hookup 326ca632f55SGrant Likely * @vendor: vendor data for the IP block 327ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 328ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 329ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 330ca632f55SGrant Likely * @master: SPI framework hookup 331ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 33214af60b6SChris Blair * @kworker: thread struct for message pump 33314af60b6SChris Blair * @kworker_task: pointer to task for message pump kworker thread 33414af60b6SChris Blair * @pump_messages: work struct for scheduling work to the message pump 335ca632f55SGrant Likely * @queue_lock: spinlock to syncronise access to message queue 336ca632f55SGrant Likely * @queue: message queue 33714af60b6SChris Blair * @busy: message pump is busy 33814af60b6SChris Blair * @running: message pump is running 339ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 340ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 341ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 342ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 3438b8d7191SVirupax Sadashivpetimath * @next_msg_cs_active: the next message in the queue has been examined 3448b8d7191SVirupax Sadashivpetimath * and it was found that it uses the same chip select as the previous 3458b8d7191SVirupax Sadashivpetimath * message, so we left it active after the previous transfer, and it's 3468b8d7191SVirupax Sadashivpetimath * active already. 347ca632f55SGrant Likely * @tx: current position in TX buffer to be read 348ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 349ca632f55SGrant Likely * @rx: current position in RX buffer to be written 350ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 351ca632f55SGrant Likely * @read: the type of read currently going on 352ca632f55SGrant Likely * @write: the type of write currently going on 353ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 354ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 355ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 356ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 357ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 358ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 359ca632f55SGrant Likely */ 360ca632f55SGrant Likely struct pl022 { 361ca632f55SGrant Likely struct amba_device *adev; 362ca632f55SGrant Likely struct vendor_data *vendor; 363ca632f55SGrant Likely resource_size_t phybase; 364ca632f55SGrant Likely void __iomem *virtbase; 365ca632f55SGrant Likely struct clk *clk; 366ca632f55SGrant Likely struct spi_master *master; 367ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 368ffbbdd21SLinus Walleij /* Message per-transfer pump */ 369ca632f55SGrant Likely struct tasklet_struct pump_transfers; 370ca632f55SGrant Likely struct spi_message *cur_msg; 371ca632f55SGrant Likely struct spi_transfer *cur_transfer; 372ca632f55SGrant Likely struct chip_data *cur_chip; 3738b8d7191SVirupax Sadashivpetimath bool next_msg_cs_active; 374ca632f55SGrant Likely void *tx; 375ca632f55SGrant Likely void *tx_end; 376ca632f55SGrant Likely void *rx; 377ca632f55SGrant Likely void *rx_end; 378ca632f55SGrant Likely enum ssp_reading read; 379ca632f55SGrant Likely enum ssp_writing write; 380ca632f55SGrant Likely u32 exp_fifo_level; 381083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 382083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 383ca632f55SGrant Likely /* DMA settings */ 384ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 385ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 386ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 387ca632f55SGrant Likely struct sg_table sgt_rx; 388ca632f55SGrant Likely struct sg_table sgt_tx; 389ca632f55SGrant Likely char *dummypage; 390ffbbdd21SLinus Walleij bool dma_running; 391ca632f55SGrant Likely #endif 392ca632f55SGrant Likely }; 393ca632f55SGrant Likely 394ca632f55SGrant Likely /** 395ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 396ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 397ca632f55SGrant Likely * register is 32 bits wide rather than just 16 398ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 399ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 400ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 401ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 402ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 403ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 404ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 405ca632f55SGrant Likely * @cs_control: chip select callback provided by chip 406ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 407ca632f55SGrant Likely * 408ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 409ca632f55SGrant Likely * This would be set according to the current message that would be served 410ca632f55SGrant Likely */ 411ca632f55SGrant Likely struct chip_data { 412ca632f55SGrant Likely u32 cr0; 413ca632f55SGrant Likely u16 cr1; 414ca632f55SGrant Likely u16 dmacr; 415ca632f55SGrant Likely u16 cpsr; 416ca632f55SGrant Likely u8 n_bytes; 417ca632f55SGrant Likely bool enable_dma; 418ca632f55SGrant Likely enum ssp_reading read; 419ca632f55SGrant Likely enum ssp_writing write; 420ca632f55SGrant Likely void (*cs_control) (u32 command); 421ca632f55SGrant Likely int xfer_type; 422ca632f55SGrant Likely }; 423ca632f55SGrant Likely 424ca632f55SGrant Likely /** 425ca632f55SGrant Likely * null_cs_control - Dummy chip select function 426ca632f55SGrant Likely * @command: select/delect the chip 427ca632f55SGrant Likely * 428ca632f55SGrant Likely * If no chip select function is provided by client this is used as dummy 429ca632f55SGrant Likely * chip select 430ca632f55SGrant Likely */ 431ca632f55SGrant Likely static void null_cs_control(u32 command) 432ca632f55SGrant Likely { 433ca632f55SGrant Likely pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 434ca632f55SGrant Likely } 435ca632f55SGrant Likely 436ca632f55SGrant Likely /** 437ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 438ca632f55SGrant Likely * callback of this message. Assumes that caller already 439ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 440ca632f55SGrant Likely * @pl022: SSP driver private data structure 441ca632f55SGrant Likely */ 442ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 443ca632f55SGrant Likely { 444ca632f55SGrant Likely struct spi_transfer *last_transfer; 4458b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = false; 446ca632f55SGrant Likely 4478b8d7191SVirupax Sadashivpetimath last_transfer = list_entry(pl022->cur_msg->transfers.prev, 448ca632f55SGrant Likely struct spi_transfer, 449ca632f55SGrant Likely transfer_list); 450ca632f55SGrant Likely 451ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 452ca632f55SGrant Likely if (last_transfer->delay_usecs) 453ca632f55SGrant Likely /* 454ca632f55SGrant Likely * FIXME: This runs in interrupt context. 455ca632f55SGrant Likely * Is this really smart? 456ca632f55SGrant Likely */ 457ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 458ca632f55SGrant Likely 4598b8d7191SVirupax Sadashivpetimath if (!last_transfer->cs_change) { 460ca632f55SGrant Likely struct spi_message *next_msg; 461ca632f55SGrant Likely 4628b8d7191SVirupax Sadashivpetimath /* 4638b8d7191SVirupax Sadashivpetimath * cs_change was not set. We can keep the chip select 4648b8d7191SVirupax Sadashivpetimath * enabled if there is message in the queue and it is 4658b8d7191SVirupax Sadashivpetimath * for the same spi device. 466ca632f55SGrant Likely * 467ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 468ca632f55SGrant Likely * after calling msg->complete (below) the driver that 469ca632f55SGrant Likely * sent the current message could be unloaded, which 470ca632f55SGrant Likely * could invalidate the cs_control() callback... 471ca632f55SGrant Likely */ 472ca632f55SGrant Likely /* get a pointer to the next message, if any */ 473ffbbdd21SLinus Walleij next_msg = spi_get_next_queued_message(pl022->master); 474ca632f55SGrant Likely 4758b8d7191SVirupax Sadashivpetimath /* 4768b8d7191SVirupax Sadashivpetimath * see if the next and current messages point 4778b8d7191SVirupax Sadashivpetimath * to the same spi device. 478ca632f55SGrant Likely */ 4798b8d7191SVirupax Sadashivpetimath if (next_msg && next_msg->spi != pl022->cur_msg->spi) 480ca632f55SGrant Likely next_msg = NULL; 4818b8d7191SVirupax Sadashivpetimath if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 4828b8d7191SVirupax Sadashivpetimath pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 4838b8d7191SVirupax Sadashivpetimath else 4848b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = true; 485ffbbdd21SLinus Walleij 486ca632f55SGrant Likely } 4878b8d7191SVirupax Sadashivpetimath 4888b8d7191SVirupax Sadashivpetimath pl022->cur_msg = NULL; 4898b8d7191SVirupax Sadashivpetimath pl022->cur_transfer = NULL; 4908b8d7191SVirupax Sadashivpetimath pl022->cur_chip = NULL; 491ffbbdd21SLinus Walleij spi_finalize_current_message(pl022->master); 492ca632f55SGrant Likely } 493ca632f55SGrant Likely 494ca632f55SGrant Likely /** 495ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 496ca632f55SGrant Likely * @pl022: SSP driver private data structure 497ca632f55SGrant Likely */ 498ca632f55SGrant Likely static int flush(struct pl022 *pl022) 499ca632f55SGrant Likely { 500ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 501ca632f55SGrant Likely 502ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 503ca632f55SGrant Likely do { 504ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 505ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 506ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 507ca632f55SGrant Likely 508ca632f55SGrant Likely pl022->exp_fifo_level = 0; 509ca632f55SGrant Likely 510ca632f55SGrant Likely return limit; 511ca632f55SGrant Likely } 512ca632f55SGrant Likely 513ca632f55SGrant Likely /** 514ca632f55SGrant Likely * restore_state - Load configuration of current chip 515ca632f55SGrant Likely * @pl022: SSP driver private data structure 516ca632f55SGrant Likely */ 517ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 518ca632f55SGrant Likely { 519ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 520ca632f55SGrant Likely 521ca632f55SGrant Likely if (pl022->vendor->extended_cr) 522ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 523ca632f55SGrant Likely else 524ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 525ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 526ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 527ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 528ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 529ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 530ca632f55SGrant Likely } 531ca632f55SGrant Likely 532ca632f55SGrant Likely /* 533ca632f55SGrant Likely * Default SSP Register Values 534ca632f55SGrant Likely */ 535ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 536ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 537ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 538ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 539ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 540ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 541ca632f55SGrant Likely ) 542ca632f55SGrant Likely 543ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 544ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 545ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 546ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 547ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 548ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 549ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 550ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 551ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 552ca632f55SGrant Likely ) 553ca632f55SGrant Likely 554ca632f55SGrant Likely /* The PL023 version is slightly different again */ 555ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 556ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 557ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 558ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 559ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 560ca632f55SGrant Likely ) 561ca632f55SGrant Likely 562ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 563ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 564ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 565ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 566ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 567ca632f55SGrant Likely ) 568ca632f55SGrant Likely 569ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 570ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 571ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 572ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 573ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 574ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 575ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 576ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 577ca632f55SGrant Likely ) 578ca632f55SGrant Likely 579ca632f55SGrant Likely /* 580ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 581ca632f55SGrant Likely * support, and a new clock feedback delay setting. 582ca632f55SGrant Likely */ 583ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 584ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 585ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 586ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 587ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 588ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 589ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 590ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 591ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 592ca632f55SGrant Likely ) 593ca632f55SGrant Likely 594ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 595ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 596ca632f55SGrant Likely ) 597ca632f55SGrant Likely 598ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 599ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 600ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 601ca632f55SGrant Likely ) 602ca632f55SGrant Likely 603ca632f55SGrant Likely /** 604ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 605ca632f55SGrant Likely * @pl022: SSP driver private data structure 606ca632f55SGrant Likely */ 607ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 608ca632f55SGrant Likely { 609ca632f55SGrant Likely if (pl022->vendor->pl023) { 610ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 611ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 612ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 613ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 614ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 615ca632f55SGrant Likely } else { 616ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 617ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 618ca632f55SGrant Likely } 619ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 620ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 621ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 622ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 623ca632f55SGrant Likely } 624ca632f55SGrant Likely 625ca632f55SGrant Likely /** 626ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 627ca632f55SGrant Likely * set in pl022. 628ca632f55SGrant Likely */ 629ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 630ca632f55SGrant Likely { 631ca632f55SGrant Likely 632ca632f55SGrant Likely /* 633ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 634ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 635ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 636ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 637ca632f55SGrant Likely * 638ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 639ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 640ca632f55SGrant Likely * FIFO status flag indicates. 641ca632f55SGrant Likely */ 642ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 643ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 644ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 645ca632f55SGrant Likely 646ca632f55SGrant Likely /* Read as much as you can */ 647ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 648ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 649ca632f55SGrant Likely switch (pl022->read) { 650ca632f55SGrant Likely case READING_NULL: 651ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 652ca632f55SGrant Likely break; 653ca632f55SGrant Likely case READING_U8: 654ca632f55SGrant Likely *(u8 *) (pl022->rx) = 655ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 656ca632f55SGrant Likely break; 657ca632f55SGrant Likely case READING_U16: 658ca632f55SGrant Likely *(u16 *) (pl022->rx) = 659ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 660ca632f55SGrant Likely break; 661ca632f55SGrant Likely case READING_U32: 662ca632f55SGrant Likely *(u32 *) (pl022->rx) = 663ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 664ca632f55SGrant Likely break; 665ca632f55SGrant Likely } 666ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 667ca632f55SGrant Likely pl022->exp_fifo_level--; 668ca632f55SGrant Likely } 669ca632f55SGrant Likely /* 670ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 671ca632f55SGrant Likely */ 672ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 673ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 674ca632f55SGrant Likely switch (pl022->write) { 675ca632f55SGrant Likely case WRITING_NULL: 676ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 677ca632f55SGrant Likely break; 678ca632f55SGrant Likely case WRITING_U8: 679ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 680ca632f55SGrant Likely break; 681ca632f55SGrant Likely case WRITING_U16: 682ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 683ca632f55SGrant Likely break; 684ca632f55SGrant Likely case WRITING_U32: 685ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 686ca632f55SGrant Likely break; 687ca632f55SGrant Likely } 688ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 689ca632f55SGrant Likely pl022->exp_fifo_level++; 690ca632f55SGrant Likely /* 691ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 692ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 693ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 694ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 695ca632f55SGrant Likely */ 696ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 697ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 698ca632f55SGrant Likely switch (pl022->read) { 699ca632f55SGrant Likely case READING_NULL: 700ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 701ca632f55SGrant Likely break; 702ca632f55SGrant Likely case READING_U8: 703ca632f55SGrant Likely *(u8 *) (pl022->rx) = 704ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 705ca632f55SGrant Likely break; 706ca632f55SGrant Likely case READING_U16: 707ca632f55SGrant Likely *(u16 *) (pl022->rx) = 708ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 709ca632f55SGrant Likely break; 710ca632f55SGrant Likely case READING_U32: 711ca632f55SGrant Likely *(u32 *) (pl022->rx) = 712ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 713ca632f55SGrant Likely break; 714ca632f55SGrant Likely } 715ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 716ca632f55SGrant Likely pl022->exp_fifo_level--; 717ca632f55SGrant Likely } 718ca632f55SGrant Likely } 719ca632f55SGrant Likely /* 720ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 721ca632f55SGrant Likely * should be empty 722ca632f55SGrant Likely */ 723ca632f55SGrant Likely } 724ca632f55SGrant Likely 725ca632f55SGrant Likely /** 726ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 727ca632f55SGrant Likely * @pl022: SSP driver private data structure 728ca632f55SGrant Likely * 729ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 730ca632f55SGrant Likely * current spi message and returns with the state of current spi 731ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 732ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 733ca632f55SGrant Likely */ 734ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 735ca632f55SGrant Likely { 736ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 737ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 738ca632f55SGrant Likely 739ca632f55SGrant Likely /* Move to next transfer */ 740ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 741ca632f55SGrant Likely pl022->cur_transfer = 742ca632f55SGrant Likely list_entry(trans->transfer_list.next, 743ca632f55SGrant Likely struct spi_transfer, transfer_list); 744ca632f55SGrant Likely return STATE_RUNNING; 745ca632f55SGrant Likely } 746ca632f55SGrant Likely return STATE_DONE; 747ca632f55SGrant Likely } 748ca632f55SGrant Likely 749ca632f55SGrant Likely /* 750ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 751ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 752ca632f55SGrant Likely */ 753ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 754ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 755ca632f55SGrant Likely { 756ca632f55SGrant Likely /* Unmap and free the SG tables */ 757ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 758ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 759ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 760ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 761ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 762ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 763ca632f55SGrant Likely } 764ca632f55SGrant Likely 765ca632f55SGrant Likely static void dma_callback(void *data) 766ca632f55SGrant Likely { 767ca632f55SGrant Likely struct pl022 *pl022 = data; 768ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 769ca632f55SGrant Likely 770ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 771ca632f55SGrant Likely 772ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 773ca632f55SGrant Likely /* 774ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 775ca632f55SGrant Likely * good if you want to convince yourself that the loopback 776ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 777ca632f55SGrant Likely * DMA engine. 778ca632f55SGrant Likely */ 779ca632f55SGrant Likely { 780ca632f55SGrant Likely struct scatterlist *sg; 781ca632f55SGrant Likely unsigned int i; 782ca632f55SGrant Likely 783ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 784ca632f55SGrant Likely pl022->sgt_rx.sgl, 785ca632f55SGrant Likely pl022->sgt_rx.nents, 786ca632f55SGrant Likely DMA_FROM_DEVICE); 787ca632f55SGrant Likely 788ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 789ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 790ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 791ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 792ca632f55SGrant Likely 16, 793ca632f55SGrant Likely 1, 794ca632f55SGrant Likely sg_virt(sg), 795ca632f55SGrant Likely sg_dma_len(sg), 796ca632f55SGrant Likely 1); 797ca632f55SGrant Likely } 798ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 799ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 800ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 801ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 802ca632f55SGrant Likely 16, 803ca632f55SGrant Likely 1, 804ca632f55SGrant Likely sg_virt(sg), 805ca632f55SGrant Likely sg_dma_len(sg), 806ca632f55SGrant Likely 1); 807ca632f55SGrant Likely } 808ca632f55SGrant Likely } 809ca632f55SGrant Likely #endif 810ca632f55SGrant Likely 811ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 812ca632f55SGrant Likely 813ca632f55SGrant Likely /* Update total bytes transferred */ 814ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 815ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 816ca632f55SGrant Likely pl022->cur_chip-> 817ca632f55SGrant Likely cs_control(SSP_CHIP_DESELECT); 818ca632f55SGrant Likely 819ca632f55SGrant Likely /* Move to next transfer */ 820ca632f55SGrant Likely msg->state = next_transfer(pl022); 821ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 822ca632f55SGrant Likely } 823ca632f55SGrant Likely 824ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 825ca632f55SGrant Likely void *buffer, 826ca632f55SGrant Likely unsigned int length, 827ca632f55SGrant Likely struct sg_table *sgtab) 828ca632f55SGrant Likely { 829ca632f55SGrant Likely struct scatterlist *sg; 830ca632f55SGrant Likely int bytesleft = length; 831ca632f55SGrant Likely void *bufp = buffer; 832ca632f55SGrant Likely int mapbytes; 833ca632f55SGrant Likely int i; 834ca632f55SGrant Likely 835ca632f55SGrant Likely if (buffer) { 836ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 837ca632f55SGrant Likely /* 838ca632f55SGrant Likely * If there are less bytes left than what fits 839ca632f55SGrant Likely * in the current page (plus page alignment offset) 840ca632f55SGrant Likely * we just feed in this, else we stuff in as much 841ca632f55SGrant Likely * as we can. 842ca632f55SGrant Likely */ 843ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 844ca632f55SGrant Likely mapbytes = bytesleft; 845ca632f55SGrant Likely else 846ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 847ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 848ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 849ca632f55SGrant Likely bufp += mapbytes; 850ca632f55SGrant Likely bytesleft -= mapbytes; 851ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 852ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 853ca632f55SGrant Likely bufp, mapbytes, bytesleft); 854ca632f55SGrant Likely } 855ca632f55SGrant Likely } else { 856ca632f55SGrant Likely /* Map the dummy buffer on every page */ 857ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 858ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 859ca632f55SGrant Likely mapbytes = bytesleft; 860ca632f55SGrant Likely else 861ca632f55SGrant Likely mapbytes = PAGE_SIZE; 862ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 863ca632f55SGrant Likely mapbytes, 0); 864ca632f55SGrant Likely bytesleft -= mapbytes; 865ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 866ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 867ca632f55SGrant Likely mapbytes, bytesleft); 868ca632f55SGrant Likely 869ca632f55SGrant Likely } 870ca632f55SGrant Likely } 871ca632f55SGrant Likely BUG_ON(bytesleft); 872ca632f55SGrant Likely } 873ca632f55SGrant Likely 874ca632f55SGrant Likely /** 875ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 876ca632f55SGrant Likely * @pl022: SSP driver's private data structure 877ca632f55SGrant Likely */ 878ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 879ca632f55SGrant Likely { 880ca632f55SGrant Likely struct dma_slave_config rx_conf = { 881ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 882a485df4bSVinod Koul .direction = DMA_DEV_TO_MEM, 883258aea76SViresh Kumar .device_fc = false, 884ca632f55SGrant Likely }; 885ca632f55SGrant Likely struct dma_slave_config tx_conf = { 886ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 887a485df4bSVinod Koul .direction = DMA_MEM_TO_DEV, 888258aea76SViresh Kumar .device_fc = false, 889ca632f55SGrant Likely }; 890ca632f55SGrant Likely unsigned int pages; 891ca632f55SGrant Likely int ret; 892ca632f55SGrant Likely int rx_sglen, tx_sglen; 893ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 894ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 895ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 896ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 897ca632f55SGrant Likely 898ca632f55SGrant Likely /* Check that the channels are available */ 899ca632f55SGrant Likely if (!rxchan || !txchan) 900ca632f55SGrant Likely return -ENODEV; 901ca632f55SGrant Likely 902083be3f0SLinus Walleij /* 903083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 904083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 905083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 906083be3f0SLinus Walleij * calculation. 907083be3f0SLinus Walleij */ 908083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 909083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 910083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 911083be3f0SLinus Walleij break; 912083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 913083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 914083be3f0SLinus Walleij break; 915083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 916083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 917083be3f0SLinus Walleij break; 918083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 919083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 920083be3f0SLinus Walleij break; 921083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 922083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 923083be3f0SLinus Walleij break; 924083be3f0SLinus Walleij default: 925083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 926083be3f0SLinus Walleij break; 927083be3f0SLinus Walleij } 928083be3f0SLinus Walleij 929083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 930083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 931083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 932083be3f0SLinus Walleij break; 933083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 934083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 935083be3f0SLinus Walleij break; 936083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 937083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 938083be3f0SLinus Walleij break; 939083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 940083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 941083be3f0SLinus Walleij break; 942083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 943083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 944083be3f0SLinus Walleij break; 945083be3f0SLinus Walleij default: 946083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 947083be3f0SLinus Walleij break; 948083be3f0SLinus Walleij } 949083be3f0SLinus Walleij 950ca632f55SGrant Likely switch (pl022->read) { 951ca632f55SGrant Likely case READING_NULL: 952ca632f55SGrant Likely /* Use the same as for writing */ 953ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 954ca632f55SGrant Likely break; 955ca632f55SGrant Likely case READING_U8: 956ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 957ca632f55SGrant Likely break; 958ca632f55SGrant Likely case READING_U16: 959ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 960ca632f55SGrant Likely break; 961ca632f55SGrant Likely case READING_U32: 962ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 963ca632f55SGrant Likely break; 964ca632f55SGrant Likely } 965ca632f55SGrant Likely 966ca632f55SGrant Likely switch (pl022->write) { 967ca632f55SGrant Likely case WRITING_NULL: 968ca632f55SGrant Likely /* Use the same as for reading */ 969ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 970ca632f55SGrant Likely break; 971ca632f55SGrant Likely case WRITING_U8: 972ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 973ca632f55SGrant Likely break; 974ca632f55SGrant Likely case WRITING_U16: 975ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 976ca632f55SGrant Likely break; 977ca632f55SGrant Likely case WRITING_U32: 978ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 979ca632f55SGrant Likely break; 980ca632f55SGrant Likely } 981ca632f55SGrant Likely 982ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 983ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 984ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 985ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 986ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 987ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 988ca632f55SGrant Likely 989ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 990ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 991ca632f55SGrant Likely 992ca632f55SGrant Likely /* Create sglists for the transfers */ 993b181565eSViresh Kumar pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 994ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 995ca632f55SGrant Likely 996538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 997ca632f55SGrant Likely if (ret) 998ca632f55SGrant Likely goto err_alloc_rx_sg; 999ca632f55SGrant Likely 1000538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1001ca632f55SGrant Likely if (ret) 1002ca632f55SGrant Likely goto err_alloc_tx_sg; 1003ca632f55SGrant Likely 1004ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1005ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1006ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1007ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1008ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1009ca632f55SGrant Likely 1010ca632f55SGrant Likely /* Map DMA buffers */ 1011ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1012ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1013ca632f55SGrant Likely if (!rx_sglen) 1014ca632f55SGrant Likely goto err_rx_sgmap; 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1017ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1018ca632f55SGrant Likely if (!tx_sglen) 1019ca632f55SGrant Likely goto err_tx_sgmap; 1020ca632f55SGrant Likely 1021ca632f55SGrant Likely /* Send both scatterlists */ 102216052827SAlexandre Bounine rxdesc = dmaengine_prep_slave_sg(rxchan, 1023ca632f55SGrant Likely pl022->sgt_rx.sgl, 1024ca632f55SGrant Likely rx_sglen, 1025a485df4bSVinod Koul DMA_DEV_TO_MEM, 1026ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1027ca632f55SGrant Likely if (!rxdesc) 1028ca632f55SGrant Likely goto err_rxdesc; 1029ca632f55SGrant Likely 103016052827SAlexandre Bounine txdesc = dmaengine_prep_slave_sg(txchan, 1031ca632f55SGrant Likely pl022->sgt_tx.sgl, 1032ca632f55SGrant Likely tx_sglen, 1033a485df4bSVinod Koul DMA_MEM_TO_DEV, 1034ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1035ca632f55SGrant Likely if (!txdesc) 1036ca632f55SGrant Likely goto err_txdesc; 1037ca632f55SGrant Likely 1038ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1039ca632f55SGrant Likely rxdesc->callback = dma_callback; 1040ca632f55SGrant Likely rxdesc->callback_param = pl022; 1041ca632f55SGrant Likely 1042ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1043ca632f55SGrant Likely dmaengine_submit(rxdesc); 1044ca632f55SGrant Likely dmaengine_submit(txdesc); 1045ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1046ca632f55SGrant Likely dma_async_issue_pending(txchan); 1047ffbbdd21SLinus Walleij pl022->dma_running = true; 1048ca632f55SGrant Likely 1049ca632f55SGrant Likely return 0; 1050ca632f55SGrant Likely 1051ca632f55SGrant Likely err_txdesc: 1052ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1053ca632f55SGrant Likely err_rxdesc: 1054ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1055ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1056ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1057ca632f55SGrant Likely err_tx_sgmap: 1058ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1059ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1060ca632f55SGrant Likely err_rx_sgmap: 1061ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1062ca632f55SGrant Likely err_alloc_tx_sg: 1063ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1064ca632f55SGrant Likely err_alloc_rx_sg: 1065ca632f55SGrant Likely return -ENOMEM; 1066ca632f55SGrant Likely } 1067ca632f55SGrant Likely 1068a5ab6291SRussell King static int __devinit pl022_dma_probe(struct pl022 *pl022) 1069ca632f55SGrant Likely { 1070ca632f55SGrant Likely dma_cap_mask_t mask; 1071ca632f55SGrant Likely 1072ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1073ca632f55SGrant Likely dma_cap_zero(mask); 1074ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1075ca632f55SGrant Likely /* 1076ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1077ca632f55SGrant Likely * of them. 1078ca632f55SGrant Likely */ 1079ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1080ca632f55SGrant Likely pl022->master_info->dma_filter, 1081ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1082ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1083ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1084ca632f55SGrant Likely goto err_no_rxchan; 1085ca632f55SGrant Likely } 1086ca632f55SGrant Likely 1087ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1088ca632f55SGrant Likely pl022->master_info->dma_filter, 1089ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1090ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1091ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1092ca632f55SGrant Likely goto err_no_txchan; 1093ca632f55SGrant Likely } 1094ca632f55SGrant Likely 1095ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1096ca632f55SGrant Likely if (!pl022->dummypage) { 1097ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1098ca632f55SGrant Likely goto err_no_dummypage; 1099ca632f55SGrant Likely } 1100ca632f55SGrant Likely 1101ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1102ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1103ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1104ca632f55SGrant Likely 1105ca632f55SGrant Likely return 0; 1106ca632f55SGrant Likely 1107ca632f55SGrant Likely err_no_dummypage: 1108ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1109ca632f55SGrant Likely err_no_txchan: 1110ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1111ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1112ca632f55SGrant Likely err_no_rxchan: 1113ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1114ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1115ca632f55SGrant Likely return -ENODEV; 1116ca632f55SGrant Likely } 1117ca632f55SGrant Likely 1118ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1119ca632f55SGrant Likely { 1120ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1121ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1122ca632f55SGrant Likely 1123ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1124ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1125ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1126ffbbdd21SLinus Walleij pl022->dma_running = false; 1127ca632f55SGrant Likely } 1128ca632f55SGrant Likely 1129ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1130ca632f55SGrant Likely { 1131ffbbdd21SLinus Walleij if (pl022->dma_running) 1132ca632f55SGrant Likely terminate_dma(pl022); 1133ca632f55SGrant Likely if (pl022->dma_tx_channel) 1134ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1135ca632f55SGrant Likely if (pl022->dma_rx_channel) 1136ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1137ca632f55SGrant Likely kfree(pl022->dummypage); 1138ca632f55SGrant Likely } 1139ca632f55SGrant Likely 1140ca632f55SGrant Likely #else 1141ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1142ca632f55SGrant Likely { 1143ca632f55SGrant Likely return -ENODEV; 1144ca632f55SGrant Likely } 1145ca632f55SGrant Likely 1146ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1147ca632f55SGrant Likely { 1148ca632f55SGrant Likely return 0; 1149ca632f55SGrant Likely } 1150ca632f55SGrant Likely 1151ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1152ca632f55SGrant Likely { 1153ca632f55SGrant Likely } 1154ca632f55SGrant Likely #endif 1155ca632f55SGrant Likely 1156ca632f55SGrant Likely /** 1157ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1158ca632f55SGrant Likely * 1159ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1160ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1161ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1162ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1163ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1164ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1165ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1166ca632f55SGrant Likely */ 1167ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1168ca632f55SGrant Likely { 1169ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1170ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1171ca632f55SGrant Likely u16 irq_status = 0; 1172ca632f55SGrant Likely u16 flag = 0; 1173ca632f55SGrant Likely 1174ca632f55SGrant Likely if (unlikely(!msg)) { 1175ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1176ca632f55SGrant Likely "bad message state in interrupt handler"); 1177ca632f55SGrant Likely /* Never fail */ 1178ca632f55SGrant Likely return IRQ_HANDLED; 1179ca632f55SGrant Likely } 1180ca632f55SGrant Likely 1181ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1182ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1183ca632f55SGrant Likely 1184ca632f55SGrant Likely if (unlikely(!irq_status)) 1185ca632f55SGrant Likely return IRQ_NONE; 1186ca632f55SGrant Likely 1187ca632f55SGrant Likely /* 1188ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1189ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1190ca632f55SGrant Likely * trusted. 1191ca632f55SGrant Likely */ 1192ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1193ca632f55SGrant Likely /* 1194ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1195ca632f55SGrant Likely * corrupted 1196ca632f55SGrant Likely */ 1197ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1198ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1199ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1200ca632f55SGrant Likely "RXFIFO is full\n"); 1201ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1202ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1203ca632f55SGrant Likely "TXFIFO is full\n"); 1204ca632f55SGrant Likely 1205ca632f55SGrant Likely /* 1206ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1207ca632f55SGrant Likely * mark message with bad status so it can be 1208ca632f55SGrant Likely * retried. 1209ca632f55SGrant Likely */ 1210ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1211ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1212ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1213ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1214ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1215ca632f55SGrant Likely msg->state = STATE_ERROR; 1216ca632f55SGrant Likely 1217ca632f55SGrant Likely /* Schedule message queue handler */ 1218ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1219ca632f55SGrant Likely return IRQ_HANDLED; 1220ca632f55SGrant Likely } 1221ca632f55SGrant Likely 1222ca632f55SGrant Likely readwriter(pl022); 1223ca632f55SGrant Likely 1224ca632f55SGrant Likely if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1225ca632f55SGrant Likely flag = 1; 1226172289dfSChris Blair /* Disable Transmit interrupt, enable receive interrupt */ 1227172289dfSChris Blair writew((readw(SSP_IMSC(pl022->virtbase)) & 1228172289dfSChris Blair ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1229ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1230ca632f55SGrant Likely } 1231ca632f55SGrant Likely 1232ca632f55SGrant Likely /* 1233ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1234ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1235ca632f55SGrant Likely * At this point, all TX will always be finished. 1236ca632f55SGrant Likely */ 1237ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1238ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1239ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1240ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1241ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1242ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1243ca632f55SGrant Likely "bytes (did you request an odd " 1244ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1245ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1246ca632f55SGrant Likely } 1247ca632f55SGrant Likely /* Update total bytes transferred */ 1248ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1249ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1250ca632f55SGrant Likely pl022->cur_chip-> 1251ca632f55SGrant Likely cs_control(SSP_CHIP_DESELECT); 1252ca632f55SGrant Likely /* Move to next transfer */ 1253ca632f55SGrant Likely msg->state = next_transfer(pl022); 1254ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1255ca632f55SGrant Likely return IRQ_HANDLED; 1256ca632f55SGrant Likely } 1257ca632f55SGrant Likely 1258ca632f55SGrant Likely return IRQ_HANDLED; 1259ca632f55SGrant Likely } 1260ca632f55SGrant Likely 1261ca632f55SGrant Likely /** 1262ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1263ca632f55SGrant Likely * send out on the SPI bus. 1264ca632f55SGrant Likely */ 1265ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1266ca632f55SGrant Likely struct spi_transfer *transfer) 1267ca632f55SGrant Likely { 1268ca632f55SGrant Likely int residue; 1269ca632f55SGrant Likely 1270ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1271ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1272ca632f55SGrant Likely if (unlikely(residue != 0)) { 1273ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1274ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1275ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1276ca632f55SGrant Likely pl022->cur_transfer->len, 1277ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1278ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1279ca632f55SGrant Likely return -EIO; 1280ca632f55SGrant Likely } 1281ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1282ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1283ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1284ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1285ca632f55SGrant Likely pl022->write = 1286ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1287ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1288ca632f55SGrant Likely return 0; 1289ca632f55SGrant Likely } 1290ca632f55SGrant Likely 1291ca632f55SGrant Likely /** 1292ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1293ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1294ca632f55SGrant Likely * @data: SSP driver private data structure 1295ca632f55SGrant Likely * 1296ca632f55SGrant Likely */ 1297ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1298ca632f55SGrant Likely { 1299ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1300ca632f55SGrant Likely struct spi_message *message = NULL; 1301ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1302ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1303ca632f55SGrant Likely 1304ca632f55SGrant Likely /* Get current state information */ 1305ca632f55SGrant Likely message = pl022->cur_msg; 1306ca632f55SGrant Likely transfer = pl022->cur_transfer; 1307ca632f55SGrant Likely 1308ca632f55SGrant Likely /* Handle for abort */ 1309ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1310ca632f55SGrant Likely message->status = -EIO; 1311ca632f55SGrant Likely giveback(pl022); 1312ca632f55SGrant Likely return; 1313ca632f55SGrant Likely } 1314ca632f55SGrant Likely 1315ca632f55SGrant Likely /* Handle end of message */ 1316ca632f55SGrant Likely if (message->state == STATE_DONE) { 1317ca632f55SGrant Likely message->status = 0; 1318ca632f55SGrant Likely giveback(pl022); 1319ca632f55SGrant Likely return; 1320ca632f55SGrant Likely } 1321ca632f55SGrant Likely 1322ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1323ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1324ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1325ca632f55SGrant Likely struct spi_transfer, 1326ca632f55SGrant Likely transfer_list); 1327ca632f55SGrant Likely if (previous->delay_usecs) 1328ca632f55SGrant Likely /* 1329ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1330ca632f55SGrant Likely * Is this really smart? 1331ca632f55SGrant Likely */ 1332ca632f55SGrant Likely udelay(previous->delay_usecs); 1333ca632f55SGrant Likely 13348b8d7191SVirupax Sadashivpetimath /* Reselect chip select only if cs_change was requested */ 1335ca632f55SGrant Likely if (previous->cs_change) 1336ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1337ca632f55SGrant Likely } else { 1338ca632f55SGrant Likely /* STATE_START */ 1339ca632f55SGrant Likely message->state = STATE_RUNNING; 1340ca632f55SGrant Likely } 1341ca632f55SGrant Likely 1342ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1343ca632f55SGrant Likely message->state = STATE_ERROR; 1344ca632f55SGrant Likely message->status = -EIO; 1345ca632f55SGrant Likely giveback(pl022); 1346ca632f55SGrant Likely return; 1347ca632f55SGrant Likely } 1348ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1349ca632f55SGrant Likely flush(pl022); 1350ca632f55SGrant Likely 1351ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1352ca632f55SGrant Likely if (configure_dma(pl022)) { 1353ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1354ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1355ca632f55SGrant Likely goto err_config_dma; 1356ca632f55SGrant Likely } 1357ca632f55SGrant Likely return; 1358ca632f55SGrant Likely } 1359ca632f55SGrant Likely 1360ca632f55SGrant Likely err_config_dma: 1361172289dfSChris Blair /* enable all interrupts except RX */ 1362172289dfSChris Blair writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1363ca632f55SGrant Likely } 1364ca632f55SGrant Likely 1365ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1366ca632f55SGrant Likely { 1367172289dfSChris Blair /* 1368172289dfSChris Blair * Default is to enable all interrupts except RX - 1369172289dfSChris Blair * this will be enabled once TX is complete 1370172289dfSChris Blair */ 1371172289dfSChris Blair u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1372ca632f55SGrant Likely 13738b8d7191SVirupax Sadashivpetimath /* Enable target chip, if not already active */ 13748b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1375ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 13768b8d7191SVirupax Sadashivpetimath 1377ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1378ca632f55SGrant Likely /* Error path */ 1379ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1380ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1381ca632f55SGrant Likely giveback(pl022); 1382ca632f55SGrant Likely return; 1383ca632f55SGrant Likely } 1384ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1385ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1386ca632f55SGrant Likely /* Configure DMA transfer */ 1387ca632f55SGrant Likely if (configure_dma(pl022)) { 1388ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1389ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1390ca632f55SGrant Likely goto err_config_dma; 1391ca632f55SGrant Likely } 1392ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1393ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1394ca632f55SGrant Likely } 1395ca632f55SGrant Likely err_config_dma: 1396ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1397ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1398ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1399ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1400ca632f55SGrant Likely } 1401ca632f55SGrant Likely 1402ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1403ca632f55SGrant Likely { 1404ca632f55SGrant Likely struct spi_message *message = NULL; 1405ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1406ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1407ca632f55SGrant Likely struct chip_data *chip; 1408ca632f55SGrant Likely unsigned long time, timeout; 1409ca632f55SGrant Likely 1410ca632f55SGrant Likely chip = pl022->cur_chip; 1411ca632f55SGrant Likely message = pl022->cur_msg; 1412ca632f55SGrant Likely 1413ca632f55SGrant Likely while (message->state != STATE_DONE) { 1414ca632f55SGrant Likely /* Handle for abort */ 1415ca632f55SGrant Likely if (message->state == STATE_ERROR) 1416ca632f55SGrant Likely break; 1417ca632f55SGrant Likely transfer = pl022->cur_transfer; 1418ca632f55SGrant Likely 1419ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1420ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1421ca632f55SGrant Likely previous = 1422ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1423ca632f55SGrant Likely struct spi_transfer, transfer_list); 1424ca632f55SGrant Likely if (previous->delay_usecs) 1425ca632f55SGrant Likely udelay(previous->delay_usecs); 1426ca632f55SGrant Likely if (previous->cs_change) 1427ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1428ca632f55SGrant Likely } else { 1429ca632f55SGrant Likely /* STATE_START */ 1430ca632f55SGrant Likely message->state = STATE_RUNNING; 14318b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1432ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1433ca632f55SGrant Likely } 1434ca632f55SGrant Likely 1435ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1436ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1437ca632f55SGrant Likely /* Error path */ 1438ca632f55SGrant Likely message->state = STATE_ERROR; 1439ca632f55SGrant Likely break; 1440ca632f55SGrant Likely } 1441ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1442ca632f55SGrant Likely flush(pl022); 1443ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1444ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1445ca632f55SGrant Likely 1446ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1447ca632f55SGrant Likely 1448ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1449ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1450ca632f55SGrant Likely time = jiffies; 1451ca632f55SGrant Likely readwriter(pl022); 1452ca632f55SGrant Likely if (time_after(time, timeout)) { 1453ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1454ca632f55SGrant Likely "%s: timeout!\n", __func__); 1455ca632f55SGrant Likely message->state = STATE_ERROR; 1456ca632f55SGrant Likely goto out; 1457ca632f55SGrant Likely } 1458ca632f55SGrant Likely cpu_relax(); 1459ca632f55SGrant Likely } 1460ca632f55SGrant Likely 1461ca632f55SGrant Likely /* Update total byte transferred */ 1462ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1463ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1464ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1465ca632f55SGrant Likely /* Move to next transfer */ 1466ca632f55SGrant Likely message->state = next_transfer(pl022); 1467ca632f55SGrant Likely } 1468ca632f55SGrant Likely out: 1469ca632f55SGrant Likely /* Handle end of message */ 1470ca632f55SGrant Likely if (message->state == STATE_DONE) 1471ca632f55SGrant Likely message->status = 0; 1472ca632f55SGrant Likely else 1473ca632f55SGrant Likely message->status = -EIO; 1474ca632f55SGrant Likely 1475ca632f55SGrant Likely giveback(pl022); 1476ca632f55SGrant Likely return; 1477ca632f55SGrant Likely } 1478ca632f55SGrant Likely 1479ffbbdd21SLinus Walleij static int pl022_transfer_one_message(struct spi_master *master, 1480ffbbdd21SLinus Walleij struct spi_message *msg) 1481ca632f55SGrant Likely { 1482ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1483ca632f55SGrant Likely 1484ffbbdd21SLinus Walleij /* Initial message state */ 1485ffbbdd21SLinus Walleij pl022->cur_msg = msg; 1486ffbbdd21SLinus Walleij msg->state = STATE_START; 1487ffbbdd21SLinus Walleij 1488ffbbdd21SLinus Walleij pl022->cur_transfer = list_entry(msg->transfers.next, 1489ffbbdd21SLinus Walleij struct spi_transfer, transfer_list); 1490ffbbdd21SLinus Walleij 1491ffbbdd21SLinus Walleij /* Setup the SPI using the per chip configuration */ 1492ffbbdd21SLinus Walleij pl022->cur_chip = spi_get_ctldata(msg->spi); 1493ffbbdd21SLinus Walleij 1494ffbbdd21SLinus Walleij restore_state(pl022); 1495ffbbdd21SLinus Walleij flush(pl022); 1496ffbbdd21SLinus Walleij 1497ffbbdd21SLinus Walleij if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1498ffbbdd21SLinus Walleij do_polling_transfer(pl022); 1499ffbbdd21SLinus Walleij else 1500ffbbdd21SLinus Walleij do_interrupt_dma_transfer(pl022); 1501ffbbdd21SLinus Walleij 1502ffbbdd21SLinus Walleij return 0; 1503ffbbdd21SLinus Walleij } 1504ffbbdd21SLinus Walleij 1505ffbbdd21SLinus Walleij static int pl022_prepare_transfer_hardware(struct spi_master *master) 1506ffbbdd21SLinus Walleij { 1507ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1508ffbbdd21SLinus Walleij 1509ffbbdd21SLinus Walleij /* 1510ffbbdd21SLinus Walleij * Just make sure we have all we need to run the transfer by syncing 1511ffbbdd21SLinus Walleij * with the runtime PM framework. 1512ffbbdd21SLinus Walleij */ 1513ffbbdd21SLinus Walleij pm_runtime_get_sync(&pl022->adev->dev); 1514ffbbdd21SLinus Walleij return 0; 1515ffbbdd21SLinus Walleij } 1516ffbbdd21SLinus Walleij 1517ffbbdd21SLinus Walleij static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1518ffbbdd21SLinus Walleij { 1519ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1520ffbbdd21SLinus Walleij 15210ad2deeaSVirupax Sadashivpetimath /* nothing more to do - disable spi/ssp and power off */ 15220ad2deeaSVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 15230ad2deeaSVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 152453e4aceaSChris Blair 152553e4aceaSChris Blair if (pl022->master_info->autosuspend_delay > 0) { 152653e4aceaSChris Blair pm_runtime_mark_last_busy(&pl022->adev->dev); 152753e4aceaSChris Blair pm_runtime_put_autosuspend(&pl022->adev->dev); 152853e4aceaSChris Blair } else { 1529d4b6af2eSChris Blair pm_runtime_put(&pl022->adev->dev); 15300ad2deeaSVirupax Sadashivpetimath } 1531ca632f55SGrant Likely 1532ca632f55SGrant Likely return 0; 1533ca632f55SGrant Likely } 1534ca632f55SGrant Likely 1535ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1536ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1537ca632f55SGrant Likely { 1538ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1539ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1540ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1541ca632f55SGrant Likely "interface is configured incorrectly\n"); 1542ca632f55SGrant Likely return -EINVAL; 1543ca632f55SGrant Likely } 1544ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1545ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1546ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1547ca632f55SGrant Likely "unidirectional mode not supported in this " 1548ca632f55SGrant Likely "hardware version\n"); 1549ca632f55SGrant Likely return -EINVAL; 1550ca632f55SGrant Likely } 1551ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1552ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1553ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1554ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1555ca632f55SGrant Likely return -EINVAL; 1556ca632f55SGrant Likely } 1557ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1558ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1559ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1560ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1561ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1562ca632f55SGrant Likely return -EINVAL; 1563ca632f55SGrant Likely } 156478b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 156578b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 156678b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 156778b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 156878b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 156978b2b911SLinus Walleij break; 157078b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 157178b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1572ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1573ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1574ca632f55SGrant Likely return -EINVAL; 1575ca632f55SGrant Likely } 157678b2b911SLinus Walleij break; 157778b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 157878b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 157978b2b911SLinus Walleij dev_err(&pl022->adev->dev, 158078b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 158178b2b911SLinus Walleij return -EINVAL; 158278b2b911SLinus Walleij } 158378b2b911SLinus Walleij break; 158478b2b911SLinus Walleij default: 158578b2b911SLinus Walleij dev_err(&pl022->adev->dev, 158678b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 158778b2b911SLinus Walleij return -EINVAL; 158878b2b911SLinus Walleij break; 158978b2b911SLinus Walleij } 159078b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 159178b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 159278b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 159378b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 159478b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 159578b2b911SLinus Walleij break; 159678b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 159778b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1598ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1599ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1600ca632f55SGrant Likely return -EINVAL; 1601ca632f55SGrant Likely } 160278b2b911SLinus Walleij break; 160378b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 160478b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 160578b2b911SLinus Walleij dev_err(&pl022->adev->dev, 160678b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 160778b2b911SLinus Walleij return -EINVAL; 160878b2b911SLinus Walleij } 160978b2b911SLinus Walleij break; 161078b2b911SLinus Walleij default: 161178b2b911SLinus Walleij dev_err(&pl022->adev->dev, 161278b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 161378b2b911SLinus Walleij return -EINVAL; 161478b2b911SLinus Walleij break; 161578b2b911SLinus Walleij } 1616ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1617ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1618ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1619ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1620ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1621ca632f55SGrant Likely return -EINVAL; 1622ca632f55SGrant Likely } 1623ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1624ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1625ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1626ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1627ca632f55SGrant Likely return -EINVAL; 1628ca632f55SGrant Likely } 1629ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1630ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1631ca632f55SGrant Likely if ((chip_info->duplex != 1632ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1633ca632f55SGrant Likely && (chip_info->duplex != 1634ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1635ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1636ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1637ca632f55SGrant Likely return -EINVAL; 1638ca632f55SGrant Likely } 1639ca632f55SGrant Likely } else { 1640ca632f55SGrant Likely if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1641ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1642ca632f55SGrant Likely "Microwire half duplex mode requested," 1643ca632f55SGrant Likely " but this is only available in the" 1644ca632f55SGrant Likely " ST version of PL022\n"); 1645ca632f55SGrant Likely return -EINVAL; 1646ca632f55SGrant Likely } 1647ca632f55SGrant Likely } 1648ca632f55SGrant Likely return 0; 1649ca632f55SGrant Likely } 1650ca632f55SGrant Likely 16510379b2a3SViresh Kumar static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 16520379b2a3SViresh Kumar { 16530379b2a3SViresh Kumar return rate / (cpsdvsr * (1 + scr)); 16540379b2a3SViresh Kumar } 16550379b2a3SViresh Kumar 16560379b2a3SViresh Kumar static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 16570379b2a3SViresh Kumar ssp_clock_params * clk_freq) 1658ca632f55SGrant Likely { 1659ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 16600379b2a3SViresh Kumar u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 16610379b2a3SViresh Kumar u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 16620379b2a3SViresh Kumar best_scr = 0, tmp, found = 0; 1663ca632f55SGrant Likely 1664ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1665ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 16660379b2a3SViresh Kumar max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1667ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 16680379b2a3SViresh Kumar min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1669ca632f55SGrant Likely 16700379b2a3SViresh Kumar if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1671ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1672ca632f55SGrant Likely "controller data is incorrect: out of range frequency"); 1673ca632f55SGrant Likely return -EINVAL; 1674ca632f55SGrant Likely } 16750379b2a3SViresh Kumar 16760379b2a3SViresh Kumar /* 16770379b2a3SViresh Kumar * best_freq will give closest possible available rate (<= requested 16780379b2a3SViresh Kumar * freq) for all values of scr & cpsdvsr. 16790379b2a3SViresh Kumar */ 16800379b2a3SViresh Kumar while ((cpsdvsr <= CPSDVR_MAX) && !found) { 16810379b2a3SViresh Kumar while (scr <= SCR_MAX) { 16820379b2a3SViresh Kumar tmp = spi_rate(rate, cpsdvsr, scr); 16830379b2a3SViresh Kumar 16840379b2a3SViresh Kumar if (tmp > freq) 16850379b2a3SViresh Kumar scr++; 16860379b2a3SViresh Kumar /* 16870379b2a3SViresh Kumar * If found exact value, update and break. 16880379b2a3SViresh Kumar * If found more closer value, update and continue. 16890379b2a3SViresh Kumar */ 16900379b2a3SViresh Kumar else if ((tmp == freq) || (tmp > best_freq)) { 16910379b2a3SViresh Kumar best_freq = tmp; 16920379b2a3SViresh Kumar best_cpsdvsr = cpsdvsr; 16930379b2a3SViresh Kumar best_scr = scr; 16940379b2a3SViresh Kumar 16950379b2a3SViresh Kumar if (tmp == freq) 16960379b2a3SViresh Kumar break; 16970379b2a3SViresh Kumar } 16980379b2a3SViresh Kumar scr++; 16990379b2a3SViresh Kumar } 17000379b2a3SViresh Kumar cpsdvsr += 2; 17010379b2a3SViresh Kumar scr = SCR_MIN; 1702ca632f55SGrant Likely } 1703ca632f55SGrant Likely 17040379b2a3SViresh Kumar clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 17050379b2a3SViresh Kumar clk_freq->scr = (u8) (best_scr & 0xFF); 17060379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, 17070379b2a3SViresh Kumar "SSP Target Frequency is: %u, Effective Frequency is %u\n", 17080379b2a3SViresh Kumar freq, best_freq); 17090379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 17100379b2a3SViresh Kumar clk_freq->cpsdvsr, clk_freq->scr); 17110379b2a3SViresh Kumar 1712ca632f55SGrant Likely return 0; 1713ca632f55SGrant Likely } 1714ca632f55SGrant Likely 1715ca632f55SGrant Likely /* 1716ca632f55SGrant Likely * A piece of default chip info unless the platform 1717ca632f55SGrant Likely * supplies it. 1718ca632f55SGrant Likely */ 1719ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1720ca632f55SGrant Likely .com_mode = POLLING_TRANSFER, 1721ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1722ca632f55SGrant Likely .hierarchy = SSP_SLAVE, 1723ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1724ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1725ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1726ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1727ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1728ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1729ca632f55SGrant Likely .cs_control = null_cs_control, 1730ca632f55SGrant Likely }; 1731ca632f55SGrant Likely 1732ca632f55SGrant Likely /** 1733ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1734ca632f55SGrant Likely * @spi: spi device which is requesting setup 1735ca632f55SGrant Likely * 1736ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1737ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1738ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1739ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1740ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1741ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1742ca632f55SGrant Likely * commence. 1743ca632f55SGrant Likely */ 1744ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1745ca632f55SGrant Likely { 1746ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 1747ca632f55SGrant Likely struct chip_data *chip; 1748c4a47843SJonas Aaberg struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1749ca632f55SGrant Likely int status = 0; 1750ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1751ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1752ca632f55SGrant Likely u32 tmp; 1753ca632f55SGrant Likely 1754ca632f55SGrant Likely if (!spi->max_speed_hz) 1755ca632f55SGrant Likely return -EINVAL; 1756ca632f55SGrant Likely 1757ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1758ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1759ca632f55SGrant Likely 1760ca632f55SGrant Likely if (chip == NULL) { 1761ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1762ca632f55SGrant Likely if (!chip) { 1763ca632f55SGrant Likely dev_err(&spi->dev, 1764ca632f55SGrant Likely "cannot allocate controller state\n"); 1765ca632f55SGrant Likely return -ENOMEM; 1766ca632f55SGrant Likely } 1767ca632f55SGrant Likely dev_dbg(&spi->dev, 1768ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1769ca632f55SGrant Likely } 1770ca632f55SGrant Likely 1771ca632f55SGrant Likely /* Get controller data if one is supplied */ 1772ca632f55SGrant Likely chip_info = spi->controller_data; 1773ca632f55SGrant Likely 1774ca632f55SGrant Likely if (chip_info == NULL) { 1775ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1776ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1777ca632f55SGrant Likely dev_dbg(&spi->dev, 1778ca632f55SGrant Likely "using default controller_data settings\n"); 1779ca632f55SGrant Likely } else 1780ca632f55SGrant Likely dev_dbg(&spi->dev, 1781ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1782ca632f55SGrant Likely 1783ca632f55SGrant Likely /* 1784ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1785ca632f55SGrant Likely * frequency setting 1786ca632f55SGrant Likely */ 1787ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1788ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1789ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1790ca632f55SGrant Likely spi->max_speed_hz, 1791ca632f55SGrant Likely &clk_freq); 1792ca632f55SGrant Likely if (status < 0) 1793ca632f55SGrant Likely goto err_config_params; 1794ca632f55SGrant Likely } else { 1795ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1796ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1797ca632f55SGrant Likely clk_freq.cpsdvsr = 1798ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1799ca632f55SGrant Likely } 1800ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1801ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1802f8db4cc4SGrant Likely status = -EINVAL; 1803ca632f55SGrant Likely dev_err(&spi->dev, 1804ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1805ca632f55SGrant Likely goto err_config_params; 1806ca632f55SGrant Likely } 1807ca632f55SGrant Likely 1808ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1809ca632f55SGrant Likely if (status) { 1810ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1811ca632f55SGrant Likely goto err_config_params; 1812ca632f55SGrant Likely } 1813ca632f55SGrant Likely 1814083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1815083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1816083be3f0SLinus Walleij 1817ca632f55SGrant Likely /* Now set controller state based on controller data */ 1818ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1819ca632f55SGrant Likely if (!chip_info->cs_control) { 1820ca632f55SGrant Likely chip->cs_control = null_cs_control; 1821ca632f55SGrant Likely dev_warn(&spi->dev, 1822ca632f55SGrant Likely "chip select function is NULL for this chip\n"); 1823ca632f55SGrant Likely } else 1824ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1825ca632f55SGrant Likely 1826*eb798c64SVinit Shenoy /* Check bits per word with vendor specific range */ 1827*eb798c64SVinit Shenoy if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1828ca632f55SGrant Likely status = -ENOTSUPP; 1829*eb798c64SVinit Shenoy dev_err(&spi->dev, "illegal data size for this controller!\n"); 1830*eb798c64SVinit Shenoy dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1831*eb798c64SVinit Shenoy pl022->vendor->max_bpw); 1832ca632f55SGrant Likely goto err_config_params; 1833ca632f55SGrant Likely } else if (bits <= 8) { 1834ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1835ca632f55SGrant Likely chip->n_bytes = 1; 1836ca632f55SGrant Likely chip->read = READING_U8; 1837ca632f55SGrant Likely chip->write = WRITING_U8; 1838ca632f55SGrant Likely } else if (bits <= 16) { 1839ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1840ca632f55SGrant Likely chip->n_bytes = 2; 1841ca632f55SGrant Likely chip->read = READING_U16; 1842ca632f55SGrant Likely chip->write = WRITING_U16; 1843ca632f55SGrant Likely } else { 1844ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1845ca632f55SGrant Likely chip->n_bytes = 4; 1846ca632f55SGrant Likely chip->read = READING_U32; 1847ca632f55SGrant Likely chip->write = WRITING_U32; 1848ca632f55SGrant Likely } 1849ca632f55SGrant Likely 1850ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 1851ca632f55SGrant Likely chip->cr0 = 0; 1852ca632f55SGrant Likely chip->cr1 = 0; 1853ca632f55SGrant Likely chip->dmacr = 0; 1854ca632f55SGrant Likely chip->cpsr = 0; 1855ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 1856ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 1857ca632f55SGrant Likely chip->enable_dma = true; 1858ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1859ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1860ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1861ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1862ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1863ca632f55SGrant Likely } else { 1864ca632f55SGrant Likely chip->enable_dma = false; 1865ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1866ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1867ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1868ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1869ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1870ca632f55SGrant Likely } 1871ca632f55SGrant Likely 1872ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 1873ca632f55SGrant Likely 1874ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 1875ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1876ca632f55SGrant Likely u32 etx; 1877ca632f55SGrant Likely 1878ca632f55SGrant Likely if (pl022->vendor->pl023) { 1879ca632f55SGrant Likely /* These bits are only in the PL023 */ 1880ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1881ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 1882ca632f55SGrant Likely } else { 1883ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 1884ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1885ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 1886ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1887ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 1888ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1889ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 1890ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1891ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 1892ca632f55SGrant Likely } 1893ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 1894ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 1895ca632f55SGrant Likely 1896ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 1897ca632f55SGrant Likely tmp = SSP_RX_LSB; 1898ca632f55SGrant Likely etx = SSP_TX_LSB; 1899ca632f55SGrant Likely } else { 1900ca632f55SGrant Likely tmp = SSP_RX_MSB; 1901ca632f55SGrant Likely etx = SSP_TX_MSB; 1902ca632f55SGrant Likely } 1903ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1904ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1905ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1906ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 1907ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1908ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 1909ca632f55SGrant Likely } else { 1910ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 1911ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 1912ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1913ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 1914ca632f55SGrant Likely } 1915ca632f55SGrant Likely 1916ca632f55SGrant Likely /* Stuff that is common for all versions */ 1917ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 1918ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 1919ca632f55SGrant Likely else 1920ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 1921ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1922ca632f55SGrant Likely 1923ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 1924ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 1925ca632f55SGrant Likely else 1926ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 1927ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 1928ca632f55SGrant Likely 1929ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1930ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 1931ca632f55SGrant Likely if (pl022->vendor->loopback) { 1932ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 1933ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 1934ca632f55SGrant Likely else 1935ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 1936ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 1937ca632f55SGrant Likely } 1938ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 1939ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 1940f1e45f86SViresh Kumar SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 1941f1e45f86SViresh Kumar 3); 1942ca632f55SGrant Likely 1943ca632f55SGrant Likely /* Save controller_state */ 1944ca632f55SGrant Likely spi_set_ctldata(spi, chip); 1945ca632f55SGrant Likely return status; 1946ca632f55SGrant Likely err_config_params: 1947ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 1948ca632f55SGrant Likely kfree(chip); 1949ca632f55SGrant Likely return status; 1950ca632f55SGrant Likely } 1951ca632f55SGrant Likely 1952ca632f55SGrant Likely /** 1953ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 1954ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 1955ca632f55SGrant Likely * 1956ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1957ca632f55SGrant Likely * controller. It will free the runtime state of chip. 1958ca632f55SGrant Likely */ 1959ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 1960ca632f55SGrant Likely { 1961ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 1962ca632f55SGrant Likely 1963ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 1964ca632f55SGrant Likely kfree(chip); 1965ca632f55SGrant Likely } 1966ca632f55SGrant Likely 1967ca632f55SGrant Likely static int __devinit 1968ca632f55SGrant Likely pl022_probe(struct amba_device *adev, const struct amba_id *id) 1969ca632f55SGrant Likely { 1970ca632f55SGrant Likely struct device *dev = &adev->dev; 1971ca632f55SGrant Likely struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 1972ca632f55SGrant Likely struct spi_master *master; 1973ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 1974ca632f55SGrant Likely int status = 0; 1975ca632f55SGrant Likely 1976ca632f55SGrant Likely dev_info(&adev->dev, 1977ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 1978ca632f55SGrant Likely if (platform_info == NULL) { 1979ca632f55SGrant Likely dev_err(&adev->dev, "probe - no platform data supplied\n"); 1980ca632f55SGrant Likely status = -ENODEV; 1981ca632f55SGrant Likely goto err_no_pdata; 1982ca632f55SGrant Likely } 1983ca632f55SGrant Likely 1984ca632f55SGrant Likely /* Allocate master with space for data */ 1985ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct pl022)); 1986ca632f55SGrant Likely if (master == NULL) { 1987ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 1988ca632f55SGrant Likely status = -ENOMEM; 1989ca632f55SGrant Likely goto err_no_master; 1990ca632f55SGrant Likely } 1991ca632f55SGrant Likely 1992ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 1993ca632f55SGrant Likely pl022->master = master; 1994ca632f55SGrant Likely pl022->master_info = platform_info; 1995ca632f55SGrant Likely pl022->adev = adev; 1996ca632f55SGrant Likely pl022->vendor = id->data; 1997ca632f55SGrant Likely 1998ca632f55SGrant Likely /* 1999ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2000ca632f55SGrant Likely * on this board 2001ca632f55SGrant Likely */ 2002ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 2003ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 2004ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2005ca632f55SGrant Likely master->setup = pl022_setup; 2006ffbbdd21SLinus Walleij master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2007ffbbdd21SLinus Walleij master->transfer_one_message = pl022_transfer_one_message; 2008ffbbdd21SLinus Walleij master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2009ffbbdd21SLinus Walleij master->rt = platform_info->rt; 2010ca632f55SGrant Likely 2011ca632f55SGrant Likely /* 2012ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2013ca632f55SGrant Likely * always MS bit first on the original pl022. 2014ca632f55SGrant Likely */ 2015ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2016ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2017ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2018ca632f55SGrant Likely 2019ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2020ca632f55SGrant Likely 2021ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2022ca632f55SGrant Likely if (status) 2023ca632f55SGrant Likely goto err_no_ioregion; 2024ca632f55SGrant Likely 2025ca632f55SGrant Likely pl022->phybase = adev->res.start; 2026ca632f55SGrant Likely pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2027ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2028ca632f55SGrant Likely status = -ENOMEM; 2029ca632f55SGrant Likely goto err_no_ioremap; 2030ca632f55SGrant Likely } 2031ca632f55SGrant Likely printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2032ca632f55SGrant Likely adev->res.start, pl022->virtbase); 2033ca632f55SGrant Likely 2034ca632f55SGrant Likely pl022->clk = clk_get(&adev->dev, NULL); 2035ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2036ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2037ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2038ca632f55SGrant Likely goto err_no_clk; 2039ca632f55SGrant Likely } 20407ff6bcf0SRussell King 20417ff6bcf0SRussell King status = clk_prepare(pl022->clk); 20427ff6bcf0SRussell King if (status) { 20437ff6bcf0SRussell King dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 20447ff6bcf0SRussell King goto err_clk_prep; 20457ff6bcf0SRussell King } 20467ff6bcf0SRussell King 204771e63e74SUlf Hansson status = clk_enable(pl022->clk); 204871e63e74SUlf Hansson if (status) { 204971e63e74SUlf Hansson dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 205071e63e74SUlf Hansson goto err_no_clk_en; 205171e63e74SUlf Hansson } 205271e63e74SUlf Hansson 2053ffbbdd21SLinus Walleij /* Initialize transfer pump */ 2054ffbbdd21SLinus Walleij tasklet_init(&pl022->pump_transfers, pump_transfers, 2055ffbbdd21SLinus Walleij (unsigned long)pl022); 2056ffbbdd21SLinus Walleij 2057ca632f55SGrant Likely /* Disable SSP */ 2058ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2059ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2060ca632f55SGrant Likely load_ssp_default_config(pl022); 2061ca632f55SGrant Likely 2062ca632f55SGrant Likely status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2063ca632f55SGrant Likely pl022); 2064ca632f55SGrant Likely if (status < 0) { 2065ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2066ca632f55SGrant Likely goto err_no_irq; 2067ca632f55SGrant Likely } 2068ca632f55SGrant Likely 2069ca632f55SGrant Likely /* Get DMA channels */ 2070ca632f55SGrant Likely if (platform_info->enable_dma) { 2071ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2072ca632f55SGrant Likely if (status != 0) 2073ca632f55SGrant Likely platform_info->enable_dma = 0; 2074ca632f55SGrant Likely } 2075ca632f55SGrant Likely 2076ca632f55SGrant Likely /* Register with the SPI framework */ 2077ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 2078ca632f55SGrant Likely status = spi_register_master(master); 2079ca632f55SGrant Likely if (status != 0) { 2080ca632f55SGrant Likely dev_err(&adev->dev, 2081ca632f55SGrant Likely "probe - problem registering spi master\n"); 2082ca632f55SGrant Likely goto err_spi_register; 2083ca632f55SGrant Likely } 2084ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 208592b97f0aSRussell King 208692b97f0aSRussell King /* let runtime pm put suspend */ 208753e4aceaSChris Blair if (platform_info->autosuspend_delay > 0) { 208853e4aceaSChris Blair dev_info(&adev->dev, 208953e4aceaSChris Blair "will use autosuspend for runtime pm, delay %dms\n", 209053e4aceaSChris Blair platform_info->autosuspend_delay); 209153e4aceaSChris Blair pm_runtime_set_autosuspend_delay(dev, 209253e4aceaSChris Blair platform_info->autosuspend_delay); 209353e4aceaSChris Blair pm_runtime_use_autosuspend(dev); 209453e4aceaSChris Blair pm_runtime_put_autosuspend(dev); 209553e4aceaSChris Blair } else { 209692b97f0aSRussell King pm_runtime_put(dev); 209753e4aceaSChris Blair } 2098ca632f55SGrant Likely return 0; 2099ca632f55SGrant Likely 2100ca632f55SGrant Likely err_spi_register: 21013e3ea716SViresh Kumar if (platform_info->enable_dma) 2102ca632f55SGrant Likely pl022_dma_remove(pl022); 21033e3ea716SViresh Kumar 2104ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2105ca632f55SGrant Likely err_no_irq: 210671e63e74SUlf Hansson clk_disable(pl022->clk); 210771e63e74SUlf Hansson err_no_clk_en: 21087ff6bcf0SRussell King clk_unprepare(pl022->clk); 21097ff6bcf0SRussell King err_clk_prep: 2110ca632f55SGrant Likely clk_put(pl022->clk); 2111ca632f55SGrant Likely err_no_clk: 2112ca632f55SGrant Likely iounmap(pl022->virtbase); 2113ca632f55SGrant Likely err_no_ioremap: 2114ca632f55SGrant Likely amba_release_regions(adev); 2115ca632f55SGrant Likely err_no_ioregion: 2116ca632f55SGrant Likely spi_master_put(master); 2117ca632f55SGrant Likely err_no_master: 2118ca632f55SGrant Likely err_no_pdata: 2119ca632f55SGrant Likely return status; 2120ca632f55SGrant Likely } 2121ca632f55SGrant Likely 2122ca632f55SGrant Likely static int __devexit 2123ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2124ca632f55SGrant Likely { 2125ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 212650658b66SLinus Walleij 2127ca632f55SGrant Likely if (!pl022) 2128ca632f55SGrant Likely return 0; 2129ca632f55SGrant Likely 213092b97f0aSRussell King /* 213192b97f0aSRussell King * undo pm_runtime_put() in probe. I assume that we're not 213292b97f0aSRussell King * accessing the primecell here. 213392b97f0aSRussell King */ 213492b97f0aSRussell King pm_runtime_get_noresume(&adev->dev); 213592b97f0aSRussell King 2136ca632f55SGrant Likely load_ssp_default_config(pl022); 21373e3ea716SViresh Kumar if (pl022->master_info->enable_dma) 2138ca632f55SGrant Likely pl022_dma_remove(pl022); 21393e3ea716SViresh Kumar 2140ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2141ca632f55SGrant Likely clk_disable(pl022->clk); 21427ff6bcf0SRussell King clk_unprepare(pl022->clk); 2143ca632f55SGrant Likely clk_put(pl022->clk); 2144ca632f55SGrant Likely iounmap(pl022->virtbase); 2145ca632f55SGrant Likely amba_release_regions(adev); 2146ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2147ca632f55SGrant Likely spi_unregister_master(pl022->master); 2148ca632f55SGrant Likely spi_master_put(pl022->master); 2149ca632f55SGrant Likely amba_set_drvdata(adev, NULL); 2150ca632f55SGrant Likely return 0; 2151ca632f55SGrant Likely } 2152ca632f55SGrant Likely 215392b97f0aSRussell King #ifdef CONFIG_SUSPEND 21546cfa6279SPeter Hüwe static int pl022_suspend(struct device *dev) 2155ca632f55SGrant Likely { 215692b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2157ffbbdd21SLinus Walleij int ret; 2158ca632f55SGrant Likely 2159ffbbdd21SLinus Walleij ret = spi_master_suspend(pl022->master); 2160ffbbdd21SLinus Walleij if (ret) { 2161ffbbdd21SLinus Walleij dev_warn(dev, "cannot suspend master\n"); 2162ffbbdd21SLinus Walleij return ret; 2163ca632f55SGrant Likely } 2164ca632f55SGrant Likely 21656cfa6279SPeter Hüwe dev_dbg(dev, "suspended\n"); 2166ca632f55SGrant Likely return 0; 2167ca632f55SGrant Likely } 2168ca632f55SGrant Likely 216992b97f0aSRussell King static int pl022_resume(struct device *dev) 2170ca632f55SGrant Likely { 217192b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2172ffbbdd21SLinus Walleij int ret; 2173ca632f55SGrant Likely 2174ca632f55SGrant Likely /* Start the queue running */ 2175ffbbdd21SLinus Walleij ret = spi_master_resume(pl022->master); 2176ffbbdd21SLinus Walleij if (ret) 2177ffbbdd21SLinus Walleij dev_err(dev, "problem starting queue (%d)\n", ret); 2178ca632f55SGrant Likely else 217992b97f0aSRussell King dev_dbg(dev, "resumed\n"); 2180ca632f55SGrant Likely 2181ffbbdd21SLinus Walleij return ret; 2182ca632f55SGrant Likely } 2183ca632f55SGrant Likely #endif /* CONFIG_PM */ 2184ca632f55SGrant Likely 218592b97f0aSRussell King #ifdef CONFIG_PM_RUNTIME 218692b97f0aSRussell King static int pl022_runtime_suspend(struct device *dev) 218792b97f0aSRussell King { 218892b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 218992b97f0aSRussell King 219092b97f0aSRussell King clk_disable(pl022->clk); 219192b97f0aSRussell King 219292b97f0aSRussell King return 0; 219392b97f0aSRussell King } 219492b97f0aSRussell King 219592b97f0aSRussell King static int pl022_runtime_resume(struct device *dev) 219692b97f0aSRussell King { 219792b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 219892b97f0aSRussell King 219992b97f0aSRussell King clk_enable(pl022->clk); 220092b97f0aSRussell King 220192b97f0aSRussell King return 0; 220292b97f0aSRussell King } 220392b97f0aSRussell King #endif 220492b97f0aSRussell King 220592b97f0aSRussell King static const struct dev_pm_ops pl022_dev_pm_ops = { 220692b97f0aSRussell King SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 220792b97f0aSRussell King SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 220892b97f0aSRussell King }; 220992b97f0aSRussell King 2210ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2211ca632f55SGrant Likely .fifodepth = 8, 2212ca632f55SGrant Likely .max_bpw = 16, 2213ca632f55SGrant Likely .unidir = false, 2214ca632f55SGrant Likely .extended_cr = false, 2215ca632f55SGrant Likely .pl023 = false, 2216ca632f55SGrant Likely .loopback = true, 2217ca632f55SGrant Likely }; 2218ca632f55SGrant Likely 2219ca632f55SGrant Likely static struct vendor_data vendor_st = { 2220ca632f55SGrant Likely .fifodepth = 32, 2221ca632f55SGrant Likely .max_bpw = 32, 2222ca632f55SGrant Likely .unidir = false, 2223ca632f55SGrant Likely .extended_cr = true, 2224ca632f55SGrant Likely .pl023 = false, 2225ca632f55SGrant Likely .loopback = true, 2226ca632f55SGrant Likely }; 2227ca632f55SGrant Likely 2228ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2229ca632f55SGrant Likely .fifodepth = 32, 2230ca632f55SGrant Likely .max_bpw = 32, 2231ca632f55SGrant Likely .unidir = false, 2232ca632f55SGrant Likely .extended_cr = true, 2233ca632f55SGrant Likely .pl023 = true, 2234ca632f55SGrant Likely .loopback = false, 2235ca632f55SGrant Likely }; 2236ca632f55SGrant Likely 2237ca632f55SGrant Likely static struct vendor_data vendor_db5500_pl023 = { 2238ca632f55SGrant Likely .fifodepth = 32, 2239ca632f55SGrant Likely .max_bpw = 32, 2240ca632f55SGrant Likely .unidir = false, 2241ca632f55SGrant Likely .extended_cr = true, 2242ca632f55SGrant Likely .pl023 = true, 2243ca632f55SGrant Likely .loopback = true, 2244ca632f55SGrant Likely }; 2245ca632f55SGrant Likely 2246ca632f55SGrant Likely static struct amba_id pl022_ids[] = { 2247ca632f55SGrant Likely { 2248ca632f55SGrant Likely /* 2249ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2250ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2251ca632f55SGrant Likely */ 2252ca632f55SGrant Likely .id = 0x00041022, 2253ca632f55SGrant Likely .mask = 0x000fffff, 2254ca632f55SGrant Likely .data = &vendor_arm, 2255ca632f55SGrant Likely }, 2256ca632f55SGrant Likely { 2257ca632f55SGrant Likely /* 2258ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2259ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2260ca632f55SGrant Likely */ 2261ca632f55SGrant Likely .id = 0x01080022, 2262ca632f55SGrant Likely .mask = 0xffffffff, 2263ca632f55SGrant Likely .data = &vendor_st, 2264ca632f55SGrant Likely }, 2265ca632f55SGrant Likely { 2266ca632f55SGrant Likely /* 2267ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2268ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2269ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2270ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2271ca632f55SGrant Likely * CR0/CR1 register 2272ca632f55SGrant Likely */ 2273ca632f55SGrant Likely .id = 0x00080023, 2274ca632f55SGrant Likely .mask = 0xffffffff, 2275ca632f55SGrant Likely .data = &vendor_st_pl023, 2276ca632f55SGrant Likely }, 2277ca632f55SGrant Likely { 2278ca632f55SGrant Likely .id = 0x10080023, 2279ca632f55SGrant Likely .mask = 0xffffffff, 2280ca632f55SGrant Likely .data = &vendor_db5500_pl023, 2281ca632f55SGrant Likely }, 2282ca632f55SGrant Likely { 0, 0 }, 2283ca632f55SGrant Likely }; 2284ca632f55SGrant Likely 22857eeac71bSDave Martin MODULE_DEVICE_TABLE(amba, pl022_ids); 22867eeac71bSDave Martin 2287ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2288ca632f55SGrant Likely .drv = { 2289ca632f55SGrant Likely .name = "ssp-pl022", 229092b97f0aSRussell King .pm = &pl022_dev_pm_ops, 2291ca632f55SGrant Likely }, 2292ca632f55SGrant Likely .id_table = pl022_ids, 2293ca632f55SGrant Likely .probe = pl022_probe, 2294ca632f55SGrant Likely .remove = __devexit_p(pl022_remove), 2295ca632f55SGrant Likely }; 2296ca632f55SGrant Likely 2297ca632f55SGrant Likely static int __init pl022_init(void) 2298ca632f55SGrant Likely { 2299ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2300ca632f55SGrant Likely } 2301ca632f55SGrant Likely subsys_initcall(pl022_init); 2302ca632f55SGrant Likely 2303ca632f55SGrant Likely static void __exit pl022_exit(void) 2304ca632f55SGrant Likely { 2305ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2306ca632f55SGrant Likely } 2307ca632f55SGrant Likely module_exit(pl022_exit); 2308ca632f55SGrant Likely 2309ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2310ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2311ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2312