1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3ca632f55SGrant Likely * 4aeef9915SLinus Walleij * Copyright (C) 2008-2012 ST-Ericsson AB 5ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6ca632f55SGrant Likely * 7ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * Initial version inspired by: 10ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11ca632f55SGrant Likely * Initial adoption to PL022 by: 12ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 15ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 16ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 17ca632f55SGrant Likely * (at your option) any later version. 18ca632f55SGrant Likely * 19ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 20ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 21ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22ca632f55SGrant Likely * GNU General Public License for more details. 23ca632f55SGrant Likely */ 24ca632f55SGrant Likely 25ca632f55SGrant Likely #include <linux/init.h> 26ca632f55SGrant Likely #include <linux/module.h> 27ca632f55SGrant Likely #include <linux/device.h> 28ca632f55SGrant Likely #include <linux/ioport.h> 29ca632f55SGrant Likely #include <linux/errno.h> 30ca632f55SGrant Likely #include <linux/interrupt.h> 31ca632f55SGrant Likely #include <linux/spi/spi.h> 32ca632f55SGrant Likely #include <linux/delay.h> 33ca632f55SGrant Likely #include <linux/clk.h> 34ca632f55SGrant Likely #include <linux/err.h> 35ca632f55SGrant Likely #include <linux/amba/bus.h> 36ca632f55SGrant Likely #include <linux/amba/pl022.h> 37ca632f55SGrant Likely #include <linux/io.h> 38ca632f55SGrant Likely #include <linux/slab.h> 39ca632f55SGrant Likely #include <linux/dmaengine.h> 40ca632f55SGrant Likely #include <linux/dma-mapping.h> 41ca632f55SGrant Likely #include <linux/scatterlist.h> 42bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 43f6f46de1SRoland Stigge #include <linux/gpio.h> 446d3952a7SRoland Stigge #include <linux/of_gpio.h> 454f5e1b37SPatrice Chotard #include <linux/pinctrl/consumer.h> 46ca632f55SGrant Likely 47ca632f55SGrant Likely /* 48ca632f55SGrant Likely * This macro is used to define some register default values. 49ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 50ca632f55SGrant Likely * val shifted sb steps to the left. 51ca632f55SGrant Likely */ 52ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 53ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 54ca632f55SGrant Likely 55ca632f55SGrant Likely /* 56ca632f55SGrant Likely * This macro is also used to define some default values. 57ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 58ca632f55SGrant Likely * the result with mask. 59ca632f55SGrant Likely */ 60ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 61ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 62ca632f55SGrant Likely 63ca632f55SGrant Likely #define DRIVE_TX 0 64ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 65ca632f55SGrant Likely 66ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 67ca632f55SGrant Likely #define QUEUE_DMA 1 68ca632f55SGrant Likely 69ca632f55SGrant Likely #define RX_TRANSFER 1 70ca632f55SGrant Likely #define TX_TRANSFER 2 71ca632f55SGrant Likely 72ca632f55SGrant Likely /* 73ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 74ca632f55SGrant Likely */ 75ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 76ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 77ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 78ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 79ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 80ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 81ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 82ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 83ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 84ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 85ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 86ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 87ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 88ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 89ca632f55SGrant Likely 90ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 91ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 92ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 93ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 94ca632f55SGrant Likely 95ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 96ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 97ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 98ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 99ca632f55SGrant Likely 100ca632f55SGrant Likely /* 101ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 102ca632f55SGrant Likely */ 103ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 104ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 105ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 106ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 107ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 108ca632f55SGrant Likely 109ca632f55SGrant Likely /* 110ca632f55SGrant Likely * The ST version of this block moves som bits 111ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 112ca632f55SGrant Likely */ 113ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 114ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 115ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 116ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 117ca632f55SGrant Likely 118ca632f55SGrant Likely /* 119ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 120ca632f55SGrant Likely */ 121ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 122ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 123ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 124ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 125ca632f55SGrant Likely 126ca632f55SGrant Likely /* 127ca632f55SGrant Likely * The ST version of this block adds some bits 128ca632f55SGrant Likely * in SSP_CR1 129ca632f55SGrant Likely */ 130ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 131ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 132ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 133ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 134ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 135ca632f55SGrant Likely /* This one is only in the PL023 variant */ 136ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 137ca632f55SGrant Likely 138ca632f55SGrant Likely /* 139ca632f55SGrant Likely * SSP Status Register - SSP_SR 140ca632f55SGrant Likely */ 141ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 142ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 143ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 144ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 145ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 146ca632f55SGrant Likely 147ca632f55SGrant Likely /* 148ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 149ca632f55SGrant Likely */ 150ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 151ca632f55SGrant Likely 152ca632f55SGrant Likely /* 153ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 154ca632f55SGrant Likely */ 155ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 156ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 157ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 158ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 159ca632f55SGrant Likely 160ca632f55SGrant Likely /* 161ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 162ca632f55SGrant Likely */ 163ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 164ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 165ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 166ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 167ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 168ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 169ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 170ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 171ca632f55SGrant Likely 172ca632f55SGrant Likely /* 173ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 174ca632f55SGrant Likely */ 175ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 176ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 177ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 178ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 179ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 180ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 181ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 182ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 183ca632f55SGrant Likely 184ca632f55SGrant Likely /* 185ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 186ca632f55SGrant Likely */ 187ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 188ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 189ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 190ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 191ca632f55SGrant Likely 192ca632f55SGrant Likely /* 193ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 194ca632f55SGrant Likely */ 195ca632f55SGrant Likely /* Receive DMA Enable bit */ 196ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 197ca632f55SGrant Likely /* Transmit DMA Enable bit */ 198ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 199ca632f55SGrant Likely 200ca632f55SGrant Likely /* 201ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 202ca632f55SGrant Likely */ 203ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 204ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 205ca632f55SGrant Likely 206ca632f55SGrant Likely /* 207ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 208ca632f55SGrant Likely */ 209ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 210ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 211ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 212ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 213ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 214ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 215ca632f55SGrant Likely 216ca632f55SGrant Likely /* 217ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 218ca632f55SGrant Likely */ 219ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 220ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 221ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 222ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 223ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 224ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 225ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 226ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 227ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 228ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 229ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 230ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 231ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 232ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 233ca632f55SGrant Likely 234ca632f55SGrant Likely /* 235ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 236ca632f55SGrant Likely */ 237ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 238ca632f55SGrant Likely 239ca632f55SGrant Likely /* 240ca632f55SGrant Likely * Message State 241ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 242ca632f55SGrant Likely * hold a single state value, that's why all this 243ca632f55SGrant Likely * (void *) casting is done here. 244ca632f55SGrant Likely */ 245ca632f55SGrant Likely #define STATE_START ((void *) 0) 246ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 247ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 248ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 249ca632f55SGrant Likely 250ca632f55SGrant Likely /* 251ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 252ca632f55SGrant Likely */ 253ca632f55SGrant Likely #define SSP_DISABLED (0) 254ca632f55SGrant Likely #define SSP_ENABLED (1) 255ca632f55SGrant Likely 256ca632f55SGrant Likely /* 257ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 258ca632f55SGrant Likely */ 259ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 260ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 261ca632f55SGrant Likely 262ca632f55SGrant Likely /* 263ca632f55SGrant Likely * SSP Clock Defaults 264ca632f55SGrant Likely */ 265ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 266ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 267ca632f55SGrant Likely 268ca632f55SGrant Likely /* 269ca632f55SGrant Likely * SSP Clock Parameter ranges 270ca632f55SGrant Likely */ 271ca632f55SGrant Likely #define CPSDVR_MIN 0x02 272ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 273ca632f55SGrant Likely #define SCR_MIN 0x00 274ca632f55SGrant Likely #define SCR_MAX 0xFF 275ca632f55SGrant Likely 276ca632f55SGrant Likely /* 277ca632f55SGrant Likely * SSP Interrupt related Macros 278ca632f55SGrant Likely */ 279ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 280ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 281ca632f55SGrant Likely #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 282ca632f55SGrant Likely 283ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 284ca632f55SGrant Likely 285ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 286ca632f55SGrant Likely 287ca632f55SGrant Likely /* 288ca632f55SGrant Likely * The type of reading going on on this chip 289ca632f55SGrant Likely */ 290ca632f55SGrant Likely enum ssp_reading { 291ca632f55SGrant Likely READING_NULL, 292ca632f55SGrant Likely READING_U8, 293ca632f55SGrant Likely READING_U16, 294ca632f55SGrant Likely READING_U32 295ca632f55SGrant Likely }; 296ca632f55SGrant Likely 297ca632f55SGrant Likely /** 298ca632f55SGrant Likely * The type of writing going on on this chip 299ca632f55SGrant Likely */ 300ca632f55SGrant Likely enum ssp_writing { 301ca632f55SGrant Likely WRITING_NULL, 302ca632f55SGrant Likely WRITING_U8, 303ca632f55SGrant Likely WRITING_U16, 304ca632f55SGrant Likely WRITING_U32 305ca632f55SGrant Likely }; 306ca632f55SGrant Likely 307ca632f55SGrant Likely /** 308ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 309ca632f55SGrant Likely * for PL022 derivates 310ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 311ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 312ca632f55SGrant Likely * @unidir: supports unidirection transfers 313ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 314ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 315ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 316ca632f55SGrant Likely */ 317ca632f55SGrant Likely struct vendor_data { 318ca632f55SGrant Likely int fifodepth; 319ca632f55SGrant Likely int max_bpw; 320ca632f55SGrant Likely bool unidir; 321ca632f55SGrant Likely bool extended_cr; 322ca632f55SGrant Likely bool pl023; 323ca632f55SGrant Likely bool loopback; 324ca632f55SGrant Likely }; 325ca632f55SGrant Likely 326ca632f55SGrant Likely /** 327ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 328ca632f55SGrant Likely * @adev: AMBA device model hookup 329ca632f55SGrant Likely * @vendor: vendor data for the IP block 330ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 331ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 332ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 333ca632f55SGrant Likely * @master: SPI framework hookup 334ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 33514af60b6SChris Blair * @kworker: thread struct for message pump 33614af60b6SChris Blair * @kworker_task: pointer to task for message pump kworker thread 33714af60b6SChris Blair * @pump_messages: work struct for scheduling work to the message pump 338ca632f55SGrant Likely * @queue_lock: spinlock to syncronise access to message queue 339ca632f55SGrant Likely * @queue: message queue 34014af60b6SChris Blair * @busy: message pump is busy 34114af60b6SChris Blair * @running: message pump is running 342ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 343ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 344ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 345ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 3468b8d7191SVirupax Sadashivpetimath * @next_msg_cs_active: the next message in the queue has been examined 3478b8d7191SVirupax Sadashivpetimath * and it was found that it uses the same chip select as the previous 3488b8d7191SVirupax Sadashivpetimath * message, so we left it active after the previous transfer, and it's 3498b8d7191SVirupax Sadashivpetimath * active already. 350ca632f55SGrant Likely * @tx: current position in TX buffer to be read 351ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 352ca632f55SGrant Likely * @rx: current position in RX buffer to be written 353ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 354ca632f55SGrant Likely * @read: the type of read currently going on 355ca632f55SGrant Likely * @write: the type of write currently going on 356ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 357ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 358ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 359ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 360ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 361ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 362f6f46de1SRoland Stigge * @cur_cs: current chip select (gpio) 363f6f46de1SRoland Stigge * @chipselects: list of chipselects (gpios) 364ca632f55SGrant Likely */ 365ca632f55SGrant Likely struct pl022 { 366ca632f55SGrant Likely struct amba_device *adev; 367ca632f55SGrant Likely struct vendor_data *vendor; 368ca632f55SGrant Likely resource_size_t phybase; 369ca632f55SGrant Likely void __iomem *virtbase; 370ca632f55SGrant Likely struct clk *clk; 3714f5e1b37SPatrice Chotard /* Two optional pin states - default & sleep */ 3724f5e1b37SPatrice Chotard struct pinctrl *pinctrl; 3734f5e1b37SPatrice Chotard struct pinctrl_state *pins_default; 374d8f18420SPatrice Chotard struct pinctrl_state *pins_idle; 3754f5e1b37SPatrice Chotard struct pinctrl_state *pins_sleep; 376ca632f55SGrant Likely struct spi_master *master; 377ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 378ffbbdd21SLinus Walleij /* Message per-transfer pump */ 379ca632f55SGrant Likely struct tasklet_struct pump_transfers; 380ca632f55SGrant Likely struct spi_message *cur_msg; 381ca632f55SGrant Likely struct spi_transfer *cur_transfer; 382ca632f55SGrant Likely struct chip_data *cur_chip; 3838b8d7191SVirupax Sadashivpetimath bool next_msg_cs_active; 384ca632f55SGrant Likely void *tx; 385ca632f55SGrant Likely void *tx_end; 386ca632f55SGrant Likely void *rx; 387ca632f55SGrant Likely void *rx_end; 388ca632f55SGrant Likely enum ssp_reading read; 389ca632f55SGrant Likely enum ssp_writing write; 390ca632f55SGrant Likely u32 exp_fifo_level; 391083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 392083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 393ca632f55SGrant Likely /* DMA settings */ 394ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 395ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 396ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 397ca632f55SGrant Likely struct sg_table sgt_rx; 398ca632f55SGrant Likely struct sg_table sgt_tx; 399ca632f55SGrant Likely char *dummypage; 400ffbbdd21SLinus Walleij bool dma_running; 401ca632f55SGrant Likely #endif 402f6f46de1SRoland Stigge int cur_cs; 403f6f46de1SRoland Stigge int *chipselects; 404ca632f55SGrant Likely }; 405ca632f55SGrant Likely 406ca632f55SGrant Likely /** 407ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 408ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 409ca632f55SGrant Likely * register is 32 bits wide rather than just 16 410ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 411ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 412ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 413ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 414ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 415ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 416ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 417ca632f55SGrant Likely * @cs_control: chip select callback provided by chip 418ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 419ca632f55SGrant Likely * 420ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 421ca632f55SGrant Likely * This would be set according to the current message that would be served 422ca632f55SGrant Likely */ 423ca632f55SGrant Likely struct chip_data { 424ca632f55SGrant Likely u32 cr0; 425ca632f55SGrant Likely u16 cr1; 426ca632f55SGrant Likely u16 dmacr; 427ca632f55SGrant Likely u16 cpsr; 428ca632f55SGrant Likely u8 n_bytes; 429ca632f55SGrant Likely bool enable_dma; 430ca632f55SGrant Likely enum ssp_reading read; 431ca632f55SGrant Likely enum ssp_writing write; 432ca632f55SGrant Likely void (*cs_control) (u32 command); 433ca632f55SGrant Likely int xfer_type; 434ca632f55SGrant Likely }; 435ca632f55SGrant Likely 436ca632f55SGrant Likely /** 437ca632f55SGrant Likely * null_cs_control - Dummy chip select function 438ca632f55SGrant Likely * @command: select/delect the chip 439ca632f55SGrant Likely * 440ca632f55SGrant Likely * If no chip select function is provided by client this is used as dummy 441ca632f55SGrant Likely * chip select 442ca632f55SGrant Likely */ 443ca632f55SGrant Likely static void null_cs_control(u32 command) 444ca632f55SGrant Likely { 445ca632f55SGrant Likely pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 446ca632f55SGrant Likely } 447ca632f55SGrant Likely 448f6f46de1SRoland Stigge static void pl022_cs_control(struct pl022 *pl022, u32 command) 449f6f46de1SRoland Stigge { 450f6f46de1SRoland Stigge if (gpio_is_valid(pl022->cur_cs)) 451f6f46de1SRoland Stigge gpio_set_value(pl022->cur_cs, command); 452f6f46de1SRoland Stigge else 453f6f46de1SRoland Stigge pl022->cur_chip->cs_control(command); 454f6f46de1SRoland Stigge } 455f6f46de1SRoland Stigge 456ca632f55SGrant Likely /** 457ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 458ca632f55SGrant Likely * callback of this message. Assumes that caller already 459ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 460ca632f55SGrant Likely * @pl022: SSP driver private data structure 461ca632f55SGrant Likely */ 462ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 463ca632f55SGrant Likely { 464ca632f55SGrant Likely struct spi_transfer *last_transfer; 4658b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = false; 466ca632f55SGrant Likely 4678b8d7191SVirupax Sadashivpetimath last_transfer = list_entry(pl022->cur_msg->transfers.prev, 468ca632f55SGrant Likely struct spi_transfer, 469ca632f55SGrant Likely transfer_list); 470ca632f55SGrant Likely 471ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 472ca632f55SGrant Likely if (last_transfer->delay_usecs) 473ca632f55SGrant Likely /* 474ca632f55SGrant Likely * FIXME: This runs in interrupt context. 475ca632f55SGrant Likely * Is this really smart? 476ca632f55SGrant Likely */ 477ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 478ca632f55SGrant Likely 4798b8d7191SVirupax Sadashivpetimath if (!last_transfer->cs_change) { 480ca632f55SGrant Likely struct spi_message *next_msg; 481ca632f55SGrant Likely 4828b8d7191SVirupax Sadashivpetimath /* 4838b8d7191SVirupax Sadashivpetimath * cs_change was not set. We can keep the chip select 4848b8d7191SVirupax Sadashivpetimath * enabled if there is message in the queue and it is 4858b8d7191SVirupax Sadashivpetimath * for the same spi device. 486ca632f55SGrant Likely * 487ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 488ca632f55SGrant Likely * after calling msg->complete (below) the driver that 489ca632f55SGrant Likely * sent the current message could be unloaded, which 490ca632f55SGrant Likely * could invalidate the cs_control() callback... 491ca632f55SGrant Likely */ 492ca632f55SGrant Likely /* get a pointer to the next message, if any */ 493ffbbdd21SLinus Walleij next_msg = spi_get_next_queued_message(pl022->master); 494ca632f55SGrant Likely 4958b8d7191SVirupax Sadashivpetimath /* 4968b8d7191SVirupax Sadashivpetimath * see if the next and current messages point 4978b8d7191SVirupax Sadashivpetimath * to the same spi device. 498ca632f55SGrant Likely */ 4998b8d7191SVirupax Sadashivpetimath if (next_msg && next_msg->spi != pl022->cur_msg->spi) 500ca632f55SGrant Likely next_msg = NULL; 5018b8d7191SVirupax Sadashivpetimath if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 502f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 5038b8d7191SVirupax Sadashivpetimath else 5048b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = true; 505ffbbdd21SLinus Walleij 506ca632f55SGrant Likely } 5078b8d7191SVirupax Sadashivpetimath 5088b8d7191SVirupax Sadashivpetimath pl022->cur_msg = NULL; 5098b8d7191SVirupax Sadashivpetimath pl022->cur_transfer = NULL; 5108b8d7191SVirupax Sadashivpetimath pl022->cur_chip = NULL; 511ffbbdd21SLinus Walleij spi_finalize_current_message(pl022->master); 512fd316941SVirupax Sadashivpetimath 513fd316941SVirupax Sadashivpetimath /* disable the SPI/SSP operation */ 514fd316941SVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 515fd316941SVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 516fd316941SVirupax Sadashivpetimath 517ca632f55SGrant Likely } 518ca632f55SGrant Likely 519ca632f55SGrant Likely /** 520ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 521ca632f55SGrant Likely * @pl022: SSP driver private data structure 522ca632f55SGrant Likely */ 523ca632f55SGrant Likely static int flush(struct pl022 *pl022) 524ca632f55SGrant Likely { 525ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 526ca632f55SGrant Likely 527ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 528ca632f55SGrant Likely do { 529ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 530ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 531ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 532ca632f55SGrant Likely 533ca632f55SGrant Likely pl022->exp_fifo_level = 0; 534ca632f55SGrant Likely 535ca632f55SGrant Likely return limit; 536ca632f55SGrant Likely } 537ca632f55SGrant Likely 538ca632f55SGrant Likely /** 539ca632f55SGrant Likely * restore_state - Load configuration of current chip 540ca632f55SGrant Likely * @pl022: SSP driver private data structure 541ca632f55SGrant Likely */ 542ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 543ca632f55SGrant Likely { 544ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 545ca632f55SGrant Likely 546ca632f55SGrant Likely if (pl022->vendor->extended_cr) 547ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 548ca632f55SGrant Likely else 549ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 550ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 551ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 552ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 553ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 554ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 555ca632f55SGrant Likely } 556ca632f55SGrant Likely 557ca632f55SGrant Likely /* 558ca632f55SGrant Likely * Default SSP Register Values 559ca632f55SGrant Likely */ 560ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 561ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 562ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 563ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 564ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 565ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 566ca632f55SGrant Likely ) 567ca632f55SGrant Likely 568ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 569ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 570ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 571ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 572ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 573ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 574ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 575ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 576ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 577ca632f55SGrant Likely ) 578ca632f55SGrant Likely 579ca632f55SGrant Likely /* The PL023 version is slightly different again */ 580ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 581ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 582ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 583ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 584ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 585ca632f55SGrant Likely ) 586ca632f55SGrant Likely 587ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 588ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 589ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 590ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 591ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 592ca632f55SGrant Likely ) 593ca632f55SGrant Likely 594ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 595ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 596ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 597ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 598ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 599ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 600ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 601ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 602ca632f55SGrant Likely ) 603ca632f55SGrant Likely 604ca632f55SGrant Likely /* 605ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 606ca632f55SGrant Likely * support, and a new clock feedback delay setting. 607ca632f55SGrant Likely */ 608ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 609ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 610ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 611ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 612ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 613ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 614ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 615ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 616ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 617ca632f55SGrant Likely ) 618ca632f55SGrant Likely 619ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 620ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 621ca632f55SGrant Likely ) 622ca632f55SGrant Likely 623ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 624ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 625ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 626ca632f55SGrant Likely ) 627ca632f55SGrant Likely 628ca632f55SGrant Likely /** 629ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 630ca632f55SGrant Likely * @pl022: SSP driver private data structure 631ca632f55SGrant Likely */ 632ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 633ca632f55SGrant Likely { 634ca632f55SGrant Likely if (pl022->vendor->pl023) { 635ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 636ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 637ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 638ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 639ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 640ca632f55SGrant Likely } else { 641ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 642ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 643ca632f55SGrant Likely } 644ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 645ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 646ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 647ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 648ca632f55SGrant Likely } 649ca632f55SGrant Likely 650ca632f55SGrant Likely /** 651ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 652ca632f55SGrant Likely * set in pl022. 653ca632f55SGrant Likely */ 654ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 655ca632f55SGrant Likely { 656ca632f55SGrant Likely 657ca632f55SGrant Likely /* 658ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 659ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 660ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 661ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 662ca632f55SGrant Likely * 663ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 664ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 665ca632f55SGrant Likely * FIFO status flag indicates. 666ca632f55SGrant Likely */ 667ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 668ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 669ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 670ca632f55SGrant Likely 671ca632f55SGrant Likely /* Read as much as you can */ 672ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 673ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 674ca632f55SGrant Likely switch (pl022->read) { 675ca632f55SGrant Likely case READING_NULL: 676ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 677ca632f55SGrant Likely break; 678ca632f55SGrant Likely case READING_U8: 679ca632f55SGrant Likely *(u8 *) (pl022->rx) = 680ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 681ca632f55SGrant Likely break; 682ca632f55SGrant Likely case READING_U16: 683ca632f55SGrant Likely *(u16 *) (pl022->rx) = 684ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 685ca632f55SGrant Likely break; 686ca632f55SGrant Likely case READING_U32: 687ca632f55SGrant Likely *(u32 *) (pl022->rx) = 688ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 689ca632f55SGrant Likely break; 690ca632f55SGrant Likely } 691ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 692ca632f55SGrant Likely pl022->exp_fifo_level--; 693ca632f55SGrant Likely } 694ca632f55SGrant Likely /* 695ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 696ca632f55SGrant Likely */ 697ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 698ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 699ca632f55SGrant Likely switch (pl022->write) { 700ca632f55SGrant Likely case WRITING_NULL: 701ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 702ca632f55SGrant Likely break; 703ca632f55SGrant Likely case WRITING_U8: 704ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 705ca632f55SGrant Likely break; 706ca632f55SGrant Likely case WRITING_U16: 707ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 708ca632f55SGrant Likely break; 709ca632f55SGrant Likely case WRITING_U32: 710ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 711ca632f55SGrant Likely break; 712ca632f55SGrant Likely } 713ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 714ca632f55SGrant Likely pl022->exp_fifo_level++; 715ca632f55SGrant Likely /* 716ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 717ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 718ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 719ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 720ca632f55SGrant Likely */ 721ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 722ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 723ca632f55SGrant Likely switch (pl022->read) { 724ca632f55SGrant Likely case READING_NULL: 725ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 726ca632f55SGrant Likely break; 727ca632f55SGrant Likely case READING_U8: 728ca632f55SGrant Likely *(u8 *) (pl022->rx) = 729ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 730ca632f55SGrant Likely break; 731ca632f55SGrant Likely case READING_U16: 732ca632f55SGrant Likely *(u16 *) (pl022->rx) = 733ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 734ca632f55SGrant Likely break; 735ca632f55SGrant Likely case READING_U32: 736ca632f55SGrant Likely *(u32 *) (pl022->rx) = 737ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 738ca632f55SGrant Likely break; 739ca632f55SGrant Likely } 740ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 741ca632f55SGrant Likely pl022->exp_fifo_level--; 742ca632f55SGrant Likely } 743ca632f55SGrant Likely } 744ca632f55SGrant Likely /* 745ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 746ca632f55SGrant Likely * should be empty 747ca632f55SGrant Likely */ 748ca632f55SGrant Likely } 749ca632f55SGrant Likely 750ca632f55SGrant Likely /** 751ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 752ca632f55SGrant Likely * @pl022: SSP driver private data structure 753ca632f55SGrant Likely * 754ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 755ca632f55SGrant Likely * current spi message and returns with the state of current spi 756ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 757ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 758ca632f55SGrant Likely */ 759ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 760ca632f55SGrant Likely { 761ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 762ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 763ca632f55SGrant Likely 764ca632f55SGrant Likely /* Move to next transfer */ 765ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 766ca632f55SGrant Likely pl022->cur_transfer = 767ca632f55SGrant Likely list_entry(trans->transfer_list.next, 768ca632f55SGrant Likely struct spi_transfer, transfer_list); 769ca632f55SGrant Likely return STATE_RUNNING; 770ca632f55SGrant Likely } 771ca632f55SGrant Likely return STATE_DONE; 772ca632f55SGrant Likely } 773ca632f55SGrant Likely 774ca632f55SGrant Likely /* 775ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 776ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 777ca632f55SGrant Likely */ 778ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 779ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 780ca632f55SGrant Likely { 781ca632f55SGrant Likely /* Unmap and free the SG tables */ 782ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 783ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 784ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 785ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 786ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 787ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 788ca632f55SGrant Likely } 789ca632f55SGrant Likely 790ca632f55SGrant Likely static void dma_callback(void *data) 791ca632f55SGrant Likely { 792ca632f55SGrant Likely struct pl022 *pl022 = data; 793ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 794ca632f55SGrant Likely 795ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 796ca632f55SGrant Likely 797ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 798ca632f55SGrant Likely /* 799ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 800ca632f55SGrant Likely * good if you want to convince yourself that the loopback 801ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 802ca632f55SGrant Likely * DMA engine. 803ca632f55SGrant Likely */ 804ca632f55SGrant Likely { 805ca632f55SGrant Likely struct scatterlist *sg; 806ca632f55SGrant Likely unsigned int i; 807ca632f55SGrant Likely 808ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 809ca632f55SGrant Likely pl022->sgt_rx.sgl, 810ca632f55SGrant Likely pl022->sgt_rx.nents, 811ca632f55SGrant Likely DMA_FROM_DEVICE); 812ca632f55SGrant Likely 813ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 814ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 815ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 816ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 817ca632f55SGrant Likely 16, 818ca632f55SGrant Likely 1, 819ca632f55SGrant Likely sg_virt(sg), 820ca632f55SGrant Likely sg_dma_len(sg), 821ca632f55SGrant Likely 1); 822ca632f55SGrant Likely } 823ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 824ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 825ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 826ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 827ca632f55SGrant Likely 16, 828ca632f55SGrant Likely 1, 829ca632f55SGrant Likely sg_virt(sg), 830ca632f55SGrant Likely sg_dma_len(sg), 831ca632f55SGrant Likely 1); 832ca632f55SGrant Likely } 833ca632f55SGrant Likely } 834ca632f55SGrant Likely #endif 835ca632f55SGrant Likely 836ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 837ca632f55SGrant Likely 838ca632f55SGrant Likely /* Update total bytes transferred */ 839ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 840ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 841f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 842ca632f55SGrant Likely 843ca632f55SGrant Likely /* Move to next transfer */ 844ca632f55SGrant Likely msg->state = next_transfer(pl022); 845ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 846ca632f55SGrant Likely } 847ca632f55SGrant Likely 848ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 849ca632f55SGrant Likely void *buffer, 850ca632f55SGrant Likely unsigned int length, 851ca632f55SGrant Likely struct sg_table *sgtab) 852ca632f55SGrant Likely { 853ca632f55SGrant Likely struct scatterlist *sg; 854ca632f55SGrant Likely int bytesleft = length; 855ca632f55SGrant Likely void *bufp = buffer; 856ca632f55SGrant Likely int mapbytes; 857ca632f55SGrant Likely int i; 858ca632f55SGrant Likely 859ca632f55SGrant Likely if (buffer) { 860ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 861ca632f55SGrant Likely /* 862ca632f55SGrant Likely * If there are less bytes left than what fits 863ca632f55SGrant Likely * in the current page (plus page alignment offset) 864ca632f55SGrant Likely * we just feed in this, else we stuff in as much 865ca632f55SGrant Likely * as we can. 866ca632f55SGrant Likely */ 867ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 868ca632f55SGrant Likely mapbytes = bytesleft; 869ca632f55SGrant Likely else 870ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 871ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 872ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 873ca632f55SGrant Likely bufp += mapbytes; 874ca632f55SGrant Likely bytesleft -= mapbytes; 875ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 876ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 877ca632f55SGrant Likely bufp, mapbytes, bytesleft); 878ca632f55SGrant Likely } 879ca632f55SGrant Likely } else { 880ca632f55SGrant Likely /* Map the dummy buffer on every page */ 881ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 882ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 883ca632f55SGrant Likely mapbytes = bytesleft; 884ca632f55SGrant Likely else 885ca632f55SGrant Likely mapbytes = PAGE_SIZE; 886ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 887ca632f55SGrant Likely mapbytes, 0); 888ca632f55SGrant Likely bytesleft -= mapbytes; 889ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 890ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 891ca632f55SGrant Likely mapbytes, bytesleft); 892ca632f55SGrant Likely 893ca632f55SGrant Likely } 894ca632f55SGrant Likely } 895ca632f55SGrant Likely BUG_ON(bytesleft); 896ca632f55SGrant Likely } 897ca632f55SGrant Likely 898ca632f55SGrant Likely /** 899ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 900ca632f55SGrant Likely * @pl022: SSP driver's private data structure 901ca632f55SGrant Likely */ 902ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 903ca632f55SGrant Likely { 904ca632f55SGrant Likely struct dma_slave_config rx_conf = { 905ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 906a485df4bSVinod Koul .direction = DMA_DEV_TO_MEM, 907258aea76SViresh Kumar .device_fc = false, 908ca632f55SGrant Likely }; 909ca632f55SGrant Likely struct dma_slave_config tx_conf = { 910ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 911a485df4bSVinod Koul .direction = DMA_MEM_TO_DEV, 912258aea76SViresh Kumar .device_fc = false, 913ca632f55SGrant Likely }; 914ca632f55SGrant Likely unsigned int pages; 915ca632f55SGrant Likely int ret; 916ca632f55SGrant Likely int rx_sglen, tx_sglen; 917ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 918ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 919ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 920ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 921ca632f55SGrant Likely 922ca632f55SGrant Likely /* Check that the channels are available */ 923ca632f55SGrant Likely if (!rxchan || !txchan) 924ca632f55SGrant Likely return -ENODEV; 925ca632f55SGrant Likely 926083be3f0SLinus Walleij /* 927083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 928083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 929083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 930083be3f0SLinus Walleij * calculation. 931083be3f0SLinus Walleij */ 932083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 933083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 934083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 935083be3f0SLinus Walleij break; 936083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 937083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 938083be3f0SLinus Walleij break; 939083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 940083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 941083be3f0SLinus Walleij break; 942083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 943083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 944083be3f0SLinus Walleij break; 945083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 946083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 947083be3f0SLinus Walleij break; 948083be3f0SLinus Walleij default: 949083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 950083be3f0SLinus Walleij break; 951083be3f0SLinus Walleij } 952083be3f0SLinus Walleij 953083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 954083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 955083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 956083be3f0SLinus Walleij break; 957083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 958083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 959083be3f0SLinus Walleij break; 960083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 961083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 962083be3f0SLinus Walleij break; 963083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 964083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 965083be3f0SLinus Walleij break; 966083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 967083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 968083be3f0SLinus Walleij break; 969083be3f0SLinus Walleij default: 970083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 971083be3f0SLinus Walleij break; 972083be3f0SLinus Walleij } 973083be3f0SLinus Walleij 974ca632f55SGrant Likely switch (pl022->read) { 975ca632f55SGrant Likely case READING_NULL: 976ca632f55SGrant Likely /* Use the same as for writing */ 977ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 978ca632f55SGrant Likely break; 979ca632f55SGrant Likely case READING_U8: 980ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 981ca632f55SGrant Likely break; 982ca632f55SGrant Likely case READING_U16: 983ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 984ca632f55SGrant Likely break; 985ca632f55SGrant Likely case READING_U32: 986ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 987ca632f55SGrant Likely break; 988ca632f55SGrant Likely } 989ca632f55SGrant Likely 990ca632f55SGrant Likely switch (pl022->write) { 991ca632f55SGrant Likely case WRITING_NULL: 992ca632f55SGrant Likely /* Use the same as for reading */ 993ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 994ca632f55SGrant Likely break; 995ca632f55SGrant Likely case WRITING_U8: 996ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 997ca632f55SGrant Likely break; 998ca632f55SGrant Likely case WRITING_U16: 999ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1000ca632f55SGrant Likely break; 1001ca632f55SGrant Likely case WRITING_U32: 1002ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1003ca632f55SGrant Likely break; 1004ca632f55SGrant Likely } 1005ca632f55SGrant Likely 1006ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 1007ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1008ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 1009ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1010ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 1011ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1012ca632f55SGrant Likely 1013ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 1014ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely /* Create sglists for the transfers */ 1017b181565eSViresh Kumar pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1018ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1019ca632f55SGrant Likely 1020538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1021ca632f55SGrant Likely if (ret) 1022ca632f55SGrant Likely goto err_alloc_rx_sg; 1023ca632f55SGrant Likely 1024538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1025ca632f55SGrant Likely if (ret) 1026ca632f55SGrant Likely goto err_alloc_tx_sg; 1027ca632f55SGrant Likely 1028ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1029ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1030ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1031ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1032ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1033ca632f55SGrant Likely 1034ca632f55SGrant Likely /* Map DMA buffers */ 1035ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1036ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1037ca632f55SGrant Likely if (!rx_sglen) 1038ca632f55SGrant Likely goto err_rx_sgmap; 1039ca632f55SGrant Likely 1040ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1041ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1042ca632f55SGrant Likely if (!tx_sglen) 1043ca632f55SGrant Likely goto err_tx_sgmap; 1044ca632f55SGrant Likely 1045ca632f55SGrant Likely /* Send both scatterlists */ 104616052827SAlexandre Bounine rxdesc = dmaengine_prep_slave_sg(rxchan, 1047ca632f55SGrant Likely pl022->sgt_rx.sgl, 1048ca632f55SGrant Likely rx_sglen, 1049a485df4bSVinod Koul DMA_DEV_TO_MEM, 1050ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1051ca632f55SGrant Likely if (!rxdesc) 1052ca632f55SGrant Likely goto err_rxdesc; 1053ca632f55SGrant Likely 105416052827SAlexandre Bounine txdesc = dmaengine_prep_slave_sg(txchan, 1055ca632f55SGrant Likely pl022->sgt_tx.sgl, 1056ca632f55SGrant Likely tx_sglen, 1057a485df4bSVinod Koul DMA_MEM_TO_DEV, 1058ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1059ca632f55SGrant Likely if (!txdesc) 1060ca632f55SGrant Likely goto err_txdesc; 1061ca632f55SGrant Likely 1062ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1063ca632f55SGrant Likely rxdesc->callback = dma_callback; 1064ca632f55SGrant Likely rxdesc->callback_param = pl022; 1065ca632f55SGrant Likely 1066ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1067ca632f55SGrant Likely dmaengine_submit(rxdesc); 1068ca632f55SGrant Likely dmaengine_submit(txdesc); 1069ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1070ca632f55SGrant Likely dma_async_issue_pending(txchan); 1071ffbbdd21SLinus Walleij pl022->dma_running = true; 1072ca632f55SGrant Likely 1073ca632f55SGrant Likely return 0; 1074ca632f55SGrant Likely 1075ca632f55SGrant Likely err_txdesc: 1076ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1077ca632f55SGrant Likely err_rxdesc: 1078ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1079ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1080ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1081ca632f55SGrant Likely err_tx_sgmap: 1082ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1083ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1084ca632f55SGrant Likely err_rx_sgmap: 1085ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1086ca632f55SGrant Likely err_alloc_tx_sg: 1087ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1088ca632f55SGrant Likely err_alloc_rx_sg: 1089ca632f55SGrant Likely return -ENOMEM; 1090ca632f55SGrant Likely } 1091ca632f55SGrant Likely 1092fd4a319bSGrant Likely static int pl022_dma_probe(struct pl022 *pl022) 1093ca632f55SGrant Likely { 1094ca632f55SGrant Likely dma_cap_mask_t mask; 1095ca632f55SGrant Likely 1096ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1097ca632f55SGrant Likely dma_cap_zero(mask); 1098ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1099ca632f55SGrant Likely /* 1100ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1101ca632f55SGrant Likely * of them. 1102ca632f55SGrant Likely */ 1103ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1104ca632f55SGrant Likely pl022->master_info->dma_filter, 1105ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1106ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1107ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1108ca632f55SGrant Likely goto err_no_rxchan; 1109ca632f55SGrant Likely } 1110ca632f55SGrant Likely 1111ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1112ca632f55SGrant Likely pl022->master_info->dma_filter, 1113ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1114ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1115ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1116ca632f55SGrant Likely goto err_no_txchan; 1117ca632f55SGrant Likely } 1118ca632f55SGrant Likely 1119ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1120ca632f55SGrant Likely if (!pl022->dummypage) { 1121ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1122ca632f55SGrant Likely goto err_no_dummypage; 1123ca632f55SGrant Likely } 1124ca632f55SGrant Likely 1125ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1126ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1127ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1128ca632f55SGrant Likely 1129ca632f55SGrant Likely return 0; 1130ca632f55SGrant Likely 1131ca632f55SGrant Likely err_no_dummypage: 1132ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1133ca632f55SGrant Likely err_no_txchan: 1134ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1135ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1136ca632f55SGrant Likely err_no_rxchan: 1137ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1138ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1139ca632f55SGrant Likely return -ENODEV; 1140ca632f55SGrant Likely } 1141ca632f55SGrant Likely 1142dc715452SArnd Bergmann static int pl022_dma_autoprobe(struct pl022 *pl022) 1143dc715452SArnd Bergmann { 1144dc715452SArnd Bergmann struct device *dev = &pl022->adev->dev; 1145dc715452SArnd Bergmann 1146dc715452SArnd Bergmann /* automatically configure DMA channels from platform, normally using DT */ 1147dc715452SArnd Bergmann pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx"); 1148dc715452SArnd Bergmann if (!pl022->dma_rx_channel) 1149dc715452SArnd Bergmann goto err_no_rxchan; 1150dc715452SArnd Bergmann 1151dc715452SArnd Bergmann pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx"); 1152dc715452SArnd Bergmann if (!pl022->dma_tx_channel) 1153dc715452SArnd Bergmann goto err_no_txchan; 1154dc715452SArnd Bergmann 1155dc715452SArnd Bergmann pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1156dc715452SArnd Bergmann if (!pl022->dummypage) 1157dc715452SArnd Bergmann goto err_no_dummypage; 1158dc715452SArnd Bergmann 1159dc715452SArnd Bergmann return 0; 1160dc715452SArnd Bergmann 1161dc715452SArnd Bergmann err_no_dummypage: 1162dc715452SArnd Bergmann dma_release_channel(pl022->dma_tx_channel); 1163dc715452SArnd Bergmann pl022->dma_tx_channel = NULL; 1164dc715452SArnd Bergmann err_no_txchan: 1165dc715452SArnd Bergmann dma_release_channel(pl022->dma_rx_channel); 1166dc715452SArnd Bergmann pl022->dma_rx_channel = NULL; 1167dc715452SArnd Bergmann err_no_rxchan: 1168dc715452SArnd Bergmann return -ENODEV; 1169dc715452SArnd Bergmann } 1170dc715452SArnd Bergmann 1171ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1172ca632f55SGrant Likely { 1173ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1174ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1175ca632f55SGrant Likely 1176ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1177ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1178ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1179ffbbdd21SLinus Walleij pl022->dma_running = false; 1180ca632f55SGrant Likely } 1181ca632f55SGrant Likely 1182ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1183ca632f55SGrant Likely { 1184ffbbdd21SLinus Walleij if (pl022->dma_running) 1185ca632f55SGrant Likely terminate_dma(pl022); 1186ca632f55SGrant Likely if (pl022->dma_tx_channel) 1187ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1188ca632f55SGrant Likely if (pl022->dma_rx_channel) 1189ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1190ca632f55SGrant Likely kfree(pl022->dummypage); 1191ca632f55SGrant Likely } 1192ca632f55SGrant Likely 1193ca632f55SGrant Likely #else 1194ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1195ca632f55SGrant Likely { 1196ca632f55SGrant Likely return -ENODEV; 1197ca632f55SGrant Likely } 1198ca632f55SGrant Likely 1199dc715452SArnd Bergmann static inline int pl022_dma_autoprobe(struct pl022 *pl022) 1200dc715452SArnd Bergmann { 1201dc715452SArnd Bergmann return 0; 1202dc715452SArnd Bergmann } 1203dc715452SArnd Bergmann 1204ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1205ca632f55SGrant Likely { 1206ca632f55SGrant Likely return 0; 1207ca632f55SGrant Likely } 1208ca632f55SGrant Likely 1209ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1210ca632f55SGrant Likely { 1211ca632f55SGrant Likely } 1212ca632f55SGrant Likely #endif 1213ca632f55SGrant Likely 1214ca632f55SGrant Likely /** 1215ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1216ca632f55SGrant Likely * 1217ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1218ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1219ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1220ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1221ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1222ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1223ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1224ca632f55SGrant Likely */ 1225ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1226ca632f55SGrant Likely { 1227ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1228ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1229ca632f55SGrant Likely u16 irq_status = 0; 1230ca632f55SGrant Likely u16 flag = 0; 1231ca632f55SGrant Likely 1232ca632f55SGrant Likely if (unlikely(!msg)) { 1233ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1234ca632f55SGrant Likely "bad message state in interrupt handler"); 1235ca632f55SGrant Likely /* Never fail */ 1236ca632f55SGrant Likely return IRQ_HANDLED; 1237ca632f55SGrant Likely } 1238ca632f55SGrant Likely 1239ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1240ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1241ca632f55SGrant Likely 1242ca632f55SGrant Likely if (unlikely(!irq_status)) 1243ca632f55SGrant Likely return IRQ_NONE; 1244ca632f55SGrant Likely 1245ca632f55SGrant Likely /* 1246ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1247ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1248ca632f55SGrant Likely * trusted. 1249ca632f55SGrant Likely */ 1250ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1251ca632f55SGrant Likely /* 1252ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1253ca632f55SGrant Likely * corrupted 1254ca632f55SGrant Likely */ 1255ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1256ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1257ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1258ca632f55SGrant Likely "RXFIFO is full\n"); 1259ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1260ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1261ca632f55SGrant Likely "TXFIFO is full\n"); 1262ca632f55SGrant Likely 1263ca632f55SGrant Likely /* 1264ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1265ca632f55SGrant Likely * mark message with bad status so it can be 1266ca632f55SGrant Likely * retried. 1267ca632f55SGrant Likely */ 1268ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1269ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1270ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1271ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1272ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1273ca632f55SGrant Likely msg->state = STATE_ERROR; 1274ca632f55SGrant Likely 1275ca632f55SGrant Likely /* Schedule message queue handler */ 1276ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1277ca632f55SGrant Likely return IRQ_HANDLED; 1278ca632f55SGrant Likely } 1279ca632f55SGrant Likely 1280ca632f55SGrant Likely readwriter(pl022); 1281ca632f55SGrant Likely 1282ca632f55SGrant Likely if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1283ca632f55SGrant Likely flag = 1; 1284172289dfSChris Blair /* Disable Transmit interrupt, enable receive interrupt */ 1285172289dfSChris Blair writew((readw(SSP_IMSC(pl022->virtbase)) & 1286172289dfSChris Blair ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1287ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1288ca632f55SGrant Likely } 1289ca632f55SGrant Likely 1290ca632f55SGrant Likely /* 1291ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1292ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1293ca632f55SGrant Likely * At this point, all TX will always be finished. 1294ca632f55SGrant Likely */ 1295ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1296ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1297ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1298ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1299ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1300ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1301ca632f55SGrant Likely "bytes (did you request an odd " 1302ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1303ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1304ca632f55SGrant Likely } 1305ca632f55SGrant Likely /* Update total bytes transferred */ 1306ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1307ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1308f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1309ca632f55SGrant Likely /* Move to next transfer */ 1310ca632f55SGrant Likely msg->state = next_transfer(pl022); 1311ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1312ca632f55SGrant Likely return IRQ_HANDLED; 1313ca632f55SGrant Likely } 1314ca632f55SGrant Likely 1315ca632f55SGrant Likely return IRQ_HANDLED; 1316ca632f55SGrant Likely } 1317ca632f55SGrant Likely 1318ca632f55SGrant Likely /** 1319ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1320ca632f55SGrant Likely * send out on the SPI bus. 1321ca632f55SGrant Likely */ 1322ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1323ca632f55SGrant Likely struct spi_transfer *transfer) 1324ca632f55SGrant Likely { 1325ca632f55SGrant Likely int residue; 1326ca632f55SGrant Likely 1327ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1328ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1329ca632f55SGrant Likely if (unlikely(residue != 0)) { 1330ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1331ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1332ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1333ca632f55SGrant Likely pl022->cur_transfer->len, 1334ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1335ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1336ca632f55SGrant Likely return -EIO; 1337ca632f55SGrant Likely } 1338ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1339ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1340ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1341ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1342ca632f55SGrant Likely pl022->write = 1343ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1344ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1345ca632f55SGrant Likely return 0; 1346ca632f55SGrant Likely } 1347ca632f55SGrant Likely 1348ca632f55SGrant Likely /** 1349ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1350ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1351ca632f55SGrant Likely * @data: SSP driver private data structure 1352ca632f55SGrant Likely * 1353ca632f55SGrant Likely */ 1354ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1355ca632f55SGrant Likely { 1356ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1357ca632f55SGrant Likely struct spi_message *message = NULL; 1358ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1359ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1360ca632f55SGrant Likely 1361ca632f55SGrant Likely /* Get current state information */ 1362ca632f55SGrant Likely message = pl022->cur_msg; 1363ca632f55SGrant Likely transfer = pl022->cur_transfer; 1364ca632f55SGrant Likely 1365ca632f55SGrant Likely /* Handle for abort */ 1366ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1367ca632f55SGrant Likely message->status = -EIO; 1368ca632f55SGrant Likely giveback(pl022); 1369ca632f55SGrant Likely return; 1370ca632f55SGrant Likely } 1371ca632f55SGrant Likely 1372ca632f55SGrant Likely /* Handle end of message */ 1373ca632f55SGrant Likely if (message->state == STATE_DONE) { 1374ca632f55SGrant Likely message->status = 0; 1375ca632f55SGrant Likely giveback(pl022); 1376ca632f55SGrant Likely return; 1377ca632f55SGrant Likely } 1378ca632f55SGrant Likely 1379ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1380ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1381ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1382ca632f55SGrant Likely struct spi_transfer, 1383ca632f55SGrant Likely transfer_list); 1384ca632f55SGrant Likely if (previous->delay_usecs) 1385ca632f55SGrant Likely /* 1386ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1387ca632f55SGrant Likely * Is this really smart? 1388ca632f55SGrant Likely */ 1389ca632f55SGrant Likely udelay(previous->delay_usecs); 1390ca632f55SGrant Likely 13918b8d7191SVirupax Sadashivpetimath /* Reselect chip select only if cs_change was requested */ 1392ca632f55SGrant Likely if (previous->cs_change) 1393f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1394ca632f55SGrant Likely } else { 1395ca632f55SGrant Likely /* STATE_START */ 1396ca632f55SGrant Likely message->state = STATE_RUNNING; 1397ca632f55SGrant Likely } 1398ca632f55SGrant Likely 1399ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1400ca632f55SGrant Likely message->state = STATE_ERROR; 1401ca632f55SGrant Likely message->status = -EIO; 1402ca632f55SGrant Likely giveback(pl022); 1403ca632f55SGrant Likely return; 1404ca632f55SGrant Likely } 1405ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1406ca632f55SGrant Likely flush(pl022); 1407ca632f55SGrant Likely 1408ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1409ca632f55SGrant Likely if (configure_dma(pl022)) { 1410ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1411ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1412ca632f55SGrant Likely goto err_config_dma; 1413ca632f55SGrant Likely } 1414ca632f55SGrant Likely return; 1415ca632f55SGrant Likely } 1416ca632f55SGrant Likely 1417ca632f55SGrant Likely err_config_dma: 1418172289dfSChris Blair /* enable all interrupts except RX */ 1419172289dfSChris Blair writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1420ca632f55SGrant Likely } 1421ca632f55SGrant Likely 1422ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1423ca632f55SGrant Likely { 1424172289dfSChris Blair /* 1425172289dfSChris Blair * Default is to enable all interrupts except RX - 1426172289dfSChris Blair * this will be enabled once TX is complete 1427172289dfSChris Blair */ 1428172289dfSChris Blair u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1429ca632f55SGrant Likely 14308b8d7191SVirupax Sadashivpetimath /* Enable target chip, if not already active */ 14318b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1432f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 14338b8d7191SVirupax Sadashivpetimath 1434ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1435ca632f55SGrant Likely /* Error path */ 1436ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1437ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1438ca632f55SGrant Likely giveback(pl022); 1439ca632f55SGrant Likely return; 1440ca632f55SGrant Likely } 1441ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1442ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1443ca632f55SGrant Likely /* Configure DMA transfer */ 1444ca632f55SGrant Likely if (configure_dma(pl022)) { 1445ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1446ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1447ca632f55SGrant Likely goto err_config_dma; 1448ca632f55SGrant Likely } 1449ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1450ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1451ca632f55SGrant Likely } 1452ca632f55SGrant Likely err_config_dma: 1453ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1454ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1455ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1456ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1457ca632f55SGrant Likely } 1458ca632f55SGrant Likely 1459ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1460ca632f55SGrant Likely { 1461ca632f55SGrant Likely struct spi_message *message = NULL; 1462ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1463ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1464ca632f55SGrant Likely struct chip_data *chip; 1465ca632f55SGrant Likely unsigned long time, timeout; 1466ca632f55SGrant Likely 1467ca632f55SGrant Likely chip = pl022->cur_chip; 1468ca632f55SGrant Likely message = pl022->cur_msg; 1469ca632f55SGrant Likely 1470ca632f55SGrant Likely while (message->state != STATE_DONE) { 1471ca632f55SGrant Likely /* Handle for abort */ 1472ca632f55SGrant Likely if (message->state == STATE_ERROR) 1473ca632f55SGrant Likely break; 1474ca632f55SGrant Likely transfer = pl022->cur_transfer; 1475ca632f55SGrant Likely 1476ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1477ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1478ca632f55SGrant Likely previous = 1479ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1480ca632f55SGrant Likely struct spi_transfer, transfer_list); 1481ca632f55SGrant Likely if (previous->delay_usecs) 1482ca632f55SGrant Likely udelay(previous->delay_usecs); 1483ca632f55SGrant Likely if (previous->cs_change) 1484f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1485ca632f55SGrant Likely } else { 1486ca632f55SGrant Likely /* STATE_START */ 1487ca632f55SGrant Likely message->state = STATE_RUNNING; 14888b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1489f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1490ca632f55SGrant Likely } 1491ca632f55SGrant Likely 1492ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1493ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1494ca632f55SGrant Likely /* Error path */ 1495ca632f55SGrant Likely message->state = STATE_ERROR; 1496ca632f55SGrant Likely break; 1497ca632f55SGrant Likely } 1498ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1499ca632f55SGrant Likely flush(pl022); 1500ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1501ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1502ca632f55SGrant Likely 1503ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1504ca632f55SGrant Likely 1505ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1506ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1507ca632f55SGrant Likely time = jiffies; 1508ca632f55SGrant Likely readwriter(pl022); 1509ca632f55SGrant Likely if (time_after(time, timeout)) { 1510ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1511ca632f55SGrant Likely "%s: timeout!\n", __func__); 1512ca632f55SGrant Likely message->state = STATE_ERROR; 1513ca632f55SGrant Likely goto out; 1514ca632f55SGrant Likely } 1515ca632f55SGrant Likely cpu_relax(); 1516ca632f55SGrant Likely } 1517ca632f55SGrant Likely 1518ca632f55SGrant Likely /* Update total byte transferred */ 1519ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1520ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1521f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1522ca632f55SGrant Likely /* Move to next transfer */ 1523ca632f55SGrant Likely message->state = next_transfer(pl022); 1524ca632f55SGrant Likely } 1525ca632f55SGrant Likely out: 1526ca632f55SGrant Likely /* Handle end of message */ 1527ca632f55SGrant Likely if (message->state == STATE_DONE) 1528ca632f55SGrant Likely message->status = 0; 1529ca632f55SGrant Likely else 1530ca632f55SGrant Likely message->status = -EIO; 1531ca632f55SGrant Likely 1532ca632f55SGrant Likely giveback(pl022); 1533ca632f55SGrant Likely return; 1534ca632f55SGrant Likely } 1535ca632f55SGrant Likely 1536ffbbdd21SLinus Walleij static int pl022_transfer_one_message(struct spi_master *master, 1537ffbbdd21SLinus Walleij struct spi_message *msg) 1538ca632f55SGrant Likely { 1539ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1540ca632f55SGrant Likely 1541ffbbdd21SLinus Walleij /* Initial message state */ 1542ffbbdd21SLinus Walleij pl022->cur_msg = msg; 1543ffbbdd21SLinus Walleij msg->state = STATE_START; 1544ffbbdd21SLinus Walleij 1545ffbbdd21SLinus Walleij pl022->cur_transfer = list_entry(msg->transfers.next, 1546ffbbdd21SLinus Walleij struct spi_transfer, transfer_list); 1547ffbbdd21SLinus Walleij 1548ffbbdd21SLinus Walleij /* Setup the SPI using the per chip configuration */ 1549ffbbdd21SLinus Walleij pl022->cur_chip = spi_get_ctldata(msg->spi); 1550f6f46de1SRoland Stigge pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1551ffbbdd21SLinus Walleij 1552ffbbdd21SLinus Walleij restore_state(pl022); 1553ffbbdd21SLinus Walleij flush(pl022); 1554ffbbdd21SLinus Walleij 1555ffbbdd21SLinus Walleij if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1556ffbbdd21SLinus Walleij do_polling_transfer(pl022); 1557ffbbdd21SLinus Walleij else 1558ffbbdd21SLinus Walleij do_interrupt_dma_transfer(pl022); 1559ffbbdd21SLinus Walleij 1560ffbbdd21SLinus Walleij return 0; 1561ffbbdd21SLinus Walleij } 1562ffbbdd21SLinus Walleij 1563ffbbdd21SLinus Walleij static int pl022_prepare_transfer_hardware(struct spi_master *master) 1564ffbbdd21SLinus Walleij { 1565ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1566ffbbdd21SLinus Walleij 1567ffbbdd21SLinus Walleij /* 1568ffbbdd21SLinus Walleij * Just make sure we have all we need to run the transfer by syncing 1569ffbbdd21SLinus Walleij * with the runtime PM framework. 1570ffbbdd21SLinus Walleij */ 1571ffbbdd21SLinus Walleij pm_runtime_get_sync(&pl022->adev->dev); 1572ffbbdd21SLinus Walleij return 0; 1573ffbbdd21SLinus Walleij } 1574ffbbdd21SLinus Walleij 1575ffbbdd21SLinus Walleij static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1576ffbbdd21SLinus Walleij { 1577ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1578ffbbdd21SLinus Walleij 15790ad2deeaSVirupax Sadashivpetimath /* nothing more to do - disable spi/ssp and power off */ 15800ad2deeaSVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 15810ad2deeaSVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 158253e4aceaSChris Blair 158353e4aceaSChris Blair if (pl022->master_info->autosuspend_delay > 0) { 158453e4aceaSChris Blair pm_runtime_mark_last_busy(&pl022->adev->dev); 158553e4aceaSChris Blair pm_runtime_put_autosuspend(&pl022->adev->dev); 158653e4aceaSChris Blair } else { 1587d4b6af2eSChris Blair pm_runtime_put(&pl022->adev->dev); 15880ad2deeaSVirupax Sadashivpetimath } 1589ca632f55SGrant Likely 1590ca632f55SGrant Likely return 0; 1591ca632f55SGrant Likely } 1592ca632f55SGrant Likely 1593ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1594ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1595ca632f55SGrant Likely { 1596ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1597ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1598ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1599ca632f55SGrant Likely "interface is configured incorrectly\n"); 1600ca632f55SGrant Likely return -EINVAL; 1601ca632f55SGrant Likely } 1602ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1603ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1604ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1605ca632f55SGrant Likely "unidirectional mode not supported in this " 1606ca632f55SGrant Likely "hardware version\n"); 1607ca632f55SGrant Likely return -EINVAL; 1608ca632f55SGrant Likely } 1609ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1610ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1611ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1612ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1613ca632f55SGrant Likely return -EINVAL; 1614ca632f55SGrant Likely } 1615ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1616ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1617ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1618ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1619ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1620ca632f55SGrant Likely return -EINVAL; 1621ca632f55SGrant Likely } 162278b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 162378b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 162478b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 162578b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 162678b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 162778b2b911SLinus Walleij break; 162878b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 162978b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1630ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1631ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1632ca632f55SGrant Likely return -EINVAL; 1633ca632f55SGrant Likely } 163478b2b911SLinus Walleij break; 163578b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 163678b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 163778b2b911SLinus Walleij dev_err(&pl022->adev->dev, 163878b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 163978b2b911SLinus Walleij return -EINVAL; 164078b2b911SLinus Walleij } 164178b2b911SLinus Walleij break; 164278b2b911SLinus Walleij default: 164378b2b911SLinus Walleij dev_err(&pl022->adev->dev, 164478b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 164578b2b911SLinus Walleij return -EINVAL; 164678b2b911SLinus Walleij break; 164778b2b911SLinus Walleij } 164878b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 164978b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 165078b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 165178b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 165278b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 165378b2b911SLinus Walleij break; 165478b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 165578b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1656ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1657ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1658ca632f55SGrant Likely return -EINVAL; 1659ca632f55SGrant Likely } 166078b2b911SLinus Walleij break; 166178b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 166278b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 166378b2b911SLinus Walleij dev_err(&pl022->adev->dev, 166478b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 166578b2b911SLinus Walleij return -EINVAL; 166678b2b911SLinus Walleij } 166778b2b911SLinus Walleij break; 166878b2b911SLinus Walleij default: 166978b2b911SLinus Walleij dev_err(&pl022->adev->dev, 167078b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 167178b2b911SLinus Walleij return -EINVAL; 167278b2b911SLinus Walleij break; 167378b2b911SLinus Walleij } 1674ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1675ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1676ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1677ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1678ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1679ca632f55SGrant Likely return -EINVAL; 1680ca632f55SGrant Likely } 1681ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1682ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1683ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1684ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1685ca632f55SGrant Likely return -EINVAL; 1686ca632f55SGrant Likely } 1687ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1688ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1689ca632f55SGrant Likely if ((chip_info->duplex != 1690ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1691ca632f55SGrant Likely && (chip_info->duplex != 1692ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1693ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1694ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1695ca632f55SGrant Likely return -EINVAL; 1696ca632f55SGrant Likely } 1697ca632f55SGrant Likely } else { 1698ca632f55SGrant Likely if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1699ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1700ca632f55SGrant Likely "Microwire half duplex mode requested," 1701ca632f55SGrant Likely " but this is only available in the" 1702ca632f55SGrant Likely " ST version of PL022\n"); 1703ca632f55SGrant Likely return -EINVAL; 1704ca632f55SGrant Likely } 1705ca632f55SGrant Likely } 1706ca632f55SGrant Likely return 0; 1707ca632f55SGrant Likely } 1708ca632f55SGrant Likely 17090379b2a3SViresh Kumar static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 17100379b2a3SViresh Kumar { 17110379b2a3SViresh Kumar return rate / (cpsdvsr * (1 + scr)); 17120379b2a3SViresh Kumar } 17130379b2a3SViresh Kumar 17140379b2a3SViresh Kumar static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 17150379b2a3SViresh Kumar ssp_clock_params * clk_freq) 1716ca632f55SGrant Likely { 1717ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 17180379b2a3SViresh Kumar u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 17190379b2a3SViresh Kumar u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 17200379b2a3SViresh Kumar best_scr = 0, tmp, found = 0; 1721ca632f55SGrant Likely 1722ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1723ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 17240379b2a3SViresh Kumar max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1725ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 17260379b2a3SViresh Kumar min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1727ca632f55SGrant Likely 1728ea505bc9SViresh Kumar if (freq > max_tclk) 1729ea505bc9SViresh Kumar dev_warn(&pl022->adev->dev, 1730ea505bc9SViresh Kumar "Max speed that can be programmed is %d Hz, you requested %d\n", 1731ea505bc9SViresh Kumar max_tclk, freq); 1732ea505bc9SViresh Kumar 1733ea505bc9SViresh Kumar if (freq < min_tclk) { 1734ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1735ea505bc9SViresh Kumar "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1736ea505bc9SViresh Kumar freq, min_tclk); 1737ca632f55SGrant Likely return -EINVAL; 1738ca632f55SGrant Likely } 17390379b2a3SViresh Kumar 17400379b2a3SViresh Kumar /* 17410379b2a3SViresh Kumar * best_freq will give closest possible available rate (<= requested 17420379b2a3SViresh Kumar * freq) for all values of scr & cpsdvsr. 17430379b2a3SViresh Kumar */ 17440379b2a3SViresh Kumar while ((cpsdvsr <= CPSDVR_MAX) && !found) { 17450379b2a3SViresh Kumar while (scr <= SCR_MAX) { 17460379b2a3SViresh Kumar tmp = spi_rate(rate, cpsdvsr, scr); 17470379b2a3SViresh Kumar 17485eb806a3SViresh Kumar if (tmp > freq) { 17495eb806a3SViresh Kumar /* we need lower freq */ 17500379b2a3SViresh Kumar scr++; 17515eb806a3SViresh Kumar continue; 17525eb806a3SViresh Kumar } 17535eb806a3SViresh Kumar 17540379b2a3SViresh Kumar /* 17555eb806a3SViresh Kumar * If found exact value, mark found and break. 17565eb806a3SViresh Kumar * If found more closer value, update and break. 17570379b2a3SViresh Kumar */ 17585eb806a3SViresh Kumar if (tmp > best_freq) { 17590379b2a3SViresh Kumar best_freq = tmp; 17600379b2a3SViresh Kumar best_cpsdvsr = cpsdvsr; 17610379b2a3SViresh Kumar best_scr = scr; 17620379b2a3SViresh Kumar 17630379b2a3SViresh Kumar if (tmp == freq) 17645eb806a3SViresh Kumar found = 1; 17650379b2a3SViresh Kumar } 17665eb806a3SViresh Kumar /* 17675eb806a3SViresh Kumar * increased scr will give lower rates, which are not 17685eb806a3SViresh Kumar * required 17695eb806a3SViresh Kumar */ 17705eb806a3SViresh Kumar break; 17710379b2a3SViresh Kumar } 17720379b2a3SViresh Kumar cpsdvsr += 2; 17730379b2a3SViresh Kumar scr = SCR_MIN; 1774ca632f55SGrant Likely } 1775ca632f55SGrant Likely 17765eb806a3SViresh Kumar WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 17775eb806a3SViresh Kumar freq); 17785eb806a3SViresh Kumar 17790379b2a3SViresh Kumar clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 17800379b2a3SViresh Kumar clk_freq->scr = (u8) (best_scr & 0xFF); 17810379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, 17820379b2a3SViresh Kumar "SSP Target Frequency is: %u, Effective Frequency is %u\n", 17830379b2a3SViresh Kumar freq, best_freq); 17840379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 17850379b2a3SViresh Kumar clk_freq->cpsdvsr, clk_freq->scr); 17860379b2a3SViresh Kumar 1787ca632f55SGrant Likely return 0; 1788ca632f55SGrant Likely } 1789ca632f55SGrant Likely 1790ca632f55SGrant Likely /* 1791ca632f55SGrant Likely * A piece of default chip info unless the platform 1792ca632f55SGrant Likely * supplies it. 1793ca632f55SGrant Likely */ 1794ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1795ca632f55SGrant Likely .com_mode = POLLING_TRANSFER, 1796ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1797ca632f55SGrant Likely .hierarchy = SSP_SLAVE, 1798ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1799ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1800ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1801ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1802ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1803ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1804ca632f55SGrant Likely .cs_control = null_cs_control, 1805ca632f55SGrant Likely }; 1806ca632f55SGrant Likely 1807ca632f55SGrant Likely /** 1808ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1809ca632f55SGrant Likely * @spi: spi device which is requesting setup 1810ca632f55SGrant Likely * 1811ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1812ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1813ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1814ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1815ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1816ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1817ca632f55SGrant Likely * commence. 1818ca632f55SGrant Likely */ 1819ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1820ca632f55SGrant Likely { 1821ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 18226d3952a7SRoland Stigge struct pl022_config_chip chip_info_dt; 1823ca632f55SGrant Likely struct chip_data *chip; 1824c4a47843SJonas Aaberg struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1825ca632f55SGrant Likely int status = 0; 1826ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1827ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1828ca632f55SGrant Likely u32 tmp; 18296d3952a7SRoland Stigge struct device_node *np = spi->dev.of_node; 1830ca632f55SGrant Likely 1831ca632f55SGrant Likely if (!spi->max_speed_hz) 1832ca632f55SGrant Likely return -EINVAL; 1833ca632f55SGrant Likely 1834ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1835ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1836ca632f55SGrant Likely 1837ca632f55SGrant Likely if (chip == NULL) { 1838ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1839ca632f55SGrant Likely if (!chip) { 1840ca632f55SGrant Likely dev_err(&spi->dev, 1841ca632f55SGrant Likely "cannot allocate controller state\n"); 1842ca632f55SGrant Likely return -ENOMEM; 1843ca632f55SGrant Likely } 1844ca632f55SGrant Likely dev_dbg(&spi->dev, 1845ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1846ca632f55SGrant Likely } 1847ca632f55SGrant Likely 1848ca632f55SGrant Likely /* Get controller data if one is supplied */ 1849ca632f55SGrant Likely chip_info = spi->controller_data; 1850ca632f55SGrant Likely 1851ca632f55SGrant Likely if (chip_info == NULL) { 18526d3952a7SRoland Stigge if (np) { 18536d3952a7SRoland Stigge chip_info_dt = pl022_default_chip_info; 18546d3952a7SRoland Stigge 18556d3952a7SRoland Stigge chip_info_dt.hierarchy = SSP_MASTER; 18566d3952a7SRoland Stigge of_property_read_u32(np, "pl022,interface", 18576d3952a7SRoland Stigge &chip_info_dt.iface); 18586d3952a7SRoland Stigge of_property_read_u32(np, "pl022,com-mode", 18596d3952a7SRoland Stigge &chip_info_dt.com_mode); 18606d3952a7SRoland Stigge of_property_read_u32(np, "pl022,rx-level-trig", 18616d3952a7SRoland Stigge &chip_info_dt.rx_lev_trig); 18626d3952a7SRoland Stigge of_property_read_u32(np, "pl022,tx-level-trig", 18636d3952a7SRoland Stigge &chip_info_dt.tx_lev_trig); 18646d3952a7SRoland Stigge of_property_read_u32(np, "pl022,ctrl-len", 18656d3952a7SRoland Stigge &chip_info_dt.ctrl_len); 18666d3952a7SRoland Stigge of_property_read_u32(np, "pl022,wait-state", 18676d3952a7SRoland Stigge &chip_info_dt.wait_state); 18686d3952a7SRoland Stigge of_property_read_u32(np, "pl022,duplex", 18696d3952a7SRoland Stigge &chip_info_dt.duplex); 18706d3952a7SRoland Stigge 18716d3952a7SRoland Stigge chip_info = &chip_info_dt; 18726d3952a7SRoland Stigge } else { 1873ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1874ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1875ca632f55SGrant Likely dev_dbg(&spi->dev, 1876ca632f55SGrant Likely "using default controller_data settings\n"); 18776d3952a7SRoland Stigge } 1878ca632f55SGrant Likely } else 1879ca632f55SGrant Likely dev_dbg(&spi->dev, 1880ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1881ca632f55SGrant Likely 1882ca632f55SGrant Likely /* 1883ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1884ca632f55SGrant Likely * frequency setting 1885ca632f55SGrant Likely */ 1886ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1887ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1888ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1889ca632f55SGrant Likely spi->max_speed_hz, 1890ca632f55SGrant Likely &clk_freq); 1891ca632f55SGrant Likely if (status < 0) 1892ca632f55SGrant Likely goto err_config_params; 1893ca632f55SGrant Likely } else { 1894ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1895ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1896ca632f55SGrant Likely clk_freq.cpsdvsr = 1897ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1898ca632f55SGrant Likely } 1899ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1900ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1901f8db4cc4SGrant Likely status = -EINVAL; 1902ca632f55SGrant Likely dev_err(&spi->dev, 1903ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1904ca632f55SGrant Likely goto err_config_params; 1905ca632f55SGrant Likely } 1906ca632f55SGrant Likely 1907ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1908ca632f55SGrant Likely if (status) { 1909ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1910ca632f55SGrant Likely goto err_config_params; 1911ca632f55SGrant Likely } 1912ca632f55SGrant Likely 1913083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1914083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1915083be3f0SLinus Walleij 1916ca632f55SGrant Likely /* Now set controller state based on controller data */ 1917ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1918ca632f55SGrant Likely if (!chip_info->cs_control) { 1919ca632f55SGrant Likely chip->cs_control = null_cs_control; 1920f6f46de1SRoland Stigge if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1921ca632f55SGrant Likely dev_warn(&spi->dev, 1922f6f46de1SRoland Stigge "invalid chip select\n"); 1923ca632f55SGrant Likely } else 1924ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1925ca632f55SGrant Likely 1926eb798c64SVinit Shenoy /* Check bits per word with vendor specific range */ 1927eb798c64SVinit Shenoy if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1928ca632f55SGrant Likely status = -ENOTSUPP; 1929eb798c64SVinit Shenoy dev_err(&spi->dev, "illegal data size for this controller!\n"); 1930eb798c64SVinit Shenoy dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1931eb798c64SVinit Shenoy pl022->vendor->max_bpw); 1932ca632f55SGrant Likely goto err_config_params; 1933ca632f55SGrant Likely } else if (bits <= 8) { 1934ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1935ca632f55SGrant Likely chip->n_bytes = 1; 1936ca632f55SGrant Likely chip->read = READING_U8; 1937ca632f55SGrant Likely chip->write = WRITING_U8; 1938ca632f55SGrant Likely } else if (bits <= 16) { 1939ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1940ca632f55SGrant Likely chip->n_bytes = 2; 1941ca632f55SGrant Likely chip->read = READING_U16; 1942ca632f55SGrant Likely chip->write = WRITING_U16; 1943ca632f55SGrant Likely } else { 1944ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1945ca632f55SGrant Likely chip->n_bytes = 4; 1946ca632f55SGrant Likely chip->read = READING_U32; 1947ca632f55SGrant Likely chip->write = WRITING_U32; 1948ca632f55SGrant Likely } 1949ca632f55SGrant Likely 1950ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 1951ca632f55SGrant Likely chip->cr0 = 0; 1952ca632f55SGrant Likely chip->cr1 = 0; 1953ca632f55SGrant Likely chip->dmacr = 0; 1954ca632f55SGrant Likely chip->cpsr = 0; 1955ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 1956ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 1957ca632f55SGrant Likely chip->enable_dma = true; 1958ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1959ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1960ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1961ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1962ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1963ca632f55SGrant Likely } else { 1964ca632f55SGrant Likely chip->enable_dma = false; 1965ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1966ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1967ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1968ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1969ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1970ca632f55SGrant Likely } 1971ca632f55SGrant Likely 1972ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 1973ca632f55SGrant Likely 1974ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 1975ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1976ca632f55SGrant Likely u32 etx; 1977ca632f55SGrant Likely 1978ca632f55SGrant Likely if (pl022->vendor->pl023) { 1979ca632f55SGrant Likely /* These bits are only in the PL023 */ 1980ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1981ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 1982ca632f55SGrant Likely } else { 1983ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 1984ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1985ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 1986ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1987ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 1988ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1989ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 1990ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1991ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 1992ca632f55SGrant Likely } 1993ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 1994ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 1995ca632f55SGrant Likely 1996ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 1997ca632f55SGrant Likely tmp = SSP_RX_LSB; 1998ca632f55SGrant Likely etx = SSP_TX_LSB; 1999ca632f55SGrant Likely } else { 2000ca632f55SGrant Likely tmp = SSP_RX_MSB; 2001ca632f55SGrant Likely etx = SSP_TX_MSB; 2002ca632f55SGrant Likely } 2003ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2004ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2005ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2006ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 2007ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2008ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 2009ca632f55SGrant Likely } else { 2010ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2011ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 2012ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2013ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 2014ca632f55SGrant Likely } 2015ca632f55SGrant Likely 2016ca632f55SGrant Likely /* Stuff that is common for all versions */ 2017ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 2018ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 2019ca632f55SGrant Likely else 2020ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 2021ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2022ca632f55SGrant Likely 2023ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 2024ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 2025ca632f55SGrant Likely else 2026ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 2027ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2028ca632f55SGrant Likely 2029ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2030ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 2031ca632f55SGrant Likely if (pl022->vendor->loopback) { 2032ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 2033ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 2034ca632f55SGrant Likely else 2035ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 2036ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2037ca632f55SGrant Likely } 2038ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2039ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2040f1e45f86SViresh Kumar SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2041f1e45f86SViresh Kumar 3); 2042ca632f55SGrant Likely 2043ca632f55SGrant Likely /* Save controller_state */ 2044ca632f55SGrant Likely spi_set_ctldata(spi, chip); 2045ca632f55SGrant Likely return status; 2046ca632f55SGrant Likely err_config_params: 2047ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2048ca632f55SGrant Likely kfree(chip); 2049ca632f55SGrant Likely return status; 2050ca632f55SGrant Likely } 2051ca632f55SGrant Likely 2052ca632f55SGrant Likely /** 2053ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 2054ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 2055ca632f55SGrant Likely * 2056ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 2057ca632f55SGrant Likely * controller. It will free the runtime state of chip. 2058ca632f55SGrant Likely */ 2059ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 2060ca632f55SGrant Likely { 2061ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 2062ca632f55SGrant Likely 2063ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2064ca632f55SGrant Likely kfree(chip); 2065ca632f55SGrant Likely } 2066ca632f55SGrant Likely 206739a6ac11SRoland Stigge static struct pl022_ssp_controller * 206839a6ac11SRoland Stigge pl022_platform_data_dt_get(struct device *dev) 206939a6ac11SRoland Stigge { 207039a6ac11SRoland Stigge struct device_node *np = dev->of_node; 207139a6ac11SRoland Stigge struct pl022_ssp_controller *pd; 207239a6ac11SRoland Stigge u32 tmp; 207339a6ac11SRoland Stigge 207439a6ac11SRoland Stigge if (!np) { 207539a6ac11SRoland Stigge dev_err(dev, "no dt node defined\n"); 207639a6ac11SRoland Stigge return NULL; 207739a6ac11SRoland Stigge } 207839a6ac11SRoland Stigge 207939a6ac11SRoland Stigge pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 208039a6ac11SRoland Stigge if (!pd) { 208139a6ac11SRoland Stigge dev_err(dev, "cannot allocate platform data memory\n"); 208239a6ac11SRoland Stigge return NULL; 208339a6ac11SRoland Stigge } 208439a6ac11SRoland Stigge 208539a6ac11SRoland Stigge pd->bus_id = -1; 2086*dbd897b9SLinus Walleij pd->enable_dma = 1; 208739a6ac11SRoland Stigge of_property_read_u32(np, "num-cs", &tmp); 208839a6ac11SRoland Stigge pd->num_chipselect = tmp; 208939a6ac11SRoland Stigge of_property_read_u32(np, "pl022,autosuspend-delay", 209039a6ac11SRoland Stigge &pd->autosuspend_delay); 209139a6ac11SRoland Stigge pd->rt = of_property_read_bool(np, "pl022,rt"); 209239a6ac11SRoland Stigge 209339a6ac11SRoland Stigge return pd; 209439a6ac11SRoland Stigge } 209539a6ac11SRoland Stigge 2096fd4a319bSGrant Likely static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2097ca632f55SGrant Likely { 2098ca632f55SGrant Likely struct device *dev = &adev->dev; 2099ca632f55SGrant Likely struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2100ca632f55SGrant Likely struct spi_master *master; 2101ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 21026d3952a7SRoland Stigge struct device_node *np = adev->dev.of_node; 21036d3952a7SRoland Stigge int status = 0, i, num_cs; 2104ca632f55SGrant Likely 2105ca632f55SGrant Likely dev_info(&adev->dev, 2106ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 210739a6ac11SRoland Stigge if (!platform_info && IS_ENABLED(CONFIG_OF)) 210839a6ac11SRoland Stigge platform_info = pl022_platform_data_dt_get(dev); 210939a6ac11SRoland Stigge 211039a6ac11SRoland Stigge if (!platform_info) { 211139a6ac11SRoland Stigge dev_err(dev, "probe: no platform data defined\n"); 2112aeef9915SLinus Walleij return -ENODEV; 2113ca632f55SGrant Likely } 2114ca632f55SGrant Likely 21156d3952a7SRoland Stigge if (platform_info->num_chipselect) { 21166d3952a7SRoland Stigge num_cs = platform_info->num_chipselect; 21176d3952a7SRoland Stigge } else { 211839a6ac11SRoland Stigge dev_err(dev, "probe: no chip select defined\n"); 2119aeef9915SLinus Walleij return -ENODEV; 21206d3952a7SRoland Stigge } 21216d3952a7SRoland Stigge 2122ca632f55SGrant Likely /* Allocate master with space for data */ 2123b4b84826SRoland Stigge master = spi_alloc_master(dev, sizeof(struct pl022)); 2124ca632f55SGrant Likely if (master == NULL) { 2125ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2126aeef9915SLinus Walleij return -ENOMEM; 2127ca632f55SGrant Likely } 2128ca632f55SGrant Likely 2129ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 2130ca632f55SGrant Likely pl022->master = master; 2131ca632f55SGrant Likely pl022->master_info = platform_info; 2132ca632f55SGrant Likely pl022->adev = adev; 2133ca632f55SGrant Likely pl022->vendor = id->data; 2134b4b84826SRoland Stigge pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2135b4b84826SRoland Stigge GFP_KERNEL); 2136ca632f55SGrant Likely 21374f5e1b37SPatrice Chotard pl022->pinctrl = devm_pinctrl_get(dev); 21384f5e1b37SPatrice Chotard if (IS_ERR(pl022->pinctrl)) { 21394f5e1b37SPatrice Chotard status = PTR_ERR(pl022->pinctrl); 21404f5e1b37SPatrice Chotard goto err_no_pinctrl; 21414f5e1b37SPatrice Chotard } 21424f5e1b37SPatrice Chotard 21434f5e1b37SPatrice Chotard pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl, 21444f5e1b37SPatrice Chotard PINCTRL_STATE_DEFAULT); 21454f5e1b37SPatrice Chotard /* enable pins to be muxed in and configured */ 21464f5e1b37SPatrice Chotard if (!IS_ERR(pl022->pins_default)) { 21474f5e1b37SPatrice Chotard status = pinctrl_select_state(pl022->pinctrl, 21484f5e1b37SPatrice Chotard pl022->pins_default); 21494f5e1b37SPatrice Chotard if (status) 21504f5e1b37SPatrice Chotard dev_err(dev, "could not set default pins\n"); 21514f5e1b37SPatrice Chotard } else 21524f5e1b37SPatrice Chotard dev_err(dev, "could not get default pinstate\n"); 21534f5e1b37SPatrice Chotard 2154d8f18420SPatrice Chotard pl022->pins_idle = pinctrl_lookup_state(pl022->pinctrl, 2155d8f18420SPatrice Chotard PINCTRL_STATE_IDLE); 2156d8f18420SPatrice Chotard if (IS_ERR(pl022->pins_idle)) 2157d8f18420SPatrice Chotard dev_dbg(dev, "could not get idle pinstate\n"); 2158d8f18420SPatrice Chotard 21594f5e1b37SPatrice Chotard pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl, 21604f5e1b37SPatrice Chotard PINCTRL_STATE_SLEEP); 21614f5e1b37SPatrice Chotard if (IS_ERR(pl022->pins_sleep)) 21624f5e1b37SPatrice Chotard dev_dbg(dev, "could not get sleep pinstate\n"); 21634f5e1b37SPatrice Chotard 2164ca632f55SGrant Likely /* 2165ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2166ca632f55SGrant Likely * on this board 2167ca632f55SGrant Likely */ 2168ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 21696d3952a7SRoland Stigge master->num_chipselect = num_cs; 2170ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2171ca632f55SGrant Likely master->setup = pl022_setup; 2172ffbbdd21SLinus Walleij master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2173ffbbdd21SLinus Walleij master->transfer_one_message = pl022_transfer_one_message; 2174ffbbdd21SLinus Walleij master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2175ffbbdd21SLinus Walleij master->rt = platform_info->rt; 21766d3952a7SRoland Stigge master->dev.of_node = dev->of_node; 2177ca632f55SGrant Likely 21786d3952a7SRoland Stigge if (platform_info->num_chipselect && platform_info->chipselects) { 21796d3952a7SRoland Stigge for (i = 0; i < num_cs; i++) 2180f6f46de1SRoland Stigge pl022->chipselects[i] = platform_info->chipselects[i]; 21816d3952a7SRoland Stigge } else if (IS_ENABLED(CONFIG_OF)) { 21826d3952a7SRoland Stigge for (i = 0; i < num_cs; i++) { 21836d3952a7SRoland Stigge int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 21846d3952a7SRoland Stigge 21856d3952a7SRoland Stigge if (cs_gpio == -EPROBE_DEFER) { 21866d3952a7SRoland Stigge status = -EPROBE_DEFER; 21876d3952a7SRoland Stigge goto err_no_gpio; 21886d3952a7SRoland Stigge } 21896d3952a7SRoland Stigge 21906d3952a7SRoland Stigge pl022->chipselects[i] = cs_gpio; 21916d3952a7SRoland Stigge 21926d3952a7SRoland Stigge if (gpio_is_valid(cs_gpio)) { 2193aeef9915SLinus Walleij if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) 21946d3952a7SRoland Stigge dev_err(&adev->dev, 21956d3952a7SRoland Stigge "could not request %d gpio\n", 21966d3952a7SRoland Stigge cs_gpio); 21976d3952a7SRoland Stigge else if (gpio_direction_output(cs_gpio, 1)) 21986d3952a7SRoland Stigge dev_err(&adev->dev, 21996d3952a7SRoland Stigge "could set gpio %d as output\n", 22006d3952a7SRoland Stigge cs_gpio); 22016d3952a7SRoland Stigge } 22026d3952a7SRoland Stigge } 22036d3952a7SRoland Stigge } 2204f6f46de1SRoland Stigge 2205ca632f55SGrant Likely /* 2206ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2207ca632f55SGrant Likely * always MS bit first on the original pl022. 2208ca632f55SGrant Likely */ 2209ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2210ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2211ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2212ca632f55SGrant Likely 2213ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2214ca632f55SGrant Likely 2215ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2216ca632f55SGrant Likely if (status) 2217ca632f55SGrant Likely goto err_no_ioregion; 2218ca632f55SGrant Likely 2219ca632f55SGrant Likely pl022->phybase = adev->res.start; 2220aeef9915SLinus Walleij pl022->virtbase = devm_ioremap(dev, adev->res.start, 2221aeef9915SLinus Walleij resource_size(&adev->res)); 2222ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2223ca632f55SGrant Likely status = -ENOMEM; 2224ca632f55SGrant Likely goto err_no_ioremap; 2225ca632f55SGrant Likely } 2226ca632f55SGrant Likely printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2227ca632f55SGrant Likely adev->res.start, pl022->virtbase); 2228ca632f55SGrant Likely 2229aeef9915SLinus Walleij pl022->clk = devm_clk_get(&adev->dev, NULL); 2230ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2231ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2232ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2233ca632f55SGrant Likely goto err_no_clk; 2234ca632f55SGrant Likely } 22357ff6bcf0SRussell King 22367ff6bcf0SRussell King status = clk_prepare(pl022->clk); 22377ff6bcf0SRussell King if (status) { 22387ff6bcf0SRussell King dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 22397ff6bcf0SRussell King goto err_clk_prep; 22407ff6bcf0SRussell King } 22417ff6bcf0SRussell King 224271e63e74SUlf Hansson status = clk_enable(pl022->clk); 224371e63e74SUlf Hansson if (status) { 224471e63e74SUlf Hansson dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 224571e63e74SUlf Hansson goto err_no_clk_en; 224671e63e74SUlf Hansson } 224771e63e74SUlf Hansson 2248ffbbdd21SLinus Walleij /* Initialize transfer pump */ 2249ffbbdd21SLinus Walleij tasklet_init(&pl022->pump_transfers, pump_transfers, 2250ffbbdd21SLinus Walleij (unsigned long)pl022); 2251ffbbdd21SLinus Walleij 2252ca632f55SGrant Likely /* Disable SSP */ 2253ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2254ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2255ca632f55SGrant Likely load_ssp_default_config(pl022); 2256ca632f55SGrant Likely 2257aeef9915SLinus Walleij status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2258aeef9915SLinus Walleij 0, "pl022", pl022); 2259ca632f55SGrant Likely if (status < 0) { 2260ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2261ca632f55SGrant Likely goto err_no_irq; 2262ca632f55SGrant Likely } 2263ca632f55SGrant Likely 2264dc715452SArnd Bergmann /* Get DMA channels, try autoconfiguration first */ 2265dc715452SArnd Bergmann status = pl022_dma_autoprobe(pl022); 2266dc715452SArnd Bergmann 2267dc715452SArnd Bergmann /* If that failed, use channels from platform_info */ 2268dc715452SArnd Bergmann if (status == 0) 2269dc715452SArnd Bergmann platform_info->enable_dma = 1; 2270dc715452SArnd Bergmann else if (platform_info->enable_dma) { 2271ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2272ca632f55SGrant Likely if (status != 0) 2273ca632f55SGrant Likely platform_info->enable_dma = 0; 2274ca632f55SGrant Likely } 2275ca632f55SGrant Likely 2276ca632f55SGrant Likely /* Register with the SPI framework */ 2277ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 2278ca632f55SGrant Likely status = spi_register_master(master); 2279ca632f55SGrant Likely if (status != 0) { 2280ca632f55SGrant Likely dev_err(&adev->dev, 2281ca632f55SGrant Likely "probe - problem registering spi master\n"); 2282ca632f55SGrant Likely goto err_spi_register; 2283ca632f55SGrant Likely } 2284ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 228592b97f0aSRussell King 228692b97f0aSRussell King /* let runtime pm put suspend */ 228753e4aceaSChris Blair if (platform_info->autosuspend_delay > 0) { 228853e4aceaSChris Blair dev_info(&adev->dev, 228953e4aceaSChris Blair "will use autosuspend for runtime pm, delay %dms\n", 229053e4aceaSChris Blair platform_info->autosuspend_delay); 229153e4aceaSChris Blair pm_runtime_set_autosuspend_delay(dev, 229253e4aceaSChris Blair platform_info->autosuspend_delay); 229353e4aceaSChris Blair pm_runtime_use_autosuspend(dev); 229453e4aceaSChris Blair } 22950df34994SUlf Hansson pm_runtime_put(dev); 22960df34994SUlf Hansson 2297ca632f55SGrant Likely return 0; 2298ca632f55SGrant Likely 2299ca632f55SGrant Likely err_spi_register: 23003e3ea716SViresh Kumar if (platform_info->enable_dma) 2301ca632f55SGrant Likely pl022_dma_remove(pl022); 2302ca632f55SGrant Likely err_no_irq: 230371e63e74SUlf Hansson clk_disable(pl022->clk); 230471e63e74SUlf Hansson err_no_clk_en: 23057ff6bcf0SRussell King clk_unprepare(pl022->clk); 23067ff6bcf0SRussell King err_clk_prep: 2307ca632f55SGrant Likely err_no_clk: 2308ca632f55SGrant Likely err_no_ioremap: 2309ca632f55SGrant Likely amba_release_regions(adev); 2310ca632f55SGrant Likely err_no_ioregion: 23116d3952a7SRoland Stigge err_no_gpio: 23124f5e1b37SPatrice Chotard err_no_pinctrl: 2313ca632f55SGrant Likely spi_master_put(master); 2314ca632f55SGrant Likely return status; 2315ca632f55SGrant Likely } 2316ca632f55SGrant Likely 2317fd4a319bSGrant Likely static int 2318ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2319ca632f55SGrant Likely { 2320ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 232150658b66SLinus Walleij 2322ca632f55SGrant Likely if (!pl022) 2323ca632f55SGrant Likely return 0; 2324ca632f55SGrant Likely 232592b97f0aSRussell King /* 232692b97f0aSRussell King * undo pm_runtime_put() in probe. I assume that we're not 232792b97f0aSRussell King * accessing the primecell here. 232892b97f0aSRussell King */ 232992b97f0aSRussell King pm_runtime_get_noresume(&adev->dev); 233092b97f0aSRussell King 2331ca632f55SGrant Likely load_ssp_default_config(pl022); 23323e3ea716SViresh Kumar if (pl022->master_info->enable_dma) 2333ca632f55SGrant Likely pl022_dma_remove(pl022); 23343e3ea716SViresh Kumar 2335ca632f55SGrant Likely clk_disable(pl022->clk); 23367ff6bcf0SRussell King clk_unprepare(pl022->clk); 2337ca632f55SGrant Likely amba_release_regions(adev); 2338ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2339ca632f55SGrant Likely spi_unregister_master(pl022->master); 2340ca632f55SGrant Likely amba_set_drvdata(adev, NULL); 2341ca632f55SGrant Likely return 0; 2342ca632f55SGrant Likely } 2343ca632f55SGrant Likely 2344ada7aec7SLinus Walleij #if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME) 2345ada7aec7SLinus Walleij /* 2346ada7aec7SLinus Walleij * These two functions are used from both suspend/resume and 2347ada7aec7SLinus Walleij * the runtime counterparts to handle external resources like 2348ada7aec7SLinus Walleij * clocks, pins and regulators when going to sleep. 2349ada7aec7SLinus Walleij */ 2350d8f18420SPatrice Chotard static void pl022_suspend_resources(struct pl022 *pl022, bool runtime) 2351ada7aec7SLinus Walleij { 2352ada7aec7SLinus Walleij int ret; 2353d8f18420SPatrice Chotard struct pinctrl_state *pins_state; 2354ada7aec7SLinus Walleij 2355ada7aec7SLinus Walleij clk_disable(pl022->clk); 2356ada7aec7SLinus Walleij 2357d8f18420SPatrice Chotard pins_state = runtime ? pl022->pins_idle : pl022->pins_sleep; 2358ada7aec7SLinus Walleij /* Optionally let pins go into sleep states */ 2359d8f18420SPatrice Chotard if (!IS_ERR(pins_state)) { 2360d8f18420SPatrice Chotard ret = pinctrl_select_state(pl022->pinctrl, pins_state); 2361ada7aec7SLinus Walleij if (ret) 2362d8f18420SPatrice Chotard dev_err(&pl022->adev->dev, "could not set %s pins\n", 2363d8f18420SPatrice Chotard runtime ? "idle" : "sleep"); 2364ada7aec7SLinus Walleij } 2365ada7aec7SLinus Walleij } 2366ada7aec7SLinus Walleij 2367d8f18420SPatrice Chotard static void pl022_resume_resources(struct pl022 *pl022, bool runtime) 2368ada7aec7SLinus Walleij { 2369ada7aec7SLinus Walleij int ret; 2370ada7aec7SLinus Walleij 2371ada7aec7SLinus Walleij /* Optionaly enable pins to be muxed in and configured */ 2372d8f18420SPatrice Chotard /* First go to the default state */ 2373ada7aec7SLinus Walleij if (!IS_ERR(pl022->pins_default)) { 2374d8f18420SPatrice Chotard ret = pinctrl_select_state(pl022->pinctrl, pl022->pins_default); 2375ada7aec7SLinus Walleij if (ret) 2376ada7aec7SLinus Walleij dev_err(&pl022->adev->dev, 2377ada7aec7SLinus Walleij "could not set default pins\n"); 2378ada7aec7SLinus Walleij } 2379ada7aec7SLinus Walleij 2380d8f18420SPatrice Chotard if (!runtime) { 2381d8f18420SPatrice Chotard /* Then let's idle the pins until the next transfer happens */ 2382d8f18420SPatrice Chotard if (!IS_ERR(pl022->pins_idle)) { 2383d8f18420SPatrice Chotard ret = pinctrl_select_state(pl022->pinctrl, 2384d8f18420SPatrice Chotard pl022->pins_idle); 2385d8f18420SPatrice Chotard if (ret) 2386d8f18420SPatrice Chotard dev_err(&pl022->adev->dev, 2387d8f18420SPatrice Chotard "could not set idle pins\n"); 2388d8f18420SPatrice Chotard } 2389d8f18420SPatrice Chotard } 2390d8f18420SPatrice Chotard 2391ada7aec7SLinus Walleij clk_enable(pl022->clk); 2392ada7aec7SLinus Walleij } 2393ada7aec7SLinus Walleij #endif 2394ada7aec7SLinus Walleij 239592b97f0aSRussell King #ifdef CONFIG_SUSPEND 23966cfa6279SPeter Hüwe static int pl022_suspend(struct device *dev) 2397ca632f55SGrant Likely { 239892b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2399ffbbdd21SLinus Walleij int ret; 2400ca632f55SGrant Likely 2401ffbbdd21SLinus Walleij ret = spi_master_suspend(pl022->master); 2402ffbbdd21SLinus Walleij if (ret) { 2403ffbbdd21SLinus Walleij dev_warn(dev, "cannot suspend master\n"); 2404ffbbdd21SLinus Walleij return ret; 2405ca632f55SGrant Likely } 24064964a26dSUlf Hansson 24074964a26dSUlf Hansson pm_runtime_get_sync(dev); 2408d8f18420SPatrice Chotard pl022_suspend_resources(pl022, false); 2409ca632f55SGrant Likely 24106cfa6279SPeter Hüwe dev_dbg(dev, "suspended\n"); 2411ca632f55SGrant Likely return 0; 2412ca632f55SGrant Likely } 2413ca632f55SGrant Likely 241492b97f0aSRussell King static int pl022_resume(struct device *dev) 2415ca632f55SGrant Likely { 241692b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2417ffbbdd21SLinus Walleij int ret; 2418ca632f55SGrant Likely 2419d8f18420SPatrice Chotard pl022_resume_resources(pl022, false); 24204964a26dSUlf Hansson pm_runtime_put(dev); 2421ada7aec7SLinus Walleij 2422ca632f55SGrant Likely /* Start the queue running */ 2423ffbbdd21SLinus Walleij ret = spi_master_resume(pl022->master); 2424ffbbdd21SLinus Walleij if (ret) 2425ffbbdd21SLinus Walleij dev_err(dev, "problem starting queue (%d)\n", ret); 2426ca632f55SGrant Likely else 242792b97f0aSRussell King dev_dbg(dev, "resumed\n"); 2428ca632f55SGrant Likely 2429ffbbdd21SLinus Walleij return ret; 2430ca632f55SGrant Likely } 2431ca632f55SGrant Likely #endif /* CONFIG_PM */ 2432ca632f55SGrant Likely 243392b97f0aSRussell King #ifdef CONFIG_PM_RUNTIME 243492b97f0aSRussell King static int pl022_runtime_suspend(struct device *dev) 243592b97f0aSRussell King { 243692b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 243792b97f0aSRussell King 2438d8f18420SPatrice Chotard pl022_suspend_resources(pl022, true); 243992b97f0aSRussell King return 0; 244092b97f0aSRussell King } 244192b97f0aSRussell King 244292b97f0aSRussell King static int pl022_runtime_resume(struct device *dev) 244392b97f0aSRussell King { 244492b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 24454f5e1b37SPatrice Chotard 2446d8f18420SPatrice Chotard pl022_resume_resources(pl022, true); 244792b97f0aSRussell King return 0; 244892b97f0aSRussell King } 244992b97f0aSRussell King #endif 245092b97f0aSRussell King 245192b97f0aSRussell King static const struct dev_pm_ops pl022_dev_pm_ops = { 245292b97f0aSRussell King SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 245392b97f0aSRussell King SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 245492b97f0aSRussell King }; 245592b97f0aSRussell King 2456ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2457ca632f55SGrant Likely .fifodepth = 8, 2458ca632f55SGrant Likely .max_bpw = 16, 2459ca632f55SGrant Likely .unidir = false, 2460ca632f55SGrant Likely .extended_cr = false, 2461ca632f55SGrant Likely .pl023 = false, 2462ca632f55SGrant Likely .loopback = true, 2463ca632f55SGrant Likely }; 2464ca632f55SGrant Likely 2465ca632f55SGrant Likely static struct vendor_data vendor_st = { 2466ca632f55SGrant Likely .fifodepth = 32, 2467ca632f55SGrant Likely .max_bpw = 32, 2468ca632f55SGrant Likely .unidir = false, 2469ca632f55SGrant Likely .extended_cr = true, 2470ca632f55SGrant Likely .pl023 = false, 2471ca632f55SGrant Likely .loopback = true, 2472ca632f55SGrant Likely }; 2473ca632f55SGrant Likely 2474ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2475ca632f55SGrant Likely .fifodepth = 32, 2476ca632f55SGrant Likely .max_bpw = 32, 2477ca632f55SGrant Likely .unidir = false, 2478ca632f55SGrant Likely .extended_cr = true, 2479ca632f55SGrant Likely .pl023 = true, 2480ca632f55SGrant Likely .loopback = false, 2481ca632f55SGrant Likely }; 2482ca632f55SGrant Likely 2483ca632f55SGrant Likely static struct amba_id pl022_ids[] = { 2484ca632f55SGrant Likely { 2485ca632f55SGrant Likely /* 2486ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2487ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2488ca632f55SGrant Likely */ 2489ca632f55SGrant Likely .id = 0x00041022, 2490ca632f55SGrant Likely .mask = 0x000fffff, 2491ca632f55SGrant Likely .data = &vendor_arm, 2492ca632f55SGrant Likely }, 2493ca632f55SGrant Likely { 2494ca632f55SGrant Likely /* 2495ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2496ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2497ca632f55SGrant Likely */ 2498ca632f55SGrant Likely .id = 0x01080022, 2499ca632f55SGrant Likely .mask = 0xffffffff, 2500ca632f55SGrant Likely .data = &vendor_st, 2501ca632f55SGrant Likely }, 2502ca632f55SGrant Likely { 2503ca632f55SGrant Likely /* 2504ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2505ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2506ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2507ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2508ca632f55SGrant Likely * CR0/CR1 register 2509ca632f55SGrant Likely */ 2510ca632f55SGrant Likely .id = 0x00080023, 2511ca632f55SGrant Likely .mask = 0xffffffff, 2512ca632f55SGrant Likely .data = &vendor_st_pl023, 2513ca632f55SGrant Likely }, 2514ca632f55SGrant Likely { 0, 0 }, 2515ca632f55SGrant Likely }; 2516ca632f55SGrant Likely 25177eeac71bSDave Martin MODULE_DEVICE_TABLE(amba, pl022_ids); 25187eeac71bSDave Martin 2519ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2520ca632f55SGrant Likely .drv = { 2521ca632f55SGrant Likely .name = "ssp-pl022", 252292b97f0aSRussell King .pm = &pl022_dev_pm_ops, 2523ca632f55SGrant Likely }, 2524ca632f55SGrant Likely .id_table = pl022_ids, 2525ca632f55SGrant Likely .probe = pl022_probe, 2526fd4a319bSGrant Likely .remove = pl022_remove, 2527ca632f55SGrant Likely }; 2528ca632f55SGrant Likely 2529ca632f55SGrant Likely static int __init pl022_init(void) 2530ca632f55SGrant Likely { 2531ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2532ca632f55SGrant Likely } 2533ca632f55SGrant Likely subsys_initcall(pl022_init); 2534ca632f55SGrant Likely 2535ca632f55SGrant Likely static void __exit pl022_exit(void) 2536ca632f55SGrant Likely { 2537ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2538ca632f55SGrant Likely } 2539ca632f55SGrant Likely module_exit(pl022_exit); 2540ca632f55SGrant Likely 2541ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2542ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2543ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2544