1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ca632f55SGrant Likely /* 3ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 4ca632f55SGrant Likely * 5aeef9915SLinus Walleij * Copyright (C) 2008-2012 ST-Ericsson AB 6ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 7ca632f55SGrant Likely * 8ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * Initial version inspired by: 11ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 12ca632f55SGrant Likely * Initial adoption to PL022 by: 13ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 14ca632f55SGrant Likely */ 15ca632f55SGrant Likely 16ca632f55SGrant Likely #include <linux/init.h> 17ca632f55SGrant Likely #include <linux/module.h> 18ca632f55SGrant Likely #include <linux/device.h> 19ca632f55SGrant Likely #include <linux/ioport.h> 20ca632f55SGrant Likely #include <linux/errno.h> 21ca632f55SGrant Likely #include <linux/interrupt.h> 22ca632f55SGrant Likely #include <linux/spi/spi.h> 23ca632f55SGrant Likely #include <linux/delay.h> 24ca632f55SGrant Likely #include <linux/clk.h> 25ca632f55SGrant Likely #include <linux/err.h> 26ca632f55SGrant Likely #include <linux/amba/bus.h> 27ca632f55SGrant Likely #include <linux/amba/pl022.h> 28ca632f55SGrant Likely #include <linux/io.h> 29ca632f55SGrant Likely #include <linux/slab.h> 30ca632f55SGrant Likely #include <linux/dmaengine.h> 31ca632f55SGrant Likely #include <linux/dma-mapping.h> 32ca632f55SGrant Likely #include <linux/scatterlist.h> 33bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 3477f983a9SLinus Walleij #include <linux/of.h> 354f5e1b37SPatrice Chotard #include <linux/pinctrl/consumer.h> 36ca632f55SGrant Likely 37ca632f55SGrant Likely /* 38ca632f55SGrant Likely * This macro is used to define some register default values. 39ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 40ca632f55SGrant Likely * val shifted sb steps to the left. 41ca632f55SGrant Likely */ 42ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 43ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 44ca632f55SGrant Likely 45ca632f55SGrant Likely /* 46ca632f55SGrant Likely * This macro is also used to define some default values. 47ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 48ca632f55SGrant Likely * the result with mask. 49ca632f55SGrant Likely */ 50ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 51ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 52ca632f55SGrant Likely 53ca632f55SGrant Likely #define DRIVE_TX 0 54ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 55ca632f55SGrant Likely 56ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 57ca632f55SGrant Likely #define QUEUE_DMA 1 58ca632f55SGrant Likely 59ca632f55SGrant Likely #define RX_TRANSFER 1 60ca632f55SGrant Likely #define TX_TRANSFER 2 61ca632f55SGrant Likely 62ca632f55SGrant Likely /* 63ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 64ca632f55SGrant Likely */ 65ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 66ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 67ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 68ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 69ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 70ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 71ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 72ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 73ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 74ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 75db4fa45eSAnders Berg #define SSP_CSR(r) (r + 0x030) /* vendor extension */ 76ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 77ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 78ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 79ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 80ca632f55SGrant Likely 81ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 82ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 83ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 84ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 85ca632f55SGrant Likely 86ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 87ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 88ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 89ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 90ca632f55SGrant Likely 91ca632f55SGrant Likely /* 92ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 93ca632f55SGrant Likely */ 94ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 95ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 96ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 97ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 98ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 99ca632f55SGrant Likely 100ca632f55SGrant Likely /* 101ca632f55SGrant Likely * The ST version of this block moves som bits 102ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 103ca632f55SGrant Likely */ 104ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 105ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 106ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 107ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 108ca632f55SGrant Likely 109ca632f55SGrant Likely /* 110ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 111ca632f55SGrant Likely */ 112ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 113ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 114ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 115ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 116ca632f55SGrant Likely 117ca632f55SGrant Likely /* 118ca632f55SGrant Likely * The ST version of this block adds some bits 119ca632f55SGrant Likely * in SSP_CR1 120ca632f55SGrant Likely */ 121ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 122ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 123ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 124ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 125ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 126ca632f55SGrant Likely /* This one is only in the PL023 variant */ 127ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 128ca632f55SGrant Likely 129ca632f55SGrant Likely /* 130ca632f55SGrant Likely * SSP Status Register - SSP_SR 131ca632f55SGrant Likely */ 132ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 133ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 134ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 135ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 136ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 137ca632f55SGrant Likely 138ca632f55SGrant Likely /* 139ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 140ca632f55SGrant Likely */ 141ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 142ca632f55SGrant Likely 143ca632f55SGrant Likely /* 144ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 145ca632f55SGrant Likely */ 146ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 147ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 148ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 149ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 150ca632f55SGrant Likely 151ca632f55SGrant Likely /* 152ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 153ca632f55SGrant Likely */ 154ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 155ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 156ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 157ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 158ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 159ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 160ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 161ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 162ca632f55SGrant Likely 163ca632f55SGrant Likely /* 164ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 165ca632f55SGrant Likely */ 166ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 167ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 168ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 169ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 170ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 171ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 172ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 173ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 174ca632f55SGrant Likely 175ca632f55SGrant Likely /* 176ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 177ca632f55SGrant Likely */ 178ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 179ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 180ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 181ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 182ca632f55SGrant Likely 183ca632f55SGrant Likely /* 184ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 185ca632f55SGrant Likely */ 186ca632f55SGrant Likely /* Receive DMA Enable bit */ 187ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 188ca632f55SGrant Likely /* Transmit DMA Enable bit */ 189ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 190ca632f55SGrant Likely 191ca632f55SGrant Likely /* 192db4fa45eSAnders Berg * SSP Chip Select Control Register - SSP_CSR 193db4fa45eSAnders Berg * (vendor extension) 194db4fa45eSAnders Berg */ 195db4fa45eSAnders Berg #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0) 196db4fa45eSAnders Berg 197db4fa45eSAnders Berg /* 198ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 199ca632f55SGrant Likely */ 200ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 201ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 202ca632f55SGrant Likely 203ca632f55SGrant Likely /* 204ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 205ca632f55SGrant Likely */ 206ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 207ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 208ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 209ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 210ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 211ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 212ca632f55SGrant Likely 213ca632f55SGrant Likely /* 214ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 215ca632f55SGrant Likely */ 216ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 217ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 218ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 219ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 220ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 221ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 222ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 223ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 224ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 225ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 226ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 227ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 228ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 229ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 230ca632f55SGrant Likely 231ca632f55SGrant Likely /* 232ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 233ca632f55SGrant Likely */ 234ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 235ca632f55SGrant Likely 236ca632f55SGrant Likely /* 237ca632f55SGrant Likely * Message State 238ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 239ca632f55SGrant Likely * hold a single state value, that's why all this 240ca632f55SGrant Likely * (void *) casting is done here. 241ca632f55SGrant Likely */ 242ca632f55SGrant Likely #define STATE_START ((void *) 0) 243ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 244ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 245ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 2467aef2b64SJiwei Sun #define STATE_TIMEOUT ((void *) -2) 247ca632f55SGrant Likely 248ca632f55SGrant Likely /* 249ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 250ca632f55SGrant Likely */ 251ca632f55SGrant Likely #define SSP_DISABLED (0) 252ca632f55SGrant Likely #define SSP_ENABLED (1) 253ca632f55SGrant Likely 254ca632f55SGrant Likely /* 255ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 256ca632f55SGrant Likely */ 257ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 258ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 259ca632f55SGrant Likely 260ca632f55SGrant Likely /* 261ca632f55SGrant Likely * SSP Clock Defaults 262ca632f55SGrant Likely */ 263ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 264ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 265ca632f55SGrant Likely 266ca632f55SGrant Likely /* 267ca632f55SGrant Likely * SSP Clock Parameter ranges 268ca632f55SGrant Likely */ 269ca632f55SGrant Likely #define CPSDVR_MIN 0x02 270ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 271ca632f55SGrant Likely #define SCR_MIN 0x00 272ca632f55SGrant Likely #define SCR_MAX 0xFF 273ca632f55SGrant Likely 274ca632f55SGrant Likely /* 275ca632f55SGrant Likely * SSP Interrupt related Macros 276ca632f55SGrant Likely */ 277ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 278ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 27985fa4e1fSAlexander Sverdlin #define ENABLE_ALL_INTERRUPTS ( \ 28085fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_RORIM | \ 28185fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_RTIM | \ 28285fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_RXIM | \ 28385fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_TXIM \ 28485fa4e1fSAlexander Sverdlin ) 285ca632f55SGrant Likely 286ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 287ca632f55SGrant Likely 288ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 289ca632f55SGrant Likely 290ca632f55SGrant Likely /* 291db56d030SJay Fang * The type of reading going on this chip 292ca632f55SGrant Likely */ 293ca632f55SGrant Likely enum ssp_reading { 294ca632f55SGrant Likely READING_NULL, 295ca632f55SGrant Likely READING_U8, 296ca632f55SGrant Likely READING_U16, 297ca632f55SGrant Likely READING_U32 298ca632f55SGrant Likely }; 299ca632f55SGrant Likely 300c7cd1dfbSLee Jones /* 301db56d030SJay Fang * The type of writing going on this chip 302ca632f55SGrant Likely */ 303ca632f55SGrant Likely enum ssp_writing { 304ca632f55SGrant Likely WRITING_NULL, 305ca632f55SGrant Likely WRITING_U8, 306ca632f55SGrant Likely WRITING_U16, 307ca632f55SGrant Likely WRITING_U32 308ca632f55SGrant Likely }; 309ca632f55SGrant Likely 310ca632f55SGrant Likely /** 311ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 312ca632f55SGrant Likely * for PL022 derivates 313ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 314ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 315ca632f55SGrant Likely * @unidir: supports unidirection transfers 316ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 317ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 318ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 319c7cd1dfbSLee Jones * @loopback: supports loopback mode 320db4fa45eSAnders Berg * @internal_cs_ctrl: supports chip select control register 321ca632f55SGrant Likely */ 322ca632f55SGrant Likely struct vendor_data { 323ca632f55SGrant Likely int fifodepth; 324ca632f55SGrant Likely int max_bpw; 325ca632f55SGrant Likely bool unidir; 326ca632f55SGrant Likely bool extended_cr; 327ca632f55SGrant Likely bool pl023; 328ca632f55SGrant Likely bool loopback; 329db4fa45eSAnders Berg bool internal_cs_ctrl; 330ca632f55SGrant Likely }; 331ca632f55SGrant Likely 332ca632f55SGrant Likely /** 333ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 334ca632f55SGrant Likely * @adev: AMBA device model hookup 335ca632f55SGrant Likely * @vendor: vendor data for the IP block 336ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 337ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 338ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 339ca632f55SGrant Likely * @master: SPI framework hookup 340ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 341ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 342ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 343ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 344ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 3458b8d7191SVirupax Sadashivpetimath * @next_msg_cs_active: the next message in the queue has been examined 3468b8d7191SVirupax Sadashivpetimath * and it was found that it uses the same chip select as the previous 3478b8d7191SVirupax Sadashivpetimath * message, so we left it active after the previous transfer, and it's 3488b8d7191SVirupax Sadashivpetimath * active already. 349ca632f55SGrant Likely * @tx: current position in TX buffer to be read 350ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 351ca632f55SGrant Likely * @rx: current position in RX buffer to be written 352ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 353ca632f55SGrant Likely * @read: the type of read currently going on 354ca632f55SGrant Likely * @write: the type of write currently going on 355ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 356c7cd1dfbSLee Jones * @rx_lev_trig: receive FIFO watermark level which triggers IRQ 357c7cd1dfbSLee Jones * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ 358ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 359ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 360ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 361ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 362ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 363c7cd1dfbSLee Jones * @dma_running: indicates whether DMA is in operation 36477f983a9SLinus Walleij * @cur_cs: current chip select index 3658bb2dbf1SLinus Walleij * @cur_gpiod: current chip select GPIO descriptor 366ca632f55SGrant Likely */ 367ca632f55SGrant Likely struct pl022 { 368ca632f55SGrant Likely struct amba_device *adev; 369ca632f55SGrant Likely struct vendor_data *vendor; 370ca632f55SGrant Likely resource_size_t phybase; 371ca632f55SGrant Likely void __iomem *virtbase; 372ca632f55SGrant Likely struct clk *clk; 373ca632f55SGrant Likely struct spi_master *master; 374ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 375ffbbdd21SLinus Walleij /* Message per-transfer pump */ 376ca632f55SGrant Likely struct tasklet_struct pump_transfers; 377ca632f55SGrant Likely struct spi_message *cur_msg; 378ca632f55SGrant Likely struct spi_transfer *cur_transfer; 379ca632f55SGrant Likely struct chip_data *cur_chip; 3808b8d7191SVirupax Sadashivpetimath bool next_msg_cs_active; 381ca632f55SGrant Likely void *tx; 382ca632f55SGrant Likely void *tx_end; 383ca632f55SGrant Likely void *rx; 384ca632f55SGrant Likely void *rx_end; 385ca632f55SGrant Likely enum ssp_reading read; 386ca632f55SGrant Likely enum ssp_writing write; 387ca632f55SGrant Likely u32 exp_fifo_level; 388083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 389083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 390ca632f55SGrant Likely /* DMA settings */ 391ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 392ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 393ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 394ca632f55SGrant Likely struct sg_table sgt_rx; 395ca632f55SGrant Likely struct sg_table sgt_tx; 396ca632f55SGrant Likely char *dummypage; 397ffbbdd21SLinus Walleij bool dma_running; 398ca632f55SGrant Likely #endif 399f6f46de1SRoland Stigge int cur_cs; 4008bb2dbf1SLinus Walleij struct gpio_desc *cur_gpiod; 401ca632f55SGrant Likely }; 402ca632f55SGrant Likely 403ca632f55SGrant Likely /** 404ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 405ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 406ca632f55SGrant Likely * register is 32 bits wide rather than just 16 407ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 408ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 409ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 410ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 411ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 412ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 413ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 414ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 415ca632f55SGrant Likely * 416ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 417ca632f55SGrant Likely * This would be set according to the current message that would be served 418ca632f55SGrant Likely */ 419ca632f55SGrant Likely struct chip_data { 420ca632f55SGrant Likely u32 cr0; 421ca632f55SGrant Likely u16 cr1; 422ca632f55SGrant Likely u16 dmacr; 423ca632f55SGrant Likely u16 cpsr; 424ca632f55SGrant Likely u8 n_bytes; 425ca632f55SGrant Likely bool enable_dma; 426ca632f55SGrant Likely enum ssp_reading read; 427ca632f55SGrant Likely enum ssp_writing write; 428ca632f55SGrant Likely int xfer_type; 429ca632f55SGrant Likely }; 430ca632f55SGrant Likely 431ca632f55SGrant Likely /** 432db4fa45eSAnders Berg * internal_cs_control - Control chip select signals via SSP_CSR. 433db4fa45eSAnders Berg * @pl022: SSP driver private data structure 434db4fa45eSAnders Berg * @command: select/delect the chip 435db4fa45eSAnders Berg * 436db4fa45eSAnders Berg * Used on controller with internal chip select control via SSP_CSR register 437db4fa45eSAnders Berg * (vendor extension). Each of the 5 LSB in the register controls one chip 438db4fa45eSAnders Berg * select signal. 439db4fa45eSAnders Berg */ 440db4fa45eSAnders Berg static void internal_cs_control(struct pl022 *pl022, u32 command) 441db4fa45eSAnders Berg { 442db4fa45eSAnders Berg u32 tmp; 443db4fa45eSAnders Berg 444db4fa45eSAnders Berg tmp = readw(SSP_CSR(pl022->virtbase)); 445db4fa45eSAnders Berg if (command == SSP_CHIP_SELECT) 446db4fa45eSAnders Berg tmp &= ~BIT(pl022->cur_cs); 447db4fa45eSAnders Berg else 448db4fa45eSAnders Berg tmp |= BIT(pl022->cur_cs); 449db4fa45eSAnders Berg writew(tmp, SSP_CSR(pl022->virtbase)); 450db4fa45eSAnders Berg } 451db4fa45eSAnders Berg 452f6f46de1SRoland Stigge static void pl022_cs_control(struct pl022 *pl022, u32 command) 453f6f46de1SRoland Stigge { 454db4fa45eSAnders Berg if (pl022->vendor->internal_cs_ctrl) 455db4fa45eSAnders Berg internal_cs_control(pl022, command); 4568bb2dbf1SLinus Walleij else if (pl022->cur_gpiod) 4578bb2dbf1SLinus Walleij /* 4588bb2dbf1SLinus Walleij * This needs to be inverted since with GPIOLIB in 4598bb2dbf1SLinus Walleij * control, the inversion will be handled by 4608bb2dbf1SLinus Walleij * GPIOLIB's active low handling. The "command" 4618bb2dbf1SLinus Walleij * passed into this function will be SSP_CHIP_SELECT 4628bb2dbf1SLinus Walleij * which is enum:ed to 0, so we need the inverse 4638bb2dbf1SLinus Walleij * (1) to activate chip select. 4648bb2dbf1SLinus Walleij */ 4658bb2dbf1SLinus Walleij gpiod_set_value(pl022->cur_gpiod, !command); 466f6f46de1SRoland Stigge } 467f6f46de1SRoland Stigge 468ca632f55SGrant Likely /** 469ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 470ca632f55SGrant Likely * callback of this message. Assumes that caller already 471ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 472ca632f55SGrant Likely * @pl022: SSP driver private data structure 473ca632f55SGrant Likely */ 474ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 475ca632f55SGrant Likely { 476ca632f55SGrant Likely struct spi_transfer *last_transfer; 4778b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = false; 478ca632f55SGrant Likely 47923e2c2aaSAxel Lin last_transfer = list_last_entry(&pl022->cur_msg->transfers, 48023e2c2aaSAxel Lin struct spi_transfer, transfer_list); 481ca632f55SGrant Likely 482ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 483ca632f55SGrant Likely /* 484ca632f55SGrant Likely * FIXME: This runs in interrupt context. 485ca632f55SGrant Likely * Is this really smart? 486ca632f55SGrant Likely */ 487e74dc5c7SAlexandru Ardelean spi_transfer_delay_exec(last_transfer); 488ca632f55SGrant Likely 4898b8d7191SVirupax Sadashivpetimath if (!last_transfer->cs_change) { 490ca632f55SGrant Likely struct spi_message *next_msg; 491ca632f55SGrant Likely 4928b8d7191SVirupax Sadashivpetimath /* 4938b8d7191SVirupax Sadashivpetimath * cs_change was not set. We can keep the chip select 4948b8d7191SVirupax Sadashivpetimath * enabled if there is message in the queue and it is 4958b8d7191SVirupax Sadashivpetimath * for the same spi device. 496ca632f55SGrant Likely * 497ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 498ca632f55SGrant Likely * after calling msg->complete (below) the driver that 499ca632f55SGrant Likely * sent the current message could be unloaded, which 500ca632f55SGrant Likely * could invalidate the cs_control() callback... 501ca632f55SGrant Likely */ 502ca632f55SGrant Likely /* get a pointer to the next message, if any */ 503ffbbdd21SLinus Walleij next_msg = spi_get_next_queued_message(pl022->master); 504ca632f55SGrant Likely 5058b8d7191SVirupax Sadashivpetimath /* 5068b8d7191SVirupax Sadashivpetimath * see if the next and current messages point 5078b8d7191SVirupax Sadashivpetimath * to the same spi device. 508ca632f55SGrant Likely */ 5098b8d7191SVirupax Sadashivpetimath if (next_msg && next_msg->spi != pl022->cur_msg->spi) 510ca632f55SGrant Likely next_msg = NULL; 5118b8d7191SVirupax Sadashivpetimath if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 512f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 5138b8d7191SVirupax Sadashivpetimath else 5148b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = true; 515ffbbdd21SLinus Walleij 516ca632f55SGrant Likely } 5178b8d7191SVirupax Sadashivpetimath 5188b8d7191SVirupax Sadashivpetimath pl022->cur_msg = NULL; 5198b8d7191SVirupax Sadashivpetimath pl022->cur_transfer = NULL; 5208b8d7191SVirupax Sadashivpetimath pl022->cur_chip = NULL; 521fd316941SVirupax Sadashivpetimath 522fd316941SVirupax Sadashivpetimath /* disable the SPI/SSP operation */ 523fd316941SVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 524fd316941SVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 525fd316941SVirupax Sadashivpetimath 526cd6fa8d2SAlexander Sverdlin spi_finalize_current_message(pl022->master); 527ca632f55SGrant Likely } 528ca632f55SGrant Likely 529ca632f55SGrant Likely /** 530ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 531ca632f55SGrant Likely * @pl022: SSP driver private data structure 532ca632f55SGrant Likely */ 533ca632f55SGrant Likely static int flush(struct pl022 *pl022) 534ca632f55SGrant Likely { 535ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 536ca632f55SGrant Likely 537ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 538ca632f55SGrant Likely do { 539ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 540ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 541ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 542ca632f55SGrant Likely 543ca632f55SGrant Likely pl022->exp_fifo_level = 0; 544ca632f55SGrant Likely 545ca632f55SGrant Likely return limit; 546ca632f55SGrant Likely } 547ca632f55SGrant Likely 548ca632f55SGrant Likely /** 549ca632f55SGrant Likely * restore_state - Load configuration of current chip 550ca632f55SGrant Likely * @pl022: SSP driver private data structure 551ca632f55SGrant Likely */ 552ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 553ca632f55SGrant Likely { 554ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 555ca632f55SGrant Likely 556ca632f55SGrant Likely if (pl022->vendor->extended_cr) 557ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 558ca632f55SGrant Likely else 559ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 560ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 561ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 562ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 563ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 564ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 565ca632f55SGrant Likely } 566ca632f55SGrant Likely 567ca632f55SGrant Likely /* 568ca632f55SGrant Likely * Default SSP Register Values 569ca632f55SGrant Likely */ 570ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 571ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 572ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 573ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 574ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 575ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 576ca632f55SGrant Likely ) 577ca632f55SGrant Likely 578ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 579ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 580ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 581ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 582ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 583ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 584ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 585ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 586ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 587ca632f55SGrant Likely ) 588ca632f55SGrant Likely 589ca632f55SGrant Likely /* The PL023 version is slightly different again */ 590ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 591ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 592ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 593ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 594ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 595ca632f55SGrant Likely ) 596ca632f55SGrant Likely 597ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 598ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 599ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 600ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 601ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 602ca632f55SGrant Likely ) 603ca632f55SGrant Likely 604ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 605ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 606ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 607ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 608ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 609ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 610ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 611ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 612ca632f55SGrant Likely ) 613ca632f55SGrant Likely 614ca632f55SGrant Likely /* 615ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 616ca632f55SGrant Likely * support, and a new clock feedback delay setting. 617ca632f55SGrant Likely */ 618ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 619ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 620ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 621ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 622ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 623ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 624ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 625ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 626ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 627ca632f55SGrant Likely ) 628ca632f55SGrant Likely 629ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 630ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 631ca632f55SGrant Likely ) 632ca632f55SGrant Likely 633ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 634ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 635ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 636ca632f55SGrant Likely ) 637ca632f55SGrant Likely 638ca632f55SGrant Likely /** 639ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 640ca632f55SGrant Likely * @pl022: SSP driver private data structure 641ca632f55SGrant Likely */ 642ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 643ca632f55SGrant Likely { 644ca632f55SGrant Likely if (pl022->vendor->pl023) { 645ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 646ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 647ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 648ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 649ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 650ca632f55SGrant Likely } else { 651ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 652ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 653ca632f55SGrant Likely } 654ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 655ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 656ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 657ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 658ca632f55SGrant Likely } 659ca632f55SGrant Likely 660c7cd1dfbSLee Jones /* 661ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 662ca632f55SGrant Likely * set in pl022. 663ca632f55SGrant Likely */ 664ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 665ca632f55SGrant Likely { 666ca632f55SGrant Likely 667ca632f55SGrant Likely /* 668ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 669ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 670ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 671ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 672ca632f55SGrant Likely * 673ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 674ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 675ca632f55SGrant Likely * FIFO status flag indicates. 676ca632f55SGrant Likely */ 677ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 678ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 679ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 680ca632f55SGrant Likely 681ca632f55SGrant Likely /* Read as much as you can */ 682ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 683ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 684ca632f55SGrant Likely switch (pl022->read) { 685ca632f55SGrant Likely case READING_NULL: 686ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 687ca632f55SGrant Likely break; 688ca632f55SGrant Likely case READING_U8: 689ca632f55SGrant Likely *(u8 *) (pl022->rx) = 690ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 691ca632f55SGrant Likely break; 692ca632f55SGrant Likely case READING_U16: 693ca632f55SGrant Likely *(u16 *) (pl022->rx) = 694ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 695ca632f55SGrant Likely break; 696ca632f55SGrant Likely case READING_U32: 697ca632f55SGrant Likely *(u32 *) (pl022->rx) = 698ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 699ca632f55SGrant Likely break; 700ca632f55SGrant Likely } 701ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 702ca632f55SGrant Likely pl022->exp_fifo_level--; 703ca632f55SGrant Likely } 704ca632f55SGrant Likely /* 705ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 706ca632f55SGrant Likely */ 707ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 708ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 709ca632f55SGrant Likely switch (pl022->write) { 710ca632f55SGrant Likely case WRITING_NULL: 711ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 712ca632f55SGrant Likely break; 713ca632f55SGrant Likely case WRITING_U8: 714ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 715ca632f55SGrant Likely break; 716ca632f55SGrant Likely case WRITING_U16: 717ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 718ca632f55SGrant Likely break; 719ca632f55SGrant Likely case WRITING_U32: 720ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 721ca632f55SGrant Likely break; 722ca632f55SGrant Likely } 723ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 724ca632f55SGrant Likely pl022->exp_fifo_level++; 725ca632f55SGrant Likely /* 726ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 727ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 728ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 729ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 730ca632f55SGrant Likely */ 731ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 732ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 733ca632f55SGrant Likely switch (pl022->read) { 734ca632f55SGrant Likely case READING_NULL: 735ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 736ca632f55SGrant Likely break; 737ca632f55SGrant Likely case READING_U8: 738ca632f55SGrant Likely *(u8 *) (pl022->rx) = 739ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 740ca632f55SGrant Likely break; 741ca632f55SGrant Likely case READING_U16: 742ca632f55SGrant Likely *(u16 *) (pl022->rx) = 743ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 744ca632f55SGrant Likely break; 745ca632f55SGrant Likely case READING_U32: 746ca632f55SGrant Likely *(u32 *) (pl022->rx) = 747ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 748ca632f55SGrant Likely break; 749ca632f55SGrant Likely } 750ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 751ca632f55SGrant Likely pl022->exp_fifo_level--; 752ca632f55SGrant Likely } 753ca632f55SGrant Likely } 754ca632f55SGrant Likely /* 755ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 756ca632f55SGrant Likely * should be empty 757ca632f55SGrant Likely */ 758ca632f55SGrant Likely } 759ca632f55SGrant Likely 760ca632f55SGrant Likely /** 761ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 762ca632f55SGrant Likely * @pl022: SSP driver private data structure 763ca632f55SGrant Likely * 764ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 765ca632f55SGrant Likely * current spi message and returns with the state of current spi 766ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 767ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 768ca632f55SGrant Likely */ 769ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 770ca632f55SGrant Likely { 771ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 772ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 773ca632f55SGrant Likely 774ca632f55SGrant Likely /* Move to next transfer */ 775ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 776ca632f55SGrant Likely pl022->cur_transfer = 777ca632f55SGrant Likely list_entry(trans->transfer_list.next, 778ca632f55SGrant Likely struct spi_transfer, transfer_list); 779ca632f55SGrant Likely return STATE_RUNNING; 780ca632f55SGrant Likely } 781ca632f55SGrant Likely return STATE_DONE; 782ca632f55SGrant Likely } 783ca632f55SGrant Likely 784ca632f55SGrant Likely /* 785ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 786ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 787ca632f55SGrant Likely */ 788ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 789ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 790ca632f55SGrant Likely { 791ca632f55SGrant Likely /* Unmap and free the SG tables */ 792ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 793ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 794ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 795ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 796ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 797ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 798ca632f55SGrant Likely } 799ca632f55SGrant Likely 800ca632f55SGrant Likely static void dma_callback(void *data) 801ca632f55SGrant Likely { 802ca632f55SGrant Likely struct pl022 *pl022 = data; 803ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 804ca632f55SGrant Likely 805ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 806ca632f55SGrant Likely 807ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 808ca632f55SGrant Likely /* 809ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 810ca632f55SGrant Likely * good if you want to convince yourself that the loopback 811ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 812ca632f55SGrant Likely * DMA engine. 813ca632f55SGrant Likely */ 814ca632f55SGrant Likely { 815ca632f55SGrant Likely struct scatterlist *sg; 816ca632f55SGrant Likely unsigned int i; 817ca632f55SGrant Likely 818ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 819ca632f55SGrant Likely pl022->sgt_rx.sgl, 820ca632f55SGrant Likely pl022->sgt_rx.nents, 821ca632f55SGrant Likely DMA_FROM_DEVICE); 822ca632f55SGrant Likely 823ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 824ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 825ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 826ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 827ca632f55SGrant Likely 16, 828ca632f55SGrant Likely 1, 829ca632f55SGrant Likely sg_virt(sg), 830ca632f55SGrant Likely sg_dma_len(sg), 831ca632f55SGrant Likely 1); 832ca632f55SGrant Likely } 833ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 834ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 835ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 836ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 837ca632f55SGrant Likely 16, 838ca632f55SGrant Likely 1, 839ca632f55SGrant Likely sg_virt(sg), 840ca632f55SGrant Likely sg_dma_len(sg), 841ca632f55SGrant Likely 1); 842ca632f55SGrant Likely } 843ca632f55SGrant Likely } 844ca632f55SGrant Likely #endif 845ca632f55SGrant Likely 846ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 847ca632f55SGrant Likely 848ca632f55SGrant Likely /* Update total bytes transferred */ 849ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 850ca632f55SGrant Likely /* Move to next transfer */ 851ca632f55SGrant Likely msg->state = next_transfer(pl022); 852c0b07605SFredrik Ternerot if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) 853c0b07605SFredrik Ternerot pl022_cs_control(pl022, SSP_CHIP_DESELECT); 854ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 855ca632f55SGrant Likely } 856ca632f55SGrant Likely 857ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 858ca632f55SGrant Likely void *buffer, 859ca632f55SGrant Likely unsigned int length, 860ca632f55SGrant Likely struct sg_table *sgtab) 861ca632f55SGrant Likely { 862ca632f55SGrant Likely struct scatterlist *sg; 863ca632f55SGrant Likely int bytesleft = length; 864ca632f55SGrant Likely void *bufp = buffer; 865ca632f55SGrant Likely int mapbytes; 866ca632f55SGrant Likely int i; 867ca632f55SGrant Likely 868ca632f55SGrant Likely if (buffer) { 869ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 870ca632f55SGrant Likely /* 871ca632f55SGrant Likely * If there are less bytes left than what fits 872ca632f55SGrant Likely * in the current page (plus page alignment offset) 873ca632f55SGrant Likely * we just feed in this, else we stuff in as much 874ca632f55SGrant Likely * as we can. 875ca632f55SGrant Likely */ 876ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 877ca632f55SGrant Likely mapbytes = bytesleft; 878ca632f55SGrant Likely else 879ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 880ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 881ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 882ca632f55SGrant Likely bufp += mapbytes; 883ca632f55SGrant Likely bytesleft -= mapbytes; 884ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 885ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 886ca632f55SGrant Likely bufp, mapbytes, bytesleft); 887ca632f55SGrant Likely } 888ca632f55SGrant Likely } else { 889ca632f55SGrant Likely /* Map the dummy buffer on every page */ 890ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 891ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 892ca632f55SGrant Likely mapbytes = bytesleft; 893ca632f55SGrant Likely else 894ca632f55SGrant Likely mapbytes = PAGE_SIZE; 895ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 896ca632f55SGrant Likely mapbytes, 0); 897ca632f55SGrant Likely bytesleft -= mapbytes; 898ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 899ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 900ca632f55SGrant Likely mapbytes, bytesleft); 901ca632f55SGrant Likely 902ca632f55SGrant Likely } 903ca632f55SGrant Likely } 904ca632f55SGrant Likely BUG_ON(bytesleft); 905ca632f55SGrant Likely } 906ca632f55SGrant Likely 907ca632f55SGrant Likely /** 908ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 909ca632f55SGrant Likely * @pl022: SSP driver's private data structure 910ca632f55SGrant Likely */ 911ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 912ca632f55SGrant Likely { 913ca632f55SGrant Likely struct dma_slave_config rx_conf = { 914ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 915a485df4bSVinod Koul .direction = DMA_DEV_TO_MEM, 916258aea76SViresh Kumar .device_fc = false, 917ca632f55SGrant Likely }; 918ca632f55SGrant Likely struct dma_slave_config tx_conf = { 919ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 920a485df4bSVinod Koul .direction = DMA_MEM_TO_DEV, 921258aea76SViresh Kumar .device_fc = false, 922ca632f55SGrant Likely }; 923ca632f55SGrant Likely unsigned int pages; 924ca632f55SGrant Likely int ret; 925ca632f55SGrant Likely int rx_sglen, tx_sglen; 926ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 927ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 928ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 929ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 930ca632f55SGrant Likely 931ca632f55SGrant Likely /* Check that the channels are available */ 932ca632f55SGrant Likely if (!rxchan || !txchan) 933ca632f55SGrant Likely return -ENODEV; 934ca632f55SGrant Likely 935083be3f0SLinus Walleij /* 936083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 937083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 938083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 939083be3f0SLinus Walleij * calculation. 940083be3f0SLinus Walleij */ 941083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 942083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 943083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 944083be3f0SLinus Walleij break; 945083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 946083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 947083be3f0SLinus Walleij break; 948083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 949083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 950083be3f0SLinus Walleij break; 951083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 952083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 953083be3f0SLinus Walleij break; 954083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 955083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 956083be3f0SLinus Walleij break; 957083be3f0SLinus Walleij default: 958083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 959083be3f0SLinus Walleij break; 960083be3f0SLinus Walleij } 961083be3f0SLinus Walleij 962083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 963083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 964083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 965083be3f0SLinus Walleij break; 966083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 967083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 968083be3f0SLinus Walleij break; 969083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 970083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 971083be3f0SLinus Walleij break; 972083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 973083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 974083be3f0SLinus Walleij break; 975083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 976083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 977083be3f0SLinus Walleij break; 978083be3f0SLinus Walleij default: 979083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 980083be3f0SLinus Walleij break; 981083be3f0SLinus Walleij } 982083be3f0SLinus Walleij 983ca632f55SGrant Likely switch (pl022->read) { 984ca632f55SGrant Likely case READING_NULL: 985ca632f55SGrant Likely /* Use the same as for writing */ 986ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 987ca632f55SGrant Likely break; 988ca632f55SGrant Likely case READING_U8: 989ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 990ca632f55SGrant Likely break; 991ca632f55SGrant Likely case READING_U16: 992ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 993ca632f55SGrant Likely break; 994ca632f55SGrant Likely case READING_U32: 995ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 996ca632f55SGrant Likely break; 997ca632f55SGrant Likely } 998ca632f55SGrant Likely 999ca632f55SGrant Likely switch (pl022->write) { 1000ca632f55SGrant Likely case WRITING_NULL: 1001ca632f55SGrant Likely /* Use the same as for reading */ 1002ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1003ca632f55SGrant Likely break; 1004ca632f55SGrant Likely case WRITING_U8: 1005ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1006ca632f55SGrant Likely break; 1007ca632f55SGrant Likely case WRITING_U16: 1008ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1009ca632f55SGrant Likely break; 1010ca632f55SGrant Likely case WRITING_U32: 1011ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1012ca632f55SGrant Likely break; 1013ca632f55SGrant Likely } 1014ca632f55SGrant Likely 1015ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 1016ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1017ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 1018ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1019ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 1020ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1021ca632f55SGrant Likely 1022ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 1023ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 1024ca632f55SGrant Likely 1025ca632f55SGrant Likely /* Create sglists for the transfers */ 1026b181565eSViresh Kumar pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1027ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1028ca632f55SGrant Likely 1029538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1030ca632f55SGrant Likely if (ret) 1031ca632f55SGrant Likely goto err_alloc_rx_sg; 1032ca632f55SGrant Likely 1033538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1034ca632f55SGrant Likely if (ret) 1035ca632f55SGrant Likely goto err_alloc_tx_sg; 1036ca632f55SGrant Likely 1037ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1038ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1039ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1040ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1041ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1042ca632f55SGrant Likely 1043ca632f55SGrant Likely /* Map DMA buffers */ 1044ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1045ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1046ca632f55SGrant Likely if (!rx_sglen) 1047ca632f55SGrant Likely goto err_rx_sgmap; 1048ca632f55SGrant Likely 1049ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1050ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1051ca632f55SGrant Likely if (!tx_sglen) 1052ca632f55SGrant Likely goto err_tx_sgmap; 1053ca632f55SGrant Likely 1054ca632f55SGrant Likely /* Send both scatterlists */ 105516052827SAlexandre Bounine rxdesc = dmaengine_prep_slave_sg(rxchan, 1056ca632f55SGrant Likely pl022->sgt_rx.sgl, 1057ca632f55SGrant Likely rx_sglen, 1058a485df4bSVinod Koul DMA_DEV_TO_MEM, 1059ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1060ca632f55SGrant Likely if (!rxdesc) 1061ca632f55SGrant Likely goto err_rxdesc; 1062ca632f55SGrant Likely 106316052827SAlexandre Bounine txdesc = dmaengine_prep_slave_sg(txchan, 1064ca632f55SGrant Likely pl022->sgt_tx.sgl, 1065ca632f55SGrant Likely tx_sglen, 1066a485df4bSVinod Koul DMA_MEM_TO_DEV, 1067ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1068ca632f55SGrant Likely if (!txdesc) 1069ca632f55SGrant Likely goto err_txdesc; 1070ca632f55SGrant Likely 1071ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1072ca632f55SGrant Likely rxdesc->callback = dma_callback; 1073ca632f55SGrant Likely rxdesc->callback_param = pl022; 1074ca632f55SGrant Likely 1075ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1076ca632f55SGrant Likely dmaengine_submit(rxdesc); 1077ca632f55SGrant Likely dmaengine_submit(txdesc); 1078ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1079ca632f55SGrant Likely dma_async_issue_pending(txchan); 1080ffbbdd21SLinus Walleij pl022->dma_running = true; 1081ca632f55SGrant Likely 1082ca632f55SGrant Likely return 0; 1083ca632f55SGrant Likely 1084ca632f55SGrant Likely err_txdesc: 1085ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1086ca632f55SGrant Likely err_rxdesc: 1087ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1088ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1089ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1090ca632f55SGrant Likely err_tx_sgmap: 1091ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 10923ffa6158SRay Jui pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1093ca632f55SGrant Likely err_rx_sgmap: 1094ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1095ca632f55SGrant Likely err_alloc_tx_sg: 1096ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1097ca632f55SGrant Likely err_alloc_rx_sg: 1098ca632f55SGrant Likely return -ENOMEM; 1099ca632f55SGrant Likely } 1100ca632f55SGrant Likely 1101fd4a319bSGrant Likely static int pl022_dma_probe(struct pl022 *pl022) 1102ca632f55SGrant Likely { 1103ca632f55SGrant Likely dma_cap_mask_t mask; 1104ca632f55SGrant Likely 1105ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1106ca632f55SGrant Likely dma_cap_zero(mask); 1107ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1108ca632f55SGrant Likely /* 1109ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1110ca632f55SGrant Likely * of them. 1111ca632f55SGrant Likely */ 1112ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1113ca632f55SGrant Likely pl022->master_info->dma_filter, 1114ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1115ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1116ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1117ca632f55SGrant Likely goto err_no_rxchan; 1118ca632f55SGrant Likely } 1119ca632f55SGrant Likely 1120ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1121ca632f55SGrant Likely pl022->master_info->dma_filter, 1122ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1123ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1124ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1125ca632f55SGrant Likely goto err_no_txchan; 1126ca632f55SGrant Likely } 1127ca632f55SGrant Likely 1128ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 112977538f4aSJingoo Han if (!pl022->dummypage) 1130ca632f55SGrant Likely goto err_no_dummypage; 1131ca632f55SGrant Likely 1132ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1133ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1134ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1135ca632f55SGrant Likely 1136ca632f55SGrant Likely return 0; 1137ca632f55SGrant Likely 1138ca632f55SGrant Likely err_no_dummypage: 1139ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1140ca632f55SGrant Likely err_no_txchan: 1141ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1142ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1143ca632f55SGrant Likely err_no_rxchan: 1144ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1145ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1146ca632f55SGrant Likely return -ENODEV; 1147ca632f55SGrant Likely } 1148ca632f55SGrant Likely 1149dc715452SArnd Bergmann static int pl022_dma_autoprobe(struct pl022 *pl022) 1150dc715452SArnd Bergmann { 1151dc715452SArnd Bergmann struct device *dev = &pl022->adev->dev; 1152f3d4bb33SRabin Vincent struct dma_chan *chan; 1153f3d4bb33SRabin Vincent int err; 1154dc715452SArnd Bergmann 1155dc715452SArnd Bergmann /* automatically configure DMA channels from platform, normally using DT */ 1156c1008957SPeter Ujfalusi chan = dma_request_chan(dev, "rx"); 1157f3d4bb33SRabin Vincent if (IS_ERR(chan)) { 1158f3d4bb33SRabin Vincent err = PTR_ERR(chan); 1159dc715452SArnd Bergmann goto err_no_rxchan; 1160f3d4bb33SRabin Vincent } 1161dc715452SArnd Bergmann 1162f3d4bb33SRabin Vincent pl022->dma_rx_channel = chan; 1163f3d4bb33SRabin Vincent 1164c1008957SPeter Ujfalusi chan = dma_request_chan(dev, "tx"); 1165f3d4bb33SRabin Vincent if (IS_ERR(chan)) { 1166f3d4bb33SRabin Vincent err = PTR_ERR(chan); 1167dc715452SArnd Bergmann goto err_no_txchan; 1168f3d4bb33SRabin Vincent } 1169f3d4bb33SRabin Vincent 1170f3d4bb33SRabin Vincent pl022->dma_tx_channel = chan; 1171dc715452SArnd Bergmann 1172dc715452SArnd Bergmann pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1173f3d4bb33SRabin Vincent if (!pl022->dummypage) { 1174f3d4bb33SRabin Vincent err = -ENOMEM; 1175dc715452SArnd Bergmann goto err_no_dummypage; 1176f3d4bb33SRabin Vincent } 1177dc715452SArnd Bergmann 1178dc715452SArnd Bergmann return 0; 1179dc715452SArnd Bergmann 1180dc715452SArnd Bergmann err_no_dummypage: 1181dc715452SArnd Bergmann dma_release_channel(pl022->dma_tx_channel); 1182dc715452SArnd Bergmann pl022->dma_tx_channel = NULL; 1183dc715452SArnd Bergmann err_no_txchan: 1184dc715452SArnd Bergmann dma_release_channel(pl022->dma_rx_channel); 1185dc715452SArnd Bergmann pl022->dma_rx_channel = NULL; 1186dc715452SArnd Bergmann err_no_rxchan: 1187f3d4bb33SRabin Vincent return err; 1188dc715452SArnd Bergmann } 1189dc715452SArnd Bergmann 1190ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1191ca632f55SGrant Likely { 1192ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1193ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1194ca632f55SGrant Likely 1195ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1196ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1197ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1198ffbbdd21SLinus Walleij pl022->dma_running = false; 1199ca632f55SGrant Likely } 1200ca632f55SGrant Likely 1201ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1202ca632f55SGrant Likely { 1203ffbbdd21SLinus Walleij if (pl022->dma_running) 1204ca632f55SGrant Likely terminate_dma(pl022); 1205ca632f55SGrant Likely if (pl022->dma_tx_channel) 1206ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1207ca632f55SGrant Likely if (pl022->dma_rx_channel) 1208ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1209ca632f55SGrant Likely kfree(pl022->dummypage); 1210ca632f55SGrant Likely } 1211ca632f55SGrant Likely 1212ca632f55SGrant Likely #else 1213ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1214ca632f55SGrant Likely { 1215ca632f55SGrant Likely return -ENODEV; 1216ca632f55SGrant Likely } 1217ca632f55SGrant Likely 1218dc715452SArnd Bergmann static inline int pl022_dma_autoprobe(struct pl022 *pl022) 1219dc715452SArnd Bergmann { 1220dc715452SArnd Bergmann return 0; 1221dc715452SArnd Bergmann } 1222dc715452SArnd Bergmann 1223ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1224ca632f55SGrant Likely { 1225ca632f55SGrant Likely return 0; 1226ca632f55SGrant Likely } 1227ca632f55SGrant Likely 1228ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1229ca632f55SGrant Likely { 1230ca632f55SGrant Likely } 1231ca632f55SGrant Likely #endif 1232ca632f55SGrant Likely 1233ca632f55SGrant Likely /** 1234ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1235c7cd1dfbSLee Jones * @irq: IRQ number 1236c7cd1dfbSLee Jones * @dev_id: Local device data 1237ca632f55SGrant Likely * 1238ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1239ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1240ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1241ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1242ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1243ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1244ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1245ca632f55SGrant Likely */ 1246ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1247ca632f55SGrant Likely { 1248ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1249ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1250ca632f55SGrant Likely u16 irq_status = 0; 1251ca632f55SGrant Likely 1252ca632f55SGrant Likely if (unlikely(!msg)) { 1253ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1254ca632f55SGrant Likely "bad message state in interrupt handler"); 1255ca632f55SGrant Likely /* Never fail */ 1256ca632f55SGrant Likely return IRQ_HANDLED; 1257ca632f55SGrant Likely } 1258ca632f55SGrant Likely 1259ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1260ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1261ca632f55SGrant Likely 1262ca632f55SGrant Likely if (unlikely(!irq_status)) 1263ca632f55SGrant Likely return IRQ_NONE; 1264ca632f55SGrant Likely 1265ca632f55SGrant Likely /* 1266ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1267ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1268ca632f55SGrant Likely * trusted. 1269ca632f55SGrant Likely */ 1270ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1271ca632f55SGrant Likely /* 1272ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1273ca632f55SGrant Likely * corrupted 1274ca632f55SGrant Likely */ 1275ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1276ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1277ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1278ca632f55SGrant Likely "RXFIFO is full\n"); 1279ca632f55SGrant Likely 1280ca632f55SGrant Likely /* 1281ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1282ca632f55SGrant Likely * mark message with bad status so it can be 1283ca632f55SGrant Likely * retried. 1284ca632f55SGrant Likely */ 1285ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1286ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1287ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1288ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1289ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1290ca632f55SGrant Likely msg->state = STATE_ERROR; 1291ca632f55SGrant Likely 1292ca632f55SGrant Likely /* Schedule message queue handler */ 1293ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1294ca632f55SGrant Likely return IRQ_HANDLED; 1295ca632f55SGrant Likely } 1296ca632f55SGrant Likely 1297ca632f55SGrant Likely readwriter(pl022); 1298ca632f55SGrant Likely 12997183d1ebSAlexander Sverdlin if (pl022->tx == pl022->tx_end) { 1300172289dfSChris Blair /* Disable Transmit interrupt, enable receive interrupt */ 1301172289dfSChris Blair writew((readw(SSP_IMSC(pl022->virtbase)) & 1302172289dfSChris Blair ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1303ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1304ca632f55SGrant Likely } 1305ca632f55SGrant Likely 1306ca632f55SGrant Likely /* 1307ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1308ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1309ca632f55SGrant Likely * At this point, all TX will always be finished. 1310ca632f55SGrant Likely */ 1311ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1312ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1313ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1314ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1315ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1316ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1317ca632f55SGrant Likely "bytes (did you request an odd " 1318ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1319ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1320ca632f55SGrant Likely } 1321ca632f55SGrant Likely /* Update total bytes transferred */ 1322ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1323ca632f55SGrant Likely /* Move to next transfer */ 1324ca632f55SGrant Likely msg->state = next_transfer(pl022); 1325c0b07605SFredrik Ternerot if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) 1326c0b07605SFredrik Ternerot pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1327ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1328ca632f55SGrant Likely return IRQ_HANDLED; 1329ca632f55SGrant Likely } 1330ca632f55SGrant Likely 1331ca632f55SGrant Likely return IRQ_HANDLED; 1332ca632f55SGrant Likely } 1333ca632f55SGrant Likely 1334c7cd1dfbSLee Jones /* 1335ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1336ca632f55SGrant Likely * send out on the SPI bus. 1337ca632f55SGrant Likely */ 1338ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1339ca632f55SGrant Likely struct spi_transfer *transfer) 1340ca632f55SGrant Likely { 1341ca632f55SGrant Likely int residue; 1342ca632f55SGrant Likely 1343ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1344ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1345ca632f55SGrant Likely if (unlikely(residue != 0)) { 1346ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1347ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1348ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1349ca632f55SGrant Likely pl022->cur_transfer->len, 1350ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1351ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1352ca632f55SGrant Likely return -EIO; 1353ca632f55SGrant Likely } 1354ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1355ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1356ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1357ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1358ca632f55SGrant Likely pl022->write = 1359ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1360ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1361ca632f55SGrant Likely return 0; 1362ca632f55SGrant Likely } 1363ca632f55SGrant Likely 1364ca632f55SGrant Likely /** 1365ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1366ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1367ca632f55SGrant Likely * @data: SSP driver private data structure 1368ca632f55SGrant Likely * 1369ca632f55SGrant Likely */ 1370ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1371ca632f55SGrant Likely { 1372ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1373ca632f55SGrant Likely struct spi_message *message = NULL; 1374ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1375ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1376ca632f55SGrant Likely 1377ca632f55SGrant Likely /* Get current state information */ 1378ca632f55SGrant Likely message = pl022->cur_msg; 1379ca632f55SGrant Likely transfer = pl022->cur_transfer; 1380ca632f55SGrant Likely 1381ca632f55SGrant Likely /* Handle for abort */ 1382ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1383ca632f55SGrant Likely message->status = -EIO; 1384ca632f55SGrant Likely giveback(pl022); 1385ca632f55SGrant Likely return; 1386ca632f55SGrant Likely } 1387ca632f55SGrant Likely 1388ca632f55SGrant Likely /* Handle end of message */ 1389ca632f55SGrant Likely if (message->state == STATE_DONE) { 1390ca632f55SGrant Likely message->status = 0; 1391ca632f55SGrant Likely giveback(pl022); 1392ca632f55SGrant Likely return; 1393ca632f55SGrant Likely } 1394ca632f55SGrant Likely 1395ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1396ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1397ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1398ca632f55SGrant Likely struct spi_transfer, 1399ca632f55SGrant Likely transfer_list); 1400ca632f55SGrant Likely /* 1401ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1402ca632f55SGrant Likely * Is this really smart? 1403ca632f55SGrant Likely */ 1404e74dc5c7SAlexandru Ardelean spi_transfer_delay_exec(previous); 1405ca632f55SGrant Likely 14068b8d7191SVirupax Sadashivpetimath /* Reselect chip select only if cs_change was requested */ 1407ca632f55SGrant Likely if (previous->cs_change) 1408f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1409ca632f55SGrant Likely } else { 1410ca632f55SGrant Likely /* STATE_START */ 1411ca632f55SGrant Likely message->state = STATE_RUNNING; 1412ca632f55SGrant Likely } 1413ca632f55SGrant Likely 1414ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1415ca632f55SGrant Likely message->state = STATE_ERROR; 1416ca632f55SGrant Likely message->status = -EIO; 1417ca632f55SGrant Likely giveback(pl022); 1418ca632f55SGrant Likely return; 1419ca632f55SGrant Likely } 1420ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1421ca632f55SGrant Likely flush(pl022); 1422ca632f55SGrant Likely 1423ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1424ca632f55SGrant Likely if (configure_dma(pl022)) { 1425ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1426ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1427ca632f55SGrant Likely goto err_config_dma; 1428ca632f55SGrant Likely } 1429ca632f55SGrant Likely return; 1430ca632f55SGrant Likely } 1431ca632f55SGrant Likely 1432ca632f55SGrant Likely err_config_dma: 1433172289dfSChris Blair /* enable all interrupts except RX */ 1434172289dfSChris Blair writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1435ca632f55SGrant Likely } 1436ca632f55SGrant Likely 1437ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1438ca632f55SGrant Likely { 1439172289dfSChris Blair /* 1440172289dfSChris Blair * Default is to enable all interrupts except RX - 1441172289dfSChris Blair * this will be enabled once TX is complete 1442172289dfSChris Blair */ 1443d555ea05SMark Brown u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); 1444ca632f55SGrant Likely 14458b8d7191SVirupax Sadashivpetimath /* Enable target chip, if not already active */ 14468b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1447f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 14488b8d7191SVirupax Sadashivpetimath 1449ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1450ca632f55SGrant Likely /* Error path */ 1451ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1452ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1453ca632f55SGrant Likely giveback(pl022); 1454ca632f55SGrant Likely return; 1455ca632f55SGrant Likely } 1456ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1457ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1458ca632f55SGrant Likely /* Configure DMA transfer */ 1459ca632f55SGrant Likely if (configure_dma(pl022)) { 1460ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1461ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1462ca632f55SGrant Likely goto err_config_dma; 1463ca632f55SGrant Likely } 1464ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1465ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1466ca632f55SGrant Likely } 1467ca632f55SGrant Likely err_config_dma: 1468ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1469ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1470ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1471ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1472ca632f55SGrant Likely } 1473ca632f55SGrant Likely 14747aef2b64SJiwei Sun static void print_current_status(struct pl022 *pl022) 14757aef2b64SJiwei Sun { 14767aef2b64SJiwei Sun u32 read_cr0; 14777aef2b64SJiwei Sun u16 read_cr1, read_dmacr, read_sr; 14787aef2b64SJiwei Sun 14797aef2b64SJiwei Sun if (pl022->vendor->extended_cr) 14807aef2b64SJiwei Sun read_cr0 = readl(SSP_CR0(pl022->virtbase)); 14817aef2b64SJiwei Sun else 14827aef2b64SJiwei Sun read_cr0 = readw(SSP_CR0(pl022->virtbase)); 14837aef2b64SJiwei Sun read_cr1 = readw(SSP_CR1(pl022->virtbase)); 14847aef2b64SJiwei Sun read_dmacr = readw(SSP_DMACR(pl022->virtbase)); 14857aef2b64SJiwei Sun read_sr = readw(SSP_SR(pl022->virtbase)); 14867aef2b64SJiwei Sun 14877aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); 14887aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); 14897aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); 14907aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); 14917aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, 14927aef2b64SJiwei Sun "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", 14937aef2b64SJiwei Sun pl022->exp_fifo_level, 14947aef2b64SJiwei Sun pl022->vendor->fifodepth); 14957aef2b64SJiwei Sun 14967aef2b64SJiwei Sun } 14977aef2b64SJiwei Sun 1498ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1499ca632f55SGrant Likely { 1500ca632f55SGrant Likely struct spi_message *message = NULL; 1501ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1502ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1503ca632f55SGrant Likely unsigned long time, timeout; 1504ca632f55SGrant Likely 1505ca632f55SGrant Likely message = pl022->cur_msg; 1506ca632f55SGrant Likely 1507ca632f55SGrant Likely while (message->state != STATE_DONE) { 1508ca632f55SGrant Likely /* Handle for abort */ 1509ca632f55SGrant Likely if (message->state == STATE_ERROR) 1510ca632f55SGrant Likely break; 1511ca632f55SGrant Likely transfer = pl022->cur_transfer; 1512ca632f55SGrant Likely 1513ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1514ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1515ca632f55SGrant Likely previous = 1516ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1517ca632f55SGrant Likely struct spi_transfer, transfer_list); 1518e74dc5c7SAlexandru Ardelean spi_transfer_delay_exec(previous); 1519ca632f55SGrant Likely if (previous->cs_change) 1520f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1521ca632f55SGrant Likely } else { 1522ca632f55SGrant Likely /* STATE_START */ 1523ca632f55SGrant Likely message->state = STATE_RUNNING; 15248b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1525f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1526ca632f55SGrant Likely } 1527ca632f55SGrant Likely 1528ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1529ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1530ca632f55SGrant Likely /* Error path */ 1531ca632f55SGrant Likely message->state = STATE_ERROR; 1532ca632f55SGrant Likely break; 1533ca632f55SGrant Likely } 1534ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1535ca632f55SGrant Likely flush(pl022); 1536ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1537ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1538ca632f55SGrant Likely 1539ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1540ca632f55SGrant Likely 1541ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1542ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1543ca632f55SGrant Likely time = jiffies; 1544ca632f55SGrant Likely readwriter(pl022); 1545ca632f55SGrant Likely if (time_after(time, timeout)) { 1546ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1547ca632f55SGrant Likely "%s: timeout!\n", __func__); 15487aef2b64SJiwei Sun message->state = STATE_TIMEOUT; 15497aef2b64SJiwei Sun print_current_status(pl022); 1550ca632f55SGrant Likely goto out; 1551ca632f55SGrant Likely } 1552ca632f55SGrant Likely cpu_relax(); 1553ca632f55SGrant Likely } 1554ca632f55SGrant Likely 1555ca632f55SGrant Likely /* Update total byte transferred */ 1556ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1557ca632f55SGrant Likely /* Move to next transfer */ 1558ca632f55SGrant Likely message->state = next_transfer(pl022); 1559c0b07605SFredrik Ternerot if (message->state != STATE_DONE 1560c0b07605SFredrik Ternerot && pl022->cur_transfer->cs_change) 1561c0b07605SFredrik Ternerot pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1562ca632f55SGrant Likely } 1563ca632f55SGrant Likely out: 1564ca632f55SGrant Likely /* Handle end of message */ 1565ca632f55SGrant Likely if (message->state == STATE_DONE) 1566ca632f55SGrant Likely message->status = 0; 15677aef2b64SJiwei Sun else if (message->state == STATE_TIMEOUT) 15687aef2b64SJiwei Sun message->status = -EAGAIN; 1569ca632f55SGrant Likely else 1570ca632f55SGrant Likely message->status = -EIO; 1571ca632f55SGrant Likely 1572ca632f55SGrant Likely giveback(pl022); 1573ca632f55SGrant Likely return; 1574ca632f55SGrant Likely } 1575ca632f55SGrant Likely 1576ffbbdd21SLinus Walleij static int pl022_transfer_one_message(struct spi_master *master, 1577ffbbdd21SLinus Walleij struct spi_message *msg) 1578ca632f55SGrant Likely { 1579ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1580ca632f55SGrant Likely 1581ffbbdd21SLinus Walleij /* Initial message state */ 1582ffbbdd21SLinus Walleij pl022->cur_msg = msg; 1583ffbbdd21SLinus Walleij msg->state = STATE_START; 1584ffbbdd21SLinus Walleij 1585ffbbdd21SLinus Walleij pl022->cur_transfer = list_entry(msg->transfers.next, 1586ffbbdd21SLinus Walleij struct spi_transfer, transfer_list); 1587ffbbdd21SLinus Walleij 1588ffbbdd21SLinus Walleij /* Setup the SPI using the per chip configuration */ 1589ffbbdd21SLinus Walleij pl022->cur_chip = spi_get_ctldata(msg->spi); 159077f983a9SLinus Walleij pl022->cur_cs = msg->spi->chip_select; 159177f983a9SLinus Walleij /* This is always available but may be set to -ENOENT */ 15928bb2dbf1SLinus Walleij pl022->cur_gpiod = msg->spi->cs_gpiod; 1593ffbbdd21SLinus Walleij 1594ffbbdd21SLinus Walleij restore_state(pl022); 1595ffbbdd21SLinus Walleij flush(pl022); 1596ffbbdd21SLinus Walleij 1597ffbbdd21SLinus Walleij if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1598ffbbdd21SLinus Walleij do_polling_transfer(pl022); 1599ffbbdd21SLinus Walleij else 1600ffbbdd21SLinus Walleij do_interrupt_dma_transfer(pl022); 1601ffbbdd21SLinus Walleij 1602ffbbdd21SLinus Walleij return 0; 1603ffbbdd21SLinus Walleij } 1604ffbbdd21SLinus Walleij 1605ffbbdd21SLinus Walleij static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1606ffbbdd21SLinus Walleij { 1607ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1608ffbbdd21SLinus Walleij 16090ad2deeaSVirupax Sadashivpetimath /* nothing more to do - disable spi/ssp and power off */ 16100ad2deeaSVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 16110ad2deeaSVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 161253e4aceaSChris Blair 1613ca632f55SGrant Likely return 0; 1614ca632f55SGrant Likely } 1615ca632f55SGrant Likely 1616ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1617ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1618ca632f55SGrant Likely { 1619ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1620ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1621ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1622ca632f55SGrant Likely "interface is configured incorrectly\n"); 1623ca632f55SGrant Likely return -EINVAL; 1624ca632f55SGrant Likely } 1625ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1626ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1627ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1628ca632f55SGrant Likely "unidirectional mode not supported in this " 1629ca632f55SGrant Likely "hardware version\n"); 1630ca632f55SGrant Likely return -EINVAL; 1631ca632f55SGrant Likely } 1632ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1633ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1634ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1635ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1636ca632f55SGrant Likely return -EINVAL; 1637ca632f55SGrant Likely } 1638ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1639ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1640ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1641ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1642ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1643ca632f55SGrant Likely return -EINVAL; 1644ca632f55SGrant Likely } 164578b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 164678b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 164778b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 164878b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 164978b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 165078b2b911SLinus Walleij break; 165178b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 165278b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1653ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1654ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1655ca632f55SGrant Likely return -EINVAL; 1656ca632f55SGrant Likely } 165778b2b911SLinus Walleij break; 165878b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 165978b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 166078b2b911SLinus Walleij dev_err(&pl022->adev->dev, 166178b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 166278b2b911SLinus Walleij return -EINVAL; 166378b2b911SLinus Walleij } 166478b2b911SLinus Walleij break; 166578b2b911SLinus Walleij default: 166678b2b911SLinus Walleij dev_err(&pl022->adev->dev, 166778b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 166878b2b911SLinus Walleij return -EINVAL; 166978b2b911SLinus Walleij } 167078b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 167178b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 167278b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 167378b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 167478b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 167578b2b911SLinus Walleij break; 167678b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 167778b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1678ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1679ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1680ca632f55SGrant Likely return -EINVAL; 1681ca632f55SGrant Likely } 168278b2b911SLinus Walleij break; 168378b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 168478b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 168578b2b911SLinus Walleij dev_err(&pl022->adev->dev, 168678b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 168778b2b911SLinus Walleij return -EINVAL; 168878b2b911SLinus Walleij } 168978b2b911SLinus Walleij break; 169078b2b911SLinus Walleij default: 169178b2b911SLinus Walleij dev_err(&pl022->adev->dev, 169278b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 169378b2b911SLinus Walleij return -EINVAL; 169478b2b911SLinus Walleij } 1695ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1696ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1697ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1698ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1699ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1700ca632f55SGrant Likely return -EINVAL; 1701ca632f55SGrant Likely } 1702ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1703ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1704ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1705ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1706ca632f55SGrant Likely return -EINVAL; 1707ca632f55SGrant Likely } 1708ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1709ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1710ca632f55SGrant Likely if ((chip_info->duplex != 1711ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1712ca632f55SGrant Likely && (chip_info->duplex != 1713ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1714ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1715ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1716ca632f55SGrant Likely return -EINVAL; 1717ca632f55SGrant Likely } 1718ca632f55SGrant Likely } else { 1719*d81d0e41SThomas Perrot if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) { 1720ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1721ca632f55SGrant Likely "Microwire half duplex mode requested," 1722ca632f55SGrant Likely " but this is only available in the" 1723ca632f55SGrant Likely " ST version of PL022\n"); 1724ca632f55SGrant Likely return -EINVAL; 1725ca632f55SGrant Likely } 1726ca632f55SGrant Likely } 1727*d81d0e41SThomas Perrot } 1728ca632f55SGrant Likely return 0; 1729ca632f55SGrant Likely } 1730ca632f55SGrant Likely 17310379b2a3SViresh Kumar static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 17320379b2a3SViresh Kumar { 17330379b2a3SViresh Kumar return rate / (cpsdvsr * (1 + scr)); 17340379b2a3SViresh Kumar } 17350379b2a3SViresh Kumar 17360379b2a3SViresh Kumar static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 17370379b2a3SViresh Kumar ssp_clock_params * clk_freq) 1738ca632f55SGrant Likely { 1739ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 17400379b2a3SViresh Kumar u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 17410379b2a3SViresh Kumar u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 17420379b2a3SViresh Kumar best_scr = 0, tmp, found = 0; 1743ca632f55SGrant Likely 1744ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1745ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 17460379b2a3SViresh Kumar max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1747ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 17480379b2a3SViresh Kumar min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1749ca632f55SGrant Likely 1750ea505bc9SViresh Kumar if (freq > max_tclk) 1751ea505bc9SViresh Kumar dev_warn(&pl022->adev->dev, 1752ea505bc9SViresh Kumar "Max speed that can be programmed is %d Hz, you requested %d\n", 1753ea505bc9SViresh Kumar max_tclk, freq); 1754ea505bc9SViresh Kumar 1755ea505bc9SViresh Kumar if (freq < min_tclk) { 1756ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1757ea505bc9SViresh Kumar "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1758ea505bc9SViresh Kumar freq, min_tclk); 1759ca632f55SGrant Likely return -EINVAL; 1760ca632f55SGrant Likely } 17610379b2a3SViresh Kumar 17620379b2a3SViresh Kumar /* 17630379b2a3SViresh Kumar * best_freq will give closest possible available rate (<= requested 17640379b2a3SViresh Kumar * freq) for all values of scr & cpsdvsr. 17650379b2a3SViresh Kumar */ 17660379b2a3SViresh Kumar while ((cpsdvsr <= CPSDVR_MAX) && !found) { 17670379b2a3SViresh Kumar while (scr <= SCR_MAX) { 17680379b2a3SViresh Kumar tmp = spi_rate(rate, cpsdvsr, scr); 17690379b2a3SViresh Kumar 17705eb806a3SViresh Kumar if (tmp > freq) { 17715eb806a3SViresh Kumar /* we need lower freq */ 17720379b2a3SViresh Kumar scr++; 17735eb806a3SViresh Kumar continue; 17745eb806a3SViresh Kumar } 17755eb806a3SViresh Kumar 17760379b2a3SViresh Kumar /* 17775eb806a3SViresh Kumar * If found exact value, mark found and break. 17785eb806a3SViresh Kumar * If found more closer value, update and break. 17790379b2a3SViresh Kumar */ 17805eb806a3SViresh Kumar if (tmp > best_freq) { 17810379b2a3SViresh Kumar best_freq = tmp; 17820379b2a3SViresh Kumar best_cpsdvsr = cpsdvsr; 17830379b2a3SViresh Kumar best_scr = scr; 17840379b2a3SViresh Kumar 17850379b2a3SViresh Kumar if (tmp == freq) 17865eb806a3SViresh Kumar found = 1; 17870379b2a3SViresh Kumar } 17885eb806a3SViresh Kumar /* 17895eb806a3SViresh Kumar * increased scr will give lower rates, which are not 17905eb806a3SViresh Kumar * required 17915eb806a3SViresh Kumar */ 17925eb806a3SViresh Kumar break; 17930379b2a3SViresh Kumar } 17940379b2a3SViresh Kumar cpsdvsr += 2; 17950379b2a3SViresh Kumar scr = SCR_MIN; 1796ca632f55SGrant Likely } 1797ca632f55SGrant Likely 17985eb806a3SViresh Kumar WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 17995eb806a3SViresh Kumar freq); 18005eb806a3SViresh Kumar 18010379b2a3SViresh Kumar clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 18020379b2a3SViresh Kumar clk_freq->scr = (u8) (best_scr & 0xFF); 18030379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, 18040379b2a3SViresh Kumar "SSP Target Frequency is: %u, Effective Frequency is %u\n", 18050379b2a3SViresh Kumar freq, best_freq); 18060379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 18070379b2a3SViresh Kumar clk_freq->cpsdvsr, clk_freq->scr); 18080379b2a3SViresh Kumar 1809ca632f55SGrant Likely return 0; 1810ca632f55SGrant Likely } 1811ca632f55SGrant Likely 1812ca632f55SGrant Likely /* 1813ca632f55SGrant Likely * A piece of default chip info unless the platform 1814ca632f55SGrant Likely * supplies it. 1815ca632f55SGrant Likely */ 1816ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1817413c601eSLinus Walleij .com_mode = INTERRUPT_TRANSFER, 1818ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1819413c601eSLinus Walleij .hierarchy = SSP_MASTER, 1820ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1821ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1822ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1823ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1824ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1825ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1826ca632f55SGrant Likely }; 1827ca632f55SGrant Likely 1828ca632f55SGrant Likely /** 1829ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1830ca632f55SGrant Likely * @spi: spi device which is requesting setup 1831ca632f55SGrant Likely * 1832ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1833ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1834ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1835ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1836ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1837ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1838ca632f55SGrant Likely * commence. 1839ca632f55SGrant Likely */ 1840ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1841ca632f55SGrant Likely { 1842ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 18436d3952a7SRoland Stigge struct pl022_config_chip chip_info_dt; 1844ca632f55SGrant Likely struct chip_data *chip; 1845c4a47843SJonas Aaberg struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1846ca632f55SGrant Likely int status = 0; 1847ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1848ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1849ca632f55SGrant Likely u32 tmp; 18506d3952a7SRoland Stigge struct device_node *np = spi->dev.of_node; 1851ca632f55SGrant Likely 1852ca632f55SGrant Likely if (!spi->max_speed_hz) 1853ca632f55SGrant Likely return -EINVAL; 1854ca632f55SGrant Likely 1855ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1856ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1857ca632f55SGrant Likely 1858ca632f55SGrant Likely if (chip == NULL) { 1859ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 186077538f4aSJingoo Han if (!chip) 1861ca632f55SGrant Likely return -ENOMEM; 1862ca632f55SGrant Likely dev_dbg(&spi->dev, 1863ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1864ca632f55SGrant Likely } 1865ca632f55SGrant Likely 1866ca632f55SGrant Likely /* Get controller data if one is supplied */ 1867ca632f55SGrant Likely chip_info = spi->controller_data; 1868ca632f55SGrant Likely 1869ca632f55SGrant Likely if (chip_info == NULL) { 18706d3952a7SRoland Stigge if (np) { 18716d3952a7SRoland Stigge chip_info_dt = pl022_default_chip_info; 18726d3952a7SRoland Stigge 18736d3952a7SRoland Stigge chip_info_dt.hierarchy = SSP_MASTER; 18746d3952a7SRoland Stigge of_property_read_u32(np, "pl022,interface", 18756d3952a7SRoland Stigge &chip_info_dt.iface); 18766d3952a7SRoland Stigge of_property_read_u32(np, "pl022,com-mode", 18776d3952a7SRoland Stigge &chip_info_dt.com_mode); 18786d3952a7SRoland Stigge of_property_read_u32(np, "pl022,rx-level-trig", 18796d3952a7SRoland Stigge &chip_info_dt.rx_lev_trig); 18806d3952a7SRoland Stigge of_property_read_u32(np, "pl022,tx-level-trig", 18816d3952a7SRoland Stigge &chip_info_dt.tx_lev_trig); 18826d3952a7SRoland Stigge of_property_read_u32(np, "pl022,ctrl-len", 18836d3952a7SRoland Stigge &chip_info_dt.ctrl_len); 18846d3952a7SRoland Stigge of_property_read_u32(np, "pl022,wait-state", 18856d3952a7SRoland Stigge &chip_info_dt.wait_state); 18866d3952a7SRoland Stigge of_property_read_u32(np, "pl022,duplex", 18876d3952a7SRoland Stigge &chip_info_dt.duplex); 18886d3952a7SRoland Stigge 18896d3952a7SRoland Stigge chip_info = &chip_info_dt; 18906d3952a7SRoland Stigge } else { 1891ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1892ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1893ca632f55SGrant Likely dev_dbg(&spi->dev, 1894ca632f55SGrant Likely "using default controller_data settings\n"); 18956d3952a7SRoland Stigge } 1896ca632f55SGrant Likely } else 1897ca632f55SGrant Likely dev_dbg(&spi->dev, 1898ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1899ca632f55SGrant Likely 1900ca632f55SGrant Likely /* 1901ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1902ca632f55SGrant Likely * frequency setting 1903ca632f55SGrant Likely */ 1904ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1905ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1906ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1907ca632f55SGrant Likely spi->max_speed_hz, 1908ca632f55SGrant Likely &clk_freq); 1909ca632f55SGrant Likely if (status < 0) 1910ca632f55SGrant Likely goto err_config_params; 1911ca632f55SGrant Likely } else { 1912ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1913ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1914ca632f55SGrant Likely clk_freq.cpsdvsr = 1915ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1916ca632f55SGrant Likely } 1917ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1918ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1919f8db4cc4SGrant Likely status = -EINVAL; 1920ca632f55SGrant Likely dev_err(&spi->dev, 1921ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1922ca632f55SGrant Likely goto err_config_params; 1923ca632f55SGrant Likely } 1924ca632f55SGrant Likely 1925ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1926ca632f55SGrant Likely if (status) { 1927ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1928ca632f55SGrant Likely goto err_config_params; 1929ca632f55SGrant Likely } 1930ca632f55SGrant Likely 1931083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1932083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1933083be3f0SLinus Walleij 1934ca632f55SGrant Likely /* Now set controller state based on controller data */ 1935ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1936ca632f55SGrant Likely 1937eb798c64SVinit Shenoy /* Check bits per word with vendor specific range */ 1938eb798c64SVinit Shenoy if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1939ca632f55SGrant Likely status = -ENOTSUPP; 1940eb798c64SVinit Shenoy dev_err(&spi->dev, "illegal data size for this controller!\n"); 1941eb798c64SVinit Shenoy dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1942eb798c64SVinit Shenoy pl022->vendor->max_bpw); 1943ca632f55SGrant Likely goto err_config_params; 1944ca632f55SGrant Likely } else if (bits <= 8) { 1945ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1946ca632f55SGrant Likely chip->n_bytes = 1; 1947ca632f55SGrant Likely chip->read = READING_U8; 1948ca632f55SGrant Likely chip->write = WRITING_U8; 1949ca632f55SGrant Likely } else if (bits <= 16) { 1950ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1951ca632f55SGrant Likely chip->n_bytes = 2; 1952ca632f55SGrant Likely chip->read = READING_U16; 1953ca632f55SGrant Likely chip->write = WRITING_U16; 1954ca632f55SGrant Likely } else { 1955ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1956ca632f55SGrant Likely chip->n_bytes = 4; 1957ca632f55SGrant Likely chip->read = READING_U32; 1958ca632f55SGrant Likely chip->write = WRITING_U32; 1959ca632f55SGrant Likely } 1960ca632f55SGrant Likely 1961ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 1962ca632f55SGrant Likely chip->cr0 = 0; 1963ca632f55SGrant Likely chip->cr1 = 0; 1964ca632f55SGrant Likely chip->dmacr = 0; 1965ca632f55SGrant Likely chip->cpsr = 0; 1966ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 1967ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 1968ca632f55SGrant Likely chip->enable_dma = true; 1969ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1970ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1971ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1972ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1973ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1974ca632f55SGrant Likely } else { 1975ca632f55SGrant Likely chip->enable_dma = false; 1976ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1977ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1978ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1979ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1980ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1981ca632f55SGrant Likely } 1982ca632f55SGrant Likely 1983ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 1984ca632f55SGrant Likely 1985ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 1986ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1987ca632f55SGrant Likely u32 etx; 1988ca632f55SGrant Likely 1989ca632f55SGrant Likely if (pl022->vendor->pl023) { 1990ca632f55SGrant Likely /* These bits are only in the PL023 */ 1991ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1992ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 1993ca632f55SGrant Likely } else { 1994ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 1995ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1996ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 1997ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1998ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 1999ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2000ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 2001ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2002ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 2003ca632f55SGrant Likely } 2004ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2005ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 2006ca632f55SGrant Likely 2007ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 2008ca632f55SGrant Likely tmp = SSP_RX_LSB; 2009ca632f55SGrant Likely etx = SSP_TX_LSB; 2010ca632f55SGrant Likely } else { 2011ca632f55SGrant Likely tmp = SSP_RX_MSB; 2012ca632f55SGrant Likely etx = SSP_TX_MSB; 2013ca632f55SGrant Likely } 2014ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2015ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2016ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2017ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 2018ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2019ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 2020ca632f55SGrant Likely } else { 2021ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2022ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 2023ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2024ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 2025ca632f55SGrant Likely } 2026ca632f55SGrant Likely 2027ca632f55SGrant Likely /* Stuff that is common for all versions */ 2028ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 2029ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 2030ca632f55SGrant Likely else 2031ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 2032ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2033ca632f55SGrant Likely 2034ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 2035ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 2036ca632f55SGrant Likely else 2037ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 2038ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2039ca632f55SGrant Likely 2040ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2041ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 2042ca632f55SGrant Likely if (pl022->vendor->loopback) { 2043ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 2044ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 2045ca632f55SGrant Likely else 2046ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 2047ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2048ca632f55SGrant Likely } 2049ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2050ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2051f1e45f86SViresh Kumar SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2052f1e45f86SViresh Kumar 3); 2053ca632f55SGrant Likely 2054ca632f55SGrant Likely /* Save controller_state */ 2055ca632f55SGrant Likely spi_set_ctldata(spi, chip); 2056ca632f55SGrant Likely return status; 2057ca632f55SGrant Likely err_config_params: 2058ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2059ca632f55SGrant Likely kfree(chip); 2060ca632f55SGrant Likely return status; 2061ca632f55SGrant Likely } 2062ca632f55SGrant Likely 2063ca632f55SGrant Likely /** 2064ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 2065ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 2066ca632f55SGrant Likely * 2067ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 2068ca632f55SGrant Likely * controller. It will free the runtime state of chip. 2069ca632f55SGrant Likely */ 2070ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 2071ca632f55SGrant Likely { 2072ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 2073ca632f55SGrant Likely 2074ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2075ca632f55SGrant Likely kfree(chip); 2076ca632f55SGrant Likely } 2077ca632f55SGrant Likely 207839a6ac11SRoland Stigge static struct pl022_ssp_controller * 207939a6ac11SRoland Stigge pl022_platform_data_dt_get(struct device *dev) 208039a6ac11SRoland Stigge { 208139a6ac11SRoland Stigge struct device_node *np = dev->of_node; 208239a6ac11SRoland Stigge struct pl022_ssp_controller *pd; 208339a6ac11SRoland Stigge 208439a6ac11SRoland Stigge if (!np) { 208539a6ac11SRoland Stigge dev_err(dev, "no dt node defined\n"); 208639a6ac11SRoland Stigge return NULL; 208739a6ac11SRoland Stigge } 208839a6ac11SRoland Stigge 208939a6ac11SRoland Stigge pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 209077538f4aSJingoo Han if (!pd) 209139a6ac11SRoland Stigge return NULL; 209239a6ac11SRoland Stigge 209339a6ac11SRoland Stigge pd->bus_id = -1; 2094dbd897b9SLinus Walleij pd->enable_dma = 1; 209539a6ac11SRoland Stigge of_property_read_u32(np, "pl022,autosuspend-delay", 209639a6ac11SRoland Stigge &pd->autosuspend_delay); 209739a6ac11SRoland Stigge pd->rt = of_property_read_bool(np, "pl022,rt"); 209839a6ac11SRoland Stigge 209939a6ac11SRoland Stigge return pd; 210039a6ac11SRoland Stigge } 210139a6ac11SRoland Stigge 2102fd4a319bSGrant Likely static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2103ca632f55SGrant Likely { 2104ca632f55SGrant Likely struct device *dev = &adev->dev; 21058074cf06SJingoo Han struct pl022_ssp_controller *platform_info = 21068074cf06SJingoo Han dev_get_platdata(&adev->dev); 2107ca632f55SGrant Likely struct spi_master *master; 2108ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 210977f983a9SLinus Walleij int status = 0; 2110ca632f55SGrant Likely 2111ca632f55SGrant Likely dev_info(&adev->dev, 2112ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 211339a6ac11SRoland Stigge if (!platform_info && IS_ENABLED(CONFIG_OF)) 211439a6ac11SRoland Stigge platform_info = pl022_platform_data_dt_get(dev); 211539a6ac11SRoland Stigge 211639a6ac11SRoland Stigge if (!platform_info) { 211739a6ac11SRoland Stigge dev_err(dev, "probe: no platform data defined\n"); 2118aeef9915SLinus Walleij return -ENODEV; 2119ca632f55SGrant Likely } 2120ca632f55SGrant Likely 2121ca632f55SGrant Likely /* Allocate master with space for data */ 2122b4b84826SRoland Stigge master = spi_alloc_master(dev, sizeof(struct pl022)); 2123ca632f55SGrant Likely if (master == NULL) { 2124ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2125aeef9915SLinus Walleij return -ENOMEM; 2126ca632f55SGrant Likely } 2127ca632f55SGrant Likely 2128ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 2129ca632f55SGrant Likely pl022->master = master; 2130ca632f55SGrant Likely pl022->master_info = platform_info; 2131ca632f55SGrant Likely pl022->adev = adev; 2132ca632f55SGrant Likely pl022->vendor = id->data; 2133ca632f55SGrant Likely 2134ca632f55SGrant Likely /* 2135ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2136ca632f55SGrant Likely * on this board 2137ca632f55SGrant Likely */ 2138ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 2139ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2140ca632f55SGrant Likely master->setup = pl022_setup; 214129b6e906SMark Brown master->auto_runtime_pm = true; 2142ffbbdd21SLinus Walleij master->transfer_one_message = pl022_transfer_one_message; 2143ffbbdd21SLinus Walleij master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2144ffbbdd21SLinus Walleij master->rt = platform_info->rt; 21456d3952a7SRoland Stigge master->dev.of_node = dev->of_node; 21468bb2dbf1SLinus Walleij master->use_gpio_descriptors = true; 2147ca632f55SGrant Likely 2148ca632f55SGrant Likely /* 2149ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2150ca632f55SGrant Likely * always MS bit first on the original pl022. 2151ca632f55SGrant Likely */ 2152ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2153ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2154ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2155ca632f55SGrant Likely 2156ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2157ca632f55SGrant Likely 2158ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2159ca632f55SGrant Likely if (status) 2160ca632f55SGrant Likely goto err_no_ioregion; 2161ca632f55SGrant Likely 2162ca632f55SGrant Likely pl022->phybase = adev->res.start; 2163aeef9915SLinus Walleij pl022->virtbase = devm_ioremap(dev, adev->res.start, 2164aeef9915SLinus Walleij resource_size(&adev->res)); 2165ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2166ca632f55SGrant Likely status = -ENOMEM; 2167ca632f55SGrant Likely goto err_no_ioremap; 2168ca632f55SGrant Likely } 21692c067509SJingoo Han dev_info(&adev->dev, "mapped registers from %pa to %p\n", 21707085f403SFabio Estevam &adev->res.start, pl022->virtbase); 2171ca632f55SGrant Likely 2172aeef9915SLinus Walleij pl022->clk = devm_clk_get(&adev->dev, NULL); 2173ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2174ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2175ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2176ca632f55SGrant Likely goto err_no_clk; 2177ca632f55SGrant Likely } 21787ff6bcf0SRussell King 21796cac167bSUlf Hansson status = clk_prepare_enable(pl022->clk); 218071e63e74SUlf Hansson if (status) { 218171e63e74SUlf Hansson dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 218271e63e74SUlf Hansson goto err_no_clk_en; 218371e63e74SUlf Hansson } 218471e63e74SUlf Hansson 2185ffbbdd21SLinus Walleij /* Initialize transfer pump */ 2186ffbbdd21SLinus Walleij tasklet_init(&pl022->pump_transfers, pump_transfers, 2187ffbbdd21SLinus Walleij (unsigned long)pl022); 2188ffbbdd21SLinus Walleij 2189ca632f55SGrant Likely /* Disable SSP */ 2190ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2191ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2192ca632f55SGrant Likely load_ssp_default_config(pl022); 2193ca632f55SGrant Likely 2194aeef9915SLinus Walleij status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2195aeef9915SLinus Walleij 0, "pl022", pl022); 2196ca632f55SGrant Likely if (status < 0) { 2197ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2198ca632f55SGrant Likely goto err_no_irq; 2199ca632f55SGrant Likely } 2200ca632f55SGrant Likely 2201dc715452SArnd Bergmann /* Get DMA channels, try autoconfiguration first */ 2202dc715452SArnd Bergmann status = pl022_dma_autoprobe(pl022); 2203f3d4bb33SRabin Vincent if (status == -EPROBE_DEFER) { 2204f3d4bb33SRabin Vincent dev_dbg(dev, "deferring probe to get DMA channel\n"); 2205f3d4bb33SRabin Vincent goto err_no_irq; 2206f3d4bb33SRabin Vincent } 2207dc715452SArnd Bergmann 2208dc715452SArnd Bergmann /* If that failed, use channels from platform_info */ 2209dc715452SArnd Bergmann if (status == 0) 2210dc715452SArnd Bergmann platform_info->enable_dma = 1; 2211dc715452SArnd Bergmann else if (platform_info->enable_dma) { 2212ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2213ca632f55SGrant Likely if (status != 0) 2214ca632f55SGrant Likely platform_info->enable_dma = 0; 2215ca632f55SGrant Likely } 2216ca632f55SGrant Likely 2217ca632f55SGrant Likely /* Register with the SPI framework */ 2218ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 221935794a77SJingoo Han status = devm_spi_register_master(&adev->dev, master); 2220ca632f55SGrant Likely if (status != 0) { 2221ca632f55SGrant Likely dev_err(&adev->dev, 2222ca632f55SGrant Likely "probe - problem registering spi master\n"); 2223ca632f55SGrant Likely goto err_spi_register; 2224ca632f55SGrant Likely } 2225ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 222692b97f0aSRussell King 222792b97f0aSRussell King /* let runtime pm put suspend */ 222853e4aceaSChris Blair if (platform_info->autosuspend_delay > 0) { 222953e4aceaSChris Blair dev_info(&adev->dev, 223053e4aceaSChris Blair "will use autosuspend for runtime pm, delay %dms\n", 223153e4aceaSChris Blair platform_info->autosuspend_delay); 223253e4aceaSChris Blair pm_runtime_set_autosuspend_delay(dev, 223353e4aceaSChris Blair platform_info->autosuspend_delay); 223453e4aceaSChris Blair pm_runtime_use_autosuspend(dev); 223553e4aceaSChris Blair } 22360df34994SUlf Hansson pm_runtime_put(dev); 22370df34994SUlf Hansson 2238ca632f55SGrant Likely return 0; 2239ca632f55SGrant Likely 2240ca632f55SGrant Likely err_spi_register: 22413e3ea716SViresh Kumar if (platform_info->enable_dma) 2242ca632f55SGrant Likely pl022_dma_remove(pl022); 2243ca632f55SGrant Likely err_no_irq: 22446cac167bSUlf Hansson clk_disable_unprepare(pl022->clk); 224571e63e74SUlf Hansson err_no_clk_en: 2246ca632f55SGrant Likely err_no_clk: 2247ca632f55SGrant Likely err_no_ioremap: 2248ca632f55SGrant Likely amba_release_regions(adev); 2249ca632f55SGrant Likely err_no_ioregion: 2250ca632f55SGrant Likely spi_master_put(master); 2251ca632f55SGrant Likely return status; 2252ca632f55SGrant Likely } 2253ca632f55SGrant Likely 22543fd269e7SUwe Kleine-König static void 2255ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2256ca632f55SGrant Likely { 2257ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 225850658b66SLinus Walleij 2259ca632f55SGrant Likely if (!pl022) 22603fd269e7SUwe Kleine-König return; 2261ca632f55SGrant Likely 226292b97f0aSRussell King /* 226392b97f0aSRussell King * undo pm_runtime_put() in probe. I assume that we're not 226492b97f0aSRussell King * accessing the primecell here. 226592b97f0aSRussell King */ 226692b97f0aSRussell King pm_runtime_get_noresume(&adev->dev); 226792b97f0aSRussell King 2268ca632f55SGrant Likely load_ssp_default_config(pl022); 22693e3ea716SViresh Kumar if (pl022->master_info->enable_dma) 2270ca632f55SGrant Likely pl022_dma_remove(pl022); 22713e3ea716SViresh Kumar 22726cac167bSUlf Hansson clk_disable_unprepare(pl022->clk); 2273ca632f55SGrant Likely amba_release_regions(adev); 2274ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2275ca632f55SGrant Likely } 2276ca632f55SGrant Likely 227784a5dc41SUlf Hansson #ifdef CONFIG_PM_SLEEP 22786cfa6279SPeter Hüwe static int pl022_suspend(struct device *dev) 2279ca632f55SGrant Likely { 228092b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2281ffbbdd21SLinus Walleij int ret; 2282ca632f55SGrant Likely 2283ffbbdd21SLinus Walleij ret = spi_master_suspend(pl022->master); 22847c5d8a24SGeert Uytterhoeven if (ret) 2285ffbbdd21SLinus Walleij return ret; 22864964a26dSUlf Hansson 228784a5dc41SUlf Hansson ret = pm_runtime_force_suspend(dev); 228884a5dc41SUlf Hansson if (ret) { 228984a5dc41SUlf Hansson spi_master_resume(pl022->master); 229084a5dc41SUlf Hansson return ret; 229184a5dc41SUlf Hansson } 229284a5dc41SUlf Hansson 229384a5dc41SUlf Hansson pinctrl_pm_select_sleep_state(dev); 2294ca632f55SGrant Likely 22956cfa6279SPeter Hüwe dev_dbg(dev, "suspended\n"); 2296ca632f55SGrant Likely return 0; 2297ca632f55SGrant Likely } 2298ca632f55SGrant Likely 229992b97f0aSRussell King static int pl022_resume(struct device *dev) 2300ca632f55SGrant Likely { 230192b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2302ffbbdd21SLinus Walleij int ret; 2303ca632f55SGrant Likely 230484a5dc41SUlf Hansson ret = pm_runtime_force_resume(dev); 230584a5dc41SUlf Hansson if (ret) 230684a5dc41SUlf Hansson dev_err(dev, "problem resuming\n"); 2307ada7aec7SLinus Walleij 2308ca632f55SGrant Likely /* Start the queue running */ 2309ffbbdd21SLinus Walleij ret = spi_master_resume(pl022->master); 23107c5d8a24SGeert Uytterhoeven if (!ret) 231192b97f0aSRussell King dev_dbg(dev, "resumed\n"); 2312ca632f55SGrant Likely 2313ffbbdd21SLinus Walleij return ret; 2314ca632f55SGrant Likely } 231584a5dc41SUlf Hansson #endif 2316ca632f55SGrant Likely 2317736198b0SUlf Hansson #ifdef CONFIG_PM 231892b97f0aSRussell King static int pl022_runtime_suspend(struct device *dev) 231992b97f0aSRussell King { 232092b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 232192b97f0aSRussell King 232284a5dc41SUlf Hansson clk_disable_unprepare(pl022->clk); 232384a5dc41SUlf Hansson pinctrl_pm_select_idle_state(dev); 232484a5dc41SUlf Hansson 232592b97f0aSRussell King return 0; 232692b97f0aSRussell King } 232792b97f0aSRussell King 232892b97f0aSRussell King static int pl022_runtime_resume(struct device *dev) 232992b97f0aSRussell King { 233092b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 23314f5e1b37SPatrice Chotard 233284a5dc41SUlf Hansson pinctrl_pm_select_default_state(dev); 233384a5dc41SUlf Hansson clk_prepare_enable(pl022->clk); 233484a5dc41SUlf Hansson 233592b97f0aSRussell King return 0; 233692b97f0aSRussell King } 233792b97f0aSRussell King #endif 233892b97f0aSRussell King 233992b97f0aSRussell King static const struct dev_pm_ops pl022_dev_pm_ops = { 234092b97f0aSRussell King SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 23416ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 234292b97f0aSRussell King }; 234392b97f0aSRussell King 2344ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2345ca632f55SGrant Likely .fifodepth = 8, 2346ca632f55SGrant Likely .max_bpw = 16, 2347ca632f55SGrant Likely .unidir = false, 2348ca632f55SGrant Likely .extended_cr = false, 2349ca632f55SGrant Likely .pl023 = false, 2350ca632f55SGrant Likely .loopback = true, 2351db4fa45eSAnders Berg .internal_cs_ctrl = false, 2352ca632f55SGrant Likely }; 2353ca632f55SGrant Likely 2354ca632f55SGrant Likely static struct vendor_data vendor_st = { 2355ca632f55SGrant Likely .fifodepth = 32, 2356ca632f55SGrant Likely .max_bpw = 32, 2357ca632f55SGrant Likely .unidir = false, 2358ca632f55SGrant Likely .extended_cr = true, 2359ca632f55SGrant Likely .pl023 = false, 2360ca632f55SGrant Likely .loopback = true, 2361db4fa45eSAnders Berg .internal_cs_ctrl = false, 2362ca632f55SGrant Likely }; 2363ca632f55SGrant Likely 2364ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2365ca632f55SGrant Likely .fifodepth = 32, 2366ca632f55SGrant Likely .max_bpw = 32, 2367ca632f55SGrant Likely .unidir = false, 2368ca632f55SGrant Likely .extended_cr = true, 2369ca632f55SGrant Likely .pl023 = true, 2370ca632f55SGrant Likely .loopback = false, 2371db4fa45eSAnders Berg .internal_cs_ctrl = false, 2372db4fa45eSAnders Berg }; 2373db4fa45eSAnders Berg 2374db4fa45eSAnders Berg static struct vendor_data vendor_lsi = { 2375db4fa45eSAnders Berg .fifodepth = 8, 2376db4fa45eSAnders Berg .max_bpw = 16, 2377db4fa45eSAnders Berg .unidir = false, 2378db4fa45eSAnders Berg .extended_cr = false, 2379db4fa45eSAnders Berg .pl023 = false, 2380db4fa45eSAnders Berg .loopback = true, 2381db4fa45eSAnders Berg .internal_cs_ctrl = true, 2382ca632f55SGrant Likely }; 2383ca632f55SGrant Likely 23845b8d5ad2SArvind Yadav static const struct amba_id pl022_ids[] = { 2385ca632f55SGrant Likely { 2386ca632f55SGrant Likely /* 2387ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2388ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2389ca632f55SGrant Likely */ 2390ca632f55SGrant Likely .id = 0x00041022, 2391ca632f55SGrant Likely .mask = 0x000fffff, 2392ca632f55SGrant Likely .data = &vendor_arm, 2393ca632f55SGrant Likely }, 2394ca632f55SGrant Likely { 2395ca632f55SGrant Likely /* 2396ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2397ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2398ca632f55SGrant Likely */ 2399ca632f55SGrant Likely .id = 0x01080022, 2400ca632f55SGrant Likely .mask = 0xffffffff, 2401ca632f55SGrant Likely .data = &vendor_st, 2402ca632f55SGrant Likely }, 2403ca632f55SGrant Likely { 2404ca632f55SGrant Likely /* 2405ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2406ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2407ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2408ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2409ca632f55SGrant Likely * CR0/CR1 register 2410ca632f55SGrant Likely */ 2411ca632f55SGrant Likely .id = 0x00080023, 2412ca632f55SGrant Likely .mask = 0xffffffff, 2413ca632f55SGrant Likely .data = &vendor_st_pl023, 2414ca632f55SGrant Likely }, 2415db4fa45eSAnders Berg { 2416db4fa45eSAnders Berg /* 2417db4fa45eSAnders Berg * PL022 variant that has a chip select control register whih 2418db4fa45eSAnders Berg * allows control of 5 output signals nCS[0:4]. 2419db4fa45eSAnders Berg */ 2420db4fa45eSAnders Berg .id = 0x000b6022, 2421db4fa45eSAnders Berg .mask = 0x000fffff, 2422db4fa45eSAnders Berg .data = &vendor_lsi, 2423db4fa45eSAnders Berg }, 2424ca632f55SGrant Likely { 0, 0 }, 2425ca632f55SGrant Likely }; 2426ca632f55SGrant Likely 24277eeac71bSDave Martin MODULE_DEVICE_TABLE(amba, pl022_ids); 24287eeac71bSDave Martin 2429ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2430ca632f55SGrant Likely .drv = { 2431ca632f55SGrant Likely .name = "ssp-pl022", 243292b97f0aSRussell King .pm = &pl022_dev_pm_ops, 2433ca632f55SGrant Likely }, 2434ca632f55SGrant Likely .id_table = pl022_ids, 2435ca632f55SGrant Likely .probe = pl022_probe, 2436fd4a319bSGrant Likely .remove = pl022_remove, 2437ca632f55SGrant Likely }; 2438ca632f55SGrant Likely 2439ca632f55SGrant Likely static int __init pl022_init(void) 2440ca632f55SGrant Likely { 2441ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2442ca632f55SGrant Likely } 2443ca632f55SGrant Likely subsys_initcall(pl022_init); 2444ca632f55SGrant Likely 2445ca632f55SGrant Likely static void __exit pl022_exit(void) 2446ca632f55SGrant Likely { 2447ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2448ca632f55SGrant Likely } 2449ca632f55SGrant Likely module_exit(pl022_exit); 2450ca632f55SGrant Likely 2451ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2452ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2453ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2454