1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2008-2009 ST-Ericsson AB 5ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6ca632f55SGrant Likely * 7ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * Initial version inspired by: 10ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11ca632f55SGrant Likely * Initial adoption to PL022 by: 12ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 15ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 16ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 17ca632f55SGrant Likely * (at your option) any later version. 18ca632f55SGrant Likely * 19ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 20ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 21ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22ca632f55SGrant Likely * GNU General Public License for more details. 23ca632f55SGrant Likely */ 24ca632f55SGrant Likely 25ca632f55SGrant Likely #include <linux/init.h> 26ca632f55SGrant Likely #include <linux/module.h> 27ca632f55SGrant Likely #include <linux/device.h> 28ca632f55SGrant Likely #include <linux/ioport.h> 29ca632f55SGrant Likely #include <linux/errno.h> 30ca632f55SGrant Likely #include <linux/interrupt.h> 31ca632f55SGrant Likely #include <linux/spi/spi.h> 32ca632f55SGrant Likely #include <linux/workqueue.h> 33ca632f55SGrant Likely #include <linux/delay.h> 34ca632f55SGrant Likely #include <linux/clk.h> 35ca632f55SGrant Likely #include <linux/err.h> 36ca632f55SGrant Likely #include <linux/amba/bus.h> 37ca632f55SGrant Likely #include <linux/amba/pl022.h> 38ca632f55SGrant Likely #include <linux/io.h> 39ca632f55SGrant Likely #include <linux/slab.h> 40ca632f55SGrant Likely #include <linux/dmaengine.h> 41ca632f55SGrant Likely #include <linux/dma-mapping.h> 42ca632f55SGrant Likely #include <linux/scatterlist.h> 43bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 44ca632f55SGrant Likely 45ca632f55SGrant Likely /* 46ca632f55SGrant Likely * This macro is used to define some register default values. 47ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 48ca632f55SGrant Likely * val shifted sb steps to the left. 49ca632f55SGrant Likely */ 50ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 51ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 52ca632f55SGrant Likely 53ca632f55SGrant Likely /* 54ca632f55SGrant Likely * This macro is also used to define some default values. 55ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 56ca632f55SGrant Likely * the result with mask. 57ca632f55SGrant Likely */ 58ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 59ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 60ca632f55SGrant Likely 61ca632f55SGrant Likely #define DRIVE_TX 0 62ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 63ca632f55SGrant Likely 64ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 65ca632f55SGrant Likely #define QUEUE_DMA 1 66ca632f55SGrant Likely 67ca632f55SGrant Likely #define RX_TRANSFER 1 68ca632f55SGrant Likely #define TX_TRANSFER 2 69ca632f55SGrant Likely 70ca632f55SGrant Likely /* 71ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 72ca632f55SGrant Likely */ 73ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 74ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 75ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 76ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 77ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 78ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 79ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 80ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 81ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 82ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 83ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 84ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 85ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 86ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 87ca632f55SGrant Likely 88ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 89ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 90ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 91ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 92ca632f55SGrant Likely 93ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 94ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 95ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 96ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 97ca632f55SGrant Likely 98ca632f55SGrant Likely /* 99ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 100ca632f55SGrant Likely */ 101ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 102ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 103ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 104ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 105ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 106ca632f55SGrant Likely 107ca632f55SGrant Likely /* 108ca632f55SGrant Likely * The ST version of this block moves som bits 109ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 110ca632f55SGrant Likely */ 111ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 112ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 113ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 114ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 115ca632f55SGrant Likely 116ca632f55SGrant Likely /* 117ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 118ca632f55SGrant Likely */ 119ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 120ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 121ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 122ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 123ca632f55SGrant Likely 124ca632f55SGrant Likely /* 125ca632f55SGrant Likely * The ST version of this block adds some bits 126ca632f55SGrant Likely * in SSP_CR1 127ca632f55SGrant Likely */ 128ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 129ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 130ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 131ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 132ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 133ca632f55SGrant Likely /* This one is only in the PL023 variant */ 134ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 135ca632f55SGrant Likely 136ca632f55SGrant Likely /* 137ca632f55SGrant Likely * SSP Status Register - SSP_SR 138ca632f55SGrant Likely */ 139ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 140ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 141ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 142ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 143ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 144ca632f55SGrant Likely 145ca632f55SGrant Likely /* 146ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 147ca632f55SGrant Likely */ 148ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 149ca632f55SGrant Likely 150ca632f55SGrant Likely /* 151ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 152ca632f55SGrant Likely */ 153ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 154ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 155ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 156ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 157ca632f55SGrant Likely 158ca632f55SGrant Likely /* 159ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 160ca632f55SGrant Likely */ 161ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 162ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 163ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 164ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 165ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 166ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 167ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 168ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 169ca632f55SGrant Likely 170ca632f55SGrant Likely /* 171ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 172ca632f55SGrant Likely */ 173ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 174ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 175ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 176ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 177ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 178ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 179ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 180ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 181ca632f55SGrant Likely 182ca632f55SGrant Likely /* 183ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 184ca632f55SGrant Likely */ 185ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 186ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 187ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 188ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 189ca632f55SGrant Likely 190ca632f55SGrant Likely /* 191ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 192ca632f55SGrant Likely */ 193ca632f55SGrant Likely /* Receive DMA Enable bit */ 194ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 195ca632f55SGrant Likely /* Transmit DMA Enable bit */ 196ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 197ca632f55SGrant Likely 198ca632f55SGrant Likely /* 199ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 200ca632f55SGrant Likely */ 201ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 202ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 203ca632f55SGrant Likely 204ca632f55SGrant Likely /* 205ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 206ca632f55SGrant Likely */ 207ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 208ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 209ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 210ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 211ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 212ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 213ca632f55SGrant Likely 214ca632f55SGrant Likely /* 215ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 216ca632f55SGrant Likely */ 217ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 218ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 219ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 220ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 221ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 222ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 223ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 224ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 225ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 226ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 227ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 228ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 229ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 230ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 231ca632f55SGrant Likely 232ca632f55SGrant Likely /* 233ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 234ca632f55SGrant Likely */ 235ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 236ca632f55SGrant Likely 237ca632f55SGrant Likely /* 238ca632f55SGrant Likely * Message State 239ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 240ca632f55SGrant Likely * hold a single state value, that's why all this 241ca632f55SGrant Likely * (void *) casting is done here. 242ca632f55SGrant Likely */ 243ca632f55SGrant Likely #define STATE_START ((void *) 0) 244ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 245ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 246ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 247ca632f55SGrant Likely 248ca632f55SGrant Likely /* 249ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 250ca632f55SGrant Likely */ 251ca632f55SGrant Likely #define SSP_DISABLED (0) 252ca632f55SGrant Likely #define SSP_ENABLED (1) 253ca632f55SGrant Likely 254ca632f55SGrant Likely /* 255ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 256ca632f55SGrant Likely */ 257ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 258ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 259ca632f55SGrant Likely 260ca632f55SGrant Likely /* 261ca632f55SGrant Likely * SSP Clock Defaults 262ca632f55SGrant Likely */ 263ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 264ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 265ca632f55SGrant Likely 266ca632f55SGrant Likely /* 267ca632f55SGrant Likely * SSP Clock Parameter ranges 268ca632f55SGrant Likely */ 269ca632f55SGrant Likely #define CPSDVR_MIN 0x02 270ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 271ca632f55SGrant Likely #define SCR_MIN 0x00 272ca632f55SGrant Likely #define SCR_MAX 0xFF 273ca632f55SGrant Likely 274ca632f55SGrant Likely /* 275ca632f55SGrant Likely * SSP Interrupt related Macros 276ca632f55SGrant Likely */ 277ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 278ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 279ca632f55SGrant Likely #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 280ca632f55SGrant Likely 281ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 282ca632f55SGrant Likely 283ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 284ca632f55SGrant Likely 285ca632f55SGrant Likely /* 286ca632f55SGrant Likely * The type of reading going on on this chip 287ca632f55SGrant Likely */ 288ca632f55SGrant Likely enum ssp_reading { 289ca632f55SGrant Likely READING_NULL, 290ca632f55SGrant Likely READING_U8, 291ca632f55SGrant Likely READING_U16, 292ca632f55SGrant Likely READING_U32 293ca632f55SGrant Likely }; 294ca632f55SGrant Likely 295ca632f55SGrant Likely /** 296ca632f55SGrant Likely * The type of writing going on on this chip 297ca632f55SGrant Likely */ 298ca632f55SGrant Likely enum ssp_writing { 299ca632f55SGrant Likely WRITING_NULL, 300ca632f55SGrant Likely WRITING_U8, 301ca632f55SGrant Likely WRITING_U16, 302ca632f55SGrant Likely WRITING_U32 303ca632f55SGrant Likely }; 304ca632f55SGrant Likely 305ca632f55SGrant Likely /** 306ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 307ca632f55SGrant Likely * for PL022 derivates 308ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 309ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 310ca632f55SGrant Likely * @unidir: supports unidirection transfers 311ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 312ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 313ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 314ca632f55SGrant Likely */ 315ca632f55SGrant Likely struct vendor_data { 316ca632f55SGrant Likely int fifodepth; 317ca632f55SGrant Likely int max_bpw; 318ca632f55SGrant Likely bool unidir; 319ca632f55SGrant Likely bool extended_cr; 320ca632f55SGrant Likely bool pl023; 321ca632f55SGrant Likely bool loopback; 322ca632f55SGrant Likely }; 323ca632f55SGrant Likely 324ca632f55SGrant Likely /** 325ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 326ca632f55SGrant Likely * @adev: AMBA device model hookup 327ca632f55SGrant Likely * @vendor: vendor data for the IP block 328ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 329ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 330ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 331ca632f55SGrant Likely * @master: SPI framework hookup 332ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 333ca632f55SGrant Likely * @workqueue: a workqueue on which any spi_message request is queued 334ca632f55SGrant Likely * @pump_messages: work struct for scheduling work to the workqueue 335ca632f55SGrant Likely * @queue_lock: spinlock to syncronise access to message queue 336ca632f55SGrant Likely * @queue: message queue 337ca632f55SGrant Likely * @busy: workqueue is busy 338ca632f55SGrant Likely * @running: workqueue is running 339ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 340ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 341ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 342ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 343ca632f55SGrant Likely * @tx: current position in TX buffer to be read 344ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 345ca632f55SGrant Likely * @rx: current position in RX buffer to be written 346ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 347ca632f55SGrant Likely * @read: the type of read currently going on 348ca632f55SGrant Likely * @write: the type of write currently going on 349ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 350ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 351ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 352ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 353ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 354ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 355ca632f55SGrant Likely */ 356ca632f55SGrant Likely struct pl022 { 357ca632f55SGrant Likely struct amba_device *adev; 358ca632f55SGrant Likely struct vendor_data *vendor; 359ca632f55SGrant Likely resource_size_t phybase; 360ca632f55SGrant Likely void __iomem *virtbase; 361ca632f55SGrant Likely struct clk *clk; 362ca632f55SGrant Likely struct spi_master *master; 363ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 364ca632f55SGrant Likely /* Driver message queue */ 365ca632f55SGrant Likely struct workqueue_struct *workqueue; 366ca632f55SGrant Likely struct work_struct pump_messages; 367ca632f55SGrant Likely spinlock_t queue_lock; 368ca632f55SGrant Likely struct list_head queue; 369ca632f55SGrant Likely bool busy; 370ca632f55SGrant Likely bool running; 371ca632f55SGrant Likely /* Message transfer pump */ 372ca632f55SGrant Likely struct tasklet_struct pump_transfers; 373ca632f55SGrant Likely struct spi_message *cur_msg; 374ca632f55SGrant Likely struct spi_transfer *cur_transfer; 375ca632f55SGrant Likely struct chip_data *cur_chip; 376ca632f55SGrant Likely void *tx; 377ca632f55SGrant Likely void *tx_end; 378ca632f55SGrant Likely void *rx; 379ca632f55SGrant Likely void *rx_end; 380ca632f55SGrant Likely enum ssp_reading read; 381ca632f55SGrant Likely enum ssp_writing write; 382ca632f55SGrant Likely u32 exp_fifo_level; 383083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 384083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 385ca632f55SGrant Likely /* DMA settings */ 386ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 387ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 388ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 389ca632f55SGrant Likely struct sg_table sgt_rx; 390ca632f55SGrant Likely struct sg_table sgt_tx; 391ca632f55SGrant Likely char *dummypage; 392ca632f55SGrant Likely #endif 393ca632f55SGrant Likely }; 394ca632f55SGrant Likely 395ca632f55SGrant Likely /** 396ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 397ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 398ca632f55SGrant Likely * register is 32 bits wide rather than just 16 399ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 400ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 401ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 402ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 403ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 404ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 405ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 406ca632f55SGrant Likely * @cs_control: chip select callback provided by chip 407ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 408ca632f55SGrant Likely * 409ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 410ca632f55SGrant Likely * This would be set according to the current message that would be served 411ca632f55SGrant Likely */ 412ca632f55SGrant Likely struct chip_data { 413ca632f55SGrant Likely u32 cr0; 414ca632f55SGrant Likely u16 cr1; 415ca632f55SGrant Likely u16 dmacr; 416ca632f55SGrant Likely u16 cpsr; 417ca632f55SGrant Likely u8 n_bytes; 418ca632f55SGrant Likely bool enable_dma; 419ca632f55SGrant Likely enum ssp_reading read; 420ca632f55SGrant Likely enum ssp_writing write; 421ca632f55SGrant Likely void (*cs_control) (u32 command); 422ca632f55SGrant Likely int xfer_type; 423ca632f55SGrant Likely }; 424ca632f55SGrant Likely 425ca632f55SGrant Likely /** 426ca632f55SGrant Likely * null_cs_control - Dummy chip select function 427ca632f55SGrant Likely * @command: select/delect the chip 428ca632f55SGrant Likely * 429ca632f55SGrant Likely * If no chip select function is provided by client this is used as dummy 430ca632f55SGrant Likely * chip select 431ca632f55SGrant Likely */ 432ca632f55SGrant Likely static void null_cs_control(u32 command) 433ca632f55SGrant Likely { 434ca632f55SGrant Likely pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 435ca632f55SGrant Likely } 436ca632f55SGrant Likely 437ca632f55SGrant Likely /** 438ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 439ca632f55SGrant Likely * callback of this message. Assumes that caller already 440ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 441ca632f55SGrant Likely * @pl022: SSP driver private data structure 442ca632f55SGrant Likely */ 443ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 444ca632f55SGrant Likely { 445ca632f55SGrant Likely struct spi_transfer *last_transfer; 446ca632f55SGrant Likely unsigned long flags; 447ca632f55SGrant Likely struct spi_message *msg; 448ca632f55SGrant Likely void (*curr_cs_control) (u32 command); 449ca632f55SGrant Likely 450ca632f55SGrant Likely /* 451ca632f55SGrant Likely * This local reference to the chip select function 452ca632f55SGrant Likely * is needed because we set curr_chip to NULL 453ca632f55SGrant Likely * as a step toward termininating the message. 454ca632f55SGrant Likely */ 455ca632f55SGrant Likely curr_cs_control = pl022->cur_chip->cs_control; 456ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 457ca632f55SGrant Likely msg = pl022->cur_msg; 458ca632f55SGrant Likely pl022->cur_msg = NULL; 459ca632f55SGrant Likely pl022->cur_transfer = NULL; 460ca632f55SGrant Likely pl022->cur_chip = NULL; 461ca632f55SGrant Likely queue_work(pl022->workqueue, &pl022->pump_messages); 462ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 463ca632f55SGrant Likely 464ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 465ca632f55SGrant Likely struct spi_transfer, 466ca632f55SGrant Likely transfer_list); 467ca632f55SGrant Likely 468ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 469ca632f55SGrant Likely if (last_transfer->delay_usecs) 470ca632f55SGrant Likely /* 471ca632f55SGrant Likely * FIXME: This runs in interrupt context. 472ca632f55SGrant Likely * Is this really smart? 473ca632f55SGrant Likely */ 474ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 475ca632f55SGrant Likely 476ca632f55SGrant Likely /* 477ca632f55SGrant Likely * Drop chip select UNLESS cs_change is true or we are returning 478ca632f55SGrant Likely * a message with an error, or next message is for another chip 479ca632f55SGrant Likely */ 480ca632f55SGrant Likely if (!last_transfer->cs_change) 481ca632f55SGrant Likely curr_cs_control(SSP_CHIP_DESELECT); 482ca632f55SGrant Likely else { 483ca632f55SGrant Likely struct spi_message *next_msg; 484ca632f55SGrant Likely 485ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 486ca632f55SGrant Likely * the next message is for the same chip. Don't waste 487ca632f55SGrant Likely * time with the following tests unless this was hinted. 488ca632f55SGrant Likely * 489ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 490ca632f55SGrant Likely * after calling msg->complete (below) the driver that 491ca632f55SGrant Likely * sent the current message could be unloaded, which 492ca632f55SGrant Likely * could invalidate the cs_control() callback... 493ca632f55SGrant Likely */ 494ca632f55SGrant Likely 495ca632f55SGrant Likely /* get a pointer to the next message, if any */ 496ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 497ca632f55SGrant Likely if (list_empty(&pl022->queue)) 498ca632f55SGrant Likely next_msg = NULL; 499ca632f55SGrant Likely else 500ca632f55SGrant Likely next_msg = list_entry(pl022->queue.next, 501ca632f55SGrant Likely struct spi_message, queue); 502ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 503ca632f55SGrant Likely 504ca632f55SGrant Likely /* see if the next and current messages point 505ca632f55SGrant Likely * to the same chip 506ca632f55SGrant Likely */ 507ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 508ca632f55SGrant Likely next_msg = NULL; 509ca632f55SGrant Likely if (!next_msg || msg->state == STATE_ERROR) 510ca632f55SGrant Likely curr_cs_control(SSP_CHIP_DESELECT); 511ca632f55SGrant Likely } 512ca632f55SGrant Likely msg->state = NULL; 513ca632f55SGrant Likely if (msg->complete) 514ca632f55SGrant Likely msg->complete(msg->context); 515ca632f55SGrant Likely } 516ca632f55SGrant Likely 517ca632f55SGrant Likely /** 518ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 519ca632f55SGrant Likely * @pl022: SSP driver private data structure 520ca632f55SGrant Likely */ 521ca632f55SGrant Likely static int flush(struct pl022 *pl022) 522ca632f55SGrant Likely { 523ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 524ca632f55SGrant Likely 525ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 526ca632f55SGrant Likely do { 527ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 528ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 529ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 530ca632f55SGrant Likely 531ca632f55SGrant Likely pl022->exp_fifo_level = 0; 532ca632f55SGrant Likely 533ca632f55SGrant Likely return limit; 534ca632f55SGrant Likely } 535ca632f55SGrant Likely 536ca632f55SGrant Likely /** 537ca632f55SGrant Likely * restore_state - Load configuration of current chip 538ca632f55SGrant Likely * @pl022: SSP driver private data structure 539ca632f55SGrant Likely */ 540ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 541ca632f55SGrant Likely { 542ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 543ca632f55SGrant Likely 544ca632f55SGrant Likely if (pl022->vendor->extended_cr) 545ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 546ca632f55SGrant Likely else 547ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 548ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 549ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 550ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 551ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 552ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 553ca632f55SGrant Likely } 554ca632f55SGrant Likely 555ca632f55SGrant Likely /* 556ca632f55SGrant Likely * Default SSP Register Values 557ca632f55SGrant Likely */ 558ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 559ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 560ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 561ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 562ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 563ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 564ca632f55SGrant Likely ) 565ca632f55SGrant Likely 566ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 567ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 568ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 569ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 570ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 571ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 572ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 573ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 574ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 575ca632f55SGrant Likely ) 576ca632f55SGrant Likely 577ca632f55SGrant Likely /* The PL023 version is slightly different again */ 578ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 579ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 580ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 581ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 582ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 583ca632f55SGrant Likely ) 584ca632f55SGrant Likely 585ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 586ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 587ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 588ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 589ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 590ca632f55SGrant Likely ) 591ca632f55SGrant Likely 592ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 593ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 594ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 595ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 596ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 597ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 598ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 599ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 600ca632f55SGrant Likely ) 601ca632f55SGrant Likely 602ca632f55SGrant Likely /* 603ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 604ca632f55SGrant Likely * support, and a new clock feedback delay setting. 605ca632f55SGrant Likely */ 606ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 607ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 608ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 609ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 610ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 611ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 612ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 613ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 614ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 615ca632f55SGrant Likely ) 616ca632f55SGrant Likely 617ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 618ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 619ca632f55SGrant Likely ) 620ca632f55SGrant Likely 621ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 622ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 623ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 624ca632f55SGrant Likely ) 625ca632f55SGrant Likely 626ca632f55SGrant Likely /** 627ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 628ca632f55SGrant Likely * @pl022: SSP driver private data structure 629ca632f55SGrant Likely */ 630ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 631ca632f55SGrant Likely { 632ca632f55SGrant Likely if (pl022->vendor->pl023) { 633ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 634ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 635ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 636ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 637ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 638ca632f55SGrant Likely } else { 639ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 640ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 641ca632f55SGrant Likely } 642ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 643ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 644ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 645ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 646ca632f55SGrant Likely } 647ca632f55SGrant Likely 648ca632f55SGrant Likely /** 649ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 650ca632f55SGrant Likely * set in pl022. 651ca632f55SGrant Likely */ 652ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 653ca632f55SGrant Likely { 654ca632f55SGrant Likely 655ca632f55SGrant Likely /* 656ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 657ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 658ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 659ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 660ca632f55SGrant Likely * 661ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 662ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 663ca632f55SGrant Likely * FIFO status flag indicates. 664ca632f55SGrant Likely */ 665ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 666ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 667ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 668ca632f55SGrant Likely 669ca632f55SGrant Likely /* Read as much as you can */ 670ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 671ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 672ca632f55SGrant Likely switch (pl022->read) { 673ca632f55SGrant Likely case READING_NULL: 674ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 675ca632f55SGrant Likely break; 676ca632f55SGrant Likely case READING_U8: 677ca632f55SGrant Likely *(u8 *) (pl022->rx) = 678ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 679ca632f55SGrant Likely break; 680ca632f55SGrant Likely case READING_U16: 681ca632f55SGrant Likely *(u16 *) (pl022->rx) = 682ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 683ca632f55SGrant Likely break; 684ca632f55SGrant Likely case READING_U32: 685ca632f55SGrant Likely *(u32 *) (pl022->rx) = 686ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 687ca632f55SGrant Likely break; 688ca632f55SGrant Likely } 689ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 690ca632f55SGrant Likely pl022->exp_fifo_level--; 691ca632f55SGrant Likely } 692ca632f55SGrant Likely /* 693ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 694ca632f55SGrant Likely */ 695ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 696ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 697ca632f55SGrant Likely switch (pl022->write) { 698ca632f55SGrant Likely case WRITING_NULL: 699ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 700ca632f55SGrant Likely break; 701ca632f55SGrant Likely case WRITING_U8: 702ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 703ca632f55SGrant Likely break; 704ca632f55SGrant Likely case WRITING_U16: 705ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 706ca632f55SGrant Likely break; 707ca632f55SGrant Likely case WRITING_U32: 708ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 709ca632f55SGrant Likely break; 710ca632f55SGrant Likely } 711ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 712ca632f55SGrant Likely pl022->exp_fifo_level++; 713ca632f55SGrant Likely /* 714ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 715ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 716ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 717ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 718ca632f55SGrant Likely */ 719ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 720ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 721ca632f55SGrant Likely switch (pl022->read) { 722ca632f55SGrant Likely case READING_NULL: 723ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 724ca632f55SGrant Likely break; 725ca632f55SGrant Likely case READING_U8: 726ca632f55SGrant Likely *(u8 *) (pl022->rx) = 727ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 728ca632f55SGrant Likely break; 729ca632f55SGrant Likely case READING_U16: 730ca632f55SGrant Likely *(u16 *) (pl022->rx) = 731ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 732ca632f55SGrant Likely break; 733ca632f55SGrant Likely case READING_U32: 734ca632f55SGrant Likely *(u32 *) (pl022->rx) = 735ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 736ca632f55SGrant Likely break; 737ca632f55SGrant Likely } 738ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 739ca632f55SGrant Likely pl022->exp_fifo_level--; 740ca632f55SGrant Likely } 741ca632f55SGrant Likely } 742ca632f55SGrant Likely /* 743ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 744ca632f55SGrant Likely * should be empty 745ca632f55SGrant Likely */ 746ca632f55SGrant Likely } 747ca632f55SGrant Likely 748ca632f55SGrant Likely /** 749ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 750ca632f55SGrant Likely * @pl022: SSP driver private data structure 751ca632f55SGrant Likely * 752ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 753ca632f55SGrant Likely * current spi message and returns with the state of current spi 754ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 755ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 756ca632f55SGrant Likely */ 757ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 758ca632f55SGrant Likely { 759ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 760ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 761ca632f55SGrant Likely 762ca632f55SGrant Likely /* Move to next transfer */ 763ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 764ca632f55SGrant Likely pl022->cur_transfer = 765ca632f55SGrant Likely list_entry(trans->transfer_list.next, 766ca632f55SGrant Likely struct spi_transfer, transfer_list); 767ca632f55SGrant Likely return STATE_RUNNING; 768ca632f55SGrant Likely } 769ca632f55SGrant Likely return STATE_DONE; 770ca632f55SGrant Likely } 771ca632f55SGrant Likely 772ca632f55SGrant Likely /* 773ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 774ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 775ca632f55SGrant Likely */ 776ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 777ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 778ca632f55SGrant Likely { 779ca632f55SGrant Likely /* Unmap and free the SG tables */ 780ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 781ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 782ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 783ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 784ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 785ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 786ca632f55SGrant Likely } 787ca632f55SGrant Likely 788ca632f55SGrant Likely static void dma_callback(void *data) 789ca632f55SGrant Likely { 790ca632f55SGrant Likely struct pl022 *pl022 = data; 791ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 792ca632f55SGrant Likely 793ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 794ca632f55SGrant Likely 795ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 796ca632f55SGrant Likely /* 797ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 798ca632f55SGrant Likely * good if you want to convince yourself that the loopback 799ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 800ca632f55SGrant Likely * DMA engine. 801ca632f55SGrant Likely */ 802ca632f55SGrant Likely { 803ca632f55SGrant Likely struct scatterlist *sg; 804ca632f55SGrant Likely unsigned int i; 805ca632f55SGrant Likely 806ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 807ca632f55SGrant Likely pl022->sgt_rx.sgl, 808ca632f55SGrant Likely pl022->sgt_rx.nents, 809ca632f55SGrant Likely DMA_FROM_DEVICE); 810ca632f55SGrant Likely 811ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 812ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 813ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 814ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 815ca632f55SGrant Likely 16, 816ca632f55SGrant Likely 1, 817ca632f55SGrant Likely sg_virt(sg), 818ca632f55SGrant Likely sg_dma_len(sg), 819ca632f55SGrant Likely 1); 820ca632f55SGrant Likely } 821ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 822ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 823ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 824ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 825ca632f55SGrant Likely 16, 826ca632f55SGrant Likely 1, 827ca632f55SGrant Likely sg_virt(sg), 828ca632f55SGrant Likely sg_dma_len(sg), 829ca632f55SGrant Likely 1); 830ca632f55SGrant Likely } 831ca632f55SGrant Likely } 832ca632f55SGrant Likely #endif 833ca632f55SGrant Likely 834ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 835ca632f55SGrant Likely 836ca632f55SGrant Likely /* Update total bytes transferred */ 837ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 838ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 839ca632f55SGrant Likely pl022->cur_chip-> 840ca632f55SGrant Likely cs_control(SSP_CHIP_DESELECT); 841ca632f55SGrant Likely 842ca632f55SGrant Likely /* Move to next transfer */ 843ca632f55SGrant Likely msg->state = next_transfer(pl022); 844ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 845ca632f55SGrant Likely } 846ca632f55SGrant Likely 847ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 848ca632f55SGrant Likely void *buffer, 849ca632f55SGrant Likely unsigned int length, 850ca632f55SGrant Likely struct sg_table *sgtab) 851ca632f55SGrant Likely { 852ca632f55SGrant Likely struct scatterlist *sg; 853ca632f55SGrant Likely int bytesleft = length; 854ca632f55SGrant Likely void *bufp = buffer; 855ca632f55SGrant Likely int mapbytes; 856ca632f55SGrant Likely int i; 857ca632f55SGrant Likely 858ca632f55SGrant Likely if (buffer) { 859ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 860ca632f55SGrant Likely /* 861ca632f55SGrant Likely * If there are less bytes left than what fits 862ca632f55SGrant Likely * in the current page (plus page alignment offset) 863ca632f55SGrant Likely * we just feed in this, else we stuff in as much 864ca632f55SGrant Likely * as we can. 865ca632f55SGrant Likely */ 866ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 867ca632f55SGrant Likely mapbytes = bytesleft; 868ca632f55SGrant Likely else 869ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 870ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 871ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 872ca632f55SGrant Likely bufp += mapbytes; 873ca632f55SGrant Likely bytesleft -= mapbytes; 874ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 875ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 876ca632f55SGrant Likely bufp, mapbytes, bytesleft); 877ca632f55SGrant Likely } 878ca632f55SGrant Likely } else { 879ca632f55SGrant Likely /* Map the dummy buffer on every page */ 880ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 881ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 882ca632f55SGrant Likely mapbytes = bytesleft; 883ca632f55SGrant Likely else 884ca632f55SGrant Likely mapbytes = PAGE_SIZE; 885ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 886ca632f55SGrant Likely mapbytes, 0); 887ca632f55SGrant Likely bytesleft -= mapbytes; 888ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 889ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 890ca632f55SGrant Likely mapbytes, bytesleft); 891ca632f55SGrant Likely 892ca632f55SGrant Likely } 893ca632f55SGrant Likely } 894ca632f55SGrant Likely BUG_ON(bytesleft); 895ca632f55SGrant Likely } 896ca632f55SGrant Likely 897ca632f55SGrant Likely /** 898ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 899ca632f55SGrant Likely * @pl022: SSP driver's private data structure 900ca632f55SGrant Likely */ 901ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 902ca632f55SGrant Likely { 903ca632f55SGrant Likely struct dma_slave_config rx_conf = { 904ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 905ca632f55SGrant Likely .direction = DMA_FROM_DEVICE, 906ca632f55SGrant Likely }; 907ca632f55SGrant Likely struct dma_slave_config tx_conf = { 908ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 909ca632f55SGrant Likely .direction = DMA_TO_DEVICE, 910ca632f55SGrant Likely }; 911ca632f55SGrant Likely unsigned int pages; 912ca632f55SGrant Likely int ret; 913ca632f55SGrant Likely int rx_sglen, tx_sglen; 914ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 915ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 916ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 917ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 918ca632f55SGrant Likely 919ca632f55SGrant Likely /* Check that the channels are available */ 920ca632f55SGrant Likely if (!rxchan || !txchan) 921ca632f55SGrant Likely return -ENODEV; 922ca632f55SGrant Likely 923083be3f0SLinus Walleij /* 924083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 925083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 926083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 927083be3f0SLinus Walleij * calculation. 928083be3f0SLinus Walleij */ 929083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 930083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 931083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 932083be3f0SLinus Walleij break; 933083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 934083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 935083be3f0SLinus Walleij break; 936083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 937083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 938083be3f0SLinus Walleij break; 939083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 940083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 941083be3f0SLinus Walleij break; 942083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 943083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 944083be3f0SLinus Walleij break; 945083be3f0SLinus Walleij default: 946083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 947083be3f0SLinus Walleij break; 948083be3f0SLinus Walleij } 949083be3f0SLinus Walleij 950083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 951083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 952083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 953083be3f0SLinus Walleij break; 954083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 955083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 956083be3f0SLinus Walleij break; 957083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 958083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 959083be3f0SLinus Walleij break; 960083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 961083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 962083be3f0SLinus Walleij break; 963083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 964083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 965083be3f0SLinus Walleij break; 966083be3f0SLinus Walleij default: 967083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 968083be3f0SLinus Walleij break; 969083be3f0SLinus Walleij } 970083be3f0SLinus Walleij 971ca632f55SGrant Likely switch (pl022->read) { 972ca632f55SGrant Likely case READING_NULL: 973ca632f55SGrant Likely /* Use the same as for writing */ 974ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 975ca632f55SGrant Likely break; 976ca632f55SGrant Likely case READING_U8: 977ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 978ca632f55SGrant Likely break; 979ca632f55SGrant Likely case READING_U16: 980ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 981ca632f55SGrant Likely break; 982ca632f55SGrant Likely case READING_U32: 983ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 984ca632f55SGrant Likely break; 985ca632f55SGrant Likely } 986ca632f55SGrant Likely 987ca632f55SGrant Likely switch (pl022->write) { 988ca632f55SGrant Likely case WRITING_NULL: 989ca632f55SGrant Likely /* Use the same as for reading */ 990ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 991ca632f55SGrant Likely break; 992ca632f55SGrant Likely case WRITING_U8: 993ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 994ca632f55SGrant Likely break; 995ca632f55SGrant Likely case WRITING_U16: 996ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 997ca632f55SGrant Likely break; 998ca632f55SGrant Likely case WRITING_U32: 999ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1000ca632f55SGrant Likely break; 1001ca632f55SGrant Likely } 1002ca632f55SGrant Likely 1003ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 1004ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1005ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 1006ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1007ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 1008ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1009ca632f55SGrant Likely 1010ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 1011ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 1012ca632f55SGrant Likely 1013ca632f55SGrant Likely /* Create sglists for the transfers */ 1014b181565eSViresh Kumar pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1015ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1016ca632f55SGrant Likely 1017538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1018ca632f55SGrant Likely if (ret) 1019ca632f55SGrant Likely goto err_alloc_rx_sg; 1020ca632f55SGrant Likely 1021538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1022ca632f55SGrant Likely if (ret) 1023ca632f55SGrant Likely goto err_alloc_tx_sg; 1024ca632f55SGrant Likely 1025ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1026ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1027ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1028ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1029ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1030ca632f55SGrant Likely 1031ca632f55SGrant Likely /* Map DMA buffers */ 1032ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1033ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1034ca632f55SGrant Likely if (!rx_sglen) 1035ca632f55SGrant Likely goto err_rx_sgmap; 1036ca632f55SGrant Likely 1037ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1038ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1039ca632f55SGrant Likely if (!tx_sglen) 1040ca632f55SGrant Likely goto err_tx_sgmap; 1041ca632f55SGrant Likely 1042ca632f55SGrant Likely /* Send both scatterlists */ 1043ca632f55SGrant Likely rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1044ca632f55SGrant Likely pl022->sgt_rx.sgl, 1045ca632f55SGrant Likely rx_sglen, 1046ca632f55SGrant Likely DMA_FROM_DEVICE, 1047ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1048ca632f55SGrant Likely if (!rxdesc) 1049ca632f55SGrant Likely goto err_rxdesc; 1050ca632f55SGrant Likely 1051ca632f55SGrant Likely txdesc = txchan->device->device_prep_slave_sg(txchan, 1052ca632f55SGrant Likely pl022->sgt_tx.sgl, 1053ca632f55SGrant Likely tx_sglen, 1054ca632f55SGrant Likely DMA_TO_DEVICE, 1055ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1056ca632f55SGrant Likely if (!txdesc) 1057ca632f55SGrant Likely goto err_txdesc; 1058ca632f55SGrant Likely 1059ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1060ca632f55SGrant Likely rxdesc->callback = dma_callback; 1061ca632f55SGrant Likely rxdesc->callback_param = pl022; 1062ca632f55SGrant Likely 1063ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1064ca632f55SGrant Likely dmaengine_submit(rxdesc); 1065ca632f55SGrant Likely dmaengine_submit(txdesc); 1066ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1067ca632f55SGrant Likely dma_async_issue_pending(txchan); 1068ca632f55SGrant Likely 1069ca632f55SGrant Likely return 0; 1070ca632f55SGrant Likely 1071ca632f55SGrant Likely err_txdesc: 1072ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1073ca632f55SGrant Likely err_rxdesc: 1074ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1075ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1076ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1077ca632f55SGrant Likely err_tx_sgmap: 1078ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1079ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1080ca632f55SGrant Likely err_rx_sgmap: 1081ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1082ca632f55SGrant Likely err_alloc_tx_sg: 1083ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1084ca632f55SGrant Likely err_alloc_rx_sg: 1085ca632f55SGrant Likely return -ENOMEM; 1086ca632f55SGrant Likely } 1087ca632f55SGrant Likely 1088ca632f55SGrant Likely static int __init pl022_dma_probe(struct pl022 *pl022) 1089ca632f55SGrant Likely { 1090ca632f55SGrant Likely dma_cap_mask_t mask; 1091ca632f55SGrant Likely 1092ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1093ca632f55SGrant Likely dma_cap_zero(mask); 1094ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1095ca632f55SGrant Likely /* 1096ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1097ca632f55SGrant Likely * of them. 1098ca632f55SGrant Likely */ 1099ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1100ca632f55SGrant Likely pl022->master_info->dma_filter, 1101ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1102ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1103ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1104ca632f55SGrant Likely goto err_no_rxchan; 1105ca632f55SGrant Likely } 1106ca632f55SGrant Likely 1107ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1108ca632f55SGrant Likely pl022->master_info->dma_filter, 1109ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1110ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1111ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1112ca632f55SGrant Likely goto err_no_txchan; 1113ca632f55SGrant Likely } 1114ca632f55SGrant Likely 1115ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1116ca632f55SGrant Likely if (!pl022->dummypage) { 1117ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1118ca632f55SGrant Likely goto err_no_dummypage; 1119ca632f55SGrant Likely } 1120ca632f55SGrant Likely 1121ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1122ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1123ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1124ca632f55SGrant Likely 1125ca632f55SGrant Likely return 0; 1126ca632f55SGrant Likely 1127ca632f55SGrant Likely err_no_dummypage: 1128ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1129ca632f55SGrant Likely err_no_txchan: 1130ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1131ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1132ca632f55SGrant Likely err_no_rxchan: 1133ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1134ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1135ca632f55SGrant Likely return -ENODEV; 1136ca632f55SGrant Likely } 1137ca632f55SGrant Likely 1138ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1139ca632f55SGrant Likely { 1140ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1141ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1142ca632f55SGrant Likely 1143ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1144ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1145ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1146ca632f55SGrant Likely } 1147ca632f55SGrant Likely 1148ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1149ca632f55SGrant Likely { 1150ca632f55SGrant Likely if (pl022->busy) 1151ca632f55SGrant Likely terminate_dma(pl022); 1152ca632f55SGrant Likely if (pl022->dma_tx_channel) 1153ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1154ca632f55SGrant Likely if (pl022->dma_rx_channel) 1155ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1156ca632f55SGrant Likely kfree(pl022->dummypage); 1157ca632f55SGrant Likely } 1158ca632f55SGrant Likely 1159ca632f55SGrant Likely #else 1160ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1161ca632f55SGrant Likely { 1162ca632f55SGrant Likely return -ENODEV; 1163ca632f55SGrant Likely } 1164ca632f55SGrant Likely 1165ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1166ca632f55SGrant Likely { 1167ca632f55SGrant Likely return 0; 1168ca632f55SGrant Likely } 1169ca632f55SGrant Likely 1170ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1171ca632f55SGrant Likely { 1172ca632f55SGrant Likely } 1173ca632f55SGrant Likely #endif 1174ca632f55SGrant Likely 1175ca632f55SGrant Likely /** 1176ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1177ca632f55SGrant Likely * 1178ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1179ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1180ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1181ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1182ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1183ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1184ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1185ca632f55SGrant Likely */ 1186ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1187ca632f55SGrant Likely { 1188ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1189ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1190ca632f55SGrant Likely u16 irq_status = 0; 1191ca632f55SGrant Likely u16 flag = 0; 1192ca632f55SGrant Likely 1193ca632f55SGrant Likely if (unlikely(!msg)) { 1194ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1195ca632f55SGrant Likely "bad message state in interrupt handler"); 1196ca632f55SGrant Likely /* Never fail */ 1197ca632f55SGrant Likely return IRQ_HANDLED; 1198ca632f55SGrant Likely } 1199ca632f55SGrant Likely 1200ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1201ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1202ca632f55SGrant Likely 1203ca632f55SGrant Likely if (unlikely(!irq_status)) 1204ca632f55SGrant Likely return IRQ_NONE; 1205ca632f55SGrant Likely 1206ca632f55SGrant Likely /* 1207ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1208ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1209ca632f55SGrant Likely * trusted. 1210ca632f55SGrant Likely */ 1211ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1212ca632f55SGrant Likely /* 1213ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1214ca632f55SGrant Likely * corrupted 1215ca632f55SGrant Likely */ 1216ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1217ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1218ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1219ca632f55SGrant Likely "RXFIFO is full\n"); 1220ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1221ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1222ca632f55SGrant Likely "TXFIFO is full\n"); 1223ca632f55SGrant Likely 1224ca632f55SGrant Likely /* 1225ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1226ca632f55SGrant Likely * mark message with bad status so it can be 1227ca632f55SGrant Likely * retried. 1228ca632f55SGrant Likely */ 1229ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1230ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1231ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1232ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1233ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1234ca632f55SGrant Likely msg->state = STATE_ERROR; 1235ca632f55SGrant Likely 1236ca632f55SGrant Likely /* Schedule message queue handler */ 1237ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1238ca632f55SGrant Likely return IRQ_HANDLED; 1239ca632f55SGrant Likely } 1240ca632f55SGrant Likely 1241ca632f55SGrant Likely readwriter(pl022); 1242ca632f55SGrant Likely 1243ca632f55SGrant Likely if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1244ca632f55SGrant Likely flag = 1; 1245172289dfSChris Blair /* Disable Transmit interrupt, enable receive interrupt */ 1246172289dfSChris Blair writew((readw(SSP_IMSC(pl022->virtbase)) & 1247172289dfSChris Blair ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1248ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1249ca632f55SGrant Likely } 1250ca632f55SGrant Likely 1251ca632f55SGrant Likely /* 1252ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1253ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1254ca632f55SGrant Likely * At this point, all TX will always be finished. 1255ca632f55SGrant Likely */ 1256ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1257ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1258ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1259ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1260ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1261ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1262ca632f55SGrant Likely "bytes (did you request an odd " 1263ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1264ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1265ca632f55SGrant Likely } 1266ca632f55SGrant Likely /* Update total bytes transferred */ 1267ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1268ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1269ca632f55SGrant Likely pl022->cur_chip-> 1270ca632f55SGrant Likely cs_control(SSP_CHIP_DESELECT); 1271ca632f55SGrant Likely /* Move to next transfer */ 1272ca632f55SGrant Likely msg->state = next_transfer(pl022); 1273ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1274ca632f55SGrant Likely return IRQ_HANDLED; 1275ca632f55SGrant Likely } 1276ca632f55SGrant Likely 1277ca632f55SGrant Likely return IRQ_HANDLED; 1278ca632f55SGrant Likely } 1279ca632f55SGrant Likely 1280ca632f55SGrant Likely /** 1281ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1282ca632f55SGrant Likely * send out on the SPI bus. 1283ca632f55SGrant Likely */ 1284ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1285ca632f55SGrant Likely struct spi_transfer *transfer) 1286ca632f55SGrant Likely { 1287ca632f55SGrant Likely int residue; 1288ca632f55SGrant Likely 1289ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1290ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1291ca632f55SGrant Likely if (unlikely(residue != 0)) { 1292ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1293ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1294ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1295ca632f55SGrant Likely pl022->cur_transfer->len, 1296ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1297ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1298ca632f55SGrant Likely return -EIO; 1299ca632f55SGrant Likely } 1300ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1301ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1302ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1303ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1304ca632f55SGrant Likely pl022->write = 1305ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1306ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1307ca632f55SGrant Likely return 0; 1308ca632f55SGrant Likely } 1309ca632f55SGrant Likely 1310ca632f55SGrant Likely /** 1311ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1312ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1313ca632f55SGrant Likely * @data: SSP driver private data structure 1314ca632f55SGrant Likely * 1315ca632f55SGrant Likely */ 1316ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1317ca632f55SGrant Likely { 1318ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1319ca632f55SGrant Likely struct spi_message *message = NULL; 1320ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1321ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1322ca632f55SGrant Likely 1323ca632f55SGrant Likely /* Get current state information */ 1324ca632f55SGrant Likely message = pl022->cur_msg; 1325ca632f55SGrant Likely transfer = pl022->cur_transfer; 1326ca632f55SGrant Likely 1327ca632f55SGrant Likely /* Handle for abort */ 1328ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1329ca632f55SGrant Likely message->status = -EIO; 1330ca632f55SGrant Likely giveback(pl022); 1331ca632f55SGrant Likely return; 1332ca632f55SGrant Likely } 1333ca632f55SGrant Likely 1334ca632f55SGrant Likely /* Handle end of message */ 1335ca632f55SGrant Likely if (message->state == STATE_DONE) { 1336ca632f55SGrant Likely message->status = 0; 1337ca632f55SGrant Likely giveback(pl022); 1338ca632f55SGrant Likely return; 1339ca632f55SGrant Likely } 1340ca632f55SGrant Likely 1341ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1342ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1343ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1344ca632f55SGrant Likely struct spi_transfer, 1345ca632f55SGrant Likely transfer_list); 1346ca632f55SGrant Likely if (previous->delay_usecs) 1347ca632f55SGrant Likely /* 1348ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1349ca632f55SGrant Likely * Is this really smart? 1350ca632f55SGrant Likely */ 1351ca632f55SGrant Likely udelay(previous->delay_usecs); 1352ca632f55SGrant Likely 1353ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 1354ca632f55SGrant Likely if (previous->cs_change) 1355ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1356ca632f55SGrant Likely } else { 1357ca632f55SGrant Likely /* STATE_START */ 1358ca632f55SGrant Likely message->state = STATE_RUNNING; 1359ca632f55SGrant Likely } 1360ca632f55SGrant Likely 1361ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1362ca632f55SGrant Likely message->state = STATE_ERROR; 1363ca632f55SGrant Likely message->status = -EIO; 1364ca632f55SGrant Likely giveback(pl022); 1365ca632f55SGrant Likely return; 1366ca632f55SGrant Likely } 1367ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1368ca632f55SGrant Likely flush(pl022); 1369ca632f55SGrant Likely 1370ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1371ca632f55SGrant Likely if (configure_dma(pl022)) { 1372ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1373ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1374ca632f55SGrant Likely goto err_config_dma; 1375ca632f55SGrant Likely } 1376ca632f55SGrant Likely return; 1377ca632f55SGrant Likely } 1378ca632f55SGrant Likely 1379ca632f55SGrant Likely err_config_dma: 1380172289dfSChris Blair /* enable all interrupts except RX */ 1381172289dfSChris Blair writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1382ca632f55SGrant Likely } 1383ca632f55SGrant Likely 1384ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1385ca632f55SGrant Likely { 1386172289dfSChris Blair /* 1387172289dfSChris Blair * Default is to enable all interrupts except RX - 1388172289dfSChris Blair * this will be enabled once TX is complete 1389172289dfSChris Blair */ 1390172289dfSChris Blair u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1391ca632f55SGrant Likely 1392ca632f55SGrant Likely /* Enable target chip */ 1393ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1394ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1395ca632f55SGrant Likely /* Error path */ 1396ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1397ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1398ca632f55SGrant Likely giveback(pl022); 1399ca632f55SGrant Likely return; 1400ca632f55SGrant Likely } 1401ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1402ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1403ca632f55SGrant Likely /* Configure DMA transfer */ 1404ca632f55SGrant Likely if (configure_dma(pl022)) { 1405ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1406ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1407ca632f55SGrant Likely goto err_config_dma; 1408ca632f55SGrant Likely } 1409ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1410ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1411ca632f55SGrant Likely } 1412ca632f55SGrant Likely err_config_dma: 1413ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1414ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1415ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1416ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1417ca632f55SGrant Likely } 1418ca632f55SGrant Likely 1419ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1420ca632f55SGrant Likely { 1421ca632f55SGrant Likely struct spi_message *message = NULL; 1422ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1423ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1424ca632f55SGrant Likely struct chip_data *chip; 1425ca632f55SGrant Likely unsigned long time, timeout; 1426ca632f55SGrant Likely 1427ca632f55SGrant Likely chip = pl022->cur_chip; 1428ca632f55SGrant Likely message = pl022->cur_msg; 1429ca632f55SGrant Likely 1430ca632f55SGrant Likely while (message->state != STATE_DONE) { 1431ca632f55SGrant Likely /* Handle for abort */ 1432ca632f55SGrant Likely if (message->state == STATE_ERROR) 1433ca632f55SGrant Likely break; 1434ca632f55SGrant Likely transfer = pl022->cur_transfer; 1435ca632f55SGrant Likely 1436ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1437ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1438ca632f55SGrant Likely previous = 1439ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1440ca632f55SGrant Likely struct spi_transfer, transfer_list); 1441ca632f55SGrant Likely if (previous->delay_usecs) 1442ca632f55SGrant Likely udelay(previous->delay_usecs); 1443ca632f55SGrant Likely if (previous->cs_change) 1444ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1445ca632f55SGrant Likely } else { 1446ca632f55SGrant Likely /* STATE_START */ 1447ca632f55SGrant Likely message->state = STATE_RUNNING; 1448ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1449ca632f55SGrant Likely } 1450ca632f55SGrant Likely 1451ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1452ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1453ca632f55SGrant Likely /* Error path */ 1454ca632f55SGrant Likely message->state = STATE_ERROR; 1455ca632f55SGrant Likely break; 1456ca632f55SGrant Likely } 1457ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1458ca632f55SGrant Likely flush(pl022); 1459ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1460ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1461ca632f55SGrant Likely 1462ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1463ca632f55SGrant Likely 1464ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1465ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1466ca632f55SGrant Likely time = jiffies; 1467ca632f55SGrant Likely readwriter(pl022); 1468ca632f55SGrant Likely if (time_after(time, timeout)) { 1469ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1470ca632f55SGrant Likely "%s: timeout!\n", __func__); 1471ca632f55SGrant Likely message->state = STATE_ERROR; 1472ca632f55SGrant Likely goto out; 1473ca632f55SGrant Likely } 1474ca632f55SGrant Likely cpu_relax(); 1475ca632f55SGrant Likely } 1476ca632f55SGrant Likely 1477ca632f55SGrant Likely /* Update total byte transferred */ 1478ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1479ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1480ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1481ca632f55SGrant Likely /* Move to next transfer */ 1482ca632f55SGrant Likely message->state = next_transfer(pl022); 1483ca632f55SGrant Likely } 1484ca632f55SGrant Likely out: 1485ca632f55SGrant Likely /* Handle end of message */ 1486ca632f55SGrant Likely if (message->state == STATE_DONE) 1487ca632f55SGrant Likely message->status = 0; 1488ca632f55SGrant Likely else 1489ca632f55SGrant Likely message->status = -EIO; 1490ca632f55SGrant Likely 1491ca632f55SGrant Likely giveback(pl022); 1492ca632f55SGrant Likely return; 1493ca632f55SGrant Likely } 1494ca632f55SGrant Likely 1495ca632f55SGrant Likely /** 1496ca632f55SGrant Likely * pump_messages - Workqueue function which processes spi message queue 1497ca632f55SGrant Likely * @data: pointer to private data of SSP driver 1498ca632f55SGrant Likely * 1499ca632f55SGrant Likely * This function checks if there is any spi message in the queue that 1500ca632f55SGrant Likely * needs processing and delegate control to appropriate function 1501ca632f55SGrant Likely * do_polling_transfer()/do_interrupt_dma_transfer() 1502ca632f55SGrant Likely * based on the kind of the transfer 1503ca632f55SGrant Likely * 1504ca632f55SGrant Likely */ 1505ca632f55SGrant Likely static void pump_messages(struct work_struct *work) 1506ca632f55SGrant Likely { 1507ca632f55SGrant Likely struct pl022 *pl022 = 1508ca632f55SGrant Likely container_of(work, struct pl022, pump_messages); 1509ca632f55SGrant Likely unsigned long flags; 1510*d4b6af2eSChris Blair bool was_busy = false; 1511ca632f55SGrant Likely 1512ca632f55SGrant Likely /* Lock queue and check for queue work */ 1513ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1514ca632f55SGrant Likely if (list_empty(&pl022->queue) || !pl022->running) { 1515*d4b6af2eSChris Blair if (pl022->busy) 1516*d4b6af2eSChris Blair pm_runtime_put(&pl022->adev->dev); 1517ca632f55SGrant Likely pl022->busy = false; 1518ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1519ca632f55SGrant Likely return; 1520ca632f55SGrant Likely } 1521*d4b6af2eSChris Blair 1522ca632f55SGrant Likely /* Make sure we are not already running a message */ 1523ca632f55SGrant Likely if (pl022->cur_msg) { 1524ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1525ca632f55SGrant Likely return; 1526ca632f55SGrant Likely } 1527ca632f55SGrant Likely /* Extract head of queue */ 1528ca632f55SGrant Likely pl022->cur_msg = 1529ca632f55SGrant Likely list_entry(pl022->queue.next, struct spi_message, queue); 1530ca632f55SGrant Likely 1531ca632f55SGrant Likely list_del_init(&pl022->cur_msg->queue); 1532*d4b6af2eSChris Blair if (pl022->busy) 1533*d4b6af2eSChris Blair was_busy = true; 1534*d4b6af2eSChris Blair else 1535ca632f55SGrant Likely pl022->busy = true; 1536ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1537ca632f55SGrant Likely 1538ca632f55SGrant Likely /* Initial message state */ 1539ca632f55SGrant Likely pl022->cur_msg->state = STATE_START; 1540ca632f55SGrant Likely pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, 1541f1e45f86SViresh Kumar struct spi_transfer, transfer_list); 1542ca632f55SGrant Likely 1543ca632f55SGrant Likely /* Setup the SPI using the per chip configuration */ 1544ca632f55SGrant Likely pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); 1545*d4b6af2eSChris Blair if (!was_busy) 1546ca632f55SGrant Likely /* 1547ca632f55SGrant Likely * We enable the core voltage and clocks here, then the clocks 1548*d4b6af2eSChris Blair * and core will be disabled when this workqueue is run again 1549*d4b6af2eSChris Blair * and there is no more work to be done. 1550ca632f55SGrant Likely */ 1551bcda6ff8SRabin Vincent pm_runtime_get_sync(&pl022->adev->dev); 1552*d4b6af2eSChris Blair 1553ca632f55SGrant Likely restore_state(pl022); 1554ca632f55SGrant Likely flush(pl022); 1555ca632f55SGrant Likely 1556ca632f55SGrant Likely if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1557ca632f55SGrant Likely do_polling_transfer(pl022); 1558ca632f55SGrant Likely else 1559ca632f55SGrant Likely do_interrupt_dma_transfer(pl022); 1560ca632f55SGrant Likely } 1561ca632f55SGrant Likely 1562ca632f55SGrant Likely static int __init init_queue(struct pl022 *pl022) 1563ca632f55SGrant Likely { 1564ca632f55SGrant Likely INIT_LIST_HEAD(&pl022->queue); 1565ca632f55SGrant Likely spin_lock_init(&pl022->queue_lock); 1566ca632f55SGrant Likely 1567ca632f55SGrant Likely pl022->running = false; 1568ca632f55SGrant Likely pl022->busy = false; 1569ca632f55SGrant Likely 1570f1e45f86SViresh Kumar tasklet_init(&pl022->pump_transfers, pump_transfers, 1571f1e45f86SViresh Kumar (unsigned long)pl022); 1572ca632f55SGrant Likely 1573ca632f55SGrant Likely INIT_WORK(&pl022->pump_messages, pump_messages); 1574ca632f55SGrant Likely pl022->workqueue = create_singlethread_workqueue( 1575ca632f55SGrant Likely dev_name(pl022->master->dev.parent)); 1576ca632f55SGrant Likely if (pl022->workqueue == NULL) 1577ca632f55SGrant Likely return -EBUSY; 1578ca632f55SGrant Likely 1579ca632f55SGrant Likely return 0; 1580ca632f55SGrant Likely } 1581ca632f55SGrant Likely 1582ca632f55SGrant Likely static int start_queue(struct pl022 *pl022) 1583ca632f55SGrant Likely { 1584ca632f55SGrant Likely unsigned long flags; 1585ca632f55SGrant Likely 1586ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1587ca632f55SGrant Likely 1588ca632f55SGrant Likely if (pl022->running || pl022->busy) { 1589ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1590ca632f55SGrant Likely return -EBUSY; 1591ca632f55SGrant Likely } 1592ca632f55SGrant Likely 1593ca632f55SGrant Likely pl022->running = true; 1594ca632f55SGrant Likely pl022->cur_msg = NULL; 1595ca632f55SGrant Likely pl022->cur_transfer = NULL; 1596ca632f55SGrant Likely pl022->cur_chip = NULL; 1597ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1598ca632f55SGrant Likely 1599ca632f55SGrant Likely queue_work(pl022->workqueue, &pl022->pump_messages); 1600ca632f55SGrant Likely 1601ca632f55SGrant Likely return 0; 1602ca632f55SGrant Likely } 1603ca632f55SGrant Likely 1604ca632f55SGrant Likely static int stop_queue(struct pl022 *pl022) 1605ca632f55SGrant Likely { 1606ca632f55SGrant Likely unsigned long flags; 1607ca632f55SGrant Likely unsigned limit = 500; 1608ca632f55SGrant Likely int status = 0; 1609ca632f55SGrant Likely 1610ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1611ca632f55SGrant Likely 1612ca632f55SGrant Likely /* This is a bit lame, but is optimized for the common execution path. 1613ca632f55SGrant Likely * A wait_queue on the pl022->busy could be used, but then the common 1614ca632f55SGrant Likely * execution path (pump_messages) would be required to call wake_up or 1615ca632f55SGrant Likely * friends on every SPI message. Do this instead */ 1616ca632f55SGrant Likely while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { 1617ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1618ca632f55SGrant Likely msleep(10); 1619ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1620ca632f55SGrant Likely } 1621ca632f55SGrant Likely 1622ca632f55SGrant Likely if (!list_empty(&pl022->queue) || pl022->busy) 1623ca632f55SGrant Likely status = -EBUSY; 1624ca632f55SGrant Likely else 1625ca632f55SGrant Likely pl022->running = false; 1626ca632f55SGrant Likely 1627ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1628ca632f55SGrant Likely 1629ca632f55SGrant Likely return status; 1630ca632f55SGrant Likely } 1631ca632f55SGrant Likely 1632ca632f55SGrant Likely static int destroy_queue(struct pl022 *pl022) 1633ca632f55SGrant Likely { 1634ca632f55SGrant Likely int status; 1635ca632f55SGrant Likely 1636ca632f55SGrant Likely status = stop_queue(pl022); 1637ca632f55SGrant Likely /* we are unloading the module or failing to load (only two calls 1638ca632f55SGrant Likely * to this routine), and neither call can handle a return value. 1639ca632f55SGrant Likely * However, destroy_workqueue calls flush_workqueue, and that will 1640ca632f55SGrant Likely * block until all work is done. If the reason that stop_queue 1641ca632f55SGrant Likely * timed out is that the work will never finish, then it does no 1642ca632f55SGrant Likely * good to call destroy_workqueue, so return anyway. */ 1643ca632f55SGrant Likely if (status != 0) 1644ca632f55SGrant Likely return status; 1645ca632f55SGrant Likely 1646ca632f55SGrant Likely destroy_workqueue(pl022->workqueue); 1647ca632f55SGrant Likely 1648ca632f55SGrant Likely return 0; 1649ca632f55SGrant Likely } 1650ca632f55SGrant Likely 1651ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1652ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1653ca632f55SGrant Likely { 1654ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1655ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1656ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1657ca632f55SGrant Likely "interface is configured incorrectly\n"); 1658ca632f55SGrant Likely return -EINVAL; 1659ca632f55SGrant Likely } 1660ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1661ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1662ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1663ca632f55SGrant Likely "unidirectional mode not supported in this " 1664ca632f55SGrant Likely "hardware version\n"); 1665ca632f55SGrant Likely return -EINVAL; 1666ca632f55SGrant Likely } 1667ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1668ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1669ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1670ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1671ca632f55SGrant Likely return -EINVAL; 1672ca632f55SGrant Likely } 1673ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1674ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1675ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1676ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1677ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1678ca632f55SGrant Likely return -EINVAL; 1679ca632f55SGrant Likely } 168078b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 168178b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 168278b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 168378b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 168478b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 168578b2b911SLinus Walleij break; 168678b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 168778b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1688ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1689ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1690ca632f55SGrant Likely return -EINVAL; 1691ca632f55SGrant Likely } 169278b2b911SLinus Walleij break; 169378b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 169478b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 169578b2b911SLinus Walleij dev_err(&pl022->adev->dev, 169678b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 169778b2b911SLinus Walleij return -EINVAL; 169878b2b911SLinus Walleij } 169978b2b911SLinus Walleij break; 170078b2b911SLinus Walleij default: 170178b2b911SLinus Walleij dev_err(&pl022->adev->dev, 170278b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 170378b2b911SLinus Walleij return -EINVAL; 170478b2b911SLinus Walleij break; 170578b2b911SLinus Walleij } 170678b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 170778b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 170878b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 170978b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 171078b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 171178b2b911SLinus Walleij break; 171278b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 171378b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1714ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1715ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1716ca632f55SGrant Likely return -EINVAL; 1717ca632f55SGrant Likely } 171878b2b911SLinus Walleij break; 171978b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 172078b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 172178b2b911SLinus Walleij dev_err(&pl022->adev->dev, 172278b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 172378b2b911SLinus Walleij return -EINVAL; 172478b2b911SLinus Walleij } 172578b2b911SLinus Walleij break; 172678b2b911SLinus Walleij default: 172778b2b911SLinus Walleij dev_err(&pl022->adev->dev, 172878b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 172978b2b911SLinus Walleij return -EINVAL; 173078b2b911SLinus Walleij break; 173178b2b911SLinus Walleij } 1732ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1733ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1734ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1735ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1736ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1737ca632f55SGrant Likely return -EINVAL; 1738ca632f55SGrant Likely } 1739ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1740ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1741ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1742ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1743ca632f55SGrant Likely return -EINVAL; 1744ca632f55SGrant Likely } 1745ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1746ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1747ca632f55SGrant Likely if ((chip_info->duplex != 1748ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1749ca632f55SGrant Likely && (chip_info->duplex != 1750ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1751ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1752ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1753ca632f55SGrant Likely return -EINVAL; 1754ca632f55SGrant Likely } 1755ca632f55SGrant Likely } else { 1756ca632f55SGrant Likely if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1757ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1758ca632f55SGrant Likely "Microwire half duplex mode requested," 1759ca632f55SGrant Likely " but this is only available in the" 1760ca632f55SGrant Likely " ST version of PL022\n"); 1761ca632f55SGrant Likely return -EINVAL; 1762ca632f55SGrant Likely } 1763ca632f55SGrant Likely } 1764ca632f55SGrant Likely return 0; 1765ca632f55SGrant Likely } 1766ca632f55SGrant Likely 1767ca632f55SGrant Likely /** 1768ca632f55SGrant Likely * pl022_transfer - transfer function registered to SPI master framework 1769ca632f55SGrant Likely * @spi: spi device which is requesting transfer 1770ca632f55SGrant Likely * @msg: spi message which is to handled is queued to driver queue 1771ca632f55SGrant Likely * 1772ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1773ca632f55SGrant Likely * controller. It will queue the spi_message in the queue of driver if 1774ca632f55SGrant Likely * the queue is not stopped and return. 1775ca632f55SGrant Likely */ 1776ca632f55SGrant Likely static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) 1777ca632f55SGrant Likely { 1778ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1779ca632f55SGrant Likely unsigned long flags; 1780ca632f55SGrant Likely 1781ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1782ca632f55SGrant Likely 1783ca632f55SGrant Likely if (!pl022->running) { 1784ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1785ca632f55SGrant Likely return -ESHUTDOWN; 1786ca632f55SGrant Likely } 1787ca632f55SGrant Likely msg->actual_length = 0; 1788ca632f55SGrant Likely msg->status = -EINPROGRESS; 1789ca632f55SGrant Likely msg->state = STATE_START; 1790ca632f55SGrant Likely 1791ca632f55SGrant Likely list_add_tail(&msg->queue, &pl022->queue); 1792ca632f55SGrant Likely if (pl022->running && !pl022->busy) 1793ca632f55SGrant Likely queue_work(pl022->workqueue, &pl022->pump_messages); 1794ca632f55SGrant Likely 1795ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1796ca632f55SGrant Likely return 0; 1797ca632f55SGrant Likely } 1798ca632f55SGrant Likely 17990379b2a3SViresh Kumar static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 18000379b2a3SViresh Kumar { 18010379b2a3SViresh Kumar return rate / (cpsdvsr * (1 + scr)); 18020379b2a3SViresh Kumar } 18030379b2a3SViresh Kumar 18040379b2a3SViresh Kumar static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 18050379b2a3SViresh Kumar ssp_clock_params * clk_freq) 1806ca632f55SGrant Likely { 1807ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 18080379b2a3SViresh Kumar u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 18090379b2a3SViresh Kumar u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 18100379b2a3SViresh Kumar best_scr = 0, tmp, found = 0; 1811ca632f55SGrant Likely 1812ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1813ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 18140379b2a3SViresh Kumar max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1815ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 18160379b2a3SViresh Kumar min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1817ca632f55SGrant Likely 18180379b2a3SViresh Kumar if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1819ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1820ca632f55SGrant Likely "controller data is incorrect: out of range frequency"); 1821ca632f55SGrant Likely return -EINVAL; 1822ca632f55SGrant Likely } 18230379b2a3SViresh Kumar 18240379b2a3SViresh Kumar /* 18250379b2a3SViresh Kumar * best_freq will give closest possible available rate (<= requested 18260379b2a3SViresh Kumar * freq) for all values of scr & cpsdvsr. 18270379b2a3SViresh Kumar */ 18280379b2a3SViresh Kumar while ((cpsdvsr <= CPSDVR_MAX) && !found) { 18290379b2a3SViresh Kumar while (scr <= SCR_MAX) { 18300379b2a3SViresh Kumar tmp = spi_rate(rate, cpsdvsr, scr); 18310379b2a3SViresh Kumar 18320379b2a3SViresh Kumar if (tmp > freq) 18330379b2a3SViresh Kumar scr++; 18340379b2a3SViresh Kumar /* 18350379b2a3SViresh Kumar * If found exact value, update and break. 18360379b2a3SViresh Kumar * If found more closer value, update and continue. 18370379b2a3SViresh Kumar */ 18380379b2a3SViresh Kumar else if ((tmp == freq) || (tmp > best_freq)) { 18390379b2a3SViresh Kumar best_freq = tmp; 18400379b2a3SViresh Kumar best_cpsdvsr = cpsdvsr; 18410379b2a3SViresh Kumar best_scr = scr; 18420379b2a3SViresh Kumar 18430379b2a3SViresh Kumar if (tmp == freq) 18440379b2a3SViresh Kumar break; 18450379b2a3SViresh Kumar } 18460379b2a3SViresh Kumar scr++; 18470379b2a3SViresh Kumar } 18480379b2a3SViresh Kumar cpsdvsr += 2; 18490379b2a3SViresh Kumar scr = SCR_MIN; 1850ca632f55SGrant Likely } 1851ca632f55SGrant Likely 18520379b2a3SViresh Kumar clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 18530379b2a3SViresh Kumar clk_freq->scr = (u8) (best_scr & 0xFF); 18540379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, 18550379b2a3SViresh Kumar "SSP Target Frequency is: %u, Effective Frequency is %u\n", 18560379b2a3SViresh Kumar freq, best_freq); 18570379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 18580379b2a3SViresh Kumar clk_freq->cpsdvsr, clk_freq->scr); 18590379b2a3SViresh Kumar 1860ca632f55SGrant Likely return 0; 1861ca632f55SGrant Likely } 1862ca632f55SGrant Likely 1863ca632f55SGrant Likely /* 1864ca632f55SGrant Likely * A piece of default chip info unless the platform 1865ca632f55SGrant Likely * supplies it. 1866ca632f55SGrant Likely */ 1867ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1868ca632f55SGrant Likely .com_mode = POLLING_TRANSFER, 1869ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1870ca632f55SGrant Likely .hierarchy = SSP_SLAVE, 1871ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1872ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1873ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1874ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1875ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1876ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1877ca632f55SGrant Likely .cs_control = null_cs_control, 1878ca632f55SGrant Likely }; 1879ca632f55SGrant Likely 1880ca632f55SGrant Likely /** 1881ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1882ca632f55SGrant Likely * @spi: spi device which is requesting setup 1883ca632f55SGrant Likely * 1884ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1885ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1886ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1887ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1888ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1889ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1890ca632f55SGrant Likely * commence. 1891ca632f55SGrant Likely */ 1892ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1893ca632f55SGrant Likely { 1894ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 1895ca632f55SGrant Likely struct chip_data *chip; 1896c4a47843SJonas Aaberg struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1897ca632f55SGrant Likely int status = 0; 1898ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1899ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1900ca632f55SGrant Likely u32 tmp; 1901ca632f55SGrant Likely 1902ca632f55SGrant Likely if (!spi->max_speed_hz) 1903ca632f55SGrant Likely return -EINVAL; 1904ca632f55SGrant Likely 1905ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1906ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1907ca632f55SGrant Likely 1908ca632f55SGrant Likely if (chip == NULL) { 1909ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1910ca632f55SGrant Likely if (!chip) { 1911ca632f55SGrant Likely dev_err(&spi->dev, 1912ca632f55SGrant Likely "cannot allocate controller state\n"); 1913ca632f55SGrant Likely return -ENOMEM; 1914ca632f55SGrant Likely } 1915ca632f55SGrant Likely dev_dbg(&spi->dev, 1916ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1917ca632f55SGrant Likely } 1918ca632f55SGrant Likely 1919ca632f55SGrant Likely /* Get controller data if one is supplied */ 1920ca632f55SGrant Likely chip_info = spi->controller_data; 1921ca632f55SGrant Likely 1922ca632f55SGrant Likely if (chip_info == NULL) { 1923ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1924ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1925ca632f55SGrant Likely dev_dbg(&spi->dev, 1926ca632f55SGrant Likely "using default controller_data settings\n"); 1927ca632f55SGrant Likely } else 1928ca632f55SGrant Likely dev_dbg(&spi->dev, 1929ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1930ca632f55SGrant Likely 1931ca632f55SGrant Likely /* 1932ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1933ca632f55SGrant Likely * frequency setting 1934ca632f55SGrant Likely */ 1935ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1936ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1937ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1938ca632f55SGrant Likely spi->max_speed_hz, 1939ca632f55SGrant Likely &clk_freq); 1940ca632f55SGrant Likely if (status < 0) 1941ca632f55SGrant Likely goto err_config_params; 1942ca632f55SGrant Likely } else { 1943ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1944ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1945ca632f55SGrant Likely clk_freq.cpsdvsr = 1946ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1947ca632f55SGrant Likely } 1948ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1949ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1950f8db4cc4SGrant Likely status = -EINVAL; 1951ca632f55SGrant Likely dev_err(&spi->dev, 1952ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1953ca632f55SGrant Likely goto err_config_params; 1954ca632f55SGrant Likely } 1955ca632f55SGrant Likely 1956ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1957ca632f55SGrant Likely if (status) { 1958ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1959ca632f55SGrant Likely goto err_config_params; 1960ca632f55SGrant Likely } 1961ca632f55SGrant Likely 1962083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1963083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1964083be3f0SLinus Walleij 1965ca632f55SGrant Likely /* Now set controller state based on controller data */ 1966ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1967ca632f55SGrant Likely if (!chip_info->cs_control) { 1968ca632f55SGrant Likely chip->cs_control = null_cs_control; 1969ca632f55SGrant Likely dev_warn(&spi->dev, 1970ca632f55SGrant Likely "chip select function is NULL for this chip\n"); 1971ca632f55SGrant Likely } else 1972ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1973ca632f55SGrant Likely 1974ca632f55SGrant Likely if (bits <= 3) { 1975ca632f55SGrant Likely /* PL022 doesn't support less than 4-bits */ 1976ca632f55SGrant Likely status = -ENOTSUPP; 1977ca632f55SGrant Likely goto err_config_params; 1978ca632f55SGrant Likely } else if (bits <= 8) { 1979ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1980ca632f55SGrant Likely chip->n_bytes = 1; 1981ca632f55SGrant Likely chip->read = READING_U8; 1982ca632f55SGrant Likely chip->write = WRITING_U8; 1983ca632f55SGrant Likely } else if (bits <= 16) { 1984ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1985ca632f55SGrant Likely chip->n_bytes = 2; 1986ca632f55SGrant Likely chip->read = READING_U16; 1987ca632f55SGrant Likely chip->write = WRITING_U16; 1988ca632f55SGrant Likely } else { 1989ca632f55SGrant Likely if (pl022->vendor->max_bpw >= 32) { 1990ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1991ca632f55SGrant Likely chip->n_bytes = 4; 1992ca632f55SGrant Likely chip->read = READING_U32; 1993ca632f55SGrant Likely chip->write = WRITING_U32; 1994ca632f55SGrant Likely } else { 1995ca632f55SGrant Likely dev_err(&spi->dev, 1996ca632f55SGrant Likely "illegal data size for this controller!\n"); 1997ca632f55SGrant Likely dev_err(&spi->dev, 1998ca632f55SGrant Likely "a standard pl022 can only handle " 1999ca632f55SGrant Likely "1 <= n <= 16 bit words\n"); 2000ca632f55SGrant Likely status = -ENOTSUPP; 2001ca632f55SGrant Likely goto err_config_params; 2002ca632f55SGrant Likely } 2003ca632f55SGrant Likely } 2004ca632f55SGrant Likely 2005ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 2006ca632f55SGrant Likely chip->cr0 = 0; 2007ca632f55SGrant Likely chip->cr1 = 0; 2008ca632f55SGrant Likely chip->dmacr = 0; 2009ca632f55SGrant Likely chip->cpsr = 0; 2010ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 2011ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 2012ca632f55SGrant Likely chip->enable_dma = true; 2013ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 2014ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2015ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 2016ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2017ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 2018ca632f55SGrant Likely } else { 2019ca632f55SGrant Likely chip->enable_dma = false; 2020ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 2021ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2022ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 2023ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2024ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 2025ca632f55SGrant Likely } 2026ca632f55SGrant Likely 2027ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 2028ca632f55SGrant Likely 2029ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 2030ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 2031ca632f55SGrant Likely u32 etx; 2032ca632f55SGrant Likely 2033ca632f55SGrant Likely if (pl022->vendor->pl023) { 2034ca632f55SGrant Likely /* These bits are only in the PL023 */ 2035ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2036ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 2037ca632f55SGrant Likely } else { 2038ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 2039ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2040ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 2041ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2042ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 2043ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2044ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 2045ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2046ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 2047ca632f55SGrant Likely } 2048ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2049ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 2050ca632f55SGrant Likely 2051ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 2052ca632f55SGrant Likely tmp = SSP_RX_LSB; 2053ca632f55SGrant Likely etx = SSP_TX_LSB; 2054ca632f55SGrant Likely } else { 2055ca632f55SGrant Likely tmp = SSP_RX_MSB; 2056ca632f55SGrant Likely etx = SSP_TX_MSB; 2057ca632f55SGrant Likely } 2058ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2059ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2060ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2061ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 2062ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2063ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 2064ca632f55SGrant Likely } else { 2065ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2066ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 2067ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2068ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 2069ca632f55SGrant Likely } 2070ca632f55SGrant Likely 2071ca632f55SGrant Likely /* Stuff that is common for all versions */ 2072ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 2073ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 2074ca632f55SGrant Likely else 2075ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 2076ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2077ca632f55SGrant Likely 2078ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 2079ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 2080ca632f55SGrant Likely else 2081ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 2082ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2083ca632f55SGrant Likely 2084ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2085ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 2086ca632f55SGrant Likely if (pl022->vendor->loopback) { 2087ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 2088ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 2089ca632f55SGrant Likely else 2090ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 2091ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2092ca632f55SGrant Likely } 2093ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2094ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2095f1e45f86SViresh Kumar SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2096f1e45f86SViresh Kumar 3); 2097ca632f55SGrant Likely 2098ca632f55SGrant Likely /* Save controller_state */ 2099ca632f55SGrant Likely spi_set_ctldata(spi, chip); 2100ca632f55SGrant Likely return status; 2101ca632f55SGrant Likely err_config_params: 2102ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2103ca632f55SGrant Likely kfree(chip); 2104ca632f55SGrant Likely return status; 2105ca632f55SGrant Likely } 2106ca632f55SGrant Likely 2107ca632f55SGrant Likely /** 2108ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 2109ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 2110ca632f55SGrant Likely * 2111ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 2112ca632f55SGrant Likely * controller. It will free the runtime state of chip. 2113ca632f55SGrant Likely */ 2114ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 2115ca632f55SGrant Likely { 2116ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 2117ca632f55SGrant Likely 2118ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2119ca632f55SGrant Likely kfree(chip); 2120ca632f55SGrant Likely } 2121ca632f55SGrant Likely 2122ca632f55SGrant Likely static int __devinit 2123ca632f55SGrant Likely pl022_probe(struct amba_device *adev, const struct amba_id *id) 2124ca632f55SGrant Likely { 2125ca632f55SGrant Likely struct device *dev = &adev->dev; 2126ca632f55SGrant Likely struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2127ca632f55SGrant Likely struct spi_master *master; 2128ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 2129ca632f55SGrant Likely int status = 0; 2130ca632f55SGrant Likely 2131ca632f55SGrant Likely dev_info(&adev->dev, 2132ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2133ca632f55SGrant Likely if (platform_info == NULL) { 2134ca632f55SGrant Likely dev_err(&adev->dev, "probe - no platform data supplied\n"); 2135ca632f55SGrant Likely status = -ENODEV; 2136ca632f55SGrant Likely goto err_no_pdata; 2137ca632f55SGrant Likely } 2138ca632f55SGrant Likely 2139ca632f55SGrant Likely /* Allocate master with space for data */ 2140ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct pl022)); 2141ca632f55SGrant Likely if (master == NULL) { 2142ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2143ca632f55SGrant Likely status = -ENOMEM; 2144ca632f55SGrant Likely goto err_no_master; 2145ca632f55SGrant Likely } 2146ca632f55SGrant Likely 2147ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 2148ca632f55SGrant Likely pl022->master = master; 2149ca632f55SGrant Likely pl022->master_info = platform_info; 2150ca632f55SGrant Likely pl022->adev = adev; 2151ca632f55SGrant Likely pl022->vendor = id->data; 2152ca632f55SGrant Likely 2153ca632f55SGrant Likely /* 2154ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2155ca632f55SGrant Likely * on this board 2156ca632f55SGrant Likely */ 2157ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 2158ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 2159ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2160ca632f55SGrant Likely master->setup = pl022_setup; 2161ca632f55SGrant Likely master->transfer = pl022_transfer; 2162ca632f55SGrant Likely 2163ca632f55SGrant Likely /* 2164ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2165ca632f55SGrant Likely * always MS bit first on the original pl022. 2166ca632f55SGrant Likely */ 2167ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2168ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2169ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2170ca632f55SGrant Likely 2171ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2172ca632f55SGrant Likely 2173ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2174ca632f55SGrant Likely if (status) 2175ca632f55SGrant Likely goto err_no_ioregion; 2176ca632f55SGrant Likely 2177ca632f55SGrant Likely pl022->phybase = adev->res.start; 2178ca632f55SGrant Likely pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2179ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2180ca632f55SGrant Likely status = -ENOMEM; 2181ca632f55SGrant Likely goto err_no_ioremap; 2182ca632f55SGrant Likely } 2183ca632f55SGrant Likely printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2184ca632f55SGrant Likely adev->res.start, pl022->virtbase); 2185ca632f55SGrant Likely 2186ca632f55SGrant Likely pl022->clk = clk_get(&adev->dev, NULL); 2187ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2188ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2189ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2190ca632f55SGrant Likely goto err_no_clk; 2191ca632f55SGrant Likely } 21927ff6bcf0SRussell King 21937ff6bcf0SRussell King status = clk_prepare(pl022->clk); 21947ff6bcf0SRussell King if (status) { 21957ff6bcf0SRussell King dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 21967ff6bcf0SRussell King goto err_clk_prep; 21977ff6bcf0SRussell King } 21987ff6bcf0SRussell King 219971e63e74SUlf Hansson status = clk_enable(pl022->clk); 220071e63e74SUlf Hansson if (status) { 220171e63e74SUlf Hansson dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 220271e63e74SUlf Hansson goto err_no_clk_en; 220371e63e74SUlf Hansson } 220471e63e74SUlf Hansson 2205ca632f55SGrant Likely /* Disable SSP */ 2206ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2207ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2208ca632f55SGrant Likely load_ssp_default_config(pl022); 2209ca632f55SGrant Likely 2210ca632f55SGrant Likely status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2211ca632f55SGrant Likely pl022); 2212ca632f55SGrant Likely if (status < 0) { 2213ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2214ca632f55SGrant Likely goto err_no_irq; 2215ca632f55SGrant Likely } 2216ca632f55SGrant Likely 2217ca632f55SGrant Likely /* Get DMA channels */ 2218ca632f55SGrant Likely if (platform_info->enable_dma) { 2219ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2220ca632f55SGrant Likely if (status != 0) 2221ca632f55SGrant Likely platform_info->enable_dma = 0; 2222ca632f55SGrant Likely } 2223ca632f55SGrant Likely 2224ca632f55SGrant Likely /* Initialize and start queue */ 2225ca632f55SGrant Likely status = init_queue(pl022); 2226ca632f55SGrant Likely if (status != 0) { 2227ca632f55SGrant Likely dev_err(&adev->dev, "probe - problem initializing queue\n"); 2228ca632f55SGrant Likely goto err_init_queue; 2229ca632f55SGrant Likely } 2230ca632f55SGrant Likely status = start_queue(pl022); 2231ca632f55SGrant Likely if (status != 0) { 2232ca632f55SGrant Likely dev_err(&adev->dev, "probe - problem starting queue\n"); 2233ca632f55SGrant Likely goto err_start_queue; 2234ca632f55SGrant Likely } 2235ca632f55SGrant Likely /* Register with the SPI framework */ 2236ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 2237ca632f55SGrant Likely status = spi_register_master(master); 2238ca632f55SGrant Likely if (status != 0) { 2239ca632f55SGrant Likely dev_err(&adev->dev, 2240ca632f55SGrant Likely "probe - problem registering spi master\n"); 2241ca632f55SGrant Likely goto err_spi_register; 2242ca632f55SGrant Likely } 2243ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 224492b97f0aSRussell King 224592b97f0aSRussell King /* let runtime pm put suspend */ 224692b97f0aSRussell King pm_runtime_put(dev); 2247ca632f55SGrant Likely return 0; 2248ca632f55SGrant Likely 2249ca632f55SGrant Likely err_spi_register: 2250ca632f55SGrant Likely err_start_queue: 2251ca632f55SGrant Likely err_init_queue: 2252ca632f55SGrant Likely destroy_queue(pl022); 22533e3ea716SViresh Kumar if (platform_info->enable_dma) 2254ca632f55SGrant Likely pl022_dma_remove(pl022); 22553e3ea716SViresh Kumar 2256ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2257ca632f55SGrant Likely err_no_irq: 225871e63e74SUlf Hansson clk_disable(pl022->clk); 225971e63e74SUlf Hansson err_no_clk_en: 22607ff6bcf0SRussell King clk_unprepare(pl022->clk); 22617ff6bcf0SRussell King err_clk_prep: 2262ca632f55SGrant Likely clk_put(pl022->clk); 2263ca632f55SGrant Likely err_no_clk: 2264ca632f55SGrant Likely iounmap(pl022->virtbase); 2265ca632f55SGrant Likely err_no_ioremap: 2266ca632f55SGrant Likely amba_release_regions(adev); 2267ca632f55SGrant Likely err_no_ioregion: 2268ca632f55SGrant Likely spi_master_put(master); 2269ca632f55SGrant Likely err_no_master: 2270ca632f55SGrant Likely err_no_pdata: 2271ca632f55SGrant Likely return status; 2272ca632f55SGrant Likely } 2273ca632f55SGrant Likely 2274ca632f55SGrant Likely static int __devexit 2275ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2276ca632f55SGrant Likely { 2277ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 227850658b66SLinus Walleij 2279ca632f55SGrant Likely if (!pl022) 2280ca632f55SGrant Likely return 0; 2281ca632f55SGrant Likely 228292b97f0aSRussell King /* 228392b97f0aSRussell King * undo pm_runtime_put() in probe. I assume that we're not 228492b97f0aSRussell King * accessing the primecell here. 228592b97f0aSRussell King */ 228692b97f0aSRussell King pm_runtime_get_noresume(&adev->dev); 228792b97f0aSRussell King 2288ca632f55SGrant Likely /* Remove the queue */ 228950658b66SLinus Walleij if (destroy_queue(pl022) != 0) 229050658b66SLinus Walleij dev_err(&adev->dev, "queue remove failed\n"); 2291ca632f55SGrant Likely load_ssp_default_config(pl022); 22923e3ea716SViresh Kumar if (pl022->master_info->enable_dma) 2293ca632f55SGrant Likely pl022_dma_remove(pl022); 22943e3ea716SViresh Kumar 2295ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2296ca632f55SGrant Likely clk_disable(pl022->clk); 22977ff6bcf0SRussell King clk_unprepare(pl022->clk); 2298ca632f55SGrant Likely clk_put(pl022->clk); 2299ca632f55SGrant Likely iounmap(pl022->virtbase); 2300ca632f55SGrant Likely amba_release_regions(adev); 2301ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2302ca632f55SGrant Likely spi_unregister_master(pl022->master); 2303ca632f55SGrant Likely spi_master_put(pl022->master); 2304ca632f55SGrant Likely amba_set_drvdata(adev, NULL); 2305ca632f55SGrant Likely return 0; 2306ca632f55SGrant Likely } 2307ca632f55SGrant Likely 230892b97f0aSRussell King #ifdef CONFIG_SUSPEND 23096cfa6279SPeter Hüwe static int pl022_suspend(struct device *dev) 2310ca632f55SGrant Likely { 231192b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2312ca632f55SGrant Likely int status = 0; 2313ca632f55SGrant Likely 2314ca632f55SGrant Likely status = stop_queue(pl022); 2315ca632f55SGrant Likely if (status) { 23166cfa6279SPeter Hüwe dev_warn(dev, "suspend cannot stop queue\n"); 2317ca632f55SGrant Likely return status; 2318ca632f55SGrant Likely } 2319ca632f55SGrant Likely 23206cfa6279SPeter Hüwe dev_dbg(dev, "suspended\n"); 2321ca632f55SGrant Likely return 0; 2322ca632f55SGrant Likely } 2323ca632f55SGrant Likely 232492b97f0aSRussell King static int pl022_resume(struct device *dev) 2325ca632f55SGrant Likely { 232692b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2327ca632f55SGrant Likely int status = 0; 2328ca632f55SGrant Likely 2329ca632f55SGrant Likely /* Start the queue running */ 2330ca632f55SGrant Likely status = start_queue(pl022); 2331ca632f55SGrant Likely if (status) 233292b97f0aSRussell King dev_err(dev, "problem starting queue (%d)\n", status); 2333ca632f55SGrant Likely else 233492b97f0aSRussell King dev_dbg(dev, "resumed\n"); 2335ca632f55SGrant Likely 2336ca632f55SGrant Likely return status; 2337ca632f55SGrant Likely } 2338ca632f55SGrant Likely #endif /* CONFIG_PM */ 2339ca632f55SGrant Likely 234092b97f0aSRussell King #ifdef CONFIG_PM_RUNTIME 234192b97f0aSRussell King static int pl022_runtime_suspend(struct device *dev) 234292b97f0aSRussell King { 234392b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 234492b97f0aSRussell King 234592b97f0aSRussell King clk_disable(pl022->clk); 234692b97f0aSRussell King amba_vcore_disable(pl022->adev); 234792b97f0aSRussell King 234892b97f0aSRussell King return 0; 234992b97f0aSRussell King } 235092b97f0aSRussell King 235192b97f0aSRussell King static int pl022_runtime_resume(struct device *dev) 235292b97f0aSRussell King { 235392b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 235492b97f0aSRussell King 235592b97f0aSRussell King amba_vcore_enable(pl022->adev); 235692b97f0aSRussell King clk_enable(pl022->clk); 235792b97f0aSRussell King 235892b97f0aSRussell King return 0; 235992b97f0aSRussell King } 236092b97f0aSRussell King #endif 236192b97f0aSRussell King 236292b97f0aSRussell King static const struct dev_pm_ops pl022_dev_pm_ops = { 236392b97f0aSRussell King SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 236492b97f0aSRussell King SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 236592b97f0aSRussell King }; 236692b97f0aSRussell King 2367ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2368ca632f55SGrant Likely .fifodepth = 8, 2369ca632f55SGrant Likely .max_bpw = 16, 2370ca632f55SGrant Likely .unidir = false, 2371ca632f55SGrant Likely .extended_cr = false, 2372ca632f55SGrant Likely .pl023 = false, 2373ca632f55SGrant Likely .loopback = true, 2374ca632f55SGrant Likely }; 2375ca632f55SGrant Likely 2376ca632f55SGrant Likely static struct vendor_data vendor_st = { 2377ca632f55SGrant Likely .fifodepth = 32, 2378ca632f55SGrant Likely .max_bpw = 32, 2379ca632f55SGrant Likely .unidir = false, 2380ca632f55SGrant Likely .extended_cr = true, 2381ca632f55SGrant Likely .pl023 = false, 2382ca632f55SGrant Likely .loopback = true, 2383ca632f55SGrant Likely }; 2384ca632f55SGrant Likely 2385ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2386ca632f55SGrant Likely .fifodepth = 32, 2387ca632f55SGrant Likely .max_bpw = 32, 2388ca632f55SGrant Likely .unidir = false, 2389ca632f55SGrant Likely .extended_cr = true, 2390ca632f55SGrant Likely .pl023 = true, 2391ca632f55SGrant Likely .loopback = false, 2392ca632f55SGrant Likely }; 2393ca632f55SGrant Likely 2394ca632f55SGrant Likely static struct vendor_data vendor_db5500_pl023 = { 2395ca632f55SGrant Likely .fifodepth = 32, 2396ca632f55SGrant Likely .max_bpw = 32, 2397ca632f55SGrant Likely .unidir = false, 2398ca632f55SGrant Likely .extended_cr = true, 2399ca632f55SGrant Likely .pl023 = true, 2400ca632f55SGrant Likely .loopback = true, 2401ca632f55SGrant Likely }; 2402ca632f55SGrant Likely 2403ca632f55SGrant Likely static struct amba_id pl022_ids[] = { 2404ca632f55SGrant Likely { 2405ca632f55SGrant Likely /* 2406ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2407ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2408ca632f55SGrant Likely */ 2409ca632f55SGrant Likely .id = 0x00041022, 2410ca632f55SGrant Likely .mask = 0x000fffff, 2411ca632f55SGrant Likely .data = &vendor_arm, 2412ca632f55SGrant Likely }, 2413ca632f55SGrant Likely { 2414ca632f55SGrant Likely /* 2415ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2416ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2417ca632f55SGrant Likely */ 2418ca632f55SGrant Likely .id = 0x01080022, 2419ca632f55SGrant Likely .mask = 0xffffffff, 2420ca632f55SGrant Likely .data = &vendor_st, 2421ca632f55SGrant Likely }, 2422ca632f55SGrant Likely { 2423ca632f55SGrant Likely /* 2424ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2425ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2426ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2427ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2428ca632f55SGrant Likely * CR0/CR1 register 2429ca632f55SGrant Likely */ 2430ca632f55SGrant Likely .id = 0x00080023, 2431ca632f55SGrant Likely .mask = 0xffffffff, 2432ca632f55SGrant Likely .data = &vendor_st_pl023, 2433ca632f55SGrant Likely }, 2434ca632f55SGrant Likely { 2435ca632f55SGrant Likely .id = 0x10080023, 2436ca632f55SGrant Likely .mask = 0xffffffff, 2437ca632f55SGrant Likely .data = &vendor_db5500_pl023, 2438ca632f55SGrant Likely }, 2439ca632f55SGrant Likely { 0, 0 }, 2440ca632f55SGrant Likely }; 2441ca632f55SGrant Likely 2442ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2443ca632f55SGrant Likely .drv = { 2444ca632f55SGrant Likely .name = "ssp-pl022", 244592b97f0aSRussell King .pm = &pl022_dev_pm_ops, 2446ca632f55SGrant Likely }, 2447ca632f55SGrant Likely .id_table = pl022_ids, 2448ca632f55SGrant Likely .probe = pl022_probe, 2449ca632f55SGrant Likely .remove = __devexit_p(pl022_remove), 2450ca632f55SGrant Likely }; 2451ca632f55SGrant Likely 2452ca632f55SGrant Likely static int __init pl022_init(void) 2453ca632f55SGrant Likely { 2454ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2455ca632f55SGrant Likely } 2456ca632f55SGrant Likely subsys_initcall(pl022_init); 2457ca632f55SGrant Likely 2458ca632f55SGrant Likely static void __exit pl022_exit(void) 2459ca632f55SGrant Likely { 2460ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2461ca632f55SGrant Likely } 2462ca632f55SGrant Likely module_exit(pl022_exit); 2463ca632f55SGrant Likely 2464ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2465ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2466ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2467