1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ca632f55SGrant Likely /* 3ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 4ca632f55SGrant Likely * 5aeef9915SLinus Walleij * Copyright (C) 2008-2012 ST-Ericsson AB 6ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 7ca632f55SGrant Likely * 8ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * Initial version inspired by: 11ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 12ca632f55SGrant Likely * Initial adoption to PL022 by: 13ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 14ca632f55SGrant Likely */ 15ca632f55SGrant Likely 16ca632f55SGrant Likely #include <linux/init.h> 17ca632f55SGrant Likely #include <linux/module.h> 18ca632f55SGrant Likely #include <linux/device.h> 19ca632f55SGrant Likely #include <linux/ioport.h> 20ca632f55SGrant Likely #include <linux/errno.h> 21ca632f55SGrant Likely #include <linux/interrupt.h> 22ca632f55SGrant Likely #include <linux/spi/spi.h> 23ca632f55SGrant Likely #include <linux/delay.h> 24ca632f55SGrant Likely #include <linux/clk.h> 25ca632f55SGrant Likely #include <linux/err.h> 26ca632f55SGrant Likely #include <linux/amba/bus.h> 27ca632f55SGrant Likely #include <linux/amba/pl022.h> 28ca632f55SGrant Likely #include <linux/io.h> 29ca632f55SGrant Likely #include <linux/slab.h> 30ca632f55SGrant Likely #include <linux/dmaengine.h> 31ca632f55SGrant Likely #include <linux/dma-mapping.h> 32ca632f55SGrant Likely #include <linux/scatterlist.h> 33bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 34f6f46de1SRoland Stigge #include <linux/gpio.h> 356d3952a7SRoland Stigge #include <linux/of_gpio.h> 364f5e1b37SPatrice Chotard #include <linux/pinctrl/consumer.h> 37ca632f55SGrant Likely 38ca632f55SGrant Likely /* 39ca632f55SGrant Likely * This macro is used to define some register default values. 40ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 41ca632f55SGrant Likely * val shifted sb steps to the left. 42ca632f55SGrant Likely */ 43ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 44ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 45ca632f55SGrant Likely 46ca632f55SGrant Likely /* 47ca632f55SGrant Likely * This macro is also used to define some default values. 48ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 49ca632f55SGrant Likely * the result with mask. 50ca632f55SGrant Likely */ 51ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 52ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 53ca632f55SGrant Likely 54ca632f55SGrant Likely #define DRIVE_TX 0 55ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 56ca632f55SGrant Likely 57ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 58ca632f55SGrant Likely #define QUEUE_DMA 1 59ca632f55SGrant Likely 60ca632f55SGrant Likely #define RX_TRANSFER 1 61ca632f55SGrant Likely #define TX_TRANSFER 2 62ca632f55SGrant Likely 63ca632f55SGrant Likely /* 64ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 65ca632f55SGrant Likely */ 66ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 67ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 68ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 69ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 70ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 71ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 72ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 73ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 74ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 75ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 76db4fa45eSAnders Berg #define SSP_CSR(r) (r + 0x030) /* vendor extension */ 77ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 78ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 79ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 80ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 81ca632f55SGrant Likely 82ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 83ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 84ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 85ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 86ca632f55SGrant Likely 87ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 88ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 89ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 90ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 91ca632f55SGrant Likely 92ca632f55SGrant Likely /* 93ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 94ca632f55SGrant Likely */ 95ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 96ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 97ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 98ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 99ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 100ca632f55SGrant Likely 101ca632f55SGrant Likely /* 102ca632f55SGrant Likely * The ST version of this block moves som bits 103ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 104ca632f55SGrant Likely */ 105ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 106ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 107ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 108ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 109ca632f55SGrant Likely 110ca632f55SGrant Likely /* 111ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 112ca632f55SGrant Likely */ 113ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 114ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 115ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 116ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 117ca632f55SGrant Likely 118ca632f55SGrant Likely /* 119ca632f55SGrant Likely * The ST version of this block adds some bits 120ca632f55SGrant Likely * in SSP_CR1 121ca632f55SGrant Likely */ 122ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 123ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 124ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 125ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 126ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 127ca632f55SGrant Likely /* This one is only in the PL023 variant */ 128ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 129ca632f55SGrant Likely 130ca632f55SGrant Likely /* 131ca632f55SGrant Likely * SSP Status Register - SSP_SR 132ca632f55SGrant Likely */ 133ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 134ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 135ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 136ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 137ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 138ca632f55SGrant Likely 139ca632f55SGrant Likely /* 140ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 141ca632f55SGrant Likely */ 142ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 143ca632f55SGrant Likely 144ca632f55SGrant Likely /* 145ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 146ca632f55SGrant Likely */ 147ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 148ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 149ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 150ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 151ca632f55SGrant Likely 152ca632f55SGrant Likely /* 153ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 154ca632f55SGrant Likely */ 155ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 156ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 157ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 158ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 159ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 160ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 161ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 162ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 163ca632f55SGrant Likely 164ca632f55SGrant Likely /* 165ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 166ca632f55SGrant Likely */ 167ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 168ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 169ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 170ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 171ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 172ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 173ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 174ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 175ca632f55SGrant Likely 176ca632f55SGrant Likely /* 177ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 178ca632f55SGrant Likely */ 179ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 180ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 181ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 182ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 183ca632f55SGrant Likely 184ca632f55SGrant Likely /* 185ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 186ca632f55SGrant Likely */ 187ca632f55SGrant Likely /* Receive DMA Enable bit */ 188ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 189ca632f55SGrant Likely /* Transmit DMA Enable bit */ 190ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 191ca632f55SGrant Likely 192ca632f55SGrant Likely /* 193db4fa45eSAnders Berg * SSP Chip Select Control Register - SSP_CSR 194db4fa45eSAnders Berg * (vendor extension) 195db4fa45eSAnders Berg */ 196db4fa45eSAnders Berg #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0) 197db4fa45eSAnders Berg 198db4fa45eSAnders Berg /* 199ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 200ca632f55SGrant Likely */ 201ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 202ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 203ca632f55SGrant Likely 204ca632f55SGrant Likely /* 205ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 206ca632f55SGrant Likely */ 207ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 208ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 209ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 210ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 211ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 212ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 213ca632f55SGrant Likely 214ca632f55SGrant Likely /* 215ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 216ca632f55SGrant Likely */ 217ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 218ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 219ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 220ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 221ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 222ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 223ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 224ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 225ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 226ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 227ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 228ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 229ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 230ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 231ca632f55SGrant Likely 232ca632f55SGrant Likely /* 233ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 234ca632f55SGrant Likely */ 235ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 236ca632f55SGrant Likely 237ca632f55SGrant Likely /* 238ca632f55SGrant Likely * Message State 239ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 240ca632f55SGrant Likely * hold a single state value, that's why all this 241ca632f55SGrant Likely * (void *) casting is done here. 242ca632f55SGrant Likely */ 243ca632f55SGrant Likely #define STATE_START ((void *) 0) 244ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 245ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 246ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 2477aef2b64SJiwei Sun #define STATE_TIMEOUT ((void *) -2) 248ca632f55SGrant Likely 249ca632f55SGrant Likely /* 250ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 251ca632f55SGrant Likely */ 252ca632f55SGrant Likely #define SSP_DISABLED (0) 253ca632f55SGrant Likely #define SSP_ENABLED (1) 254ca632f55SGrant Likely 255ca632f55SGrant Likely /* 256ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 257ca632f55SGrant Likely */ 258ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 259ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 260ca632f55SGrant Likely 261ca632f55SGrant Likely /* 262ca632f55SGrant Likely * SSP Clock Defaults 263ca632f55SGrant Likely */ 264ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 265ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 266ca632f55SGrant Likely 267ca632f55SGrant Likely /* 268ca632f55SGrant Likely * SSP Clock Parameter ranges 269ca632f55SGrant Likely */ 270ca632f55SGrant Likely #define CPSDVR_MIN 0x02 271ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 272ca632f55SGrant Likely #define SCR_MIN 0x00 273ca632f55SGrant Likely #define SCR_MAX 0xFF 274ca632f55SGrant Likely 275ca632f55SGrant Likely /* 276ca632f55SGrant Likely * SSP Interrupt related Macros 277ca632f55SGrant Likely */ 278ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 279ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 28085fa4e1fSAlexander Sverdlin #define ENABLE_ALL_INTERRUPTS ( \ 28185fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_RORIM | \ 28285fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_RTIM | \ 28385fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_RXIM | \ 28485fa4e1fSAlexander Sverdlin SSP_IMSC_MASK_TXIM \ 28585fa4e1fSAlexander Sverdlin ) 286ca632f55SGrant Likely 287ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 288ca632f55SGrant Likely 289ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 290ca632f55SGrant Likely 291ca632f55SGrant Likely /* 292ca632f55SGrant Likely * The type of reading going on on this chip 293ca632f55SGrant Likely */ 294ca632f55SGrant Likely enum ssp_reading { 295ca632f55SGrant Likely READING_NULL, 296ca632f55SGrant Likely READING_U8, 297ca632f55SGrant Likely READING_U16, 298ca632f55SGrant Likely READING_U32 299ca632f55SGrant Likely }; 300ca632f55SGrant Likely 301*c7cd1dfbSLee Jones /* 302ca632f55SGrant Likely * The type of writing going on on this chip 303ca632f55SGrant Likely */ 304ca632f55SGrant Likely enum ssp_writing { 305ca632f55SGrant Likely WRITING_NULL, 306ca632f55SGrant Likely WRITING_U8, 307ca632f55SGrant Likely WRITING_U16, 308ca632f55SGrant Likely WRITING_U32 309ca632f55SGrant Likely }; 310ca632f55SGrant Likely 311ca632f55SGrant Likely /** 312ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 313ca632f55SGrant Likely * for PL022 derivates 314ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 315ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 316ca632f55SGrant Likely * @unidir: supports unidirection transfers 317ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 318ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 319ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 320*c7cd1dfbSLee Jones * @loopback: supports loopback mode 321db4fa45eSAnders Berg * @internal_cs_ctrl: supports chip select control register 322ca632f55SGrant Likely */ 323ca632f55SGrant Likely struct vendor_data { 324ca632f55SGrant Likely int fifodepth; 325ca632f55SGrant Likely int max_bpw; 326ca632f55SGrant Likely bool unidir; 327ca632f55SGrant Likely bool extended_cr; 328ca632f55SGrant Likely bool pl023; 329ca632f55SGrant Likely bool loopback; 330db4fa45eSAnders Berg bool internal_cs_ctrl; 331ca632f55SGrant Likely }; 332ca632f55SGrant Likely 333ca632f55SGrant Likely /** 334ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 335ca632f55SGrant Likely * @adev: AMBA device model hookup 336ca632f55SGrant Likely * @vendor: vendor data for the IP block 337ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 338ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 339ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 340ca632f55SGrant Likely * @master: SPI framework hookup 341ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 342ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 343ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 344ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 345ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 3468b8d7191SVirupax Sadashivpetimath * @next_msg_cs_active: the next message in the queue has been examined 3478b8d7191SVirupax Sadashivpetimath * and it was found that it uses the same chip select as the previous 3488b8d7191SVirupax Sadashivpetimath * message, so we left it active after the previous transfer, and it's 3498b8d7191SVirupax Sadashivpetimath * active already. 350ca632f55SGrant Likely * @tx: current position in TX buffer to be read 351ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 352ca632f55SGrant Likely * @rx: current position in RX buffer to be written 353ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 354ca632f55SGrant Likely * @read: the type of read currently going on 355ca632f55SGrant Likely * @write: the type of write currently going on 356ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 357*c7cd1dfbSLee Jones * @rx_lev_trig: receive FIFO watermark level which triggers IRQ 358*c7cd1dfbSLee Jones * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ 359ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 360ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 361ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 362ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 363ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 364*c7cd1dfbSLee Jones * @dma_running: indicates whether DMA is in operation 365f6f46de1SRoland Stigge * @cur_cs: current chip select (gpio) 366f6f46de1SRoland Stigge * @chipselects: list of chipselects (gpios) 367ca632f55SGrant Likely */ 368ca632f55SGrant Likely struct pl022 { 369ca632f55SGrant Likely struct amba_device *adev; 370ca632f55SGrant Likely struct vendor_data *vendor; 371ca632f55SGrant Likely resource_size_t phybase; 372ca632f55SGrant Likely void __iomem *virtbase; 373ca632f55SGrant Likely struct clk *clk; 374ca632f55SGrant Likely struct spi_master *master; 375ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 376ffbbdd21SLinus Walleij /* Message per-transfer pump */ 377ca632f55SGrant Likely struct tasklet_struct pump_transfers; 378ca632f55SGrant Likely struct spi_message *cur_msg; 379ca632f55SGrant Likely struct spi_transfer *cur_transfer; 380ca632f55SGrant Likely struct chip_data *cur_chip; 3818b8d7191SVirupax Sadashivpetimath bool next_msg_cs_active; 382ca632f55SGrant Likely void *tx; 383ca632f55SGrant Likely void *tx_end; 384ca632f55SGrant Likely void *rx; 385ca632f55SGrant Likely void *rx_end; 386ca632f55SGrant Likely enum ssp_reading read; 387ca632f55SGrant Likely enum ssp_writing write; 388ca632f55SGrant Likely u32 exp_fifo_level; 389083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 390083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 391ca632f55SGrant Likely /* DMA settings */ 392ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 393ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 394ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 395ca632f55SGrant Likely struct sg_table sgt_rx; 396ca632f55SGrant Likely struct sg_table sgt_tx; 397ca632f55SGrant Likely char *dummypage; 398ffbbdd21SLinus Walleij bool dma_running; 399ca632f55SGrant Likely #endif 400f6f46de1SRoland Stigge int cur_cs; 401f6f46de1SRoland Stigge int *chipselects; 402ca632f55SGrant Likely }; 403ca632f55SGrant Likely 404ca632f55SGrant Likely /** 405ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 406ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 407ca632f55SGrant Likely * register is 32 bits wide rather than just 16 408ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 409ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 410ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 411ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 412ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 413ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 414ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 415ca632f55SGrant Likely * @cs_control: chip select callback provided by chip 416ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 417ca632f55SGrant Likely * 418ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 419ca632f55SGrant Likely * This would be set according to the current message that would be served 420ca632f55SGrant Likely */ 421ca632f55SGrant Likely struct chip_data { 422ca632f55SGrant Likely u32 cr0; 423ca632f55SGrant Likely u16 cr1; 424ca632f55SGrant Likely u16 dmacr; 425ca632f55SGrant Likely u16 cpsr; 426ca632f55SGrant Likely u8 n_bytes; 427ca632f55SGrant Likely bool enable_dma; 428ca632f55SGrant Likely enum ssp_reading read; 429ca632f55SGrant Likely enum ssp_writing write; 430ca632f55SGrant Likely void (*cs_control) (u32 command); 431ca632f55SGrant Likely int xfer_type; 432ca632f55SGrant Likely }; 433ca632f55SGrant Likely 434ca632f55SGrant Likely /** 435ca632f55SGrant Likely * null_cs_control - Dummy chip select function 436ca632f55SGrant Likely * @command: select/delect the chip 437ca632f55SGrant Likely * 438ca632f55SGrant Likely * If no chip select function is provided by client this is used as dummy 439ca632f55SGrant Likely * chip select 440ca632f55SGrant Likely */ 441ca632f55SGrant Likely static void null_cs_control(u32 command) 442ca632f55SGrant Likely { 443ca632f55SGrant Likely pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 444ca632f55SGrant Likely } 445ca632f55SGrant Likely 446db4fa45eSAnders Berg /** 447db4fa45eSAnders Berg * internal_cs_control - Control chip select signals via SSP_CSR. 448db4fa45eSAnders Berg * @pl022: SSP driver private data structure 449db4fa45eSAnders Berg * @command: select/delect the chip 450db4fa45eSAnders Berg * 451db4fa45eSAnders Berg * Used on controller with internal chip select control via SSP_CSR register 452db4fa45eSAnders Berg * (vendor extension). Each of the 5 LSB in the register controls one chip 453db4fa45eSAnders Berg * select signal. 454db4fa45eSAnders Berg */ 455db4fa45eSAnders Berg static void internal_cs_control(struct pl022 *pl022, u32 command) 456db4fa45eSAnders Berg { 457db4fa45eSAnders Berg u32 tmp; 458db4fa45eSAnders Berg 459db4fa45eSAnders Berg tmp = readw(SSP_CSR(pl022->virtbase)); 460db4fa45eSAnders Berg if (command == SSP_CHIP_SELECT) 461db4fa45eSAnders Berg tmp &= ~BIT(pl022->cur_cs); 462db4fa45eSAnders Berg else 463db4fa45eSAnders Berg tmp |= BIT(pl022->cur_cs); 464db4fa45eSAnders Berg writew(tmp, SSP_CSR(pl022->virtbase)); 465db4fa45eSAnders Berg } 466db4fa45eSAnders Berg 467f6f46de1SRoland Stigge static void pl022_cs_control(struct pl022 *pl022, u32 command) 468f6f46de1SRoland Stigge { 469db4fa45eSAnders Berg if (pl022->vendor->internal_cs_ctrl) 470db4fa45eSAnders Berg internal_cs_control(pl022, command); 471db4fa45eSAnders Berg else if (gpio_is_valid(pl022->cur_cs)) 472f6f46de1SRoland Stigge gpio_set_value(pl022->cur_cs, command); 473f6f46de1SRoland Stigge else 474f6f46de1SRoland Stigge pl022->cur_chip->cs_control(command); 475f6f46de1SRoland Stigge } 476f6f46de1SRoland Stigge 477ca632f55SGrant Likely /** 478ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 479ca632f55SGrant Likely * callback of this message. Assumes that caller already 480ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 481ca632f55SGrant Likely * @pl022: SSP driver private data structure 482ca632f55SGrant Likely */ 483ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 484ca632f55SGrant Likely { 485ca632f55SGrant Likely struct spi_transfer *last_transfer; 4868b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = false; 487ca632f55SGrant Likely 48823e2c2aaSAxel Lin last_transfer = list_last_entry(&pl022->cur_msg->transfers, 48923e2c2aaSAxel Lin struct spi_transfer, transfer_list); 490ca632f55SGrant Likely 491ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 492ca632f55SGrant Likely /* 493ca632f55SGrant Likely * FIXME: This runs in interrupt context. 494ca632f55SGrant Likely * Is this really smart? 495ca632f55SGrant Likely */ 496e74dc5c7SAlexandru Ardelean spi_transfer_delay_exec(last_transfer); 497ca632f55SGrant Likely 4988b8d7191SVirupax Sadashivpetimath if (!last_transfer->cs_change) { 499ca632f55SGrant Likely struct spi_message *next_msg; 500ca632f55SGrant Likely 5018b8d7191SVirupax Sadashivpetimath /* 5028b8d7191SVirupax Sadashivpetimath * cs_change was not set. We can keep the chip select 5038b8d7191SVirupax Sadashivpetimath * enabled if there is message in the queue and it is 5048b8d7191SVirupax Sadashivpetimath * for the same spi device. 505ca632f55SGrant Likely * 506ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 507ca632f55SGrant Likely * after calling msg->complete (below) the driver that 508ca632f55SGrant Likely * sent the current message could be unloaded, which 509ca632f55SGrant Likely * could invalidate the cs_control() callback... 510ca632f55SGrant Likely */ 511ca632f55SGrant Likely /* get a pointer to the next message, if any */ 512ffbbdd21SLinus Walleij next_msg = spi_get_next_queued_message(pl022->master); 513ca632f55SGrant Likely 5148b8d7191SVirupax Sadashivpetimath /* 5158b8d7191SVirupax Sadashivpetimath * see if the next and current messages point 5168b8d7191SVirupax Sadashivpetimath * to the same spi device. 517ca632f55SGrant Likely */ 5188b8d7191SVirupax Sadashivpetimath if (next_msg && next_msg->spi != pl022->cur_msg->spi) 519ca632f55SGrant Likely next_msg = NULL; 5208b8d7191SVirupax Sadashivpetimath if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 521f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 5228b8d7191SVirupax Sadashivpetimath else 5238b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = true; 524ffbbdd21SLinus Walleij 525ca632f55SGrant Likely } 5268b8d7191SVirupax Sadashivpetimath 5278b8d7191SVirupax Sadashivpetimath pl022->cur_msg = NULL; 5288b8d7191SVirupax Sadashivpetimath pl022->cur_transfer = NULL; 5298b8d7191SVirupax Sadashivpetimath pl022->cur_chip = NULL; 530fd316941SVirupax Sadashivpetimath 531fd316941SVirupax Sadashivpetimath /* disable the SPI/SSP operation */ 532fd316941SVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 533fd316941SVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 534fd316941SVirupax Sadashivpetimath 535cd6fa8d2SAlexander Sverdlin spi_finalize_current_message(pl022->master); 536ca632f55SGrant Likely } 537ca632f55SGrant Likely 538ca632f55SGrant Likely /** 539ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 540ca632f55SGrant Likely * @pl022: SSP driver private data structure 541ca632f55SGrant Likely */ 542ca632f55SGrant Likely static int flush(struct pl022 *pl022) 543ca632f55SGrant Likely { 544ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 545ca632f55SGrant Likely 546ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 547ca632f55SGrant Likely do { 548ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 549ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 550ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 551ca632f55SGrant Likely 552ca632f55SGrant Likely pl022->exp_fifo_level = 0; 553ca632f55SGrant Likely 554ca632f55SGrant Likely return limit; 555ca632f55SGrant Likely } 556ca632f55SGrant Likely 557ca632f55SGrant Likely /** 558ca632f55SGrant Likely * restore_state - Load configuration of current chip 559ca632f55SGrant Likely * @pl022: SSP driver private data structure 560ca632f55SGrant Likely */ 561ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 562ca632f55SGrant Likely { 563ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 564ca632f55SGrant Likely 565ca632f55SGrant Likely if (pl022->vendor->extended_cr) 566ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 567ca632f55SGrant Likely else 568ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 569ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 570ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 571ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 572ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 573ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 574ca632f55SGrant Likely } 575ca632f55SGrant Likely 576ca632f55SGrant Likely /* 577ca632f55SGrant Likely * Default SSP Register Values 578ca632f55SGrant Likely */ 579ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 580ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 581ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 582ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 583ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 584ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 585ca632f55SGrant Likely ) 586ca632f55SGrant Likely 587ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 588ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 589ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 590ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 591ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 592ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 593ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 594ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 595ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 596ca632f55SGrant Likely ) 597ca632f55SGrant Likely 598ca632f55SGrant Likely /* The PL023 version is slightly different again */ 599ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 600ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 601ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 602ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 603ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 604ca632f55SGrant Likely ) 605ca632f55SGrant Likely 606ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 607ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 608ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 609ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 610ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 611ca632f55SGrant Likely ) 612ca632f55SGrant Likely 613ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 614ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 615ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 616ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 617ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 618ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 619ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 620ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 621ca632f55SGrant Likely ) 622ca632f55SGrant Likely 623ca632f55SGrant Likely /* 624ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 625ca632f55SGrant Likely * support, and a new clock feedback delay setting. 626ca632f55SGrant Likely */ 627ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 628ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 629ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 630ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 631ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 632ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 633ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 634ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 635ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 636ca632f55SGrant Likely ) 637ca632f55SGrant Likely 638ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 639ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 640ca632f55SGrant Likely ) 641ca632f55SGrant Likely 642ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 643ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 644ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 645ca632f55SGrant Likely ) 646ca632f55SGrant Likely 647ca632f55SGrant Likely /** 648ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 649ca632f55SGrant Likely * @pl022: SSP driver private data structure 650ca632f55SGrant Likely */ 651ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 652ca632f55SGrant Likely { 653ca632f55SGrant Likely if (pl022->vendor->pl023) { 654ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 655ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 656ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 657ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 658ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 659ca632f55SGrant Likely } else { 660ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 661ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 662ca632f55SGrant Likely } 663ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 664ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 665ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 666ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 667ca632f55SGrant Likely } 668ca632f55SGrant Likely 669*c7cd1dfbSLee Jones /* 670ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 671ca632f55SGrant Likely * set in pl022. 672ca632f55SGrant Likely */ 673ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 674ca632f55SGrant Likely { 675ca632f55SGrant Likely 676ca632f55SGrant Likely /* 677ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 678ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 679ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 680ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 681ca632f55SGrant Likely * 682ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 683ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 684ca632f55SGrant Likely * FIFO status flag indicates. 685ca632f55SGrant Likely */ 686ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 687ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 688ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 689ca632f55SGrant Likely 690ca632f55SGrant Likely /* Read as much as you can */ 691ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 692ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 693ca632f55SGrant Likely switch (pl022->read) { 694ca632f55SGrant Likely case READING_NULL: 695ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 696ca632f55SGrant Likely break; 697ca632f55SGrant Likely case READING_U8: 698ca632f55SGrant Likely *(u8 *) (pl022->rx) = 699ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 700ca632f55SGrant Likely break; 701ca632f55SGrant Likely case READING_U16: 702ca632f55SGrant Likely *(u16 *) (pl022->rx) = 703ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 704ca632f55SGrant Likely break; 705ca632f55SGrant Likely case READING_U32: 706ca632f55SGrant Likely *(u32 *) (pl022->rx) = 707ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 708ca632f55SGrant Likely break; 709ca632f55SGrant Likely } 710ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 711ca632f55SGrant Likely pl022->exp_fifo_level--; 712ca632f55SGrant Likely } 713ca632f55SGrant Likely /* 714ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 715ca632f55SGrant Likely */ 716ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 717ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 718ca632f55SGrant Likely switch (pl022->write) { 719ca632f55SGrant Likely case WRITING_NULL: 720ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 721ca632f55SGrant Likely break; 722ca632f55SGrant Likely case WRITING_U8: 723ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 724ca632f55SGrant Likely break; 725ca632f55SGrant Likely case WRITING_U16: 726ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 727ca632f55SGrant Likely break; 728ca632f55SGrant Likely case WRITING_U32: 729ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 730ca632f55SGrant Likely break; 731ca632f55SGrant Likely } 732ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 733ca632f55SGrant Likely pl022->exp_fifo_level++; 734ca632f55SGrant Likely /* 735ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 736ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 737ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 738ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 739ca632f55SGrant Likely */ 740ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 741ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 742ca632f55SGrant Likely switch (pl022->read) { 743ca632f55SGrant Likely case READING_NULL: 744ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 745ca632f55SGrant Likely break; 746ca632f55SGrant Likely case READING_U8: 747ca632f55SGrant Likely *(u8 *) (pl022->rx) = 748ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 749ca632f55SGrant Likely break; 750ca632f55SGrant Likely case READING_U16: 751ca632f55SGrant Likely *(u16 *) (pl022->rx) = 752ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 753ca632f55SGrant Likely break; 754ca632f55SGrant Likely case READING_U32: 755ca632f55SGrant Likely *(u32 *) (pl022->rx) = 756ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 757ca632f55SGrant Likely break; 758ca632f55SGrant Likely } 759ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 760ca632f55SGrant Likely pl022->exp_fifo_level--; 761ca632f55SGrant Likely } 762ca632f55SGrant Likely } 763ca632f55SGrant Likely /* 764ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 765ca632f55SGrant Likely * should be empty 766ca632f55SGrant Likely */ 767ca632f55SGrant Likely } 768ca632f55SGrant Likely 769ca632f55SGrant Likely /** 770ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 771ca632f55SGrant Likely * @pl022: SSP driver private data structure 772ca632f55SGrant Likely * 773ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 774ca632f55SGrant Likely * current spi message and returns with the state of current spi 775ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 776ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 777ca632f55SGrant Likely */ 778ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 779ca632f55SGrant Likely { 780ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 781ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 782ca632f55SGrant Likely 783ca632f55SGrant Likely /* Move to next transfer */ 784ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 785ca632f55SGrant Likely pl022->cur_transfer = 786ca632f55SGrant Likely list_entry(trans->transfer_list.next, 787ca632f55SGrant Likely struct spi_transfer, transfer_list); 788ca632f55SGrant Likely return STATE_RUNNING; 789ca632f55SGrant Likely } 790ca632f55SGrant Likely return STATE_DONE; 791ca632f55SGrant Likely } 792ca632f55SGrant Likely 793ca632f55SGrant Likely /* 794ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 795ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 796ca632f55SGrant Likely */ 797ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 798ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 799ca632f55SGrant Likely { 800ca632f55SGrant Likely /* Unmap and free the SG tables */ 801ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 802ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 803ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 804ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 805ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 806ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 807ca632f55SGrant Likely } 808ca632f55SGrant Likely 809ca632f55SGrant Likely static void dma_callback(void *data) 810ca632f55SGrant Likely { 811ca632f55SGrant Likely struct pl022 *pl022 = data; 812ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 813ca632f55SGrant Likely 814ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 815ca632f55SGrant Likely 816ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 817ca632f55SGrant Likely /* 818ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 819ca632f55SGrant Likely * good if you want to convince yourself that the loopback 820ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 821ca632f55SGrant Likely * DMA engine. 822ca632f55SGrant Likely */ 823ca632f55SGrant Likely { 824ca632f55SGrant Likely struct scatterlist *sg; 825ca632f55SGrant Likely unsigned int i; 826ca632f55SGrant Likely 827ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 828ca632f55SGrant Likely pl022->sgt_rx.sgl, 829ca632f55SGrant Likely pl022->sgt_rx.nents, 830ca632f55SGrant Likely DMA_FROM_DEVICE); 831ca632f55SGrant Likely 832ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 833ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 834ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 835ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 836ca632f55SGrant Likely 16, 837ca632f55SGrant Likely 1, 838ca632f55SGrant Likely sg_virt(sg), 839ca632f55SGrant Likely sg_dma_len(sg), 840ca632f55SGrant Likely 1); 841ca632f55SGrant Likely } 842ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 843ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 844ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 845ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 846ca632f55SGrant Likely 16, 847ca632f55SGrant Likely 1, 848ca632f55SGrant Likely sg_virt(sg), 849ca632f55SGrant Likely sg_dma_len(sg), 850ca632f55SGrant Likely 1); 851ca632f55SGrant Likely } 852ca632f55SGrant Likely } 853ca632f55SGrant Likely #endif 854ca632f55SGrant Likely 855ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 856ca632f55SGrant Likely 857ca632f55SGrant Likely /* Update total bytes transferred */ 858ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 859ca632f55SGrant Likely /* Move to next transfer */ 860ca632f55SGrant Likely msg->state = next_transfer(pl022); 861c0b07605SFredrik Ternerot if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) 862c0b07605SFredrik Ternerot pl022_cs_control(pl022, SSP_CHIP_DESELECT); 863ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 864ca632f55SGrant Likely } 865ca632f55SGrant Likely 866ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 867ca632f55SGrant Likely void *buffer, 868ca632f55SGrant Likely unsigned int length, 869ca632f55SGrant Likely struct sg_table *sgtab) 870ca632f55SGrant Likely { 871ca632f55SGrant Likely struct scatterlist *sg; 872ca632f55SGrant Likely int bytesleft = length; 873ca632f55SGrant Likely void *bufp = buffer; 874ca632f55SGrant Likely int mapbytes; 875ca632f55SGrant Likely int i; 876ca632f55SGrant Likely 877ca632f55SGrant Likely if (buffer) { 878ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 879ca632f55SGrant Likely /* 880ca632f55SGrant Likely * If there are less bytes left than what fits 881ca632f55SGrant Likely * in the current page (plus page alignment offset) 882ca632f55SGrant Likely * we just feed in this, else we stuff in as much 883ca632f55SGrant Likely * as we can. 884ca632f55SGrant Likely */ 885ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 886ca632f55SGrant Likely mapbytes = bytesleft; 887ca632f55SGrant Likely else 888ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 889ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 890ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 891ca632f55SGrant Likely bufp += mapbytes; 892ca632f55SGrant Likely bytesleft -= mapbytes; 893ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 894ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 895ca632f55SGrant Likely bufp, mapbytes, bytesleft); 896ca632f55SGrant Likely } 897ca632f55SGrant Likely } else { 898ca632f55SGrant Likely /* Map the dummy buffer on every page */ 899ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 900ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 901ca632f55SGrant Likely mapbytes = bytesleft; 902ca632f55SGrant Likely else 903ca632f55SGrant Likely mapbytes = PAGE_SIZE; 904ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 905ca632f55SGrant Likely mapbytes, 0); 906ca632f55SGrant Likely bytesleft -= mapbytes; 907ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 908ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 909ca632f55SGrant Likely mapbytes, bytesleft); 910ca632f55SGrant Likely 911ca632f55SGrant Likely } 912ca632f55SGrant Likely } 913ca632f55SGrant Likely BUG_ON(bytesleft); 914ca632f55SGrant Likely } 915ca632f55SGrant Likely 916ca632f55SGrant Likely /** 917ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 918ca632f55SGrant Likely * @pl022: SSP driver's private data structure 919ca632f55SGrant Likely */ 920ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 921ca632f55SGrant Likely { 922ca632f55SGrant Likely struct dma_slave_config rx_conf = { 923ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 924a485df4bSVinod Koul .direction = DMA_DEV_TO_MEM, 925258aea76SViresh Kumar .device_fc = false, 926ca632f55SGrant Likely }; 927ca632f55SGrant Likely struct dma_slave_config tx_conf = { 928ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 929a485df4bSVinod Koul .direction = DMA_MEM_TO_DEV, 930258aea76SViresh Kumar .device_fc = false, 931ca632f55SGrant Likely }; 932ca632f55SGrant Likely unsigned int pages; 933ca632f55SGrant Likely int ret; 934ca632f55SGrant Likely int rx_sglen, tx_sglen; 935ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 936ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 937ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 938ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 939ca632f55SGrant Likely 940ca632f55SGrant Likely /* Check that the channels are available */ 941ca632f55SGrant Likely if (!rxchan || !txchan) 942ca632f55SGrant Likely return -ENODEV; 943ca632f55SGrant Likely 944083be3f0SLinus Walleij /* 945083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 946083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 947083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 948083be3f0SLinus Walleij * calculation. 949083be3f0SLinus Walleij */ 950083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 951083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 952083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 953083be3f0SLinus Walleij break; 954083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 955083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 956083be3f0SLinus Walleij break; 957083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 958083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 959083be3f0SLinus Walleij break; 960083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 961083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 962083be3f0SLinus Walleij break; 963083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 964083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 965083be3f0SLinus Walleij break; 966083be3f0SLinus Walleij default: 967083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 968083be3f0SLinus Walleij break; 969083be3f0SLinus Walleij } 970083be3f0SLinus Walleij 971083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 972083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 973083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 974083be3f0SLinus Walleij break; 975083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 976083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 977083be3f0SLinus Walleij break; 978083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 979083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 980083be3f0SLinus Walleij break; 981083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 982083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 983083be3f0SLinus Walleij break; 984083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 985083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 986083be3f0SLinus Walleij break; 987083be3f0SLinus Walleij default: 988083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 989083be3f0SLinus Walleij break; 990083be3f0SLinus Walleij } 991083be3f0SLinus Walleij 992ca632f55SGrant Likely switch (pl022->read) { 993ca632f55SGrant Likely case READING_NULL: 994ca632f55SGrant Likely /* Use the same as for writing */ 995ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 996ca632f55SGrant Likely break; 997ca632f55SGrant Likely case READING_U8: 998ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 999ca632f55SGrant Likely break; 1000ca632f55SGrant Likely case READING_U16: 1001ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1002ca632f55SGrant Likely break; 1003ca632f55SGrant Likely case READING_U32: 1004ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1005ca632f55SGrant Likely break; 1006ca632f55SGrant Likely } 1007ca632f55SGrant Likely 1008ca632f55SGrant Likely switch (pl022->write) { 1009ca632f55SGrant Likely case WRITING_NULL: 1010ca632f55SGrant Likely /* Use the same as for reading */ 1011ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1012ca632f55SGrant Likely break; 1013ca632f55SGrant Likely case WRITING_U8: 1014ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1015ca632f55SGrant Likely break; 1016ca632f55SGrant Likely case WRITING_U16: 1017ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1018ca632f55SGrant Likely break; 1019ca632f55SGrant Likely case WRITING_U32: 1020ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1021ca632f55SGrant Likely break; 1022ca632f55SGrant Likely } 1023ca632f55SGrant Likely 1024ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 1025ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1026ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 1027ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1028ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 1029ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1030ca632f55SGrant Likely 1031ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 1032ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 1033ca632f55SGrant Likely 1034ca632f55SGrant Likely /* Create sglists for the transfers */ 1035b181565eSViresh Kumar pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1036ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1037ca632f55SGrant Likely 1038538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1039ca632f55SGrant Likely if (ret) 1040ca632f55SGrant Likely goto err_alloc_rx_sg; 1041ca632f55SGrant Likely 1042538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1043ca632f55SGrant Likely if (ret) 1044ca632f55SGrant Likely goto err_alloc_tx_sg; 1045ca632f55SGrant Likely 1046ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1047ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1048ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1049ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1050ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1051ca632f55SGrant Likely 1052ca632f55SGrant Likely /* Map DMA buffers */ 1053ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1054ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1055ca632f55SGrant Likely if (!rx_sglen) 1056ca632f55SGrant Likely goto err_rx_sgmap; 1057ca632f55SGrant Likely 1058ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1059ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1060ca632f55SGrant Likely if (!tx_sglen) 1061ca632f55SGrant Likely goto err_tx_sgmap; 1062ca632f55SGrant Likely 1063ca632f55SGrant Likely /* Send both scatterlists */ 106416052827SAlexandre Bounine rxdesc = dmaengine_prep_slave_sg(rxchan, 1065ca632f55SGrant Likely pl022->sgt_rx.sgl, 1066ca632f55SGrant Likely rx_sglen, 1067a485df4bSVinod Koul DMA_DEV_TO_MEM, 1068ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1069ca632f55SGrant Likely if (!rxdesc) 1070ca632f55SGrant Likely goto err_rxdesc; 1071ca632f55SGrant Likely 107216052827SAlexandre Bounine txdesc = dmaengine_prep_slave_sg(txchan, 1073ca632f55SGrant Likely pl022->sgt_tx.sgl, 1074ca632f55SGrant Likely tx_sglen, 1075a485df4bSVinod Koul DMA_MEM_TO_DEV, 1076ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1077ca632f55SGrant Likely if (!txdesc) 1078ca632f55SGrant Likely goto err_txdesc; 1079ca632f55SGrant Likely 1080ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1081ca632f55SGrant Likely rxdesc->callback = dma_callback; 1082ca632f55SGrant Likely rxdesc->callback_param = pl022; 1083ca632f55SGrant Likely 1084ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1085ca632f55SGrant Likely dmaengine_submit(rxdesc); 1086ca632f55SGrant Likely dmaengine_submit(txdesc); 1087ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1088ca632f55SGrant Likely dma_async_issue_pending(txchan); 1089ffbbdd21SLinus Walleij pl022->dma_running = true; 1090ca632f55SGrant Likely 1091ca632f55SGrant Likely return 0; 1092ca632f55SGrant Likely 1093ca632f55SGrant Likely err_txdesc: 1094ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1095ca632f55SGrant Likely err_rxdesc: 1096ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1097ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1098ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1099ca632f55SGrant Likely err_tx_sgmap: 1100ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 11013ffa6158SRay Jui pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1102ca632f55SGrant Likely err_rx_sgmap: 1103ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1104ca632f55SGrant Likely err_alloc_tx_sg: 1105ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1106ca632f55SGrant Likely err_alloc_rx_sg: 1107ca632f55SGrant Likely return -ENOMEM; 1108ca632f55SGrant Likely } 1109ca632f55SGrant Likely 1110fd4a319bSGrant Likely static int pl022_dma_probe(struct pl022 *pl022) 1111ca632f55SGrant Likely { 1112ca632f55SGrant Likely dma_cap_mask_t mask; 1113ca632f55SGrant Likely 1114ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1115ca632f55SGrant Likely dma_cap_zero(mask); 1116ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1117ca632f55SGrant Likely /* 1118ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1119ca632f55SGrant Likely * of them. 1120ca632f55SGrant Likely */ 1121ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1122ca632f55SGrant Likely pl022->master_info->dma_filter, 1123ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1124ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1125ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1126ca632f55SGrant Likely goto err_no_rxchan; 1127ca632f55SGrant Likely } 1128ca632f55SGrant Likely 1129ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1130ca632f55SGrant Likely pl022->master_info->dma_filter, 1131ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1132ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1133ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1134ca632f55SGrant Likely goto err_no_txchan; 1135ca632f55SGrant Likely } 1136ca632f55SGrant Likely 1137ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 113877538f4aSJingoo Han if (!pl022->dummypage) 1139ca632f55SGrant Likely goto err_no_dummypage; 1140ca632f55SGrant Likely 1141ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1142ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1143ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1144ca632f55SGrant Likely 1145ca632f55SGrant Likely return 0; 1146ca632f55SGrant Likely 1147ca632f55SGrant Likely err_no_dummypage: 1148ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1149ca632f55SGrant Likely err_no_txchan: 1150ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1151ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1152ca632f55SGrant Likely err_no_rxchan: 1153ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1154ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1155ca632f55SGrant Likely return -ENODEV; 1156ca632f55SGrant Likely } 1157ca632f55SGrant Likely 1158dc715452SArnd Bergmann static int pl022_dma_autoprobe(struct pl022 *pl022) 1159dc715452SArnd Bergmann { 1160dc715452SArnd Bergmann struct device *dev = &pl022->adev->dev; 1161f3d4bb33SRabin Vincent struct dma_chan *chan; 1162f3d4bb33SRabin Vincent int err; 1163dc715452SArnd Bergmann 1164dc715452SArnd Bergmann /* automatically configure DMA channels from platform, normally using DT */ 1165c1008957SPeter Ujfalusi chan = dma_request_chan(dev, "rx"); 1166f3d4bb33SRabin Vincent if (IS_ERR(chan)) { 1167f3d4bb33SRabin Vincent err = PTR_ERR(chan); 1168dc715452SArnd Bergmann goto err_no_rxchan; 1169f3d4bb33SRabin Vincent } 1170dc715452SArnd Bergmann 1171f3d4bb33SRabin Vincent pl022->dma_rx_channel = chan; 1172f3d4bb33SRabin Vincent 1173c1008957SPeter Ujfalusi chan = dma_request_chan(dev, "tx"); 1174f3d4bb33SRabin Vincent if (IS_ERR(chan)) { 1175f3d4bb33SRabin Vincent err = PTR_ERR(chan); 1176dc715452SArnd Bergmann goto err_no_txchan; 1177f3d4bb33SRabin Vincent } 1178f3d4bb33SRabin Vincent 1179f3d4bb33SRabin Vincent pl022->dma_tx_channel = chan; 1180dc715452SArnd Bergmann 1181dc715452SArnd Bergmann pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1182f3d4bb33SRabin Vincent if (!pl022->dummypage) { 1183f3d4bb33SRabin Vincent err = -ENOMEM; 1184dc715452SArnd Bergmann goto err_no_dummypage; 1185f3d4bb33SRabin Vincent } 1186dc715452SArnd Bergmann 1187dc715452SArnd Bergmann return 0; 1188dc715452SArnd Bergmann 1189dc715452SArnd Bergmann err_no_dummypage: 1190dc715452SArnd Bergmann dma_release_channel(pl022->dma_tx_channel); 1191dc715452SArnd Bergmann pl022->dma_tx_channel = NULL; 1192dc715452SArnd Bergmann err_no_txchan: 1193dc715452SArnd Bergmann dma_release_channel(pl022->dma_rx_channel); 1194dc715452SArnd Bergmann pl022->dma_rx_channel = NULL; 1195dc715452SArnd Bergmann err_no_rxchan: 1196f3d4bb33SRabin Vincent return err; 1197dc715452SArnd Bergmann } 1198dc715452SArnd Bergmann 1199ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1200ca632f55SGrant Likely { 1201ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1202ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1203ca632f55SGrant Likely 1204ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1205ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1206ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1207ffbbdd21SLinus Walleij pl022->dma_running = false; 1208ca632f55SGrant Likely } 1209ca632f55SGrant Likely 1210ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1211ca632f55SGrant Likely { 1212ffbbdd21SLinus Walleij if (pl022->dma_running) 1213ca632f55SGrant Likely terminate_dma(pl022); 1214ca632f55SGrant Likely if (pl022->dma_tx_channel) 1215ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1216ca632f55SGrant Likely if (pl022->dma_rx_channel) 1217ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1218ca632f55SGrant Likely kfree(pl022->dummypage); 1219ca632f55SGrant Likely } 1220ca632f55SGrant Likely 1221ca632f55SGrant Likely #else 1222ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1223ca632f55SGrant Likely { 1224ca632f55SGrant Likely return -ENODEV; 1225ca632f55SGrant Likely } 1226ca632f55SGrant Likely 1227dc715452SArnd Bergmann static inline int pl022_dma_autoprobe(struct pl022 *pl022) 1228dc715452SArnd Bergmann { 1229dc715452SArnd Bergmann return 0; 1230dc715452SArnd Bergmann } 1231dc715452SArnd Bergmann 1232ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1233ca632f55SGrant Likely { 1234ca632f55SGrant Likely return 0; 1235ca632f55SGrant Likely } 1236ca632f55SGrant Likely 1237ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1238ca632f55SGrant Likely { 1239ca632f55SGrant Likely } 1240ca632f55SGrant Likely #endif 1241ca632f55SGrant Likely 1242ca632f55SGrant Likely /** 1243ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1244*c7cd1dfbSLee Jones * @irq: IRQ number 1245*c7cd1dfbSLee Jones * @dev_id: Local device data 1246ca632f55SGrant Likely * 1247ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1248ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1249ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1250ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1251ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1252ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1253ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1254ca632f55SGrant Likely */ 1255ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1256ca632f55SGrant Likely { 1257ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1258ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1259ca632f55SGrant Likely u16 irq_status = 0; 1260ca632f55SGrant Likely 1261ca632f55SGrant Likely if (unlikely(!msg)) { 1262ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1263ca632f55SGrant Likely "bad message state in interrupt handler"); 1264ca632f55SGrant Likely /* Never fail */ 1265ca632f55SGrant Likely return IRQ_HANDLED; 1266ca632f55SGrant Likely } 1267ca632f55SGrant Likely 1268ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1269ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1270ca632f55SGrant Likely 1271ca632f55SGrant Likely if (unlikely(!irq_status)) 1272ca632f55SGrant Likely return IRQ_NONE; 1273ca632f55SGrant Likely 1274ca632f55SGrant Likely /* 1275ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1276ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1277ca632f55SGrant Likely * trusted. 1278ca632f55SGrant Likely */ 1279ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1280ca632f55SGrant Likely /* 1281ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1282ca632f55SGrant Likely * corrupted 1283ca632f55SGrant Likely */ 1284ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1285ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1286ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1287ca632f55SGrant Likely "RXFIFO is full\n"); 1288ca632f55SGrant Likely 1289ca632f55SGrant Likely /* 1290ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1291ca632f55SGrant Likely * mark message with bad status so it can be 1292ca632f55SGrant Likely * retried. 1293ca632f55SGrant Likely */ 1294ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1295ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1296ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1297ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1298ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1299ca632f55SGrant Likely msg->state = STATE_ERROR; 1300ca632f55SGrant Likely 1301ca632f55SGrant Likely /* Schedule message queue handler */ 1302ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1303ca632f55SGrant Likely return IRQ_HANDLED; 1304ca632f55SGrant Likely } 1305ca632f55SGrant Likely 1306ca632f55SGrant Likely readwriter(pl022); 1307ca632f55SGrant Likely 13087183d1ebSAlexander Sverdlin if (pl022->tx == pl022->tx_end) { 1309172289dfSChris Blair /* Disable Transmit interrupt, enable receive interrupt */ 1310172289dfSChris Blair writew((readw(SSP_IMSC(pl022->virtbase)) & 1311172289dfSChris Blair ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1312ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1313ca632f55SGrant Likely } 1314ca632f55SGrant Likely 1315ca632f55SGrant Likely /* 1316ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1317ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1318ca632f55SGrant Likely * At this point, all TX will always be finished. 1319ca632f55SGrant Likely */ 1320ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1321ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1322ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1323ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1324ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1325ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1326ca632f55SGrant Likely "bytes (did you request an odd " 1327ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1328ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1329ca632f55SGrant Likely } 1330ca632f55SGrant Likely /* Update total bytes transferred */ 1331ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1332ca632f55SGrant Likely /* Move to next transfer */ 1333ca632f55SGrant Likely msg->state = next_transfer(pl022); 1334c0b07605SFredrik Ternerot if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) 1335c0b07605SFredrik Ternerot pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1336ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1337ca632f55SGrant Likely return IRQ_HANDLED; 1338ca632f55SGrant Likely } 1339ca632f55SGrant Likely 1340ca632f55SGrant Likely return IRQ_HANDLED; 1341ca632f55SGrant Likely } 1342ca632f55SGrant Likely 1343*c7cd1dfbSLee Jones /* 1344ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1345ca632f55SGrant Likely * send out on the SPI bus. 1346ca632f55SGrant Likely */ 1347ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1348ca632f55SGrant Likely struct spi_transfer *transfer) 1349ca632f55SGrant Likely { 1350ca632f55SGrant Likely int residue; 1351ca632f55SGrant Likely 1352ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1353ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1354ca632f55SGrant Likely if (unlikely(residue != 0)) { 1355ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1356ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1357ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1358ca632f55SGrant Likely pl022->cur_transfer->len, 1359ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1360ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1361ca632f55SGrant Likely return -EIO; 1362ca632f55SGrant Likely } 1363ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1364ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1365ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1366ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1367ca632f55SGrant Likely pl022->write = 1368ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1369ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1370ca632f55SGrant Likely return 0; 1371ca632f55SGrant Likely } 1372ca632f55SGrant Likely 1373ca632f55SGrant Likely /** 1374ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1375ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1376ca632f55SGrant Likely * @data: SSP driver private data structure 1377ca632f55SGrant Likely * 1378ca632f55SGrant Likely */ 1379ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1380ca632f55SGrant Likely { 1381ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1382ca632f55SGrant Likely struct spi_message *message = NULL; 1383ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1384ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1385ca632f55SGrant Likely 1386ca632f55SGrant Likely /* Get current state information */ 1387ca632f55SGrant Likely message = pl022->cur_msg; 1388ca632f55SGrant Likely transfer = pl022->cur_transfer; 1389ca632f55SGrant Likely 1390ca632f55SGrant Likely /* Handle for abort */ 1391ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1392ca632f55SGrant Likely message->status = -EIO; 1393ca632f55SGrant Likely giveback(pl022); 1394ca632f55SGrant Likely return; 1395ca632f55SGrant Likely } 1396ca632f55SGrant Likely 1397ca632f55SGrant Likely /* Handle end of message */ 1398ca632f55SGrant Likely if (message->state == STATE_DONE) { 1399ca632f55SGrant Likely message->status = 0; 1400ca632f55SGrant Likely giveback(pl022); 1401ca632f55SGrant Likely return; 1402ca632f55SGrant Likely } 1403ca632f55SGrant Likely 1404ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1405ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1406ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1407ca632f55SGrant Likely struct spi_transfer, 1408ca632f55SGrant Likely transfer_list); 1409ca632f55SGrant Likely /* 1410ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1411ca632f55SGrant Likely * Is this really smart? 1412ca632f55SGrant Likely */ 1413e74dc5c7SAlexandru Ardelean spi_transfer_delay_exec(previous); 1414ca632f55SGrant Likely 14158b8d7191SVirupax Sadashivpetimath /* Reselect chip select only if cs_change was requested */ 1416ca632f55SGrant Likely if (previous->cs_change) 1417f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1418ca632f55SGrant Likely } else { 1419ca632f55SGrant Likely /* STATE_START */ 1420ca632f55SGrant Likely message->state = STATE_RUNNING; 1421ca632f55SGrant Likely } 1422ca632f55SGrant Likely 1423ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1424ca632f55SGrant Likely message->state = STATE_ERROR; 1425ca632f55SGrant Likely message->status = -EIO; 1426ca632f55SGrant Likely giveback(pl022); 1427ca632f55SGrant Likely return; 1428ca632f55SGrant Likely } 1429ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1430ca632f55SGrant Likely flush(pl022); 1431ca632f55SGrant Likely 1432ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1433ca632f55SGrant Likely if (configure_dma(pl022)) { 1434ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1435ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1436ca632f55SGrant Likely goto err_config_dma; 1437ca632f55SGrant Likely } 1438ca632f55SGrant Likely return; 1439ca632f55SGrant Likely } 1440ca632f55SGrant Likely 1441ca632f55SGrant Likely err_config_dma: 1442172289dfSChris Blair /* enable all interrupts except RX */ 1443172289dfSChris Blair writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1444ca632f55SGrant Likely } 1445ca632f55SGrant Likely 1446ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1447ca632f55SGrant Likely { 1448172289dfSChris Blair /* 1449172289dfSChris Blair * Default is to enable all interrupts except RX - 1450172289dfSChris Blair * this will be enabled once TX is complete 1451172289dfSChris Blair */ 1452d555ea05SMark Brown u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); 1453ca632f55SGrant Likely 14548b8d7191SVirupax Sadashivpetimath /* Enable target chip, if not already active */ 14558b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1456f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 14578b8d7191SVirupax Sadashivpetimath 1458ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1459ca632f55SGrant Likely /* Error path */ 1460ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1461ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1462ca632f55SGrant Likely giveback(pl022); 1463ca632f55SGrant Likely return; 1464ca632f55SGrant Likely } 1465ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1466ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1467ca632f55SGrant Likely /* Configure DMA transfer */ 1468ca632f55SGrant Likely if (configure_dma(pl022)) { 1469ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1470ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1471ca632f55SGrant Likely goto err_config_dma; 1472ca632f55SGrant Likely } 1473ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1474ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1475ca632f55SGrant Likely } 1476ca632f55SGrant Likely err_config_dma: 1477ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1478ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1479ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1480ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1481ca632f55SGrant Likely } 1482ca632f55SGrant Likely 14837aef2b64SJiwei Sun static void print_current_status(struct pl022 *pl022) 14847aef2b64SJiwei Sun { 14857aef2b64SJiwei Sun u32 read_cr0; 14867aef2b64SJiwei Sun u16 read_cr1, read_dmacr, read_sr; 14877aef2b64SJiwei Sun 14887aef2b64SJiwei Sun if (pl022->vendor->extended_cr) 14897aef2b64SJiwei Sun read_cr0 = readl(SSP_CR0(pl022->virtbase)); 14907aef2b64SJiwei Sun else 14917aef2b64SJiwei Sun read_cr0 = readw(SSP_CR0(pl022->virtbase)); 14927aef2b64SJiwei Sun read_cr1 = readw(SSP_CR1(pl022->virtbase)); 14937aef2b64SJiwei Sun read_dmacr = readw(SSP_DMACR(pl022->virtbase)); 14947aef2b64SJiwei Sun read_sr = readw(SSP_SR(pl022->virtbase)); 14957aef2b64SJiwei Sun 14967aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); 14977aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); 14987aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); 14997aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); 15007aef2b64SJiwei Sun dev_warn(&pl022->adev->dev, 15017aef2b64SJiwei Sun "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", 15027aef2b64SJiwei Sun pl022->exp_fifo_level, 15037aef2b64SJiwei Sun pl022->vendor->fifodepth); 15047aef2b64SJiwei Sun 15057aef2b64SJiwei Sun } 15067aef2b64SJiwei Sun 1507ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1508ca632f55SGrant Likely { 1509ca632f55SGrant Likely struct spi_message *message = NULL; 1510ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1511ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1512ca632f55SGrant Likely unsigned long time, timeout; 1513ca632f55SGrant Likely 1514ca632f55SGrant Likely message = pl022->cur_msg; 1515ca632f55SGrant Likely 1516ca632f55SGrant Likely while (message->state != STATE_DONE) { 1517ca632f55SGrant Likely /* Handle for abort */ 1518ca632f55SGrant Likely if (message->state == STATE_ERROR) 1519ca632f55SGrant Likely break; 1520ca632f55SGrant Likely transfer = pl022->cur_transfer; 1521ca632f55SGrant Likely 1522ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1523ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1524ca632f55SGrant Likely previous = 1525ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1526ca632f55SGrant Likely struct spi_transfer, transfer_list); 1527e74dc5c7SAlexandru Ardelean spi_transfer_delay_exec(previous); 1528ca632f55SGrant Likely if (previous->cs_change) 1529f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1530ca632f55SGrant Likely } else { 1531ca632f55SGrant Likely /* STATE_START */ 1532ca632f55SGrant Likely message->state = STATE_RUNNING; 15338b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1534f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1535ca632f55SGrant Likely } 1536ca632f55SGrant Likely 1537ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1538ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1539ca632f55SGrant Likely /* Error path */ 1540ca632f55SGrant Likely message->state = STATE_ERROR; 1541ca632f55SGrant Likely break; 1542ca632f55SGrant Likely } 1543ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1544ca632f55SGrant Likely flush(pl022); 1545ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1546ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1547ca632f55SGrant Likely 1548ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1549ca632f55SGrant Likely 1550ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1551ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1552ca632f55SGrant Likely time = jiffies; 1553ca632f55SGrant Likely readwriter(pl022); 1554ca632f55SGrant Likely if (time_after(time, timeout)) { 1555ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1556ca632f55SGrant Likely "%s: timeout!\n", __func__); 15577aef2b64SJiwei Sun message->state = STATE_TIMEOUT; 15587aef2b64SJiwei Sun print_current_status(pl022); 1559ca632f55SGrant Likely goto out; 1560ca632f55SGrant Likely } 1561ca632f55SGrant Likely cpu_relax(); 1562ca632f55SGrant Likely } 1563ca632f55SGrant Likely 1564ca632f55SGrant Likely /* Update total byte transferred */ 1565ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1566ca632f55SGrant Likely /* Move to next transfer */ 1567ca632f55SGrant Likely message->state = next_transfer(pl022); 1568c0b07605SFredrik Ternerot if (message->state != STATE_DONE 1569c0b07605SFredrik Ternerot && pl022->cur_transfer->cs_change) 1570c0b07605SFredrik Ternerot pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1571ca632f55SGrant Likely } 1572ca632f55SGrant Likely out: 1573ca632f55SGrant Likely /* Handle end of message */ 1574ca632f55SGrant Likely if (message->state == STATE_DONE) 1575ca632f55SGrant Likely message->status = 0; 15767aef2b64SJiwei Sun else if (message->state == STATE_TIMEOUT) 15777aef2b64SJiwei Sun message->status = -EAGAIN; 1578ca632f55SGrant Likely else 1579ca632f55SGrant Likely message->status = -EIO; 1580ca632f55SGrant Likely 1581ca632f55SGrant Likely giveback(pl022); 1582ca632f55SGrant Likely return; 1583ca632f55SGrant Likely } 1584ca632f55SGrant Likely 1585ffbbdd21SLinus Walleij static int pl022_transfer_one_message(struct spi_master *master, 1586ffbbdd21SLinus Walleij struct spi_message *msg) 1587ca632f55SGrant Likely { 1588ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1589ca632f55SGrant Likely 1590ffbbdd21SLinus Walleij /* Initial message state */ 1591ffbbdd21SLinus Walleij pl022->cur_msg = msg; 1592ffbbdd21SLinus Walleij msg->state = STATE_START; 1593ffbbdd21SLinus Walleij 1594ffbbdd21SLinus Walleij pl022->cur_transfer = list_entry(msg->transfers.next, 1595ffbbdd21SLinus Walleij struct spi_transfer, transfer_list); 1596ffbbdd21SLinus Walleij 1597ffbbdd21SLinus Walleij /* Setup the SPI using the per chip configuration */ 1598ffbbdd21SLinus Walleij pl022->cur_chip = spi_get_ctldata(msg->spi); 1599f6f46de1SRoland Stigge pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1600ffbbdd21SLinus Walleij 1601ffbbdd21SLinus Walleij restore_state(pl022); 1602ffbbdd21SLinus Walleij flush(pl022); 1603ffbbdd21SLinus Walleij 1604ffbbdd21SLinus Walleij if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1605ffbbdd21SLinus Walleij do_polling_transfer(pl022); 1606ffbbdd21SLinus Walleij else 1607ffbbdd21SLinus Walleij do_interrupt_dma_transfer(pl022); 1608ffbbdd21SLinus Walleij 1609ffbbdd21SLinus Walleij return 0; 1610ffbbdd21SLinus Walleij } 1611ffbbdd21SLinus Walleij 1612ffbbdd21SLinus Walleij static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1613ffbbdd21SLinus Walleij { 1614ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1615ffbbdd21SLinus Walleij 16160ad2deeaSVirupax Sadashivpetimath /* nothing more to do - disable spi/ssp and power off */ 16170ad2deeaSVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 16180ad2deeaSVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 161953e4aceaSChris Blair 1620ca632f55SGrant Likely return 0; 1621ca632f55SGrant Likely } 1622ca632f55SGrant Likely 1623ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1624ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1625ca632f55SGrant Likely { 1626ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1627ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1628ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1629ca632f55SGrant Likely "interface is configured incorrectly\n"); 1630ca632f55SGrant Likely return -EINVAL; 1631ca632f55SGrant Likely } 1632ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1633ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1634ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1635ca632f55SGrant Likely "unidirectional mode not supported in this " 1636ca632f55SGrant Likely "hardware version\n"); 1637ca632f55SGrant Likely return -EINVAL; 1638ca632f55SGrant Likely } 1639ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1640ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1641ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1642ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1643ca632f55SGrant Likely return -EINVAL; 1644ca632f55SGrant Likely } 1645ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1646ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1647ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1648ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1649ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1650ca632f55SGrant Likely return -EINVAL; 1651ca632f55SGrant Likely } 165278b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 165378b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 165478b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 165578b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 165678b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 165778b2b911SLinus Walleij break; 165878b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 165978b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1660ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1661ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1662ca632f55SGrant Likely return -EINVAL; 1663ca632f55SGrant Likely } 166478b2b911SLinus Walleij break; 166578b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 166678b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 166778b2b911SLinus Walleij dev_err(&pl022->adev->dev, 166878b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 166978b2b911SLinus Walleij return -EINVAL; 167078b2b911SLinus Walleij } 167178b2b911SLinus Walleij break; 167278b2b911SLinus Walleij default: 167378b2b911SLinus Walleij dev_err(&pl022->adev->dev, 167478b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 167578b2b911SLinus Walleij return -EINVAL; 167678b2b911SLinus Walleij } 167778b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 167878b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 167978b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 168078b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 168178b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 168278b2b911SLinus Walleij break; 168378b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 168478b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1685ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1686ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1687ca632f55SGrant Likely return -EINVAL; 1688ca632f55SGrant Likely } 168978b2b911SLinus Walleij break; 169078b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 169178b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 169278b2b911SLinus Walleij dev_err(&pl022->adev->dev, 169378b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 169478b2b911SLinus Walleij return -EINVAL; 169578b2b911SLinus Walleij } 169678b2b911SLinus Walleij break; 169778b2b911SLinus Walleij default: 169878b2b911SLinus Walleij dev_err(&pl022->adev->dev, 169978b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 170078b2b911SLinus Walleij return -EINVAL; 170178b2b911SLinus Walleij } 1702ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1703ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1704ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1705ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1706ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1707ca632f55SGrant Likely return -EINVAL; 1708ca632f55SGrant Likely } 1709ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1710ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1711ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1712ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1713ca632f55SGrant Likely return -EINVAL; 1714ca632f55SGrant Likely } 1715ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1716ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1717ca632f55SGrant Likely if ((chip_info->duplex != 1718ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1719ca632f55SGrant Likely && (chip_info->duplex != 1720ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1721ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1722ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1723ca632f55SGrant Likely return -EINVAL; 1724ca632f55SGrant Likely } 1725ca632f55SGrant Likely } else { 1726ca632f55SGrant Likely if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1727ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1728ca632f55SGrant Likely "Microwire half duplex mode requested," 1729ca632f55SGrant Likely " but this is only available in the" 1730ca632f55SGrant Likely " ST version of PL022\n"); 1731ca632f55SGrant Likely return -EINVAL; 1732ca632f55SGrant Likely } 1733ca632f55SGrant Likely } 1734ca632f55SGrant Likely return 0; 1735ca632f55SGrant Likely } 1736ca632f55SGrant Likely 17370379b2a3SViresh Kumar static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 17380379b2a3SViresh Kumar { 17390379b2a3SViresh Kumar return rate / (cpsdvsr * (1 + scr)); 17400379b2a3SViresh Kumar } 17410379b2a3SViresh Kumar 17420379b2a3SViresh Kumar static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 17430379b2a3SViresh Kumar ssp_clock_params * clk_freq) 1744ca632f55SGrant Likely { 1745ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 17460379b2a3SViresh Kumar u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 17470379b2a3SViresh Kumar u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 17480379b2a3SViresh Kumar best_scr = 0, tmp, found = 0; 1749ca632f55SGrant Likely 1750ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1751ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 17520379b2a3SViresh Kumar max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1753ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 17540379b2a3SViresh Kumar min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1755ca632f55SGrant Likely 1756ea505bc9SViresh Kumar if (freq > max_tclk) 1757ea505bc9SViresh Kumar dev_warn(&pl022->adev->dev, 1758ea505bc9SViresh Kumar "Max speed that can be programmed is %d Hz, you requested %d\n", 1759ea505bc9SViresh Kumar max_tclk, freq); 1760ea505bc9SViresh Kumar 1761ea505bc9SViresh Kumar if (freq < min_tclk) { 1762ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1763ea505bc9SViresh Kumar "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1764ea505bc9SViresh Kumar freq, min_tclk); 1765ca632f55SGrant Likely return -EINVAL; 1766ca632f55SGrant Likely } 17670379b2a3SViresh Kumar 17680379b2a3SViresh Kumar /* 17690379b2a3SViresh Kumar * best_freq will give closest possible available rate (<= requested 17700379b2a3SViresh Kumar * freq) for all values of scr & cpsdvsr. 17710379b2a3SViresh Kumar */ 17720379b2a3SViresh Kumar while ((cpsdvsr <= CPSDVR_MAX) && !found) { 17730379b2a3SViresh Kumar while (scr <= SCR_MAX) { 17740379b2a3SViresh Kumar tmp = spi_rate(rate, cpsdvsr, scr); 17750379b2a3SViresh Kumar 17765eb806a3SViresh Kumar if (tmp > freq) { 17775eb806a3SViresh Kumar /* we need lower freq */ 17780379b2a3SViresh Kumar scr++; 17795eb806a3SViresh Kumar continue; 17805eb806a3SViresh Kumar } 17815eb806a3SViresh Kumar 17820379b2a3SViresh Kumar /* 17835eb806a3SViresh Kumar * If found exact value, mark found and break. 17845eb806a3SViresh Kumar * If found more closer value, update and break. 17850379b2a3SViresh Kumar */ 17865eb806a3SViresh Kumar if (tmp > best_freq) { 17870379b2a3SViresh Kumar best_freq = tmp; 17880379b2a3SViresh Kumar best_cpsdvsr = cpsdvsr; 17890379b2a3SViresh Kumar best_scr = scr; 17900379b2a3SViresh Kumar 17910379b2a3SViresh Kumar if (tmp == freq) 17925eb806a3SViresh Kumar found = 1; 17930379b2a3SViresh Kumar } 17945eb806a3SViresh Kumar /* 17955eb806a3SViresh Kumar * increased scr will give lower rates, which are not 17965eb806a3SViresh Kumar * required 17975eb806a3SViresh Kumar */ 17985eb806a3SViresh Kumar break; 17990379b2a3SViresh Kumar } 18000379b2a3SViresh Kumar cpsdvsr += 2; 18010379b2a3SViresh Kumar scr = SCR_MIN; 1802ca632f55SGrant Likely } 1803ca632f55SGrant Likely 18045eb806a3SViresh Kumar WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 18055eb806a3SViresh Kumar freq); 18065eb806a3SViresh Kumar 18070379b2a3SViresh Kumar clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 18080379b2a3SViresh Kumar clk_freq->scr = (u8) (best_scr & 0xFF); 18090379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, 18100379b2a3SViresh Kumar "SSP Target Frequency is: %u, Effective Frequency is %u\n", 18110379b2a3SViresh Kumar freq, best_freq); 18120379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 18130379b2a3SViresh Kumar clk_freq->cpsdvsr, clk_freq->scr); 18140379b2a3SViresh Kumar 1815ca632f55SGrant Likely return 0; 1816ca632f55SGrant Likely } 1817ca632f55SGrant Likely 1818ca632f55SGrant Likely /* 1819ca632f55SGrant Likely * A piece of default chip info unless the platform 1820ca632f55SGrant Likely * supplies it. 1821ca632f55SGrant Likely */ 1822ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1823ca632f55SGrant Likely .com_mode = POLLING_TRANSFER, 1824ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1825ca632f55SGrant Likely .hierarchy = SSP_SLAVE, 1826ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1827ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1828ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1829ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1830ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1831ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1832ca632f55SGrant Likely .cs_control = null_cs_control, 1833ca632f55SGrant Likely }; 1834ca632f55SGrant Likely 1835ca632f55SGrant Likely /** 1836ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1837ca632f55SGrant Likely * @spi: spi device which is requesting setup 1838ca632f55SGrant Likely * 1839ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1840ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1841ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1842ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1843ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1844ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1845ca632f55SGrant Likely * commence. 1846ca632f55SGrant Likely */ 1847ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1848ca632f55SGrant Likely { 1849ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 18506d3952a7SRoland Stigge struct pl022_config_chip chip_info_dt; 1851ca632f55SGrant Likely struct chip_data *chip; 1852c4a47843SJonas Aaberg struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1853ca632f55SGrant Likely int status = 0; 1854ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1855ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1856ca632f55SGrant Likely u32 tmp; 18576d3952a7SRoland Stigge struct device_node *np = spi->dev.of_node; 1858ca632f55SGrant Likely 1859ca632f55SGrant Likely if (!spi->max_speed_hz) 1860ca632f55SGrant Likely return -EINVAL; 1861ca632f55SGrant Likely 1862ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1863ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1864ca632f55SGrant Likely 1865ca632f55SGrant Likely if (chip == NULL) { 1866ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 186777538f4aSJingoo Han if (!chip) 1868ca632f55SGrant Likely return -ENOMEM; 1869ca632f55SGrant Likely dev_dbg(&spi->dev, 1870ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1871ca632f55SGrant Likely } 1872ca632f55SGrant Likely 1873ca632f55SGrant Likely /* Get controller data if one is supplied */ 1874ca632f55SGrant Likely chip_info = spi->controller_data; 1875ca632f55SGrant Likely 1876ca632f55SGrant Likely if (chip_info == NULL) { 18776d3952a7SRoland Stigge if (np) { 18786d3952a7SRoland Stigge chip_info_dt = pl022_default_chip_info; 18796d3952a7SRoland Stigge 18806d3952a7SRoland Stigge chip_info_dt.hierarchy = SSP_MASTER; 18816d3952a7SRoland Stigge of_property_read_u32(np, "pl022,interface", 18826d3952a7SRoland Stigge &chip_info_dt.iface); 18836d3952a7SRoland Stigge of_property_read_u32(np, "pl022,com-mode", 18846d3952a7SRoland Stigge &chip_info_dt.com_mode); 18856d3952a7SRoland Stigge of_property_read_u32(np, "pl022,rx-level-trig", 18866d3952a7SRoland Stigge &chip_info_dt.rx_lev_trig); 18876d3952a7SRoland Stigge of_property_read_u32(np, "pl022,tx-level-trig", 18886d3952a7SRoland Stigge &chip_info_dt.tx_lev_trig); 18896d3952a7SRoland Stigge of_property_read_u32(np, "pl022,ctrl-len", 18906d3952a7SRoland Stigge &chip_info_dt.ctrl_len); 18916d3952a7SRoland Stigge of_property_read_u32(np, "pl022,wait-state", 18926d3952a7SRoland Stigge &chip_info_dt.wait_state); 18936d3952a7SRoland Stigge of_property_read_u32(np, "pl022,duplex", 18946d3952a7SRoland Stigge &chip_info_dt.duplex); 18956d3952a7SRoland Stigge 18966d3952a7SRoland Stigge chip_info = &chip_info_dt; 18976d3952a7SRoland Stigge } else { 1898ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1899ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1900ca632f55SGrant Likely dev_dbg(&spi->dev, 1901ca632f55SGrant Likely "using default controller_data settings\n"); 19026d3952a7SRoland Stigge } 1903ca632f55SGrant Likely } else 1904ca632f55SGrant Likely dev_dbg(&spi->dev, 1905ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1906ca632f55SGrant Likely 1907ca632f55SGrant Likely /* 1908ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1909ca632f55SGrant Likely * frequency setting 1910ca632f55SGrant Likely */ 1911ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1912ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1913ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1914ca632f55SGrant Likely spi->max_speed_hz, 1915ca632f55SGrant Likely &clk_freq); 1916ca632f55SGrant Likely if (status < 0) 1917ca632f55SGrant Likely goto err_config_params; 1918ca632f55SGrant Likely } else { 1919ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1920ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1921ca632f55SGrant Likely clk_freq.cpsdvsr = 1922ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1923ca632f55SGrant Likely } 1924ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1925ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1926f8db4cc4SGrant Likely status = -EINVAL; 1927ca632f55SGrant Likely dev_err(&spi->dev, 1928ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1929ca632f55SGrant Likely goto err_config_params; 1930ca632f55SGrant Likely } 1931ca632f55SGrant Likely 1932ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1933ca632f55SGrant Likely if (status) { 1934ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1935ca632f55SGrant Likely goto err_config_params; 1936ca632f55SGrant Likely } 1937ca632f55SGrant Likely 1938083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1939083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1940083be3f0SLinus Walleij 1941ca632f55SGrant Likely /* Now set controller state based on controller data */ 1942ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1943ca632f55SGrant Likely if (!chip_info->cs_control) { 1944ca632f55SGrant Likely chip->cs_control = null_cs_control; 1945f6f46de1SRoland Stigge if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1946ca632f55SGrant Likely dev_warn(&spi->dev, 1947f6f46de1SRoland Stigge "invalid chip select\n"); 1948ca632f55SGrant Likely } else 1949ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1950ca632f55SGrant Likely 1951eb798c64SVinit Shenoy /* Check bits per word with vendor specific range */ 1952eb798c64SVinit Shenoy if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1953ca632f55SGrant Likely status = -ENOTSUPP; 1954eb798c64SVinit Shenoy dev_err(&spi->dev, "illegal data size for this controller!\n"); 1955eb798c64SVinit Shenoy dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1956eb798c64SVinit Shenoy pl022->vendor->max_bpw); 1957ca632f55SGrant Likely goto err_config_params; 1958ca632f55SGrant Likely } else if (bits <= 8) { 1959ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1960ca632f55SGrant Likely chip->n_bytes = 1; 1961ca632f55SGrant Likely chip->read = READING_U8; 1962ca632f55SGrant Likely chip->write = WRITING_U8; 1963ca632f55SGrant Likely } else if (bits <= 16) { 1964ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1965ca632f55SGrant Likely chip->n_bytes = 2; 1966ca632f55SGrant Likely chip->read = READING_U16; 1967ca632f55SGrant Likely chip->write = WRITING_U16; 1968ca632f55SGrant Likely } else { 1969ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1970ca632f55SGrant Likely chip->n_bytes = 4; 1971ca632f55SGrant Likely chip->read = READING_U32; 1972ca632f55SGrant Likely chip->write = WRITING_U32; 1973ca632f55SGrant Likely } 1974ca632f55SGrant Likely 1975ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 1976ca632f55SGrant Likely chip->cr0 = 0; 1977ca632f55SGrant Likely chip->cr1 = 0; 1978ca632f55SGrant Likely chip->dmacr = 0; 1979ca632f55SGrant Likely chip->cpsr = 0; 1980ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 1981ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 1982ca632f55SGrant Likely chip->enable_dma = true; 1983ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1984ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1985ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1986ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1987ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1988ca632f55SGrant Likely } else { 1989ca632f55SGrant Likely chip->enable_dma = false; 1990ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1991ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1992ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1993ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1994ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1995ca632f55SGrant Likely } 1996ca632f55SGrant Likely 1997ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 1998ca632f55SGrant Likely 1999ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 2000ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 2001ca632f55SGrant Likely u32 etx; 2002ca632f55SGrant Likely 2003ca632f55SGrant Likely if (pl022->vendor->pl023) { 2004ca632f55SGrant Likely /* These bits are only in the PL023 */ 2005ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2006ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 2007ca632f55SGrant Likely } else { 2008ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 2009ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2010ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 2011ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2012ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 2013ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2014ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 2015ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2016ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 2017ca632f55SGrant Likely } 2018ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2019ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 2020ca632f55SGrant Likely 2021ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 2022ca632f55SGrant Likely tmp = SSP_RX_LSB; 2023ca632f55SGrant Likely etx = SSP_TX_LSB; 2024ca632f55SGrant Likely } else { 2025ca632f55SGrant Likely tmp = SSP_RX_MSB; 2026ca632f55SGrant Likely etx = SSP_TX_MSB; 2027ca632f55SGrant Likely } 2028ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2029ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2030ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2031ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 2032ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2033ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 2034ca632f55SGrant Likely } else { 2035ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2036ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 2037ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2038ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 2039ca632f55SGrant Likely } 2040ca632f55SGrant Likely 2041ca632f55SGrant Likely /* Stuff that is common for all versions */ 2042ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 2043ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 2044ca632f55SGrant Likely else 2045ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 2046ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2047ca632f55SGrant Likely 2048ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 2049ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 2050ca632f55SGrant Likely else 2051ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 2052ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2053ca632f55SGrant Likely 2054ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2055ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 2056ca632f55SGrant Likely if (pl022->vendor->loopback) { 2057ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 2058ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 2059ca632f55SGrant Likely else 2060ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 2061ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2062ca632f55SGrant Likely } 2063ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2064ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2065f1e45f86SViresh Kumar SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2066f1e45f86SViresh Kumar 3); 2067ca632f55SGrant Likely 2068ca632f55SGrant Likely /* Save controller_state */ 2069ca632f55SGrant Likely spi_set_ctldata(spi, chip); 2070ca632f55SGrant Likely return status; 2071ca632f55SGrant Likely err_config_params: 2072ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2073ca632f55SGrant Likely kfree(chip); 2074ca632f55SGrant Likely return status; 2075ca632f55SGrant Likely } 2076ca632f55SGrant Likely 2077ca632f55SGrant Likely /** 2078ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 2079ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 2080ca632f55SGrant Likely * 2081ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 2082ca632f55SGrant Likely * controller. It will free the runtime state of chip. 2083ca632f55SGrant Likely */ 2084ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 2085ca632f55SGrant Likely { 2086ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 2087ca632f55SGrant Likely 2088ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2089ca632f55SGrant Likely kfree(chip); 2090ca632f55SGrant Likely } 2091ca632f55SGrant Likely 209239a6ac11SRoland Stigge static struct pl022_ssp_controller * 209339a6ac11SRoland Stigge pl022_platform_data_dt_get(struct device *dev) 209439a6ac11SRoland Stigge { 209539a6ac11SRoland Stigge struct device_node *np = dev->of_node; 209639a6ac11SRoland Stigge struct pl022_ssp_controller *pd; 2097849794c5SRabin Vincent u32 tmp = 0; 209839a6ac11SRoland Stigge 209939a6ac11SRoland Stigge if (!np) { 210039a6ac11SRoland Stigge dev_err(dev, "no dt node defined\n"); 210139a6ac11SRoland Stigge return NULL; 210239a6ac11SRoland Stigge } 210339a6ac11SRoland Stigge 210439a6ac11SRoland Stigge pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 210577538f4aSJingoo Han if (!pd) 210639a6ac11SRoland Stigge return NULL; 210739a6ac11SRoland Stigge 210839a6ac11SRoland Stigge pd->bus_id = -1; 2109dbd897b9SLinus Walleij pd->enable_dma = 1; 211039a6ac11SRoland Stigge of_property_read_u32(np, "num-cs", &tmp); 211139a6ac11SRoland Stigge pd->num_chipselect = tmp; 211239a6ac11SRoland Stigge of_property_read_u32(np, "pl022,autosuspend-delay", 211339a6ac11SRoland Stigge &pd->autosuspend_delay); 211439a6ac11SRoland Stigge pd->rt = of_property_read_bool(np, "pl022,rt"); 211539a6ac11SRoland Stigge 211639a6ac11SRoland Stigge return pd; 211739a6ac11SRoland Stigge } 211839a6ac11SRoland Stigge 2119fd4a319bSGrant Likely static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2120ca632f55SGrant Likely { 2121ca632f55SGrant Likely struct device *dev = &adev->dev; 21228074cf06SJingoo Han struct pl022_ssp_controller *platform_info = 21238074cf06SJingoo Han dev_get_platdata(&adev->dev); 2124ca632f55SGrant Likely struct spi_master *master; 2125ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 21266d3952a7SRoland Stigge struct device_node *np = adev->dev.of_node; 21276d3952a7SRoland Stigge int status = 0, i, num_cs; 2128ca632f55SGrant Likely 2129ca632f55SGrant Likely dev_info(&adev->dev, 2130ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 213139a6ac11SRoland Stigge if (!platform_info && IS_ENABLED(CONFIG_OF)) 213239a6ac11SRoland Stigge platform_info = pl022_platform_data_dt_get(dev); 213339a6ac11SRoland Stigge 213439a6ac11SRoland Stigge if (!platform_info) { 213539a6ac11SRoland Stigge dev_err(dev, "probe: no platform data defined\n"); 2136aeef9915SLinus Walleij return -ENODEV; 2137ca632f55SGrant Likely } 2138ca632f55SGrant Likely 21396d3952a7SRoland Stigge if (platform_info->num_chipselect) { 21406d3952a7SRoland Stigge num_cs = platform_info->num_chipselect; 21416d3952a7SRoland Stigge } else { 214239a6ac11SRoland Stigge dev_err(dev, "probe: no chip select defined\n"); 2143aeef9915SLinus Walleij return -ENODEV; 21446d3952a7SRoland Stigge } 21456d3952a7SRoland Stigge 2146ca632f55SGrant Likely /* Allocate master with space for data */ 2147b4b84826SRoland Stigge master = spi_alloc_master(dev, sizeof(struct pl022)); 2148ca632f55SGrant Likely if (master == NULL) { 2149ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2150aeef9915SLinus Walleij return -ENOMEM; 2151ca632f55SGrant Likely } 2152ca632f55SGrant Likely 2153ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 2154ca632f55SGrant Likely pl022->master = master; 2155ca632f55SGrant Likely pl022->master_info = platform_info; 2156ca632f55SGrant Likely pl022->adev = adev; 2157ca632f55SGrant Likely pl022->vendor = id->data; 2158a86854d0SKees Cook pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int), 2159b4b84826SRoland Stigge GFP_KERNEL); 216073e3f1ebSKiran Padwal if (!pl022->chipselects) { 216173e3f1ebSKiran Padwal status = -ENOMEM; 216273e3f1ebSKiran Padwal goto err_no_mem; 216373e3f1ebSKiran Padwal } 2164ca632f55SGrant Likely 2165ca632f55SGrant Likely /* 2166ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2167ca632f55SGrant Likely * on this board 2168ca632f55SGrant Likely */ 2169ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 21706d3952a7SRoland Stigge master->num_chipselect = num_cs; 2171ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2172ca632f55SGrant Likely master->setup = pl022_setup; 217329b6e906SMark Brown master->auto_runtime_pm = true; 2174ffbbdd21SLinus Walleij master->transfer_one_message = pl022_transfer_one_message; 2175ffbbdd21SLinus Walleij master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2176ffbbdd21SLinus Walleij master->rt = platform_info->rt; 21776d3952a7SRoland Stigge master->dev.of_node = dev->of_node; 2178ca632f55SGrant Likely 21796d3952a7SRoland Stigge if (platform_info->num_chipselect && platform_info->chipselects) { 21806d3952a7SRoland Stigge for (i = 0; i < num_cs; i++) 2181f6f46de1SRoland Stigge pl022->chipselects[i] = platform_info->chipselects[i]; 2182db4fa45eSAnders Berg } else if (pl022->vendor->internal_cs_ctrl) { 2183db4fa45eSAnders Berg for (i = 0; i < num_cs; i++) 2184db4fa45eSAnders Berg pl022->chipselects[i] = i; 21856d3952a7SRoland Stigge } else if (IS_ENABLED(CONFIG_OF)) { 21866d3952a7SRoland Stigge for (i = 0; i < num_cs; i++) { 21876d3952a7SRoland Stigge int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 21886d3952a7SRoland Stigge 21896d3952a7SRoland Stigge if (cs_gpio == -EPROBE_DEFER) { 21906d3952a7SRoland Stigge status = -EPROBE_DEFER; 21916d3952a7SRoland Stigge goto err_no_gpio; 21926d3952a7SRoland Stigge } 21936d3952a7SRoland Stigge 21946d3952a7SRoland Stigge pl022->chipselects[i] = cs_gpio; 21956d3952a7SRoland Stigge 21966d3952a7SRoland Stigge if (gpio_is_valid(cs_gpio)) { 2197aeef9915SLinus Walleij if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) 21986d3952a7SRoland Stigge dev_err(&adev->dev, 21996d3952a7SRoland Stigge "could not request %d gpio\n", 22006d3952a7SRoland Stigge cs_gpio); 22016d3952a7SRoland Stigge else if (gpio_direction_output(cs_gpio, 1)) 22026d3952a7SRoland Stigge dev_err(&adev->dev, 220361e89e65SRoland Stigge "could not set gpio %d as output\n", 22046d3952a7SRoland Stigge cs_gpio); 22056d3952a7SRoland Stigge } 22066d3952a7SRoland Stigge } 22076d3952a7SRoland Stigge } 2208f6f46de1SRoland Stigge 2209ca632f55SGrant Likely /* 2210ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2211ca632f55SGrant Likely * always MS bit first on the original pl022. 2212ca632f55SGrant Likely */ 2213ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2214ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2215ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2216ca632f55SGrant Likely 2217ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2218ca632f55SGrant Likely 2219ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2220ca632f55SGrant Likely if (status) 2221ca632f55SGrant Likely goto err_no_ioregion; 2222ca632f55SGrant Likely 2223ca632f55SGrant Likely pl022->phybase = adev->res.start; 2224aeef9915SLinus Walleij pl022->virtbase = devm_ioremap(dev, adev->res.start, 2225aeef9915SLinus Walleij resource_size(&adev->res)); 2226ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2227ca632f55SGrant Likely status = -ENOMEM; 2228ca632f55SGrant Likely goto err_no_ioremap; 2229ca632f55SGrant Likely } 22302c067509SJingoo Han dev_info(&adev->dev, "mapped registers from %pa to %p\n", 22317085f403SFabio Estevam &adev->res.start, pl022->virtbase); 2232ca632f55SGrant Likely 2233aeef9915SLinus Walleij pl022->clk = devm_clk_get(&adev->dev, NULL); 2234ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2235ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2236ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2237ca632f55SGrant Likely goto err_no_clk; 2238ca632f55SGrant Likely } 22397ff6bcf0SRussell King 22406cac167bSUlf Hansson status = clk_prepare_enable(pl022->clk); 224171e63e74SUlf Hansson if (status) { 224271e63e74SUlf Hansson dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 224371e63e74SUlf Hansson goto err_no_clk_en; 224471e63e74SUlf Hansson } 224571e63e74SUlf Hansson 2246ffbbdd21SLinus Walleij /* Initialize transfer pump */ 2247ffbbdd21SLinus Walleij tasklet_init(&pl022->pump_transfers, pump_transfers, 2248ffbbdd21SLinus Walleij (unsigned long)pl022); 2249ffbbdd21SLinus Walleij 2250ca632f55SGrant Likely /* Disable SSP */ 2251ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2252ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2253ca632f55SGrant Likely load_ssp_default_config(pl022); 2254ca632f55SGrant Likely 2255aeef9915SLinus Walleij status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2256aeef9915SLinus Walleij 0, "pl022", pl022); 2257ca632f55SGrant Likely if (status < 0) { 2258ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2259ca632f55SGrant Likely goto err_no_irq; 2260ca632f55SGrant Likely } 2261ca632f55SGrant Likely 2262dc715452SArnd Bergmann /* Get DMA channels, try autoconfiguration first */ 2263dc715452SArnd Bergmann status = pl022_dma_autoprobe(pl022); 2264f3d4bb33SRabin Vincent if (status == -EPROBE_DEFER) { 2265f3d4bb33SRabin Vincent dev_dbg(dev, "deferring probe to get DMA channel\n"); 2266f3d4bb33SRabin Vincent goto err_no_irq; 2267f3d4bb33SRabin Vincent } 2268dc715452SArnd Bergmann 2269dc715452SArnd Bergmann /* If that failed, use channels from platform_info */ 2270dc715452SArnd Bergmann if (status == 0) 2271dc715452SArnd Bergmann platform_info->enable_dma = 1; 2272dc715452SArnd Bergmann else if (platform_info->enable_dma) { 2273ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2274ca632f55SGrant Likely if (status != 0) 2275ca632f55SGrant Likely platform_info->enable_dma = 0; 2276ca632f55SGrant Likely } 2277ca632f55SGrant Likely 2278ca632f55SGrant Likely /* Register with the SPI framework */ 2279ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 228035794a77SJingoo Han status = devm_spi_register_master(&adev->dev, master); 2281ca632f55SGrant Likely if (status != 0) { 2282ca632f55SGrant Likely dev_err(&adev->dev, 2283ca632f55SGrant Likely "probe - problem registering spi master\n"); 2284ca632f55SGrant Likely goto err_spi_register; 2285ca632f55SGrant Likely } 2286ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 228792b97f0aSRussell King 228892b97f0aSRussell King /* let runtime pm put suspend */ 228953e4aceaSChris Blair if (platform_info->autosuspend_delay > 0) { 229053e4aceaSChris Blair dev_info(&adev->dev, 229153e4aceaSChris Blair "will use autosuspend for runtime pm, delay %dms\n", 229253e4aceaSChris Blair platform_info->autosuspend_delay); 229353e4aceaSChris Blair pm_runtime_set_autosuspend_delay(dev, 229453e4aceaSChris Blair platform_info->autosuspend_delay); 229553e4aceaSChris Blair pm_runtime_use_autosuspend(dev); 229653e4aceaSChris Blair } 22970df34994SUlf Hansson pm_runtime_put(dev); 22980df34994SUlf Hansson 2299ca632f55SGrant Likely return 0; 2300ca632f55SGrant Likely 2301ca632f55SGrant Likely err_spi_register: 23023e3ea716SViresh Kumar if (platform_info->enable_dma) 2303ca632f55SGrant Likely pl022_dma_remove(pl022); 2304ca632f55SGrant Likely err_no_irq: 23056cac167bSUlf Hansson clk_disable_unprepare(pl022->clk); 230671e63e74SUlf Hansson err_no_clk_en: 2307ca632f55SGrant Likely err_no_clk: 2308ca632f55SGrant Likely err_no_ioremap: 2309ca632f55SGrant Likely amba_release_regions(adev); 2310ca632f55SGrant Likely err_no_ioregion: 23116d3952a7SRoland Stigge err_no_gpio: 231273e3f1ebSKiran Padwal err_no_mem: 2313ca632f55SGrant Likely spi_master_put(master); 2314ca632f55SGrant Likely return status; 2315ca632f55SGrant Likely } 2316ca632f55SGrant Likely 2317fd4a319bSGrant Likely static int 2318ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2319ca632f55SGrant Likely { 2320ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 232150658b66SLinus Walleij 2322ca632f55SGrant Likely if (!pl022) 2323ca632f55SGrant Likely return 0; 2324ca632f55SGrant Likely 232592b97f0aSRussell King /* 232692b97f0aSRussell King * undo pm_runtime_put() in probe. I assume that we're not 232792b97f0aSRussell King * accessing the primecell here. 232892b97f0aSRussell King */ 232992b97f0aSRussell King pm_runtime_get_noresume(&adev->dev); 233092b97f0aSRussell King 2331ca632f55SGrant Likely load_ssp_default_config(pl022); 23323e3ea716SViresh Kumar if (pl022->master_info->enable_dma) 2333ca632f55SGrant Likely pl022_dma_remove(pl022); 23343e3ea716SViresh Kumar 23356cac167bSUlf Hansson clk_disable_unprepare(pl022->clk); 2336ca632f55SGrant Likely amba_release_regions(adev); 2337ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2338ca632f55SGrant Likely return 0; 2339ca632f55SGrant Likely } 2340ca632f55SGrant Likely 234184a5dc41SUlf Hansson #ifdef CONFIG_PM_SLEEP 23426cfa6279SPeter Hüwe static int pl022_suspend(struct device *dev) 2343ca632f55SGrant Likely { 234492b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2345ffbbdd21SLinus Walleij int ret; 2346ca632f55SGrant Likely 2347ffbbdd21SLinus Walleij ret = spi_master_suspend(pl022->master); 23487c5d8a24SGeert Uytterhoeven if (ret) 2349ffbbdd21SLinus Walleij return ret; 23504964a26dSUlf Hansson 235184a5dc41SUlf Hansson ret = pm_runtime_force_suspend(dev); 235284a5dc41SUlf Hansson if (ret) { 235384a5dc41SUlf Hansson spi_master_resume(pl022->master); 235484a5dc41SUlf Hansson return ret; 235584a5dc41SUlf Hansson } 235684a5dc41SUlf Hansson 235784a5dc41SUlf Hansson pinctrl_pm_select_sleep_state(dev); 2358ca632f55SGrant Likely 23596cfa6279SPeter Hüwe dev_dbg(dev, "suspended\n"); 2360ca632f55SGrant Likely return 0; 2361ca632f55SGrant Likely } 2362ca632f55SGrant Likely 236392b97f0aSRussell King static int pl022_resume(struct device *dev) 2364ca632f55SGrant Likely { 236592b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2366ffbbdd21SLinus Walleij int ret; 2367ca632f55SGrant Likely 236884a5dc41SUlf Hansson ret = pm_runtime_force_resume(dev); 236984a5dc41SUlf Hansson if (ret) 237084a5dc41SUlf Hansson dev_err(dev, "problem resuming\n"); 2371ada7aec7SLinus Walleij 2372ca632f55SGrant Likely /* Start the queue running */ 2373ffbbdd21SLinus Walleij ret = spi_master_resume(pl022->master); 23747c5d8a24SGeert Uytterhoeven if (!ret) 237592b97f0aSRussell King dev_dbg(dev, "resumed\n"); 2376ca632f55SGrant Likely 2377ffbbdd21SLinus Walleij return ret; 2378ca632f55SGrant Likely } 237984a5dc41SUlf Hansson #endif 2380ca632f55SGrant Likely 2381736198b0SUlf Hansson #ifdef CONFIG_PM 238292b97f0aSRussell King static int pl022_runtime_suspend(struct device *dev) 238392b97f0aSRussell King { 238492b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 238592b97f0aSRussell King 238684a5dc41SUlf Hansson clk_disable_unprepare(pl022->clk); 238784a5dc41SUlf Hansson pinctrl_pm_select_idle_state(dev); 238884a5dc41SUlf Hansson 238992b97f0aSRussell King return 0; 239092b97f0aSRussell King } 239192b97f0aSRussell King 239292b97f0aSRussell King static int pl022_runtime_resume(struct device *dev) 239392b97f0aSRussell King { 239492b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 23954f5e1b37SPatrice Chotard 239684a5dc41SUlf Hansson pinctrl_pm_select_default_state(dev); 239784a5dc41SUlf Hansson clk_prepare_enable(pl022->clk); 239884a5dc41SUlf Hansson 239992b97f0aSRussell King return 0; 240092b97f0aSRussell King } 240192b97f0aSRussell King #endif 240292b97f0aSRussell King 240392b97f0aSRussell King static const struct dev_pm_ops pl022_dev_pm_ops = { 240492b97f0aSRussell King SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 24056ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 240692b97f0aSRussell King }; 240792b97f0aSRussell King 2408ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2409ca632f55SGrant Likely .fifodepth = 8, 2410ca632f55SGrant Likely .max_bpw = 16, 2411ca632f55SGrant Likely .unidir = false, 2412ca632f55SGrant Likely .extended_cr = false, 2413ca632f55SGrant Likely .pl023 = false, 2414ca632f55SGrant Likely .loopback = true, 2415db4fa45eSAnders Berg .internal_cs_ctrl = false, 2416ca632f55SGrant Likely }; 2417ca632f55SGrant Likely 2418ca632f55SGrant Likely static struct vendor_data vendor_st = { 2419ca632f55SGrant Likely .fifodepth = 32, 2420ca632f55SGrant Likely .max_bpw = 32, 2421ca632f55SGrant Likely .unidir = false, 2422ca632f55SGrant Likely .extended_cr = true, 2423ca632f55SGrant Likely .pl023 = false, 2424ca632f55SGrant Likely .loopback = true, 2425db4fa45eSAnders Berg .internal_cs_ctrl = false, 2426ca632f55SGrant Likely }; 2427ca632f55SGrant Likely 2428ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2429ca632f55SGrant Likely .fifodepth = 32, 2430ca632f55SGrant Likely .max_bpw = 32, 2431ca632f55SGrant Likely .unidir = false, 2432ca632f55SGrant Likely .extended_cr = true, 2433ca632f55SGrant Likely .pl023 = true, 2434ca632f55SGrant Likely .loopback = false, 2435db4fa45eSAnders Berg .internal_cs_ctrl = false, 2436db4fa45eSAnders Berg }; 2437db4fa45eSAnders Berg 2438db4fa45eSAnders Berg static struct vendor_data vendor_lsi = { 2439db4fa45eSAnders Berg .fifodepth = 8, 2440db4fa45eSAnders Berg .max_bpw = 16, 2441db4fa45eSAnders Berg .unidir = false, 2442db4fa45eSAnders Berg .extended_cr = false, 2443db4fa45eSAnders Berg .pl023 = false, 2444db4fa45eSAnders Berg .loopback = true, 2445db4fa45eSAnders Berg .internal_cs_ctrl = true, 2446ca632f55SGrant Likely }; 2447ca632f55SGrant Likely 24485b8d5ad2SArvind Yadav static const struct amba_id pl022_ids[] = { 2449ca632f55SGrant Likely { 2450ca632f55SGrant Likely /* 2451ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2452ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2453ca632f55SGrant Likely */ 2454ca632f55SGrant Likely .id = 0x00041022, 2455ca632f55SGrant Likely .mask = 0x000fffff, 2456ca632f55SGrant Likely .data = &vendor_arm, 2457ca632f55SGrant Likely }, 2458ca632f55SGrant Likely { 2459ca632f55SGrant Likely /* 2460ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2461ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2462ca632f55SGrant Likely */ 2463ca632f55SGrant Likely .id = 0x01080022, 2464ca632f55SGrant Likely .mask = 0xffffffff, 2465ca632f55SGrant Likely .data = &vendor_st, 2466ca632f55SGrant Likely }, 2467ca632f55SGrant Likely { 2468ca632f55SGrant Likely /* 2469ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2470ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2471ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2472ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2473ca632f55SGrant Likely * CR0/CR1 register 2474ca632f55SGrant Likely */ 2475ca632f55SGrant Likely .id = 0x00080023, 2476ca632f55SGrant Likely .mask = 0xffffffff, 2477ca632f55SGrant Likely .data = &vendor_st_pl023, 2478ca632f55SGrant Likely }, 2479db4fa45eSAnders Berg { 2480db4fa45eSAnders Berg /* 2481db4fa45eSAnders Berg * PL022 variant that has a chip select control register whih 2482db4fa45eSAnders Berg * allows control of 5 output signals nCS[0:4]. 2483db4fa45eSAnders Berg */ 2484db4fa45eSAnders Berg .id = 0x000b6022, 2485db4fa45eSAnders Berg .mask = 0x000fffff, 2486db4fa45eSAnders Berg .data = &vendor_lsi, 2487db4fa45eSAnders Berg }, 2488ca632f55SGrant Likely { 0, 0 }, 2489ca632f55SGrant Likely }; 2490ca632f55SGrant Likely 24917eeac71bSDave Martin MODULE_DEVICE_TABLE(amba, pl022_ids); 24927eeac71bSDave Martin 2493ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2494ca632f55SGrant Likely .drv = { 2495ca632f55SGrant Likely .name = "ssp-pl022", 249692b97f0aSRussell King .pm = &pl022_dev_pm_ops, 2497ca632f55SGrant Likely }, 2498ca632f55SGrant Likely .id_table = pl022_ids, 2499ca632f55SGrant Likely .probe = pl022_probe, 2500fd4a319bSGrant Likely .remove = pl022_remove, 2501ca632f55SGrant Likely }; 2502ca632f55SGrant Likely 2503ca632f55SGrant Likely static int __init pl022_init(void) 2504ca632f55SGrant Likely { 2505ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2506ca632f55SGrant Likely } 2507ca632f55SGrant Likely subsys_initcall(pl022_init); 2508ca632f55SGrant Likely 2509ca632f55SGrant Likely static void __exit pl022_exit(void) 2510ca632f55SGrant Likely { 2511ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2512ca632f55SGrant Likely } 2513ca632f55SGrant Likely module_exit(pl022_exit); 2514ca632f55SGrant Likely 2515ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2516ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2517ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2518