1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2008-2009 ST-Ericsson AB 5ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6ca632f55SGrant Likely * 7ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * Initial version inspired by: 10ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11ca632f55SGrant Likely * Initial adoption to PL022 by: 12ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 15ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 16ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 17ca632f55SGrant Likely * (at your option) any later version. 18ca632f55SGrant Likely * 19ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 20ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 21ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22ca632f55SGrant Likely * GNU General Public License for more details. 23ca632f55SGrant Likely */ 24ca632f55SGrant Likely 25ca632f55SGrant Likely #include <linux/init.h> 26ca632f55SGrant Likely #include <linux/module.h> 27ca632f55SGrant Likely #include <linux/device.h> 28ca632f55SGrant Likely #include <linux/ioport.h> 29ca632f55SGrant Likely #include <linux/errno.h> 30ca632f55SGrant Likely #include <linux/interrupt.h> 31ca632f55SGrant Likely #include <linux/spi/spi.h> 32ca632f55SGrant Likely #include <linux/delay.h> 33ca632f55SGrant Likely #include <linux/clk.h> 34ca632f55SGrant Likely #include <linux/err.h> 35ca632f55SGrant Likely #include <linux/amba/bus.h> 36ca632f55SGrant Likely #include <linux/amba/pl022.h> 37ca632f55SGrant Likely #include <linux/io.h> 38ca632f55SGrant Likely #include <linux/slab.h> 39ca632f55SGrant Likely #include <linux/dmaengine.h> 40ca632f55SGrant Likely #include <linux/dma-mapping.h> 41ca632f55SGrant Likely #include <linux/scatterlist.h> 42bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 43f6f46de1SRoland Stigge #include <linux/gpio.h> 446d3952a7SRoland Stigge #include <linux/of_gpio.h> 45ca632f55SGrant Likely 46ca632f55SGrant Likely /* 47ca632f55SGrant Likely * This macro is used to define some register default values. 48ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 49ca632f55SGrant Likely * val shifted sb steps to the left. 50ca632f55SGrant Likely */ 51ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 52ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 53ca632f55SGrant Likely 54ca632f55SGrant Likely /* 55ca632f55SGrant Likely * This macro is also used to define some default values. 56ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 57ca632f55SGrant Likely * the result with mask. 58ca632f55SGrant Likely */ 59ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 60ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 61ca632f55SGrant Likely 62ca632f55SGrant Likely #define DRIVE_TX 0 63ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 64ca632f55SGrant Likely 65ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 66ca632f55SGrant Likely #define QUEUE_DMA 1 67ca632f55SGrant Likely 68ca632f55SGrant Likely #define RX_TRANSFER 1 69ca632f55SGrant Likely #define TX_TRANSFER 2 70ca632f55SGrant Likely 71ca632f55SGrant Likely /* 72ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 73ca632f55SGrant Likely */ 74ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 75ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 76ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 77ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 78ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 79ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 80ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 81ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 82ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 83ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 84ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 85ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 86ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 87ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 88ca632f55SGrant Likely 89ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 90ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 91ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 92ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 93ca632f55SGrant Likely 94ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 95ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 96ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 97ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 98ca632f55SGrant Likely 99ca632f55SGrant Likely /* 100ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 101ca632f55SGrant Likely */ 102ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 103ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 104ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 105ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 106ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 107ca632f55SGrant Likely 108ca632f55SGrant Likely /* 109ca632f55SGrant Likely * The ST version of this block moves som bits 110ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 111ca632f55SGrant Likely */ 112ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 113ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 114ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 115ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 116ca632f55SGrant Likely 117ca632f55SGrant Likely /* 118ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 119ca632f55SGrant Likely */ 120ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 121ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 122ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 123ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 124ca632f55SGrant Likely 125ca632f55SGrant Likely /* 126ca632f55SGrant Likely * The ST version of this block adds some bits 127ca632f55SGrant Likely * in SSP_CR1 128ca632f55SGrant Likely */ 129ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 130ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 131ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 132ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 133ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 134ca632f55SGrant Likely /* This one is only in the PL023 variant */ 135ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 136ca632f55SGrant Likely 137ca632f55SGrant Likely /* 138ca632f55SGrant Likely * SSP Status Register - SSP_SR 139ca632f55SGrant Likely */ 140ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 141ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 142ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 143ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 144ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 145ca632f55SGrant Likely 146ca632f55SGrant Likely /* 147ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 148ca632f55SGrant Likely */ 149ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 150ca632f55SGrant Likely 151ca632f55SGrant Likely /* 152ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 153ca632f55SGrant Likely */ 154ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 155ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 156ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 157ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 158ca632f55SGrant Likely 159ca632f55SGrant Likely /* 160ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 161ca632f55SGrant Likely */ 162ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 163ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 164ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 165ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 166ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 167ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 168ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 169ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 170ca632f55SGrant Likely 171ca632f55SGrant Likely /* 172ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 173ca632f55SGrant Likely */ 174ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 175ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 176ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 177ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 178ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 179ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 180ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 181ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 182ca632f55SGrant Likely 183ca632f55SGrant Likely /* 184ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 185ca632f55SGrant Likely */ 186ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 187ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 188ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 189ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 190ca632f55SGrant Likely 191ca632f55SGrant Likely /* 192ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 193ca632f55SGrant Likely */ 194ca632f55SGrant Likely /* Receive DMA Enable bit */ 195ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 196ca632f55SGrant Likely /* Transmit DMA Enable bit */ 197ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 198ca632f55SGrant Likely 199ca632f55SGrant Likely /* 200ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 201ca632f55SGrant Likely */ 202ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 203ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 204ca632f55SGrant Likely 205ca632f55SGrant Likely /* 206ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 207ca632f55SGrant Likely */ 208ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 209ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 210ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 211ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 212ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 213ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 214ca632f55SGrant Likely 215ca632f55SGrant Likely /* 216ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 217ca632f55SGrant Likely */ 218ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 219ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 220ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 221ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 222ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 223ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 224ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 225ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 226ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 227ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 228ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 229ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 230ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 231ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 232ca632f55SGrant Likely 233ca632f55SGrant Likely /* 234ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 235ca632f55SGrant Likely */ 236ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 237ca632f55SGrant Likely 238ca632f55SGrant Likely /* 239ca632f55SGrant Likely * Message State 240ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 241ca632f55SGrant Likely * hold a single state value, that's why all this 242ca632f55SGrant Likely * (void *) casting is done here. 243ca632f55SGrant Likely */ 244ca632f55SGrant Likely #define STATE_START ((void *) 0) 245ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 246ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 247ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 248ca632f55SGrant Likely 249ca632f55SGrant Likely /* 250ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 251ca632f55SGrant Likely */ 252ca632f55SGrant Likely #define SSP_DISABLED (0) 253ca632f55SGrant Likely #define SSP_ENABLED (1) 254ca632f55SGrant Likely 255ca632f55SGrant Likely /* 256ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 257ca632f55SGrant Likely */ 258ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 259ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 260ca632f55SGrant Likely 261ca632f55SGrant Likely /* 262ca632f55SGrant Likely * SSP Clock Defaults 263ca632f55SGrant Likely */ 264ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 265ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 266ca632f55SGrant Likely 267ca632f55SGrant Likely /* 268ca632f55SGrant Likely * SSP Clock Parameter ranges 269ca632f55SGrant Likely */ 270ca632f55SGrant Likely #define CPSDVR_MIN 0x02 271ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 272ca632f55SGrant Likely #define SCR_MIN 0x00 273ca632f55SGrant Likely #define SCR_MAX 0xFF 274ca632f55SGrant Likely 275ca632f55SGrant Likely /* 276ca632f55SGrant Likely * SSP Interrupt related Macros 277ca632f55SGrant Likely */ 278ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 279ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 280ca632f55SGrant Likely #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 281ca632f55SGrant Likely 282ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 283ca632f55SGrant Likely 284ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 285ca632f55SGrant Likely 286ca632f55SGrant Likely /* 287ca632f55SGrant Likely * The type of reading going on on this chip 288ca632f55SGrant Likely */ 289ca632f55SGrant Likely enum ssp_reading { 290ca632f55SGrant Likely READING_NULL, 291ca632f55SGrant Likely READING_U8, 292ca632f55SGrant Likely READING_U16, 293ca632f55SGrant Likely READING_U32 294ca632f55SGrant Likely }; 295ca632f55SGrant Likely 296ca632f55SGrant Likely /** 297ca632f55SGrant Likely * The type of writing going on on this chip 298ca632f55SGrant Likely */ 299ca632f55SGrant Likely enum ssp_writing { 300ca632f55SGrant Likely WRITING_NULL, 301ca632f55SGrant Likely WRITING_U8, 302ca632f55SGrant Likely WRITING_U16, 303ca632f55SGrant Likely WRITING_U32 304ca632f55SGrant Likely }; 305ca632f55SGrant Likely 306ca632f55SGrant Likely /** 307ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 308ca632f55SGrant Likely * for PL022 derivates 309ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 310ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 311ca632f55SGrant Likely * @unidir: supports unidirection transfers 312ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 313ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 314ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 315ca632f55SGrant Likely */ 316ca632f55SGrant Likely struct vendor_data { 317ca632f55SGrant Likely int fifodepth; 318ca632f55SGrant Likely int max_bpw; 319ca632f55SGrant Likely bool unidir; 320ca632f55SGrant Likely bool extended_cr; 321ca632f55SGrant Likely bool pl023; 322ca632f55SGrant Likely bool loopback; 323ca632f55SGrant Likely }; 324ca632f55SGrant Likely 325ca632f55SGrant Likely /** 326ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 327ca632f55SGrant Likely * @adev: AMBA device model hookup 328ca632f55SGrant Likely * @vendor: vendor data for the IP block 329ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 330ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 331ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 332ca632f55SGrant Likely * @master: SPI framework hookup 333ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 33414af60b6SChris Blair * @kworker: thread struct for message pump 33514af60b6SChris Blair * @kworker_task: pointer to task for message pump kworker thread 33614af60b6SChris Blair * @pump_messages: work struct for scheduling work to the message pump 337ca632f55SGrant Likely * @queue_lock: spinlock to syncronise access to message queue 338ca632f55SGrant Likely * @queue: message queue 33914af60b6SChris Blair * @busy: message pump is busy 34014af60b6SChris Blair * @running: message pump is running 341ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 342ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 343ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 344ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 3458b8d7191SVirupax Sadashivpetimath * @next_msg_cs_active: the next message in the queue has been examined 3468b8d7191SVirupax Sadashivpetimath * and it was found that it uses the same chip select as the previous 3478b8d7191SVirupax Sadashivpetimath * message, so we left it active after the previous transfer, and it's 3488b8d7191SVirupax Sadashivpetimath * active already. 349ca632f55SGrant Likely * @tx: current position in TX buffer to be read 350ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 351ca632f55SGrant Likely * @rx: current position in RX buffer to be written 352ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 353ca632f55SGrant Likely * @read: the type of read currently going on 354ca632f55SGrant Likely * @write: the type of write currently going on 355ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 356ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 357ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 358ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 359ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 360ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 361f6f46de1SRoland Stigge * @cur_cs: current chip select (gpio) 362f6f46de1SRoland Stigge * @chipselects: list of chipselects (gpios) 363ca632f55SGrant Likely */ 364ca632f55SGrant Likely struct pl022 { 365ca632f55SGrant Likely struct amba_device *adev; 366ca632f55SGrant Likely struct vendor_data *vendor; 367ca632f55SGrant Likely resource_size_t phybase; 368ca632f55SGrant Likely void __iomem *virtbase; 369ca632f55SGrant Likely struct clk *clk; 370ca632f55SGrant Likely struct spi_master *master; 371ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 372ffbbdd21SLinus Walleij /* Message per-transfer pump */ 373ca632f55SGrant Likely struct tasklet_struct pump_transfers; 374ca632f55SGrant Likely struct spi_message *cur_msg; 375ca632f55SGrant Likely struct spi_transfer *cur_transfer; 376ca632f55SGrant Likely struct chip_data *cur_chip; 3778b8d7191SVirupax Sadashivpetimath bool next_msg_cs_active; 378ca632f55SGrant Likely void *tx; 379ca632f55SGrant Likely void *tx_end; 380ca632f55SGrant Likely void *rx; 381ca632f55SGrant Likely void *rx_end; 382ca632f55SGrant Likely enum ssp_reading read; 383ca632f55SGrant Likely enum ssp_writing write; 384ca632f55SGrant Likely u32 exp_fifo_level; 385083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 386083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 387ca632f55SGrant Likely /* DMA settings */ 388ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 389ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 390ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 391ca632f55SGrant Likely struct sg_table sgt_rx; 392ca632f55SGrant Likely struct sg_table sgt_tx; 393ca632f55SGrant Likely char *dummypage; 394ffbbdd21SLinus Walleij bool dma_running; 395ca632f55SGrant Likely #endif 396f6f46de1SRoland Stigge int cur_cs; 397f6f46de1SRoland Stigge int *chipselects; 398ca632f55SGrant Likely }; 399ca632f55SGrant Likely 400ca632f55SGrant Likely /** 401ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 402ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 403ca632f55SGrant Likely * register is 32 bits wide rather than just 16 404ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 405ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 406ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 407ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 408ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 409ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 410ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 411ca632f55SGrant Likely * @cs_control: chip select callback provided by chip 412ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 413ca632f55SGrant Likely * 414ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 415ca632f55SGrant Likely * This would be set according to the current message that would be served 416ca632f55SGrant Likely */ 417ca632f55SGrant Likely struct chip_data { 418ca632f55SGrant Likely u32 cr0; 419ca632f55SGrant Likely u16 cr1; 420ca632f55SGrant Likely u16 dmacr; 421ca632f55SGrant Likely u16 cpsr; 422ca632f55SGrant Likely u8 n_bytes; 423ca632f55SGrant Likely bool enable_dma; 424ca632f55SGrant Likely enum ssp_reading read; 425ca632f55SGrant Likely enum ssp_writing write; 426ca632f55SGrant Likely void (*cs_control) (u32 command); 427ca632f55SGrant Likely int xfer_type; 428ca632f55SGrant Likely }; 429ca632f55SGrant Likely 430ca632f55SGrant Likely /** 431ca632f55SGrant Likely * null_cs_control - Dummy chip select function 432ca632f55SGrant Likely * @command: select/delect the chip 433ca632f55SGrant Likely * 434ca632f55SGrant Likely * If no chip select function is provided by client this is used as dummy 435ca632f55SGrant Likely * chip select 436ca632f55SGrant Likely */ 437ca632f55SGrant Likely static void null_cs_control(u32 command) 438ca632f55SGrant Likely { 439ca632f55SGrant Likely pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 440ca632f55SGrant Likely } 441ca632f55SGrant Likely 442f6f46de1SRoland Stigge static void pl022_cs_control(struct pl022 *pl022, u32 command) 443f6f46de1SRoland Stigge { 444f6f46de1SRoland Stigge if (gpio_is_valid(pl022->cur_cs)) 445f6f46de1SRoland Stigge gpio_set_value(pl022->cur_cs, command); 446f6f46de1SRoland Stigge else 447f6f46de1SRoland Stigge pl022->cur_chip->cs_control(command); 448f6f46de1SRoland Stigge } 449f6f46de1SRoland Stigge 450ca632f55SGrant Likely /** 451ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 452ca632f55SGrant Likely * callback of this message. Assumes that caller already 453ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 454ca632f55SGrant Likely * @pl022: SSP driver private data structure 455ca632f55SGrant Likely */ 456ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 457ca632f55SGrant Likely { 458ca632f55SGrant Likely struct spi_transfer *last_transfer; 4598b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = false; 460ca632f55SGrant Likely 4618b8d7191SVirupax Sadashivpetimath last_transfer = list_entry(pl022->cur_msg->transfers.prev, 462ca632f55SGrant Likely struct spi_transfer, 463ca632f55SGrant Likely transfer_list); 464ca632f55SGrant Likely 465ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 466ca632f55SGrant Likely if (last_transfer->delay_usecs) 467ca632f55SGrant Likely /* 468ca632f55SGrant Likely * FIXME: This runs in interrupt context. 469ca632f55SGrant Likely * Is this really smart? 470ca632f55SGrant Likely */ 471ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 472ca632f55SGrant Likely 4738b8d7191SVirupax Sadashivpetimath if (!last_transfer->cs_change) { 474ca632f55SGrant Likely struct spi_message *next_msg; 475ca632f55SGrant Likely 4768b8d7191SVirupax Sadashivpetimath /* 4778b8d7191SVirupax Sadashivpetimath * cs_change was not set. We can keep the chip select 4788b8d7191SVirupax Sadashivpetimath * enabled if there is message in the queue and it is 4798b8d7191SVirupax Sadashivpetimath * for the same spi device. 480ca632f55SGrant Likely * 481ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 482ca632f55SGrant Likely * after calling msg->complete (below) the driver that 483ca632f55SGrant Likely * sent the current message could be unloaded, which 484ca632f55SGrant Likely * could invalidate the cs_control() callback... 485ca632f55SGrant Likely */ 486ca632f55SGrant Likely /* get a pointer to the next message, if any */ 487ffbbdd21SLinus Walleij next_msg = spi_get_next_queued_message(pl022->master); 488ca632f55SGrant Likely 4898b8d7191SVirupax Sadashivpetimath /* 4908b8d7191SVirupax Sadashivpetimath * see if the next and current messages point 4918b8d7191SVirupax Sadashivpetimath * to the same spi device. 492ca632f55SGrant Likely */ 4938b8d7191SVirupax Sadashivpetimath if (next_msg && next_msg->spi != pl022->cur_msg->spi) 494ca632f55SGrant Likely next_msg = NULL; 4958b8d7191SVirupax Sadashivpetimath if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 496f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 4978b8d7191SVirupax Sadashivpetimath else 4988b8d7191SVirupax Sadashivpetimath pl022->next_msg_cs_active = true; 499ffbbdd21SLinus Walleij 500ca632f55SGrant Likely } 5018b8d7191SVirupax Sadashivpetimath 5028b8d7191SVirupax Sadashivpetimath pl022->cur_msg = NULL; 5038b8d7191SVirupax Sadashivpetimath pl022->cur_transfer = NULL; 5048b8d7191SVirupax Sadashivpetimath pl022->cur_chip = NULL; 505ffbbdd21SLinus Walleij spi_finalize_current_message(pl022->master); 506fd316941SVirupax Sadashivpetimath 507fd316941SVirupax Sadashivpetimath /* disable the SPI/SSP operation */ 508fd316941SVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 509fd316941SVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 510fd316941SVirupax Sadashivpetimath 511ca632f55SGrant Likely } 512ca632f55SGrant Likely 513ca632f55SGrant Likely /** 514ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 515ca632f55SGrant Likely * @pl022: SSP driver private data structure 516ca632f55SGrant Likely */ 517ca632f55SGrant Likely static int flush(struct pl022 *pl022) 518ca632f55SGrant Likely { 519ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 520ca632f55SGrant Likely 521ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 522ca632f55SGrant Likely do { 523ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 524ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 525ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 526ca632f55SGrant Likely 527ca632f55SGrant Likely pl022->exp_fifo_level = 0; 528ca632f55SGrant Likely 529ca632f55SGrant Likely return limit; 530ca632f55SGrant Likely } 531ca632f55SGrant Likely 532ca632f55SGrant Likely /** 533ca632f55SGrant Likely * restore_state - Load configuration of current chip 534ca632f55SGrant Likely * @pl022: SSP driver private data structure 535ca632f55SGrant Likely */ 536ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 537ca632f55SGrant Likely { 538ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 539ca632f55SGrant Likely 540ca632f55SGrant Likely if (pl022->vendor->extended_cr) 541ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 542ca632f55SGrant Likely else 543ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 544ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 545ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 546ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 547ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 548ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 549ca632f55SGrant Likely } 550ca632f55SGrant Likely 551ca632f55SGrant Likely /* 552ca632f55SGrant Likely * Default SSP Register Values 553ca632f55SGrant Likely */ 554ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 555ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 556ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 557ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 558ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 559ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 560ca632f55SGrant Likely ) 561ca632f55SGrant Likely 562ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 563ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 564ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 565ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 566ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 567ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 568ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 569ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 570ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 571ca632f55SGrant Likely ) 572ca632f55SGrant Likely 573ca632f55SGrant Likely /* The PL023 version is slightly different again */ 574ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 575ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 576ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 577ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 578ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 579ca632f55SGrant Likely ) 580ca632f55SGrant Likely 581ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 582ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 583ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 584ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 585ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 586ca632f55SGrant Likely ) 587ca632f55SGrant Likely 588ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 589ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 590ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 591ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 592ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 593ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 594ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 595ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 596ca632f55SGrant Likely ) 597ca632f55SGrant Likely 598ca632f55SGrant Likely /* 599ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 600ca632f55SGrant Likely * support, and a new clock feedback delay setting. 601ca632f55SGrant Likely */ 602ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 603ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 604ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 605ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 606ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 607ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 608ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 609ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 610ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 611ca632f55SGrant Likely ) 612ca632f55SGrant Likely 613ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 614ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 615ca632f55SGrant Likely ) 616ca632f55SGrant Likely 617ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 618ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 619ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 620ca632f55SGrant Likely ) 621ca632f55SGrant Likely 622ca632f55SGrant Likely /** 623ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 624ca632f55SGrant Likely * @pl022: SSP driver private data structure 625ca632f55SGrant Likely */ 626ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 627ca632f55SGrant Likely { 628ca632f55SGrant Likely if (pl022->vendor->pl023) { 629ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 630ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 631ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 632ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 633ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 634ca632f55SGrant Likely } else { 635ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 636ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 637ca632f55SGrant Likely } 638ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 639ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 640ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 641ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 642ca632f55SGrant Likely } 643ca632f55SGrant Likely 644ca632f55SGrant Likely /** 645ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 646ca632f55SGrant Likely * set in pl022. 647ca632f55SGrant Likely */ 648ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 649ca632f55SGrant Likely { 650ca632f55SGrant Likely 651ca632f55SGrant Likely /* 652ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 653ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 654ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 655ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 656ca632f55SGrant Likely * 657ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 658ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 659ca632f55SGrant Likely * FIFO status flag indicates. 660ca632f55SGrant Likely */ 661ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 662ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 663ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 664ca632f55SGrant Likely 665ca632f55SGrant Likely /* Read as much as you can */ 666ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 667ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 668ca632f55SGrant Likely switch (pl022->read) { 669ca632f55SGrant Likely case READING_NULL: 670ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 671ca632f55SGrant Likely break; 672ca632f55SGrant Likely case READING_U8: 673ca632f55SGrant Likely *(u8 *) (pl022->rx) = 674ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 675ca632f55SGrant Likely break; 676ca632f55SGrant Likely case READING_U16: 677ca632f55SGrant Likely *(u16 *) (pl022->rx) = 678ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 679ca632f55SGrant Likely break; 680ca632f55SGrant Likely case READING_U32: 681ca632f55SGrant Likely *(u32 *) (pl022->rx) = 682ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 683ca632f55SGrant Likely break; 684ca632f55SGrant Likely } 685ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 686ca632f55SGrant Likely pl022->exp_fifo_level--; 687ca632f55SGrant Likely } 688ca632f55SGrant Likely /* 689ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 690ca632f55SGrant Likely */ 691ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 692ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 693ca632f55SGrant Likely switch (pl022->write) { 694ca632f55SGrant Likely case WRITING_NULL: 695ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 696ca632f55SGrant Likely break; 697ca632f55SGrant Likely case WRITING_U8: 698ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 699ca632f55SGrant Likely break; 700ca632f55SGrant Likely case WRITING_U16: 701ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 702ca632f55SGrant Likely break; 703ca632f55SGrant Likely case WRITING_U32: 704ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 705ca632f55SGrant Likely break; 706ca632f55SGrant Likely } 707ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 708ca632f55SGrant Likely pl022->exp_fifo_level++; 709ca632f55SGrant Likely /* 710ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 711ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 712ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 713ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 714ca632f55SGrant Likely */ 715ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 716ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 717ca632f55SGrant Likely switch (pl022->read) { 718ca632f55SGrant Likely case READING_NULL: 719ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 720ca632f55SGrant Likely break; 721ca632f55SGrant Likely case READING_U8: 722ca632f55SGrant Likely *(u8 *) (pl022->rx) = 723ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 724ca632f55SGrant Likely break; 725ca632f55SGrant Likely case READING_U16: 726ca632f55SGrant Likely *(u16 *) (pl022->rx) = 727ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 728ca632f55SGrant Likely break; 729ca632f55SGrant Likely case READING_U32: 730ca632f55SGrant Likely *(u32 *) (pl022->rx) = 731ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 732ca632f55SGrant Likely break; 733ca632f55SGrant Likely } 734ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 735ca632f55SGrant Likely pl022->exp_fifo_level--; 736ca632f55SGrant Likely } 737ca632f55SGrant Likely } 738ca632f55SGrant Likely /* 739ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 740ca632f55SGrant Likely * should be empty 741ca632f55SGrant Likely */ 742ca632f55SGrant Likely } 743ca632f55SGrant Likely 744ca632f55SGrant Likely /** 745ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 746ca632f55SGrant Likely * @pl022: SSP driver private data structure 747ca632f55SGrant Likely * 748ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 749ca632f55SGrant Likely * current spi message and returns with the state of current spi 750ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 751ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 752ca632f55SGrant Likely */ 753ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 754ca632f55SGrant Likely { 755ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 756ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 757ca632f55SGrant Likely 758ca632f55SGrant Likely /* Move to next transfer */ 759ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 760ca632f55SGrant Likely pl022->cur_transfer = 761ca632f55SGrant Likely list_entry(trans->transfer_list.next, 762ca632f55SGrant Likely struct spi_transfer, transfer_list); 763ca632f55SGrant Likely return STATE_RUNNING; 764ca632f55SGrant Likely } 765ca632f55SGrant Likely return STATE_DONE; 766ca632f55SGrant Likely } 767ca632f55SGrant Likely 768ca632f55SGrant Likely /* 769ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 770ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 771ca632f55SGrant Likely */ 772ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 773ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 774ca632f55SGrant Likely { 775ca632f55SGrant Likely /* Unmap and free the SG tables */ 776ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 777ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 778ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 779ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 780ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 781ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 782ca632f55SGrant Likely } 783ca632f55SGrant Likely 784ca632f55SGrant Likely static void dma_callback(void *data) 785ca632f55SGrant Likely { 786ca632f55SGrant Likely struct pl022 *pl022 = data; 787ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 788ca632f55SGrant Likely 789ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 790ca632f55SGrant Likely 791ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 792ca632f55SGrant Likely /* 793ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 794ca632f55SGrant Likely * good if you want to convince yourself that the loopback 795ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 796ca632f55SGrant Likely * DMA engine. 797ca632f55SGrant Likely */ 798ca632f55SGrant Likely { 799ca632f55SGrant Likely struct scatterlist *sg; 800ca632f55SGrant Likely unsigned int i; 801ca632f55SGrant Likely 802ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 803ca632f55SGrant Likely pl022->sgt_rx.sgl, 804ca632f55SGrant Likely pl022->sgt_rx.nents, 805ca632f55SGrant Likely DMA_FROM_DEVICE); 806ca632f55SGrant Likely 807ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 808ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 809ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 810ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 811ca632f55SGrant Likely 16, 812ca632f55SGrant Likely 1, 813ca632f55SGrant Likely sg_virt(sg), 814ca632f55SGrant Likely sg_dma_len(sg), 815ca632f55SGrant Likely 1); 816ca632f55SGrant Likely } 817ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 818ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 819ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 820ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 821ca632f55SGrant Likely 16, 822ca632f55SGrant Likely 1, 823ca632f55SGrant Likely sg_virt(sg), 824ca632f55SGrant Likely sg_dma_len(sg), 825ca632f55SGrant Likely 1); 826ca632f55SGrant Likely } 827ca632f55SGrant Likely } 828ca632f55SGrant Likely #endif 829ca632f55SGrant Likely 830ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 831ca632f55SGrant Likely 832ca632f55SGrant Likely /* Update total bytes transferred */ 833ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 834ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 835f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 836ca632f55SGrant Likely 837ca632f55SGrant Likely /* Move to next transfer */ 838ca632f55SGrant Likely msg->state = next_transfer(pl022); 839ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 840ca632f55SGrant Likely } 841ca632f55SGrant Likely 842ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 843ca632f55SGrant Likely void *buffer, 844ca632f55SGrant Likely unsigned int length, 845ca632f55SGrant Likely struct sg_table *sgtab) 846ca632f55SGrant Likely { 847ca632f55SGrant Likely struct scatterlist *sg; 848ca632f55SGrant Likely int bytesleft = length; 849ca632f55SGrant Likely void *bufp = buffer; 850ca632f55SGrant Likely int mapbytes; 851ca632f55SGrant Likely int i; 852ca632f55SGrant Likely 853ca632f55SGrant Likely if (buffer) { 854ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 855ca632f55SGrant Likely /* 856ca632f55SGrant Likely * If there are less bytes left than what fits 857ca632f55SGrant Likely * in the current page (plus page alignment offset) 858ca632f55SGrant Likely * we just feed in this, else we stuff in as much 859ca632f55SGrant Likely * as we can. 860ca632f55SGrant Likely */ 861ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 862ca632f55SGrant Likely mapbytes = bytesleft; 863ca632f55SGrant Likely else 864ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 865ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 866ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 867ca632f55SGrant Likely bufp += mapbytes; 868ca632f55SGrant Likely bytesleft -= mapbytes; 869ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 870ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 871ca632f55SGrant Likely bufp, mapbytes, bytesleft); 872ca632f55SGrant Likely } 873ca632f55SGrant Likely } else { 874ca632f55SGrant Likely /* Map the dummy buffer on every page */ 875ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 876ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 877ca632f55SGrant Likely mapbytes = bytesleft; 878ca632f55SGrant Likely else 879ca632f55SGrant Likely mapbytes = PAGE_SIZE; 880ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 881ca632f55SGrant Likely mapbytes, 0); 882ca632f55SGrant Likely bytesleft -= mapbytes; 883ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 884ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 885ca632f55SGrant Likely mapbytes, bytesleft); 886ca632f55SGrant Likely 887ca632f55SGrant Likely } 888ca632f55SGrant Likely } 889ca632f55SGrant Likely BUG_ON(bytesleft); 890ca632f55SGrant Likely } 891ca632f55SGrant Likely 892ca632f55SGrant Likely /** 893ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 894ca632f55SGrant Likely * @pl022: SSP driver's private data structure 895ca632f55SGrant Likely */ 896ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 897ca632f55SGrant Likely { 898ca632f55SGrant Likely struct dma_slave_config rx_conf = { 899ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 900a485df4bSVinod Koul .direction = DMA_DEV_TO_MEM, 901258aea76SViresh Kumar .device_fc = false, 902ca632f55SGrant Likely }; 903ca632f55SGrant Likely struct dma_slave_config tx_conf = { 904ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 905a485df4bSVinod Koul .direction = DMA_MEM_TO_DEV, 906258aea76SViresh Kumar .device_fc = false, 907ca632f55SGrant Likely }; 908ca632f55SGrant Likely unsigned int pages; 909ca632f55SGrant Likely int ret; 910ca632f55SGrant Likely int rx_sglen, tx_sglen; 911ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 912ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 913ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 914ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 915ca632f55SGrant Likely 916ca632f55SGrant Likely /* Check that the channels are available */ 917ca632f55SGrant Likely if (!rxchan || !txchan) 918ca632f55SGrant Likely return -ENODEV; 919ca632f55SGrant Likely 920083be3f0SLinus Walleij /* 921083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 922083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 923083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 924083be3f0SLinus Walleij * calculation. 925083be3f0SLinus Walleij */ 926083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 927083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 928083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 929083be3f0SLinus Walleij break; 930083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 931083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 932083be3f0SLinus Walleij break; 933083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 934083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 935083be3f0SLinus Walleij break; 936083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 937083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 938083be3f0SLinus Walleij break; 939083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 940083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 941083be3f0SLinus Walleij break; 942083be3f0SLinus Walleij default: 943083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 944083be3f0SLinus Walleij break; 945083be3f0SLinus Walleij } 946083be3f0SLinus Walleij 947083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 948083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 949083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 950083be3f0SLinus Walleij break; 951083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 952083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 953083be3f0SLinus Walleij break; 954083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 955083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 956083be3f0SLinus Walleij break; 957083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 958083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 959083be3f0SLinus Walleij break; 960083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 961083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 962083be3f0SLinus Walleij break; 963083be3f0SLinus Walleij default: 964083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 965083be3f0SLinus Walleij break; 966083be3f0SLinus Walleij } 967083be3f0SLinus Walleij 968ca632f55SGrant Likely switch (pl022->read) { 969ca632f55SGrant Likely case READING_NULL: 970ca632f55SGrant Likely /* Use the same as for writing */ 971ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 972ca632f55SGrant Likely break; 973ca632f55SGrant Likely case READING_U8: 974ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 975ca632f55SGrant Likely break; 976ca632f55SGrant Likely case READING_U16: 977ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 978ca632f55SGrant Likely break; 979ca632f55SGrant Likely case READING_U32: 980ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 981ca632f55SGrant Likely break; 982ca632f55SGrant Likely } 983ca632f55SGrant Likely 984ca632f55SGrant Likely switch (pl022->write) { 985ca632f55SGrant Likely case WRITING_NULL: 986ca632f55SGrant Likely /* Use the same as for reading */ 987ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 988ca632f55SGrant Likely break; 989ca632f55SGrant Likely case WRITING_U8: 990ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 991ca632f55SGrant Likely break; 992ca632f55SGrant Likely case WRITING_U16: 993ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 994ca632f55SGrant Likely break; 995ca632f55SGrant Likely case WRITING_U32: 996ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 997ca632f55SGrant Likely break; 998ca632f55SGrant Likely } 999ca632f55SGrant Likely 1000ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 1001ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1002ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 1003ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1004ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 1005ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1006ca632f55SGrant Likely 1007ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 1008ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 1009ca632f55SGrant Likely 1010ca632f55SGrant Likely /* Create sglists for the transfers */ 1011b181565eSViresh Kumar pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1012ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1013ca632f55SGrant Likely 1014538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1015ca632f55SGrant Likely if (ret) 1016ca632f55SGrant Likely goto err_alloc_rx_sg; 1017ca632f55SGrant Likely 1018538a18dcSViresh Kumar ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1019ca632f55SGrant Likely if (ret) 1020ca632f55SGrant Likely goto err_alloc_tx_sg; 1021ca632f55SGrant Likely 1022ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1023ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1024ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1025ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1026ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1027ca632f55SGrant Likely 1028ca632f55SGrant Likely /* Map DMA buffers */ 1029ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1030ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1031ca632f55SGrant Likely if (!rx_sglen) 1032ca632f55SGrant Likely goto err_rx_sgmap; 1033ca632f55SGrant Likely 1034ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1035ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1036ca632f55SGrant Likely if (!tx_sglen) 1037ca632f55SGrant Likely goto err_tx_sgmap; 1038ca632f55SGrant Likely 1039ca632f55SGrant Likely /* Send both scatterlists */ 104016052827SAlexandre Bounine rxdesc = dmaengine_prep_slave_sg(rxchan, 1041ca632f55SGrant Likely pl022->sgt_rx.sgl, 1042ca632f55SGrant Likely rx_sglen, 1043a485df4bSVinod Koul DMA_DEV_TO_MEM, 1044ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1045ca632f55SGrant Likely if (!rxdesc) 1046ca632f55SGrant Likely goto err_rxdesc; 1047ca632f55SGrant Likely 104816052827SAlexandre Bounine txdesc = dmaengine_prep_slave_sg(txchan, 1049ca632f55SGrant Likely pl022->sgt_tx.sgl, 1050ca632f55SGrant Likely tx_sglen, 1051a485df4bSVinod Koul DMA_MEM_TO_DEV, 1052ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1053ca632f55SGrant Likely if (!txdesc) 1054ca632f55SGrant Likely goto err_txdesc; 1055ca632f55SGrant Likely 1056ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1057ca632f55SGrant Likely rxdesc->callback = dma_callback; 1058ca632f55SGrant Likely rxdesc->callback_param = pl022; 1059ca632f55SGrant Likely 1060ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1061ca632f55SGrant Likely dmaengine_submit(rxdesc); 1062ca632f55SGrant Likely dmaengine_submit(txdesc); 1063ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1064ca632f55SGrant Likely dma_async_issue_pending(txchan); 1065ffbbdd21SLinus Walleij pl022->dma_running = true; 1066ca632f55SGrant Likely 1067ca632f55SGrant Likely return 0; 1068ca632f55SGrant Likely 1069ca632f55SGrant Likely err_txdesc: 1070ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1071ca632f55SGrant Likely err_rxdesc: 1072ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1073ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1074ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1075ca632f55SGrant Likely err_tx_sgmap: 1076ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1077ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1078ca632f55SGrant Likely err_rx_sgmap: 1079ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1080ca632f55SGrant Likely err_alloc_tx_sg: 1081ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1082ca632f55SGrant Likely err_alloc_rx_sg: 1083ca632f55SGrant Likely return -ENOMEM; 1084ca632f55SGrant Likely } 1085ca632f55SGrant Likely 1086a5ab6291SRussell King static int __devinit pl022_dma_probe(struct pl022 *pl022) 1087ca632f55SGrant Likely { 1088ca632f55SGrant Likely dma_cap_mask_t mask; 1089ca632f55SGrant Likely 1090ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1091ca632f55SGrant Likely dma_cap_zero(mask); 1092ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1093ca632f55SGrant Likely /* 1094ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1095ca632f55SGrant Likely * of them. 1096ca632f55SGrant Likely */ 1097ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1098ca632f55SGrant Likely pl022->master_info->dma_filter, 1099ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1100ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1101ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1102ca632f55SGrant Likely goto err_no_rxchan; 1103ca632f55SGrant Likely } 1104ca632f55SGrant Likely 1105ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1106ca632f55SGrant Likely pl022->master_info->dma_filter, 1107ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1108ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1109ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1110ca632f55SGrant Likely goto err_no_txchan; 1111ca632f55SGrant Likely } 1112ca632f55SGrant Likely 1113ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1114ca632f55SGrant Likely if (!pl022->dummypage) { 1115ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1116ca632f55SGrant Likely goto err_no_dummypage; 1117ca632f55SGrant Likely } 1118ca632f55SGrant Likely 1119ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1120ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1121ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1122ca632f55SGrant Likely 1123ca632f55SGrant Likely return 0; 1124ca632f55SGrant Likely 1125ca632f55SGrant Likely err_no_dummypage: 1126ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1127ca632f55SGrant Likely err_no_txchan: 1128ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1129ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1130ca632f55SGrant Likely err_no_rxchan: 1131ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1132ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1133ca632f55SGrant Likely return -ENODEV; 1134ca632f55SGrant Likely } 1135ca632f55SGrant Likely 1136ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1137ca632f55SGrant Likely { 1138ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1139ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1140ca632f55SGrant Likely 1141ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1142ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1143ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1144ffbbdd21SLinus Walleij pl022->dma_running = false; 1145ca632f55SGrant Likely } 1146ca632f55SGrant Likely 1147ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1148ca632f55SGrant Likely { 1149ffbbdd21SLinus Walleij if (pl022->dma_running) 1150ca632f55SGrant Likely terminate_dma(pl022); 1151ca632f55SGrant Likely if (pl022->dma_tx_channel) 1152ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1153ca632f55SGrant Likely if (pl022->dma_rx_channel) 1154ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1155ca632f55SGrant Likely kfree(pl022->dummypage); 1156ca632f55SGrant Likely } 1157ca632f55SGrant Likely 1158ca632f55SGrant Likely #else 1159ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1160ca632f55SGrant Likely { 1161ca632f55SGrant Likely return -ENODEV; 1162ca632f55SGrant Likely } 1163ca632f55SGrant Likely 1164ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1165ca632f55SGrant Likely { 1166ca632f55SGrant Likely return 0; 1167ca632f55SGrant Likely } 1168ca632f55SGrant Likely 1169ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1170ca632f55SGrant Likely { 1171ca632f55SGrant Likely } 1172ca632f55SGrant Likely #endif 1173ca632f55SGrant Likely 1174ca632f55SGrant Likely /** 1175ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1176ca632f55SGrant Likely * 1177ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1178ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1179ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1180ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1181ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1182ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1183ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1184ca632f55SGrant Likely */ 1185ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1186ca632f55SGrant Likely { 1187ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1188ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1189ca632f55SGrant Likely u16 irq_status = 0; 1190ca632f55SGrant Likely u16 flag = 0; 1191ca632f55SGrant Likely 1192ca632f55SGrant Likely if (unlikely(!msg)) { 1193ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1194ca632f55SGrant Likely "bad message state in interrupt handler"); 1195ca632f55SGrant Likely /* Never fail */ 1196ca632f55SGrant Likely return IRQ_HANDLED; 1197ca632f55SGrant Likely } 1198ca632f55SGrant Likely 1199ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1200ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1201ca632f55SGrant Likely 1202ca632f55SGrant Likely if (unlikely(!irq_status)) 1203ca632f55SGrant Likely return IRQ_NONE; 1204ca632f55SGrant Likely 1205ca632f55SGrant Likely /* 1206ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1207ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1208ca632f55SGrant Likely * trusted. 1209ca632f55SGrant Likely */ 1210ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1211ca632f55SGrant Likely /* 1212ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1213ca632f55SGrant Likely * corrupted 1214ca632f55SGrant Likely */ 1215ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1216ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1217ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1218ca632f55SGrant Likely "RXFIFO is full\n"); 1219ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1220ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1221ca632f55SGrant Likely "TXFIFO is full\n"); 1222ca632f55SGrant Likely 1223ca632f55SGrant Likely /* 1224ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1225ca632f55SGrant Likely * mark message with bad status so it can be 1226ca632f55SGrant Likely * retried. 1227ca632f55SGrant Likely */ 1228ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1229ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1230ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1231ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1232ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1233ca632f55SGrant Likely msg->state = STATE_ERROR; 1234ca632f55SGrant Likely 1235ca632f55SGrant Likely /* Schedule message queue handler */ 1236ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1237ca632f55SGrant Likely return IRQ_HANDLED; 1238ca632f55SGrant Likely } 1239ca632f55SGrant Likely 1240ca632f55SGrant Likely readwriter(pl022); 1241ca632f55SGrant Likely 1242ca632f55SGrant Likely if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1243ca632f55SGrant Likely flag = 1; 1244172289dfSChris Blair /* Disable Transmit interrupt, enable receive interrupt */ 1245172289dfSChris Blair writew((readw(SSP_IMSC(pl022->virtbase)) & 1246172289dfSChris Blair ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1247ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1248ca632f55SGrant Likely } 1249ca632f55SGrant Likely 1250ca632f55SGrant Likely /* 1251ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1252ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1253ca632f55SGrant Likely * At this point, all TX will always be finished. 1254ca632f55SGrant Likely */ 1255ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1256ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1257ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1258ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1259ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1260ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1261ca632f55SGrant Likely "bytes (did you request an odd " 1262ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1263ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1264ca632f55SGrant Likely } 1265ca632f55SGrant Likely /* Update total bytes transferred */ 1266ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1267ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1268f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1269ca632f55SGrant Likely /* Move to next transfer */ 1270ca632f55SGrant Likely msg->state = next_transfer(pl022); 1271ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1272ca632f55SGrant Likely return IRQ_HANDLED; 1273ca632f55SGrant Likely } 1274ca632f55SGrant Likely 1275ca632f55SGrant Likely return IRQ_HANDLED; 1276ca632f55SGrant Likely } 1277ca632f55SGrant Likely 1278ca632f55SGrant Likely /** 1279ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1280ca632f55SGrant Likely * send out on the SPI bus. 1281ca632f55SGrant Likely */ 1282ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1283ca632f55SGrant Likely struct spi_transfer *transfer) 1284ca632f55SGrant Likely { 1285ca632f55SGrant Likely int residue; 1286ca632f55SGrant Likely 1287ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1288ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1289ca632f55SGrant Likely if (unlikely(residue != 0)) { 1290ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1291ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1292ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1293ca632f55SGrant Likely pl022->cur_transfer->len, 1294ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1295ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1296ca632f55SGrant Likely return -EIO; 1297ca632f55SGrant Likely } 1298ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1299ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1300ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1301ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1302ca632f55SGrant Likely pl022->write = 1303ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1304ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1305ca632f55SGrant Likely return 0; 1306ca632f55SGrant Likely } 1307ca632f55SGrant Likely 1308ca632f55SGrant Likely /** 1309ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1310ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1311ca632f55SGrant Likely * @data: SSP driver private data structure 1312ca632f55SGrant Likely * 1313ca632f55SGrant Likely */ 1314ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1315ca632f55SGrant Likely { 1316ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1317ca632f55SGrant Likely struct spi_message *message = NULL; 1318ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1319ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1320ca632f55SGrant Likely 1321ca632f55SGrant Likely /* Get current state information */ 1322ca632f55SGrant Likely message = pl022->cur_msg; 1323ca632f55SGrant Likely transfer = pl022->cur_transfer; 1324ca632f55SGrant Likely 1325ca632f55SGrant Likely /* Handle for abort */ 1326ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1327ca632f55SGrant Likely message->status = -EIO; 1328ca632f55SGrant Likely giveback(pl022); 1329ca632f55SGrant Likely return; 1330ca632f55SGrant Likely } 1331ca632f55SGrant Likely 1332ca632f55SGrant Likely /* Handle end of message */ 1333ca632f55SGrant Likely if (message->state == STATE_DONE) { 1334ca632f55SGrant Likely message->status = 0; 1335ca632f55SGrant Likely giveback(pl022); 1336ca632f55SGrant Likely return; 1337ca632f55SGrant Likely } 1338ca632f55SGrant Likely 1339ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1340ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1341ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1342ca632f55SGrant Likely struct spi_transfer, 1343ca632f55SGrant Likely transfer_list); 1344ca632f55SGrant Likely if (previous->delay_usecs) 1345ca632f55SGrant Likely /* 1346ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1347ca632f55SGrant Likely * Is this really smart? 1348ca632f55SGrant Likely */ 1349ca632f55SGrant Likely udelay(previous->delay_usecs); 1350ca632f55SGrant Likely 13518b8d7191SVirupax Sadashivpetimath /* Reselect chip select only if cs_change was requested */ 1352ca632f55SGrant Likely if (previous->cs_change) 1353f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1354ca632f55SGrant Likely } else { 1355ca632f55SGrant Likely /* STATE_START */ 1356ca632f55SGrant Likely message->state = STATE_RUNNING; 1357ca632f55SGrant Likely } 1358ca632f55SGrant Likely 1359ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1360ca632f55SGrant Likely message->state = STATE_ERROR; 1361ca632f55SGrant Likely message->status = -EIO; 1362ca632f55SGrant Likely giveback(pl022); 1363ca632f55SGrant Likely return; 1364ca632f55SGrant Likely } 1365ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1366ca632f55SGrant Likely flush(pl022); 1367ca632f55SGrant Likely 1368ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1369ca632f55SGrant Likely if (configure_dma(pl022)) { 1370ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1371ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1372ca632f55SGrant Likely goto err_config_dma; 1373ca632f55SGrant Likely } 1374ca632f55SGrant Likely return; 1375ca632f55SGrant Likely } 1376ca632f55SGrant Likely 1377ca632f55SGrant Likely err_config_dma: 1378172289dfSChris Blair /* enable all interrupts except RX */ 1379172289dfSChris Blair writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1380ca632f55SGrant Likely } 1381ca632f55SGrant Likely 1382ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1383ca632f55SGrant Likely { 1384172289dfSChris Blair /* 1385172289dfSChris Blair * Default is to enable all interrupts except RX - 1386172289dfSChris Blair * this will be enabled once TX is complete 1387172289dfSChris Blair */ 1388172289dfSChris Blair u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1389ca632f55SGrant Likely 13908b8d7191SVirupax Sadashivpetimath /* Enable target chip, if not already active */ 13918b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1392f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 13938b8d7191SVirupax Sadashivpetimath 1394ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1395ca632f55SGrant Likely /* Error path */ 1396ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1397ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1398ca632f55SGrant Likely giveback(pl022); 1399ca632f55SGrant Likely return; 1400ca632f55SGrant Likely } 1401ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1402ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1403ca632f55SGrant Likely /* Configure DMA transfer */ 1404ca632f55SGrant Likely if (configure_dma(pl022)) { 1405ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1406ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1407ca632f55SGrant Likely goto err_config_dma; 1408ca632f55SGrant Likely } 1409ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1410ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1411ca632f55SGrant Likely } 1412ca632f55SGrant Likely err_config_dma: 1413ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1414ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1415ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1416ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1417ca632f55SGrant Likely } 1418ca632f55SGrant Likely 1419ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1420ca632f55SGrant Likely { 1421ca632f55SGrant Likely struct spi_message *message = NULL; 1422ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1423ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1424ca632f55SGrant Likely struct chip_data *chip; 1425ca632f55SGrant Likely unsigned long time, timeout; 1426ca632f55SGrant Likely 1427ca632f55SGrant Likely chip = pl022->cur_chip; 1428ca632f55SGrant Likely message = pl022->cur_msg; 1429ca632f55SGrant Likely 1430ca632f55SGrant Likely while (message->state != STATE_DONE) { 1431ca632f55SGrant Likely /* Handle for abort */ 1432ca632f55SGrant Likely if (message->state == STATE_ERROR) 1433ca632f55SGrant Likely break; 1434ca632f55SGrant Likely transfer = pl022->cur_transfer; 1435ca632f55SGrant Likely 1436ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1437ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1438ca632f55SGrant Likely previous = 1439ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1440ca632f55SGrant Likely struct spi_transfer, transfer_list); 1441ca632f55SGrant Likely if (previous->delay_usecs) 1442ca632f55SGrant Likely udelay(previous->delay_usecs); 1443ca632f55SGrant Likely if (previous->cs_change) 1444f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1445ca632f55SGrant Likely } else { 1446ca632f55SGrant Likely /* STATE_START */ 1447ca632f55SGrant Likely message->state = STATE_RUNNING; 14488b8d7191SVirupax Sadashivpetimath if (!pl022->next_msg_cs_active) 1449f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_SELECT); 1450ca632f55SGrant Likely } 1451ca632f55SGrant Likely 1452ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1453ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1454ca632f55SGrant Likely /* Error path */ 1455ca632f55SGrant Likely message->state = STATE_ERROR; 1456ca632f55SGrant Likely break; 1457ca632f55SGrant Likely } 1458ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1459ca632f55SGrant Likely flush(pl022); 1460ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1461ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1462ca632f55SGrant Likely 1463ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1464ca632f55SGrant Likely 1465ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1466ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1467ca632f55SGrant Likely time = jiffies; 1468ca632f55SGrant Likely readwriter(pl022); 1469ca632f55SGrant Likely if (time_after(time, timeout)) { 1470ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1471ca632f55SGrant Likely "%s: timeout!\n", __func__); 1472ca632f55SGrant Likely message->state = STATE_ERROR; 1473ca632f55SGrant Likely goto out; 1474ca632f55SGrant Likely } 1475ca632f55SGrant Likely cpu_relax(); 1476ca632f55SGrant Likely } 1477ca632f55SGrant Likely 1478ca632f55SGrant Likely /* Update total byte transferred */ 1479ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1480ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1481f6f46de1SRoland Stigge pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1482ca632f55SGrant Likely /* Move to next transfer */ 1483ca632f55SGrant Likely message->state = next_transfer(pl022); 1484ca632f55SGrant Likely } 1485ca632f55SGrant Likely out: 1486ca632f55SGrant Likely /* Handle end of message */ 1487ca632f55SGrant Likely if (message->state == STATE_DONE) 1488ca632f55SGrant Likely message->status = 0; 1489ca632f55SGrant Likely else 1490ca632f55SGrant Likely message->status = -EIO; 1491ca632f55SGrant Likely 1492ca632f55SGrant Likely giveback(pl022); 1493ca632f55SGrant Likely return; 1494ca632f55SGrant Likely } 1495ca632f55SGrant Likely 1496ffbbdd21SLinus Walleij static int pl022_transfer_one_message(struct spi_master *master, 1497ffbbdd21SLinus Walleij struct spi_message *msg) 1498ca632f55SGrant Likely { 1499ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1500ca632f55SGrant Likely 1501ffbbdd21SLinus Walleij /* Initial message state */ 1502ffbbdd21SLinus Walleij pl022->cur_msg = msg; 1503ffbbdd21SLinus Walleij msg->state = STATE_START; 1504ffbbdd21SLinus Walleij 1505ffbbdd21SLinus Walleij pl022->cur_transfer = list_entry(msg->transfers.next, 1506ffbbdd21SLinus Walleij struct spi_transfer, transfer_list); 1507ffbbdd21SLinus Walleij 1508ffbbdd21SLinus Walleij /* Setup the SPI using the per chip configuration */ 1509ffbbdd21SLinus Walleij pl022->cur_chip = spi_get_ctldata(msg->spi); 1510f6f46de1SRoland Stigge pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1511ffbbdd21SLinus Walleij 1512ffbbdd21SLinus Walleij restore_state(pl022); 1513ffbbdd21SLinus Walleij flush(pl022); 1514ffbbdd21SLinus Walleij 1515ffbbdd21SLinus Walleij if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1516ffbbdd21SLinus Walleij do_polling_transfer(pl022); 1517ffbbdd21SLinus Walleij else 1518ffbbdd21SLinus Walleij do_interrupt_dma_transfer(pl022); 1519ffbbdd21SLinus Walleij 1520ffbbdd21SLinus Walleij return 0; 1521ffbbdd21SLinus Walleij } 1522ffbbdd21SLinus Walleij 1523ffbbdd21SLinus Walleij static int pl022_prepare_transfer_hardware(struct spi_master *master) 1524ffbbdd21SLinus Walleij { 1525ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1526ffbbdd21SLinus Walleij 1527ffbbdd21SLinus Walleij /* 1528ffbbdd21SLinus Walleij * Just make sure we have all we need to run the transfer by syncing 1529ffbbdd21SLinus Walleij * with the runtime PM framework. 1530ffbbdd21SLinus Walleij */ 1531ffbbdd21SLinus Walleij pm_runtime_get_sync(&pl022->adev->dev); 1532ffbbdd21SLinus Walleij return 0; 1533ffbbdd21SLinus Walleij } 1534ffbbdd21SLinus Walleij 1535ffbbdd21SLinus Walleij static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1536ffbbdd21SLinus Walleij { 1537ffbbdd21SLinus Walleij struct pl022 *pl022 = spi_master_get_devdata(master); 1538ffbbdd21SLinus Walleij 15390ad2deeaSVirupax Sadashivpetimath /* nothing more to do - disable spi/ssp and power off */ 15400ad2deeaSVirupax Sadashivpetimath writew((readw(SSP_CR1(pl022->virtbase)) & 15410ad2deeaSVirupax Sadashivpetimath (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 154253e4aceaSChris Blair 154353e4aceaSChris Blair if (pl022->master_info->autosuspend_delay > 0) { 154453e4aceaSChris Blair pm_runtime_mark_last_busy(&pl022->adev->dev); 154553e4aceaSChris Blair pm_runtime_put_autosuspend(&pl022->adev->dev); 154653e4aceaSChris Blair } else { 1547d4b6af2eSChris Blair pm_runtime_put(&pl022->adev->dev); 15480ad2deeaSVirupax Sadashivpetimath } 1549ca632f55SGrant Likely 1550ca632f55SGrant Likely return 0; 1551ca632f55SGrant Likely } 1552ca632f55SGrant Likely 1553ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1554ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1555ca632f55SGrant Likely { 1556ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1557ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1558ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1559ca632f55SGrant Likely "interface is configured incorrectly\n"); 1560ca632f55SGrant Likely return -EINVAL; 1561ca632f55SGrant Likely } 1562ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1563ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1564ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1565ca632f55SGrant Likely "unidirectional mode not supported in this " 1566ca632f55SGrant Likely "hardware version\n"); 1567ca632f55SGrant Likely return -EINVAL; 1568ca632f55SGrant Likely } 1569ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1570ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1571ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1572ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1573ca632f55SGrant Likely return -EINVAL; 1574ca632f55SGrant Likely } 1575ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1576ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1577ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1578ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1579ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1580ca632f55SGrant Likely return -EINVAL; 1581ca632f55SGrant Likely } 158278b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 158378b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 158478b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 158578b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 158678b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 158778b2b911SLinus Walleij break; 158878b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 158978b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1590ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1591ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1592ca632f55SGrant Likely return -EINVAL; 1593ca632f55SGrant Likely } 159478b2b911SLinus Walleij break; 159578b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 159678b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 159778b2b911SLinus Walleij dev_err(&pl022->adev->dev, 159878b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 159978b2b911SLinus Walleij return -EINVAL; 160078b2b911SLinus Walleij } 160178b2b911SLinus Walleij break; 160278b2b911SLinus Walleij default: 160378b2b911SLinus Walleij dev_err(&pl022->adev->dev, 160478b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 160578b2b911SLinus Walleij return -EINVAL; 160678b2b911SLinus Walleij break; 160778b2b911SLinus Walleij } 160878b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 160978b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 161078b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 161178b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 161278b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 161378b2b911SLinus Walleij break; 161478b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 161578b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1616ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1617ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1618ca632f55SGrant Likely return -EINVAL; 1619ca632f55SGrant Likely } 162078b2b911SLinus Walleij break; 162178b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 162278b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 162378b2b911SLinus Walleij dev_err(&pl022->adev->dev, 162478b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 162578b2b911SLinus Walleij return -EINVAL; 162678b2b911SLinus Walleij } 162778b2b911SLinus Walleij break; 162878b2b911SLinus Walleij default: 162978b2b911SLinus Walleij dev_err(&pl022->adev->dev, 163078b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 163178b2b911SLinus Walleij return -EINVAL; 163278b2b911SLinus Walleij break; 163378b2b911SLinus Walleij } 1634ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1635ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1636ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1637ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1638ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1639ca632f55SGrant Likely return -EINVAL; 1640ca632f55SGrant Likely } 1641ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1642ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1643ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1644ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1645ca632f55SGrant Likely return -EINVAL; 1646ca632f55SGrant Likely } 1647ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1648ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1649ca632f55SGrant Likely if ((chip_info->duplex != 1650ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1651ca632f55SGrant Likely && (chip_info->duplex != 1652ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1653ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1654ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1655ca632f55SGrant Likely return -EINVAL; 1656ca632f55SGrant Likely } 1657ca632f55SGrant Likely } else { 1658ca632f55SGrant Likely if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1659ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1660ca632f55SGrant Likely "Microwire half duplex mode requested," 1661ca632f55SGrant Likely " but this is only available in the" 1662ca632f55SGrant Likely " ST version of PL022\n"); 1663ca632f55SGrant Likely return -EINVAL; 1664ca632f55SGrant Likely } 1665ca632f55SGrant Likely } 1666ca632f55SGrant Likely return 0; 1667ca632f55SGrant Likely } 1668ca632f55SGrant Likely 16690379b2a3SViresh Kumar static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 16700379b2a3SViresh Kumar { 16710379b2a3SViresh Kumar return rate / (cpsdvsr * (1 + scr)); 16720379b2a3SViresh Kumar } 16730379b2a3SViresh Kumar 16740379b2a3SViresh Kumar static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 16750379b2a3SViresh Kumar ssp_clock_params * clk_freq) 1676ca632f55SGrant Likely { 1677ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 16780379b2a3SViresh Kumar u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 16790379b2a3SViresh Kumar u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 16800379b2a3SViresh Kumar best_scr = 0, tmp, found = 0; 1681ca632f55SGrant Likely 1682ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1683ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 16840379b2a3SViresh Kumar max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1685ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 16860379b2a3SViresh Kumar min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1687ca632f55SGrant Likely 1688ea505bc9SViresh Kumar if (freq > max_tclk) 1689ea505bc9SViresh Kumar dev_warn(&pl022->adev->dev, 1690ea505bc9SViresh Kumar "Max speed that can be programmed is %d Hz, you requested %d\n", 1691ea505bc9SViresh Kumar max_tclk, freq); 1692ea505bc9SViresh Kumar 1693ea505bc9SViresh Kumar if (freq < min_tclk) { 1694ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1695ea505bc9SViresh Kumar "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1696ea505bc9SViresh Kumar freq, min_tclk); 1697ca632f55SGrant Likely return -EINVAL; 1698ca632f55SGrant Likely } 16990379b2a3SViresh Kumar 17000379b2a3SViresh Kumar /* 17010379b2a3SViresh Kumar * best_freq will give closest possible available rate (<= requested 17020379b2a3SViresh Kumar * freq) for all values of scr & cpsdvsr. 17030379b2a3SViresh Kumar */ 17040379b2a3SViresh Kumar while ((cpsdvsr <= CPSDVR_MAX) && !found) { 17050379b2a3SViresh Kumar while (scr <= SCR_MAX) { 17060379b2a3SViresh Kumar tmp = spi_rate(rate, cpsdvsr, scr); 17070379b2a3SViresh Kumar 17085eb806a3SViresh Kumar if (tmp > freq) { 17095eb806a3SViresh Kumar /* we need lower freq */ 17100379b2a3SViresh Kumar scr++; 17115eb806a3SViresh Kumar continue; 17125eb806a3SViresh Kumar } 17135eb806a3SViresh Kumar 17140379b2a3SViresh Kumar /* 17155eb806a3SViresh Kumar * If found exact value, mark found and break. 17165eb806a3SViresh Kumar * If found more closer value, update and break. 17170379b2a3SViresh Kumar */ 17185eb806a3SViresh Kumar if (tmp > best_freq) { 17190379b2a3SViresh Kumar best_freq = tmp; 17200379b2a3SViresh Kumar best_cpsdvsr = cpsdvsr; 17210379b2a3SViresh Kumar best_scr = scr; 17220379b2a3SViresh Kumar 17230379b2a3SViresh Kumar if (tmp == freq) 17245eb806a3SViresh Kumar found = 1; 17250379b2a3SViresh Kumar } 17265eb806a3SViresh Kumar /* 17275eb806a3SViresh Kumar * increased scr will give lower rates, which are not 17285eb806a3SViresh Kumar * required 17295eb806a3SViresh Kumar */ 17305eb806a3SViresh Kumar break; 17310379b2a3SViresh Kumar } 17320379b2a3SViresh Kumar cpsdvsr += 2; 17330379b2a3SViresh Kumar scr = SCR_MIN; 1734ca632f55SGrant Likely } 1735ca632f55SGrant Likely 17365eb806a3SViresh Kumar WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 17375eb806a3SViresh Kumar freq); 17385eb806a3SViresh Kumar 17390379b2a3SViresh Kumar clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 17400379b2a3SViresh Kumar clk_freq->scr = (u8) (best_scr & 0xFF); 17410379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, 17420379b2a3SViresh Kumar "SSP Target Frequency is: %u, Effective Frequency is %u\n", 17430379b2a3SViresh Kumar freq, best_freq); 17440379b2a3SViresh Kumar dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 17450379b2a3SViresh Kumar clk_freq->cpsdvsr, clk_freq->scr); 17460379b2a3SViresh Kumar 1747ca632f55SGrant Likely return 0; 1748ca632f55SGrant Likely } 1749ca632f55SGrant Likely 1750ca632f55SGrant Likely /* 1751ca632f55SGrant Likely * A piece of default chip info unless the platform 1752ca632f55SGrant Likely * supplies it. 1753ca632f55SGrant Likely */ 1754ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1755ca632f55SGrant Likely .com_mode = POLLING_TRANSFER, 1756ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1757ca632f55SGrant Likely .hierarchy = SSP_SLAVE, 1758ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1759ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1760ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1761ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1762ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1763ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1764ca632f55SGrant Likely .cs_control = null_cs_control, 1765ca632f55SGrant Likely }; 1766ca632f55SGrant Likely 1767ca632f55SGrant Likely /** 1768ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1769ca632f55SGrant Likely * @spi: spi device which is requesting setup 1770ca632f55SGrant Likely * 1771ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1772ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1773ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1774ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1775ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1776ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1777ca632f55SGrant Likely * commence. 1778ca632f55SGrant Likely */ 1779ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1780ca632f55SGrant Likely { 1781ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 17826d3952a7SRoland Stigge struct pl022_config_chip chip_info_dt; 1783ca632f55SGrant Likely struct chip_data *chip; 1784c4a47843SJonas Aaberg struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1785ca632f55SGrant Likely int status = 0; 1786ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1787ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1788ca632f55SGrant Likely u32 tmp; 17896d3952a7SRoland Stigge struct device_node *np = spi->dev.of_node; 1790ca632f55SGrant Likely 1791ca632f55SGrant Likely if (!spi->max_speed_hz) 1792ca632f55SGrant Likely return -EINVAL; 1793ca632f55SGrant Likely 1794ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1795ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1796ca632f55SGrant Likely 1797ca632f55SGrant Likely if (chip == NULL) { 1798ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1799ca632f55SGrant Likely if (!chip) { 1800ca632f55SGrant Likely dev_err(&spi->dev, 1801ca632f55SGrant Likely "cannot allocate controller state\n"); 1802ca632f55SGrant Likely return -ENOMEM; 1803ca632f55SGrant Likely } 1804ca632f55SGrant Likely dev_dbg(&spi->dev, 1805ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1806ca632f55SGrant Likely } 1807ca632f55SGrant Likely 1808ca632f55SGrant Likely /* Get controller data if one is supplied */ 1809ca632f55SGrant Likely chip_info = spi->controller_data; 1810ca632f55SGrant Likely 1811ca632f55SGrant Likely if (chip_info == NULL) { 18126d3952a7SRoland Stigge if (np) { 18136d3952a7SRoland Stigge chip_info_dt = pl022_default_chip_info; 18146d3952a7SRoland Stigge 18156d3952a7SRoland Stigge chip_info_dt.hierarchy = SSP_MASTER; 18166d3952a7SRoland Stigge of_property_read_u32(np, "pl022,interface", 18176d3952a7SRoland Stigge &chip_info_dt.iface); 18186d3952a7SRoland Stigge of_property_read_u32(np, "pl022,com-mode", 18196d3952a7SRoland Stigge &chip_info_dt.com_mode); 18206d3952a7SRoland Stigge of_property_read_u32(np, "pl022,rx-level-trig", 18216d3952a7SRoland Stigge &chip_info_dt.rx_lev_trig); 18226d3952a7SRoland Stigge of_property_read_u32(np, "pl022,tx-level-trig", 18236d3952a7SRoland Stigge &chip_info_dt.tx_lev_trig); 18246d3952a7SRoland Stigge of_property_read_u32(np, "pl022,ctrl-len", 18256d3952a7SRoland Stigge &chip_info_dt.ctrl_len); 18266d3952a7SRoland Stigge of_property_read_u32(np, "pl022,wait-state", 18276d3952a7SRoland Stigge &chip_info_dt.wait_state); 18286d3952a7SRoland Stigge of_property_read_u32(np, "pl022,duplex", 18296d3952a7SRoland Stigge &chip_info_dt.duplex); 18306d3952a7SRoland Stigge 18316d3952a7SRoland Stigge chip_info = &chip_info_dt; 18326d3952a7SRoland Stigge } else { 1833ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1834ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1835ca632f55SGrant Likely dev_dbg(&spi->dev, 1836ca632f55SGrant Likely "using default controller_data settings\n"); 18376d3952a7SRoland Stigge } 1838ca632f55SGrant Likely } else 1839ca632f55SGrant Likely dev_dbg(&spi->dev, 1840ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1841ca632f55SGrant Likely 1842ca632f55SGrant Likely /* 1843ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1844ca632f55SGrant Likely * frequency setting 1845ca632f55SGrant Likely */ 1846ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1847ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1848ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1849ca632f55SGrant Likely spi->max_speed_hz, 1850ca632f55SGrant Likely &clk_freq); 1851ca632f55SGrant Likely if (status < 0) 1852ca632f55SGrant Likely goto err_config_params; 1853ca632f55SGrant Likely } else { 1854ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1855ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1856ca632f55SGrant Likely clk_freq.cpsdvsr = 1857ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1858ca632f55SGrant Likely } 1859ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1860ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1861f8db4cc4SGrant Likely status = -EINVAL; 1862ca632f55SGrant Likely dev_err(&spi->dev, 1863ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1864ca632f55SGrant Likely goto err_config_params; 1865ca632f55SGrant Likely } 1866ca632f55SGrant Likely 1867ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1868ca632f55SGrant Likely if (status) { 1869ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1870ca632f55SGrant Likely goto err_config_params; 1871ca632f55SGrant Likely } 1872ca632f55SGrant Likely 1873083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1874083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1875083be3f0SLinus Walleij 1876ca632f55SGrant Likely /* Now set controller state based on controller data */ 1877ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1878ca632f55SGrant Likely if (!chip_info->cs_control) { 1879ca632f55SGrant Likely chip->cs_control = null_cs_control; 1880f6f46de1SRoland Stigge if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1881ca632f55SGrant Likely dev_warn(&spi->dev, 1882f6f46de1SRoland Stigge "invalid chip select\n"); 1883ca632f55SGrant Likely } else 1884ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1885ca632f55SGrant Likely 1886eb798c64SVinit Shenoy /* Check bits per word with vendor specific range */ 1887eb798c64SVinit Shenoy if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1888ca632f55SGrant Likely status = -ENOTSUPP; 1889eb798c64SVinit Shenoy dev_err(&spi->dev, "illegal data size for this controller!\n"); 1890eb798c64SVinit Shenoy dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1891eb798c64SVinit Shenoy pl022->vendor->max_bpw); 1892ca632f55SGrant Likely goto err_config_params; 1893ca632f55SGrant Likely } else if (bits <= 8) { 1894ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1895ca632f55SGrant Likely chip->n_bytes = 1; 1896ca632f55SGrant Likely chip->read = READING_U8; 1897ca632f55SGrant Likely chip->write = WRITING_U8; 1898ca632f55SGrant Likely } else if (bits <= 16) { 1899ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1900ca632f55SGrant Likely chip->n_bytes = 2; 1901ca632f55SGrant Likely chip->read = READING_U16; 1902ca632f55SGrant Likely chip->write = WRITING_U16; 1903ca632f55SGrant Likely } else { 1904ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1905ca632f55SGrant Likely chip->n_bytes = 4; 1906ca632f55SGrant Likely chip->read = READING_U32; 1907ca632f55SGrant Likely chip->write = WRITING_U32; 1908ca632f55SGrant Likely } 1909ca632f55SGrant Likely 1910ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 1911ca632f55SGrant Likely chip->cr0 = 0; 1912ca632f55SGrant Likely chip->cr1 = 0; 1913ca632f55SGrant Likely chip->dmacr = 0; 1914ca632f55SGrant Likely chip->cpsr = 0; 1915ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 1916ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 1917ca632f55SGrant Likely chip->enable_dma = true; 1918ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1919ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1920ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1921ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1922ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1923ca632f55SGrant Likely } else { 1924ca632f55SGrant Likely chip->enable_dma = false; 1925ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1926ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1927ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 1928ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1929ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 1930ca632f55SGrant Likely } 1931ca632f55SGrant Likely 1932ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 1933ca632f55SGrant Likely 1934ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 1935ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1936ca632f55SGrant Likely u32 etx; 1937ca632f55SGrant Likely 1938ca632f55SGrant Likely if (pl022->vendor->pl023) { 1939ca632f55SGrant Likely /* These bits are only in the PL023 */ 1940ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1941ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 1942ca632f55SGrant Likely } else { 1943ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 1944ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1945ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 1946ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1947ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 1948ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1949ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 1950ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1951ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 1952ca632f55SGrant Likely } 1953ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 1954ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 1955ca632f55SGrant Likely 1956ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 1957ca632f55SGrant Likely tmp = SSP_RX_LSB; 1958ca632f55SGrant Likely etx = SSP_TX_LSB; 1959ca632f55SGrant Likely } else { 1960ca632f55SGrant Likely tmp = SSP_RX_MSB; 1961ca632f55SGrant Likely etx = SSP_TX_MSB; 1962ca632f55SGrant Likely } 1963ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1964ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1965ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1966ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 1967ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1968ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 1969ca632f55SGrant Likely } else { 1970ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 1971ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 1972ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1973ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 1974ca632f55SGrant Likely } 1975ca632f55SGrant Likely 1976ca632f55SGrant Likely /* Stuff that is common for all versions */ 1977ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 1978ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 1979ca632f55SGrant Likely else 1980ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 1981ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1982ca632f55SGrant Likely 1983ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 1984ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 1985ca632f55SGrant Likely else 1986ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 1987ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 1988ca632f55SGrant Likely 1989ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1990ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 1991ca632f55SGrant Likely if (pl022->vendor->loopback) { 1992ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 1993ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 1994ca632f55SGrant Likely else 1995ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 1996ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 1997ca632f55SGrant Likely } 1998ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 1999ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2000f1e45f86SViresh Kumar SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2001f1e45f86SViresh Kumar 3); 2002ca632f55SGrant Likely 2003ca632f55SGrant Likely /* Save controller_state */ 2004ca632f55SGrant Likely spi_set_ctldata(spi, chip); 2005ca632f55SGrant Likely return status; 2006ca632f55SGrant Likely err_config_params: 2007ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2008ca632f55SGrant Likely kfree(chip); 2009ca632f55SGrant Likely return status; 2010ca632f55SGrant Likely } 2011ca632f55SGrant Likely 2012ca632f55SGrant Likely /** 2013ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 2014ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 2015ca632f55SGrant Likely * 2016ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 2017ca632f55SGrant Likely * controller. It will free the runtime state of chip. 2018ca632f55SGrant Likely */ 2019ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 2020ca632f55SGrant Likely { 2021ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 2022ca632f55SGrant Likely 2023ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2024ca632f55SGrant Likely kfree(chip); 2025ca632f55SGrant Likely } 2026ca632f55SGrant Likely 2027ca632f55SGrant Likely static int __devinit 2028ca632f55SGrant Likely pl022_probe(struct amba_device *adev, const struct amba_id *id) 2029ca632f55SGrant Likely { 2030ca632f55SGrant Likely struct device *dev = &adev->dev; 2031ca632f55SGrant Likely struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2032ca632f55SGrant Likely struct spi_master *master; 2033ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 20346d3952a7SRoland Stigge struct device_node *np = adev->dev.of_node; 20356d3952a7SRoland Stigge int status = 0, i, num_cs; 2036ca632f55SGrant Likely 2037ca632f55SGrant Likely dev_info(&adev->dev, 2038ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2039ca632f55SGrant Likely if (platform_info == NULL) { 2040ca632f55SGrant Likely dev_err(&adev->dev, "probe - no platform data supplied\n"); 2041ca632f55SGrant Likely status = -ENODEV; 2042ca632f55SGrant Likely goto err_no_pdata; 2043ca632f55SGrant Likely } 2044ca632f55SGrant Likely 20456d3952a7SRoland Stigge if (platform_info->num_chipselect) { 20466d3952a7SRoland Stigge num_cs = platform_info->num_chipselect; 20476d3952a7SRoland Stigge } else if (IS_ENABLED(CONFIG_OF)) { 20486d3952a7SRoland Stigge of_property_read_u32(np, "num-cs", &num_cs); 20496d3952a7SRoland Stigge } else { 20506d3952a7SRoland Stigge dev_err(&adev->dev, "probe: no chip select defined\n"); 20516d3952a7SRoland Stigge status = -ENODEV; 20526d3952a7SRoland Stigge goto err_no_pdata; 20536d3952a7SRoland Stigge } 20546d3952a7SRoland Stigge 2055ca632f55SGrant Likely /* Allocate master with space for data */ 2056*b4b84826SRoland Stigge master = spi_alloc_master(dev, sizeof(struct pl022)); 2057ca632f55SGrant Likely if (master == NULL) { 2058ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2059ca632f55SGrant Likely status = -ENOMEM; 2060ca632f55SGrant Likely goto err_no_master; 2061ca632f55SGrant Likely } 2062ca632f55SGrant Likely 2063ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 2064ca632f55SGrant Likely pl022->master = master; 2065ca632f55SGrant Likely pl022->master_info = platform_info; 2066ca632f55SGrant Likely pl022->adev = adev; 2067ca632f55SGrant Likely pl022->vendor = id->data; 2068*b4b84826SRoland Stigge pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2069*b4b84826SRoland Stigge GFP_KERNEL); 2070ca632f55SGrant Likely 2071ca632f55SGrant Likely /* 2072ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2073ca632f55SGrant Likely * on this board 2074ca632f55SGrant Likely */ 2075ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 20766d3952a7SRoland Stigge master->num_chipselect = num_cs; 2077ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2078ca632f55SGrant Likely master->setup = pl022_setup; 2079ffbbdd21SLinus Walleij master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2080ffbbdd21SLinus Walleij master->transfer_one_message = pl022_transfer_one_message; 2081ffbbdd21SLinus Walleij master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2082ffbbdd21SLinus Walleij master->rt = platform_info->rt; 20836d3952a7SRoland Stigge master->dev.of_node = dev->of_node; 2084ca632f55SGrant Likely 20856d3952a7SRoland Stigge if (platform_info->num_chipselect && platform_info->chipselects) { 20866d3952a7SRoland Stigge for (i = 0; i < num_cs; i++) 2087f6f46de1SRoland Stigge pl022->chipselects[i] = platform_info->chipselects[i]; 20886d3952a7SRoland Stigge } else if (IS_ENABLED(CONFIG_OF)) { 20896d3952a7SRoland Stigge for (i = 0; i < num_cs; i++) { 20906d3952a7SRoland Stigge int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 20916d3952a7SRoland Stigge 20926d3952a7SRoland Stigge if (cs_gpio == -EPROBE_DEFER) { 20936d3952a7SRoland Stigge status = -EPROBE_DEFER; 20946d3952a7SRoland Stigge goto err_no_gpio; 20956d3952a7SRoland Stigge } 20966d3952a7SRoland Stigge 20976d3952a7SRoland Stigge pl022->chipselects[i] = cs_gpio; 20986d3952a7SRoland Stigge 20996d3952a7SRoland Stigge if (gpio_is_valid(cs_gpio)) { 21006d3952a7SRoland Stigge if (gpio_request(cs_gpio, "ssp-pl022")) 21016d3952a7SRoland Stigge dev_err(&adev->dev, 21026d3952a7SRoland Stigge "could not request %d gpio\n", 21036d3952a7SRoland Stigge cs_gpio); 21046d3952a7SRoland Stigge else if (gpio_direction_output(cs_gpio, 1)) 21056d3952a7SRoland Stigge dev_err(&adev->dev, 21066d3952a7SRoland Stigge "could set gpio %d as output\n", 21076d3952a7SRoland Stigge cs_gpio); 21086d3952a7SRoland Stigge } 21096d3952a7SRoland Stigge } 21106d3952a7SRoland Stigge } 2111f6f46de1SRoland Stigge 2112ca632f55SGrant Likely /* 2113ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2114ca632f55SGrant Likely * always MS bit first on the original pl022. 2115ca632f55SGrant Likely */ 2116ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2117ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2118ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2119ca632f55SGrant Likely 2120ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2121ca632f55SGrant Likely 2122ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2123ca632f55SGrant Likely if (status) 2124ca632f55SGrant Likely goto err_no_ioregion; 2125ca632f55SGrant Likely 2126ca632f55SGrant Likely pl022->phybase = adev->res.start; 2127ca632f55SGrant Likely pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2128ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2129ca632f55SGrant Likely status = -ENOMEM; 2130ca632f55SGrant Likely goto err_no_ioremap; 2131ca632f55SGrant Likely } 2132ca632f55SGrant Likely printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2133ca632f55SGrant Likely adev->res.start, pl022->virtbase); 2134ca632f55SGrant Likely 21352fb30d11SLinus Walleij pm_runtime_enable(dev); 21362fb30d11SLinus Walleij pm_runtime_resume(dev); 21372fb30d11SLinus Walleij 2138ca632f55SGrant Likely pl022->clk = clk_get(&adev->dev, NULL); 2139ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2140ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2141ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2142ca632f55SGrant Likely goto err_no_clk; 2143ca632f55SGrant Likely } 21447ff6bcf0SRussell King 21457ff6bcf0SRussell King status = clk_prepare(pl022->clk); 21467ff6bcf0SRussell King if (status) { 21477ff6bcf0SRussell King dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 21487ff6bcf0SRussell King goto err_clk_prep; 21497ff6bcf0SRussell King } 21507ff6bcf0SRussell King 215171e63e74SUlf Hansson status = clk_enable(pl022->clk); 215271e63e74SUlf Hansson if (status) { 215371e63e74SUlf Hansson dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 215471e63e74SUlf Hansson goto err_no_clk_en; 215571e63e74SUlf Hansson } 215671e63e74SUlf Hansson 2157ffbbdd21SLinus Walleij /* Initialize transfer pump */ 2158ffbbdd21SLinus Walleij tasklet_init(&pl022->pump_transfers, pump_transfers, 2159ffbbdd21SLinus Walleij (unsigned long)pl022); 2160ffbbdd21SLinus Walleij 2161ca632f55SGrant Likely /* Disable SSP */ 2162ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2163ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2164ca632f55SGrant Likely load_ssp_default_config(pl022); 2165ca632f55SGrant Likely 2166ca632f55SGrant Likely status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2167ca632f55SGrant Likely pl022); 2168ca632f55SGrant Likely if (status < 0) { 2169ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2170ca632f55SGrant Likely goto err_no_irq; 2171ca632f55SGrant Likely } 2172ca632f55SGrant Likely 2173ca632f55SGrant Likely /* Get DMA channels */ 2174ca632f55SGrant Likely if (platform_info->enable_dma) { 2175ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2176ca632f55SGrant Likely if (status != 0) 2177ca632f55SGrant Likely platform_info->enable_dma = 0; 2178ca632f55SGrant Likely } 2179ca632f55SGrant Likely 2180ca632f55SGrant Likely /* Register with the SPI framework */ 2181ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 2182ca632f55SGrant Likely status = spi_register_master(master); 2183ca632f55SGrant Likely if (status != 0) { 2184ca632f55SGrant Likely dev_err(&adev->dev, 2185ca632f55SGrant Likely "probe - problem registering spi master\n"); 2186ca632f55SGrant Likely goto err_spi_register; 2187ca632f55SGrant Likely } 2188ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 218992b97f0aSRussell King 219092b97f0aSRussell King /* let runtime pm put suspend */ 219153e4aceaSChris Blair if (platform_info->autosuspend_delay > 0) { 219253e4aceaSChris Blair dev_info(&adev->dev, 219353e4aceaSChris Blair "will use autosuspend for runtime pm, delay %dms\n", 219453e4aceaSChris Blair platform_info->autosuspend_delay); 219553e4aceaSChris Blair pm_runtime_set_autosuspend_delay(dev, 219653e4aceaSChris Blair platform_info->autosuspend_delay); 219753e4aceaSChris Blair pm_runtime_use_autosuspend(dev); 219853e4aceaSChris Blair pm_runtime_put_autosuspend(dev); 219953e4aceaSChris Blair } else { 220092b97f0aSRussell King pm_runtime_put(dev); 220153e4aceaSChris Blair } 2202ca632f55SGrant Likely return 0; 2203ca632f55SGrant Likely 2204ca632f55SGrant Likely err_spi_register: 22053e3ea716SViresh Kumar if (platform_info->enable_dma) 2206ca632f55SGrant Likely pl022_dma_remove(pl022); 22073e3ea716SViresh Kumar 2208ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2209ca632f55SGrant Likely err_no_irq: 221071e63e74SUlf Hansson clk_disable(pl022->clk); 221171e63e74SUlf Hansson err_no_clk_en: 22127ff6bcf0SRussell King clk_unprepare(pl022->clk); 22137ff6bcf0SRussell King err_clk_prep: 2214ca632f55SGrant Likely clk_put(pl022->clk); 2215ca632f55SGrant Likely err_no_clk: 2216ca632f55SGrant Likely iounmap(pl022->virtbase); 2217ca632f55SGrant Likely err_no_ioremap: 2218ca632f55SGrant Likely amba_release_regions(adev); 2219ca632f55SGrant Likely err_no_ioregion: 22206d3952a7SRoland Stigge err_no_gpio: 2221ca632f55SGrant Likely spi_master_put(master); 2222ca632f55SGrant Likely err_no_master: 2223ca632f55SGrant Likely err_no_pdata: 2224ca632f55SGrant Likely return status; 2225ca632f55SGrant Likely } 2226ca632f55SGrant Likely 2227ca632f55SGrant Likely static int __devexit 2228ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2229ca632f55SGrant Likely { 2230ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 223150658b66SLinus Walleij 2232ca632f55SGrant Likely if (!pl022) 2233ca632f55SGrant Likely return 0; 2234ca632f55SGrant Likely 223592b97f0aSRussell King /* 223692b97f0aSRussell King * undo pm_runtime_put() in probe. I assume that we're not 223792b97f0aSRussell King * accessing the primecell here. 223892b97f0aSRussell King */ 223992b97f0aSRussell King pm_runtime_get_noresume(&adev->dev); 224092b97f0aSRussell King 2241ca632f55SGrant Likely load_ssp_default_config(pl022); 22423e3ea716SViresh Kumar if (pl022->master_info->enable_dma) 2243ca632f55SGrant Likely pl022_dma_remove(pl022); 22443e3ea716SViresh Kumar 2245ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2246ca632f55SGrant Likely clk_disable(pl022->clk); 22477ff6bcf0SRussell King clk_unprepare(pl022->clk); 2248ca632f55SGrant Likely clk_put(pl022->clk); 22492fb30d11SLinus Walleij pm_runtime_disable(&adev->dev); 2250ca632f55SGrant Likely iounmap(pl022->virtbase); 2251ca632f55SGrant Likely amba_release_regions(adev); 2252ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2253ca632f55SGrant Likely spi_unregister_master(pl022->master); 2254ca632f55SGrant Likely amba_set_drvdata(adev, NULL); 2255ca632f55SGrant Likely return 0; 2256ca632f55SGrant Likely } 2257ca632f55SGrant Likely 225892b97f0aSRussell King #ifdef CONFIG_SUSPEND 22596cfa6279SPeter Hüwe static int pl022_suspend(struct device *dev) 2260ca632f55SGrant Likely { 226192b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2262ffbbdd21SLinus Walleij int ret; 2263ca632f55SGrant Likely 2264ffbbdd21SLinus Walleij ret = spi_master_suspend(pl022->master); 2265ffbbdd21SLinus Walleij if (ret) { 2266ffbbdd21SLinus Walleij dev_warn(dev, "cannot suspend master\n"); 2267ffbbdd21SLinus Walleij return ret; 2268ca632f55SGrant Likely } 2269ca632f55SGrant Likely 22706cfa6279SPeter Hüwe dev_dbg(dev, "suspended\n"); 2271ca632f55SGrant Likely return 0; 2272ca632f55SGrant Likely } 2273ca632f55SGrant Likely 227492b97f0aSRussell King static int pl022_resume(struct device *dev) 2275ca632f55SGrant Likely { 227692b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 2277ffbbdd21SLinus Walleij int ret; 2278ca632f55SGrant Likely 2279ca632f55SGrant Likely /* Start the queue running */ 2280ffbbdd21SLinus Walleij ret = spi_master_resume(pl022->master); 2281ffbbdd21SLinus Walleij if (ret) 2282ffbbdd21SLinus Walleij dev_err(dev, "problem starting queue (%d)\n", ret); 2283ca632f55SGrant Likely else 228492b97f0aSRussell King dev_dbg(dev, "resumed\n"); 2285ca632f55SGrant Likely 2286ffbbdd21SLinus Walleij return ret; 2287ca632f55SGrant Likely } 2288ca632f55SGrant Likely #endif /* CONFIG_PM */ 2289ca632f55SGrant Likely 229092b97f0aSRussell King #ifdef CONFIG_PM_RUNTIME 229192b97f0aSRussell King static int pl022_runtime_suspend(struct device *dev) 229292b97f0aSRussell King { 229392b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 229492b97f0aSRussell King 229592b97f0aSRussell King clk_disable(pl022->clk); 229692b97f0aSRussell King 229792b97f0aSRussell King return 0; 229892b97f0aSRussell King } 229992b97f0aSRussell King 230092b97f0aSRussell King static int pl022_runtime_resume(struct device *dev) 230192b97f0aSRussell King { 230292b97f0aSRussell King struct pl022 *pl022 = dev_get_drvdata(dev); 230392b97f0aSRussell King 230492b97f0aSRussell King clk_enable(pl022->clk); 230592b97f0aSRussell King 230692b97f0aSRussell King return 0; 230792b97f0aSRussell King } 230892b97f0aSRussell King #endif 230992b97f0aSRussell King 231092b97f0aSRussell King static const struct dev_pm_ops pl022_dev_pm_ops = { 231192b97f0aSRussell King SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 231292b97f0aSRussell King SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 231392b97f0aSRussell King }; 231492b97f0aSRussell King 2315ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2316ca632f55SGrant Likely .fifodepth = 8, 2317ca632f55SGrant Likely .max_bpw = 16, 2318ca632f55SGrant Likely .unidir = false, 2319ca632f55SGrant Likely .extended_cr = false, 2320ca632f55SGrant Likely .pl023 = false, 2321ca632f55SGrant Likely .loopback = true, 2322ca632f55SGrant Likely }; 2323ca632f55SGrant Likely 2324ca632f55SGrant Likely static struct vendor_data vendor_st = { 2325ca632f55SGrant Likely .fifodepth = 32, 2326ca632f55SGrant Likely .max_bpw = 32, 2327ca632f55SGrant Likely .unidir = false, 2328ca632f55SGrant Likely .extended_cr = true, 2329ca632f55SGrant Likely .pl023 = false, 2330ca632f55SGrant Likely .loopback = true, 2331ca632f55SGrant Likely }; 2332ca632f55SGrant Likely 2333ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2334ca632f55SGrant Likely .fifodepth = 32, 2335ca632f55SGrant Likely .max_bpw = 32, 2336ca632f55SGrant Likely .unidir = false, 2337ca632f55SGrant Likely .extended_cr = true, 2338ca632f55SGrant Likely .pl023 = true, 2339ca632f55SGrant Likely .loopback = false, 2340ca632f55SGrant Likely }; 2341ca632f55SGrant Likely 2342ca632f55SGrant Likely static struct amba_id pl022_ids[] = { 2343ca632f55SGrant Likely { 2344ca632f55SGrant Likely /* 2345ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2346ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2347ca632f55SGrant Likely */ 2348ca632f55SGrant Likely .id = 0x00041022, 2349ca632f55SGrant Likely .mask = 0x000fffff, 2350ca632f55SGrant Likely .data = &vendor_arm, 2351ca632f55SGrant Likely }, 2352ca632f55SGrant Likely { 2353ca632f55SGrant Likely /* 2354ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2355ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2356ca632f55SGrant Likely */ 2357ca632f55SGrant Likely .id = 0x01080022, 2358ca632f55SGrant Likely .mask = 0xffffffff, 2359ca632f55SGrant Likely .data = &vendor_st, 2360ca632f55SGrant Likely }, 2361ca632f55SGrant Likely { 2362ca632f55SGrant Likely /* 2363ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2364ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2365ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2366ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2367ca632f55SGrant Likely * CR0/CR1 register 2368ca632f55SGrant Likely */ 2369ca632f55SGrant Likely .id = 0x00080023, 2370ca632f55SGrant Likely .mask = 0xffffffff, 2371ca632f55SGrant Likely .data = &vendor_st_pl023, 2372ca632f55SGrant Likely }, 2373ca632f55SGrant Likely { 0, 0 }, 2374ca632f55SGrant Likely }; 2375ca632f55SGrant Likely 23767eeac71bSDave Martin MODULE_DEVICE_TABLE(amba, pl022_ids); 23777eeac71bSDave Martin 2378ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2379ca632f55SGrant Likely .drv = { 2380ca632f55SGrant Likely .name = "ssp-pl022", 238192b97f0aSRussell King .pm = &pl022_dev_pm_ops, 2382ca632f55SGrant Likely }, 2383ca632f55SGrant Likely .id_table = pl022_ids, 2384ca632f55SGrant Likely .probe = pl022_probe, 2385ca632f55SGrant Likely .remove = __devexit_p(pl022_remove), 2386ca632f55SGrant Likely }; 2387ca632f55SGrant Likely 2388ca632f55SGrant Likely static int __init pl022_init(void) 2389ca632f55SGrant Likely { 2390ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2391ca632f55SGrant Likely } 2392ca632f55SGrant Likely subsys_initcall(pl022_init); 2393ca632f55SGrant Likely 2394ca632f55SGrant Likely static void __exit pl022_exit(void) 2395ca632f55SGrant Likely { 2396ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2397ca632f55SGrant Likely } 2398ca632f55SGrant Likely module_exit(pl022_exit); 2399ca632f55SGrant Likely 2400ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2401ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2402ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2403