1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2008-2009 ST-Ericsson AB 5ca632f55SGrant Likely * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6ca632f55SGrant Likely * 7ca632f55SGrant Likely * Author: Linus Walleij <linus.walleij@stericsson.com> 8ca632f55SGrant Likely * 9ca632f55SGrant Likely * Initial version inspired by: 10ca632f55SGrant Likely * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11ca632f55SGrant Likely * Initial adoption to PL022 by: 12ca632f55SGrant Likely * Sachin Verma <sachin.verma@st.com> 13ca632f55SGrant Likely * 14ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 15ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 16ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 17ca632f55SGrant Likely * (at your option) any later version. 18ca632f55SGrant Likely * 19ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 20ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 21ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22ca632f55SGrant Likely * GNU General Public License for more details. 23ca632f55SGrant Likely */ 24ca632f55SGrant Likely 25ca632f55SGrant Likely #include <linux/init.h> 26ca632f55SGrant Likely #include <linux/module.h> 27ca632f55SGrant Likely #include <linux/device.h> 28ca632f55SGrant Likely #include <linux/ioport.h> 29ca632f55SGrant Likely #include <linux/errno.h> 30ca632f55SGrant Likely #include <linux/interrupt.h> 31ca632f55SGrant Likely #include <linux/spi/spi.h> 32ca632f55SGrant Likely #include <linux/workqueue.h> 33ca632f55SGrant Likely #include <linux/delay.h> 34ca632f55SGrant Likely #include <linux/clk.h> 35ca632f55SGrant Likely #include <linux/err.h> 36ca632f55SGrant Likely #include <linux/amba/bus.h> 37ca632f55SGrant Likely #include <linux/amba/pl022.h> 38ca632f55SGrant Likely #include <linux/io.h> 39ca632f55SGrant Likely #include <linux/slab.h> 40ca632f55SGrant Likely #include <linux/dmaengine.h> 41ca632f55SGrant Likely #include <linux/dma-mapping.h> 42ca632f55SGrant Likely #include <linux/scatterlist.h> 43bcda6ff8SRabin Vincent #include <linux/pm_runtime.h> 44ca632f55SGrant Likely 45ca632f55SGrant Likely /* 46ca632f55SGrant Likely * This macro is used to define some register default values. 47ca632f55SGrant Likely * reg is masked with mask, the OR:ed with an (again masked) 48ca632f55SGrant Likely * val shifted sb steps to the left. 49ca632f55SGrant Likely */ 50ca632f55SGrant Likely #define SSP_WRITE_BITS(reg, val, mask, sb) \ 51ca632f55SGrant Likely ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 52ca632f55SGrant Likely 53ca632f55SGrant Likely /* 54ca632f55SGrant Likely * This macro is also used to define some default values. 55ca632f55SGrant Likely * It will just shift val by sb steps to the left and mask 56ca632f55SGrant Likely * the result with mask. 57ca632f55SGrant Likely */ 58ca632f55SGrant Likely #define GEN_MASK_BITS(val, mask, sb) \ 59ca632f55SGrant Likely (((val)<<(sb)) & (mask)) 60ca632f55SGrant Likely 61ca632f55SGrant Likely #define DRIVE_TX 0 62ca632f55SGrant Likely #define DO_NOT_DRIVE_TX 1 63ca632f55SGrant Likely 64ca632f55SGrant Likely #define DO_NOT_QUEUE_DMA 0 65ca632f55SGrant Likely #define QUEUE_DMA 1 66ca632f55SGrant Likely 67ca632f55SGrant Likely #define RX_TRANSFER 1 68ca632f55SGrant Likely #define TX_TRANSFER 2 69ca632f55SGrant Likely 70ca632f55SGrant Likely /* 71ca632f55SGrant Likely * Macros to access SSP Registers with their offsets 72ca632f55SGrant Likely */ 73ca632f55SGrant Likely #define SSP_CR0(r) (r + 0x000) 74ca632f55SGrant Likely #define SSP_CR1(r) (r + 0x004) 75ca632f55SGrant Likely #define SSP_DR(r) (r + 0x008) 76ca632f55SGrant Likely #define SSP_SR(r) (r + 0x00C) 77ca632f55SGrant Likely #define SSP_CPSR(r) (r + 0x010) 78ca632f55SGrant Likely #define SSP_IMSC(r) (r + 0x014) 79ca632f55SGrant Likely #define SSP_RIS(r) (r + 0x018) 80ca632f55SGrant Likely #define SSP_MIS(r) (r + 0x01C) 81ca632f55SGrant Likely #define SSP_ICR(r) (r + 0x020) 82ca632f55SGrant Likely #define SSP_DMACR(r) (r + 0x024) 83ca632f55SGrant Likely #define SSP_ITCR(r) (r + 0x080) 84ca632f55SGrant Likely #define SSP_ITIP(r) (r + 0x084) 85ca632f55SGrant Likely #define SSP_ITOP(r) (r + 0x088) 86ca632f55SGrant Likely #define SSP_TDR(r) (r + 0x08C) 87ca632f55SGrant Likely 88ca632f55SGrant Likely #define SSP_PID0(r) (r + 0xFE0) 89ca632f55SGrant Likely #define SSP_PID1(r) (r + 0xFE4) 90ca632f55SGrant Likely #define SSP_PID2(r) (r + 0xFE8) 91ca632f55SGrant Likely #define SSP_PID3(r) (r + 0xFEC) 92ca632f55SGrant Likely 93ca632f55SGrant Likely #define SSP_CID0(r) (r + 0xFF0) 94ca632f55SGrant Likely #define SSP_CID1(r) (r + 0xFF4) 95ca632f55SGrant Likely #define SSP_CID2(r) (r + 0xFF8) 96ca632f55SGrant Likely #define SSP_CID3(r) (r + 0xFFC) 97ca632f55SGrant Likely 98ca632f55SGrant Likely /* 99ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR0 100ca632f55SGrant Likely */ 101ca632f55SGrant Likely #define SSP_CR0_MASK_DSS (0x0FUL << 0) 102ca632f55SGrant Likely #define SSP_CR0_MASK_FRF (0x3UL << 4) 103ca632f55SGrant Likely #define SSP_CR0_MASK_SPO (0x1UL << 6) 104ca632f55SGrant Likely #define SSP_CR0_MASK_SPH (0x1UL << 7) 105ca632f55SGrant Likely #define SSP_CR0_MASK_SCR (0xFFUL << 8) 106ca632f55SGrant Likely 107ca632f55SGrant Likely /* 108ca632f55SGrant Likely * The ST version of this block moves som bits 109ca632f55SGrant Likely * in SSP_CR0 and extends it to 32 bits 110ca632f55SGrant Likely */ 111ca632f55SGrant Likely #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 112ca632f55SGrant Likely #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 113ca632f55SGrant Likely #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 114ca632f55SGrant Likely #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 115ca632f55SGrant Likely 116ca632f55SGrant Likely 117ca632f55SGrant Likely /* 118ca632f55SGrant Likely * SSP Control Register 0 - SSP_CR1 119ca632f55SGrant Likely */ 120ca632f55SGrant Likely #define SSP_CR1_MASK_LBM (0x1UL << 0) 121ca632f55SGrant Likely #define SSP_CR1_MASK_SSE (0x1UL << 1) 122ca632f55SGrant Likely #define SSP_CR1_MASK_MS (0x1UL << 2) 123ca632f55SGrant Likely #define SSP_CR1_MASK_SOD (0x1UL << 3) 124ca632f55SGrant Likely 125ca632f55SGrant Likely /* 126ca632f55SGrant Likely * The ST version of this block adds some bits 127ca632f55SGrant Likely * in SSP_CR1 128ca632f55SGrant Likely */ 129ca632f55SGrant Likely #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 130ca632f55SGrant Likely #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 131ca632f55SGrant Likely #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 132ca632f55SGrant Likely #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 133ca632f55SGrant Likely #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 134ca632f55SGrant Likely /* This one is only in the PL023 variant */ 135ca632f55SGrant Likely #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 136ca632f55SGrant Likely 137ca632f55SGrant Likely /* 138ca632f55SGrant Likely * SSP Status Register - SSP_SR 139ca632f55SGrant Likely */ 140ca632f55SGrant Likely #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 141ca632f55SGrant Likely #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 142ca632f55SGrant Likely #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 143ca632f55SGrant Likely #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 144ca632f55SGrant Likely #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 145ca632f55SGrant Likely 146ca632f55SGrant Likely /* 147ca632f55SGrant Likely * SSP Clock Prescale Register - SSP_CPSR 148ca632f55SGrant Likely */ 149ca632f55SGrant Likely #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 150ca632f55SGrant Likely 151ca632f55SGrant Likely /* 152ca632f55SGrant Likely * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 153ca632f55SGrant Likely */ 154ca632f55SGrant Likely #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 155ca632f55SGrant Likely #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 156ca632f55SGrant Likely #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 157ca632f55SGrant Likely #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 158ca632f55SGrant Likely 159ca632f55SGrant Likely /* 160ca632f55SGrant Likely * SSP Raw Interrupt Status Register - SSP_RIS 161ca632f55SGrant Likely */ 162ca632f55SGrant Likely /* Receive Overrun Raw Interrupt status */ 163ca632f55SGrant Likely #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 164ca632f55SGrant Likely /* Receive Timeout Raw Interrupt status */ 165ca632f55SGrant Likely #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 166ca632f55SGrant Likely /* Receive FIFO Raw Interrupt status */ 167ca632f55SGrant Likely #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 168ca632f55SGrant Likely /* Transmit FIFO Raw Interrupt status */ 169ca632f55SGrant Likely #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 170ca632f55SGrant Likely 171ca632f55SGrant Likely /* 172ca632f55SGrant Likely * SSP Masked Interrupt Status Register - SSP_MIS 173ca632f55SGrant Likely */ 174ca632f55SGrant Likely /* Receive Overrun Masked Interrupt status */ 175ca632f55SGrant Likely #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 176ca632f55SGrant Likely /* Receive Timeout Masked Interrupt status */ 177ca632f55SGrant Likely #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 178ca632f55SGrant Likely /* Receive FIFO Masked Interrupt status */ 179ca632f55SGrant Likely #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 180ca632f55SGrant Likely /* Transmit FIFO Masked Interrupt status */ 181ca632f55SGrant Likely #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 182ca632f55SGrant Likely 183ca632f55SGrant Likely /* 184ca632f55SGrant Likely * SSP Interrupt Clear Register - SSP_ICR 185ca632f55SGrant Likely */ 186ca632f55SGrant Likely /* Receive Overrun Raw Clear Interrupt bit */ 187ca632f55SGrant Likely #define SSP_ICR_MASK_RORIC (0x1UL << 0) 188ca632f55SGrant Likely /* Receive Timeout Clear Interrupt bit */ 189ca632f55SGrant Likely #define SSP_ICR_MASK_RTIC (0x1UL << 1) 190ca632f55SGrant Likely 191ca632f55SGrant Likely /* 192ca632f55SGrant Likely * SSP DMA Control Register - SSP_DMACR 193ca632f55SGrant Likely */ 194ca632f55SGrant Likely /* Receive DMA Enable bit */ 195ca632f55SGrant Likely #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 196ca632f55SGrant Likely /* Transmit DMA Enable bit */ 197ca632f55SGrant Likely #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 198ca632f55SGrant Likely 199ca632f55SGrant Likely /* 200ca632f55SGrant Likely * SSP Integration Test control Register - SSP_ITCR 201ca632f55SGrant Likely */ 202ca632f55SGrant Likely #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 203ca632f55SGrant Likely #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 204ca632f55SGrant Likely 205ca632f55SGrant Likely /* 206ca632f55SGrant Likely * SSP Integration Test Input Register - SSP_ITIP 207ca632f55SGrant Likely */ 208ca632f55SGrant Likely #define ITIP_MASK_SSPRXD (0x1UL << 0) 209ca632f55SGrant Likely #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 210ca632f55SGrant Likely #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 211ca632f55SGrant Likely #define ITIP_MASK_RXDMAC (0x1UL << 3) 212ca632f55SGrant Likely #define ITIP_MASK_TXDMAC (0x1UL << 4) 213ca632f55SGrant Likely #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 214ca632f55SGrant Likely 215ca632f55SGrant Likely /* 216ca632f55SGrant Likely * SSP Integration Test output Register - SSP_ITOP 217ca632f55SGrant Likely */ 218ca632f55SGrant Likely #define ITOP_MASK_SSPTXD (0x1UL << 0) 219ca632f55SGrant Likely #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 220ca632f55SGrant Likely #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 221ca632f55SGrant Likely #define ITOP_MASK_SSPOEn (0x1UL << 3) 222ca632f55SGrant Likely #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 223ca632f55SGrant Likely #define ITOP_MASK_RORINTR (0x1UL << 5) 224ca632f55SGrant Likely #define ITOP_MASK_RTINTR (0x1UL << 6) 225ca632f55SGrant Likely #define ITOP_MASK_RXINTR (0x1UL << 7) 226ca632f55SGrant Likely #define ITOP_MASK_TXINTR (0x1UL << 8) 227ca632f55SGrant Likely #define ITOP_MASK_INTR (0x1UL << 9) 228ca632f55SGrant Likely #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 229ca632f55SGrant Likely #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 230ca632f55SGrant Likely #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 231ca632f55SGrant Likely #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 232ca632f55SGrant Likely 233ca632f55SGrant Likely /* 234ca632f55SGrant Likely * SSP Test Data Register - SSP_TDR 235ca632f55SGrant Likely */ 236ca632f55SGrant Likely #define TDR_MASK_TESTDATA (0xFFFFFFFF) 237ca632f55SGrant Likely 238ca632f55SGrant Likely /* 239ca632f55SGrant Likely * Message State 240ca632f55SGrant Likely * we use the spi_message.state (void *) pointer to 241ca632f55SGrant Likely * hold a single state value, that's why all this 242ca632f55SGrant Likely * (void *) casting is done here. 243ca632f55SGrant Likely */ 244ca632f55SGrant Likely #define STATE_START ((void *) 0) 245ca632f55SGrant Likely #define STATE_RUNNING ((void *) 1) 246ca632f55SGrant Likely #define STATE_DONE ((void *) 2) 247ca632f55SGrant Likely #define STATE_ERROR ((void *) -1) 248ca632f55SGrant Likely 249ca632f55SGrant Likely /* 250ca632f55SGrant Likely * SSP State - Whether Enabled or Disabled 251ca632f55SGrant Likely */ 252ca632f55SGrant Likely #define SSP_DISABLED (0) 253ca632f55SGrant Likely #define SSP_ENABLED (1) 254ca632f55SGrant Likely 255ca632f55SGrant Likely /* 256ca632f55SGrant Likely * SSP DMA State - Whether DMA Enabled or Disabled 257ca632f55SGrant Likely */ 258ca632f55SGrant Likely #define SSP_DMA_DISABLED (0) 259ca632f55SGrant Likely #define SSP_DMA_ENABLED (1) 260ca632f55SGrant Likely 261ca632f55SGrant Likely /* 262ca632f55SGrant Likely * SSP Clock Defaults 263ca632f55SGrant Likely */ 264ca632f55SGrant Likely #define SSP_DEFAULT_CLKRATE 0x2 265ca632f55SGrant Likely #define SSP_DEFAULT_PRESCALE 0x40 266ca632f55SGrant Likely 267ca632f55SGrant Likely /* 268ca632f55SGrant Likely * SSP Clock Parameter ranges 269ca632f55SGrant Likely */ 270ca632f55SGrant Likely #define CPSDVR_MIN 0x02 271ca632f55SGrant Likely #define CPSDVR_MAX 0xFE 272ca632f55SGrant Likely #define SCR_MIN 0x00 273ca632f55SGrant Likely #define SCR_MAX 0xFF 274ca632f55SGrant Likely 275ca632f55SGrant Likely /* 276ca632f55SGrant Likely * SSP Interrupt related Macros 277ca632f55SGrant Likely */ 278ca632f55SGrant Likely #define DEFAULT_SSP_REG_IMSC 0x0UL 279ca632f55SGrant Likely #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 280ca632f55SGrant Likely #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 281ca632f55SGrant Likely 282ca632f55SGrant Likely #define CLEAR_ALL_INTERRUPTS 0x3 283ca632f55SGrant Likely 284ca632f55SGrant Likely #define SPI_POLLING_TIMEOUT 1000 285ca632f55SGrant Likely 286ca632f55SGrant Likely 287ca632f55SGrant Likely /* 288ca632f55SGrant Likely * The type of reading going on on this chip 289ca632f55SGrant Likely */ 290ca632f55SGrant Likely enum ssp_reading { 291ca632f55SGrant Likely READING_NULL, 292ca632f55SGrant Likely READING_U8, 293ca632f55SGrant Likely READING_U16, 294ca632f55SGrant Likely READING_U32 295ca632f55SGrant Likely }; 296ca632f55SGrant Likely 297ca632f55SGrant Likely /** 298ca632f55SGrant Likely * The type of writing going on on this chip 299ca632f55SGrant Likely */ 300ca632f55SGrant Likely enum ssp_writing { 301ca632f55SGrant Likely WRITING_NULL, 302ca632f55SGrant Likely WRITING_U8, 303ca632f55SGrant Likely WRITING_U16, 304ca632f55SGrant Likely WRITING_U32 305ca632f55SGrant Likely }; 306ca632f55SGrant Likely 307ca632f55SGrant Likely /** 308ca632f55SGrant Likely * struct vendor_data - vendor-specific config parameters 309ca632f55SGrant Likely * for PL022 derivates 310ca632f55SGrant Likely * @fifodepth: depth of FIFOs (both) 311ca632f55SGrant Likely * @max_bpw: maximum number of bits per word 312ca632f55SGrant Likely * @unidir: supports unidirection transfers 313ca632f55SGrant Likely * @extended_cr: 32 bit wide control register 0 with extra 314ca632f55SGrant Likely * features and extra features in CR1 as found in the ST variants 315ca632f55SGrant Likely * @pl023: supports a subset of the ST extensions called "PL023" 316ca632f55SGrant Likely */ 317ca632f55SGrant Likely struct vendor_data { 318ca632f55SGrant Likely int fifodepth; 319ca632f55SGrant Likely int max_bpw; 320ca632f55SGrant Likely bool unidir; 321ca632f55SGrant Likely bool extended_cr; 322ca632f55SGrant Likely bool pl023; 323ca632f55SGrant Likely bool loopback; 324ca632f55SGrant Likely }; 325ca632f55SGrant Likely 326ca632f55SGrant Likely /** 327ca632f55SGrant Likely * struct pl022 - This is the private SSP driver data structure 328ca632f55SGrant Likely * @adev: AMBA device model hookup 329ca632f55SGrant Likely * @vendor: vendor data for the IP block 330ca632f55SGrant Likely * @phybase: the physical memory where the SSP device resides 331ca632f55SGrant Likely * @virtbase: the virtual memory where the SSP is mapped 332ca632f55SGrant Likely * @clk: outgoing clock "SPICLK" for the SPI bus 333ca632f55SGrant Likely * @master: SPI framework hookup 334ca632f55SGrant Likely * @master_info: controller-specific data from machine setup 335ca632f55SGrant Likely * @workqueue: a workqueue on which any spi_message request is queued 336ca632f55SGrant Likely * @pump_messages: work struct for scheduling work to the workqueue 337ca632f55SGrant Likely * @queue_lock: spinlock to syncronise access to message queue 338ca632f55SGrant Likely * @queue: message queue 339ca632f55SGrant Likely * @busy: workqueue is busy 340ca632f55SGrant Likely * @running: workqueue is running 341ca632f55SGrant Likely * @pump_transfers: Tasklet used in Interrupt Transfer mode 342ca632f55SGrant Likely * @cur_msg: Pointer to current spi_message being processed 343ca632f55SGrant Likely * @cur_transfer: Pointer to current spi_transfer 344ca632f55SGrant Likely * @cur_chip: pointer to current clients chip(assigned from controller_state) 345ca632f55SGrant Likely * @tx: current position in TX buffer to be read 346ca632f55SGrant Likely * @tx_end: end position in TX buffer to be read 347ca632f55SGrant Likely * @rx: current position in RX buffer to be written 348ca632f55SGrant Likely * @rx_end: end position in RX buffer to be written 349ca632f55SGrant Likely * @read: the type of read currently going on 350ca632f55SGrant Likely * @write: the type of write currently going on 351ca632f55SGrant Likely * @exp_fifo_level: expected FIFO level 352ca632f55SGrant Likely * @dma_rx_channel: optional channel for RX DMA 353ca632f55SGrant Likely * @dma_tx_channel: optional channel for TX DMA 354ca632f55SGrant Likely * @sgt_rx: scattertable for the RX transfer 355ca632f55SGrant Likely * @sgt_tx: scattertable for the TX transfer 356ca632f55SGrant Likely * @dummypage: a dummy page used for driving data on the bus with DMA 357ca632f55SGrant Likely */ 358ca632f55SGrant Likely struct pl022 { 359ca632f55SGrant Likely struct amba_device *adev; 360ca632f55SGrant Likely struct vendor_data *vendor; 361ca632f55SGrant Likely resource_size_t phybase; 362ca632f55SGrant Likely void __iomem *virtbase; 363ca632f55SGrant Likely struct clk *clk; 364ca632f55SGrant Likely struct spi_master *master; 365ca632f55SGrant Likely struct pl022_ssp_controller *master_info; 366ca632f55SGrant Likely /* Driver message queue */ 367ca632f55SGrant Likely struct workqueue_struct *workqueue; 368ca632f55SGrant Likely struct work_struct pump_messages; 369ca632f55SGrant Likely spinlock_t queue_lock; 370ca632f55SGrant Likely struct list_head queue; 371ca632f55SGrant Likely bool busy; 372ca632f55SGrant Likely bool running; 373ca632f55SGrant Likely /* Message transfer pump */ 374ca632f55SGrant Likely struct tasklet_struct pump_transfers; 375ca632f55SGrant Likely struct spi_message *cur_msg; 376ca632f55SGrant Likely struct spi_transfer *cur_transfer; 377ca632f55SGrant Likely struct chip_data *cur_chip; 378ca632f55SGrant Likely void *tx; 379ca632f55SGrant Likely void *tx_end; 380ca632f55SGrant Likely void *rx; 381ca632f55SGrant Likely void *rx_end; 382ca632f55SGrant Likely enum ssp_reading read; 383ca632f55SGrant Likely enum ssp_writing write; 384ca632f55SGrant Likely u32 exp_fifo_level; 385083be3f0SLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 386083be3f0SLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 387ca632f55SGrant Likely /* DMA settings */ 388ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 389ca632f55SGrant Likely struct dma_chan *dma_rx_channel; 390ca632f55SGrant Likely struct dma_chan *dma_tx_channel; 391ca632f55SGrant Likely struct sg_table sgt_rx; 392ca632f55SGrant Likely struct sg_table sgt_tx; 393ca632f55SGrant Likely char *dummypage; 394ca632f55SGrant Likely #endif 395ca632f55SGrant Likely }; 396ca632f55SGrant Likely 397ca632f55SGrant Likely /** 398ca632f55SGrant Likely * struct chip_data - To maintain runtime state of SSP for each client chip 399ca632f55SGrant Likely * @cr0: Value of control register CR0 of SSP - on later ST variants this 400ca632f55SGrant Likely * register is 32 bits wide rather than just 16 401ca632f55SGrant Likely * @cr1: Value of control register CR1 of SSP 402ca632f55SGrant Likely * @dmacr: Value of DMA control Register of SSP 403ca632f55SGrant Likely * @cpsr: Value of Clock prescale register 404ca632f55SGrant Likely * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 405ca632f55SGrant Likely * @enable_dma: Whether to enable DMA or not 406ca632f55SGrant Likely * @read: function ptr to be used to read when doing xfer for this chip 407ca632f55SGrant Likely * @write: function ptr to be used to write when doing xfer for this chip 408ca632f55SGrant Likely * @cs_control: chip select callback provided by chip 409ca632f55SGrant Likely * @xfer_type: polling/interrupt/DMA 410ca632f55SGrant Likely * 411ca632f55SGrant Likely * Runtime state of the SSP controller, maintained per chip, 412ca632f55SGrant Likely * This would be set according to the current message that would be served 413ca632f55SGrant Likely */ 414ca632f55SGrant Likely struct chip_data { 415ca632f55SGrant Likely u32 cr0; 416ca632f55SGrant Likely u16 cr1; 417ca632f55SGrant Likely u16 dmacr; 418ca632f55SGrant Likely u16 cpsr; 419ca632f55SGrant Likely u8 n_bytes; 420ca632f55SGrant Likely bool enable_dma; 421ca632f55SGrant Likely enum ssp_reading read; 422ca632f55SGrant Likely enum ssp_writing write; 423ca632f55SGrant Likely void (*cs_control) (u32 command); 424ca632f55SGrant Likely int xfer_type; 425ca632f55SGrant Likely }; 426ca632f55SGrant Likely 427ca632f55SGrant Likely /** 428ca632f55SGrant Likely * null_cs_control - Dummy chip select function 429ca632f55SGrant Likely * @command: select/delect the chip 430ca632f55SGrant Likely * 431ca632f55SGrant Likely * If no chip select function is provided by client this is used as dummy 432ca632f55SGrant Likely * chip select 433ca632f55SGrant Likely */ 434ca632f55SGrant Likely static void null_cs_control(u32 command) 435ca632f55SGrant Likely { 436ca632f55SGrant Likely pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 437ca632f55SGrant Likely } 438ca632f55SGrant Likely 439ca632f55SGrant Likely /** 440ca632f55SGrant Likely * giveback - current spi_message is over, schedule next message and call 441ca632f55SGrant Likely * callback of this message. Assumes that caller already 442ca632f55SGrant Likely * set message->status; dma and pio irqs are blocked 443ca632f55SGrant Likely * @pl022: SSP driver private data structure 444ca632f55SGrant Likely */ 445ca632f55SGrant Likely static void giveback(struct pl022 *pl022) 446ca632f55SGrant Likely { 447ca632f55SGrant Likely struct spi_transfer *last_transfer; 448ca632f55SGrant Likely unsigned long flags; 449ca632f55SGrant Likely struct spi_message *msg; 450ca632f55SGrant Likely void (*curr_cs_control) (u32 command); 451ca632f55SGrant Likely 452ca632f55SGrant Likely /* 453ca632f55SGrant Likely * This local reference to the chip select function 454ca632f55SGrant Likely * is needed because we set curr_chip to NULL 455ca632f55SGrant Likely * as a step toward termininating the message. 456ca632f55SGrant Likely */ 457ca632f55SGrant Likely curr_cs_control = pl022->cur_chip->cs_control; 458ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 459ca632f55SGrant Likely msg = pl022->cur_msg; 460ca632f55SGrant Likely pl022->cur_msg = NULL; 461ca632f55SGrant Likely pl022->cur_transfer = NULL; 462ca632f55SGrant Likely pl022->cur_chip = NULL; 463ca632f55SGrant Likely queue_work(pl022->workqueue, &pl022->pump_messages); 464ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 465ca632f55SGrant Likely 466ca632f55SGrant Likely last_transfer = list_entry(msg->transfers.prev, 467ca632f55SGrant Likely struct spi_transfer, 468ca632f55SGrant Likely transfer_list); 469ca632f55SGrant Likely 470ca632f55SGrant Likely /* Delay if requested before any change in chip select */ 471ca632f55SGrant Likely if (last_transfer->delay_usecs) 472ca632f55SGrant Likely /* 473ca632f55SGrant Likely * FIXME: This runs in interrupt context. 474ca632f55SGrant Likely * Is this really smart? 475ca632f55SGrant Likely */ 476ca632f55SGrant Likely udelay(last_transfer->delay_usecs); 477ca632f55SGrant Likely 478ca632f55SGrant Likely /* 479ca632f55SGrant Likely * Drop chip select UNLESS cs_change is true or we are returning 480ca632f55SGrant Likely * a message with an error, or next message is for another chip 481ca632f55SGrant Likely */ 482ca632f55SGrant Likely if (!last_transfer->cs_change) 483ca632f55SGrant Likely curr_cs_control(SSP_CHIP_DESELECT); 484ca632f55SGrant Likely else { 485ca632f55SGrant Likely struct spi_message *next_msg; 486ca632f55SGrant Likely 487ca632f55SGrant Likely /* Holding of cs was hinted, but we need to make sure 488ca632f55SGrant Likely * the next message is for the same chip. Don't waste 489ca632f55SGrant Likely * time with the following tests unless this was hinted. 490ca632f55SGrant Likely * 491ca632f55SGrant Likely * We cannot postpone this until pump_messages, because 492ca632f55SGrant Likely * after calling msg->complete (below) the driver that 493ca632f55SGrant Likely * sent the current message could be unloaded, which 494ca632f55SGrant Likely * could invalidate the cs_control() callback... 495ca632f55SGrant Likely */ 496ca632f55SGrant Likely 497ca632f55SGrant Likely /* get a pointer to the next message, if any */ 498ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 499ca632f55SGrant Likely if (list_empty(&pl022->queue)) 500ca632f55SGrant Likely next_msg = NULL; 501ca632f55SGrant Likely else 502ca632f55SGrant Likely next_msg = list_entry(pl022->queue.next, 503ca632f55SGrant Likely struct spi_message, queue); 504ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 505ca632f55SGrant Likely 506ca632f55SGrant Likely /* see if the next and current messages point 507ca632f55SGrant Likely * to the same chip 508ca632f55SGrant Likely */ 509ca632f55SGrant Likely if (next_msg && next_msg->spi != msg->spi) 510ca632f55SGrant Likely next_msg = NULL; 511ca632f55SGrant Likely if (!next_msg || msg->state == STATE_ERROR) 512ca632f55SGrant Likely curr_cs_control(SSP_CHIP_DESELECT); 513ca632f55SGrant Likely } 514ca632f55SGrant Likely msg->state = NULL; 515ca632f55SGrant Likely if (msg->complete) 516ca632f55SGrant Likely msg->complete(msg->context); 517ca632f55SGrant Likely /* This message is completed, so let's turn off the clocks & power */ 518ca632f55SGrant Likely clk_disable(pl022->clk); 519ca632f55SGrant Likely amba_pclk_disable(pl022->adev); 520ca632f55SGrant Likely amba_vcore_disable(pl022->adev); 521bcda6ff8SRabin Vincent pm_runtime_put(&pl022->adev->dev); 522ca632f55SGrant Likely } 523ca632f55SGrant Likely 524ca632f55SGrant Likely /** 525ca632f55SGrant Likely * flush - flush the FIFO to reach a clean state 526ca632f55SGrant Likely * @pl022: SSP driver private data structure 527ca632f55SGrant Likely */ 528ca632f55SGrant Likely static int flush(struct pl022 *pl022) 529ca632f55SGrant Likely { 530ca632f55SGrant Likely unsigned long limit = loops_per_jiffy << 1; 531ca632f55SGrant Likely 532ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "flush\n"); 533ca632f55SGrant Likely do { 534ca632f55SGrant Likely while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 535ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 536ca632f55SGrant Likely } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 537ca632f55SGrant Likely 538ca632f55SGrant Likely pl022->exp_fifo_level = 0; 539ca632f55SGrant Likely 540ca632f55SGrant Likely return limit; 541ca632f55SGrant Likely } 542ca632f55SGrant Likely 543ca632f55SGrant Likely /** 544ca632f55SGrant Likely * restore_state - Load configuration of current chip 545ca632f55SGrant Likely * @pl022: SSP driver private data structure 546ca632f55SGrant Likely */ 547ca632f55SGrant Likely static void restore_state(struct pl022 *pl022) 548ca632f55SGrant Likely { 549ca632f55SGrant Likely struct chip_data *chip = pl022->cur_chip; 550ca632f55SGrant Likely 551ca632f55SGrant Likely if (pl022->vendor->extended_cr) 552ca632f55SGrant Likely writel(chip->cr0, SSP_CR0(pl022->virtbase)); 553ca632f55SGrant Likely else 554ca632f55SGrant Likely writew(chip->cr0, SSP_CR0(pl022->virtbase)); 555ca632f55SGrant Likely writew(chip->cr1, SSP_CR1(pl022->virtbase)); 556ca632f55SGrant Likely writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 557ca632f55SGrant Likely writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 558ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 559ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 560ca632f55SGrant Likely } 561ca632f55SGrant Likely 562ca632f55SGrant Likely /* 563ca632f55SGrant Likely * Default SSP Register Values 564ca632f55SGrant Likely */ 565ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0 ( \ 566ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 567ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 568ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 569ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 570ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 571ca632f55SGrant Likely ) 572ca632f55SGrant Likely 573ca632f55SGrant Likely /* ST versions have slightly different bit layout */ 574ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST ( \ 575ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 576ca632f55SGrant Likely GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 577ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 578ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 579ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 580ca632f55SGrant Likely GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 581ca632f55SGrant Likely GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 582ca632f55SGrant Likely ) 583ca632f55SGrant Likely 584ca632f55SGrant Likely /* The PL023 version is slightly different again */ 585ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 586ca632f55SGrant Likely GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 587ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 588ca632f55SGrant Likely GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 589ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 590ca632f55SGrant Likely ) 591ca632f55SGrant Likely 592ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1 ( \ 593ca632f55SGrant Likely GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 594ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 595ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 596ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 597ca632f55SGrant Likely ) 598ca632f55SGrant Likely 599ca632f55SGrant Likely /* ST versions extend this register to use all 16 bits */ 600ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST ( \ 601ca632f55SGrant Likely DEFAULT_SSP_REG_CR1 | \ 602ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 603ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 604ca632f55SGrant Likely GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 605ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 606ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 607ca632f55SGrant Likely ) 608ca632f55SGrant Likely 609ca632f55SGrant Likely /* 610ca632f55SGrant Likely * The PL023 variant has further differences: no loopback mode, no microwire 611ca632f55SGrant Likely * support, and a new clock feedback delay setting. 612ca632f55SGrant Likely */ 613ca632f55SGrant Likely #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 614ca632f55SGrant Likely GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 615ca632f55SGrant Likely GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 616ca632f55SGrant Likely GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 617ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 618ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 619ca632f55SGrant Likely GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 620ca632f55SGrant Likely GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 621ca632f55SGrant Likely GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 622ca632f55SGrant Likely ) 623ca632f55SGrant Likely 624ca632f55SGrant Likely #define DEFAULT_SSP_REG_CPSR ( \ 625ca632f55SGrant Likely GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 626ca632f55SGrant Likely ) 627ca632f55SGrant Likely 628ca632f55SGrant Likely #define DEFAULT_SSP_REG_DMACR (\ 629ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 630ca632f55SGrant Likely GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 631ca632f55SGrant Likely ) 632ca632f55SGrant Likely 633ca632f55SGrant Likely /** 634ca632f55SGrant Likely * load_ssp_default_config - Load default configuration for SSP 635ca632f55SGrant Likely * @pl022: SSP driver private data structure 636ca632f55SGrant Likely */ 637ca632f55SGrant Likely static void load_ssp_default_config(struct pl022 *pl022) 638ca632f55SGrant Likely { 639ca632f55SGrant Likely if (pl022->vendor->pl023) { 640ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 641ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 642ca632f55SGrant Likely } else if (pl022->vendor->extended_cr) { 643ca632f55SGrant Likely writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 644ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 645ca632f55SGrant Likely } else { 646ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 647ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 648ca632f55SGrant Likely } 649ca632f55SGrant Likely writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 650ca632f55SGrant Likely writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 651ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 652ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 653ca632f55SGrant Likely } 654ca632f55SGrant Likely 655ca632f55SGrant Likely /** 656ca632f55SGrant Likely * This will write to TX and read from RX according to the parameters 657ca632f55SGrant Likely * set in pl022. 658ca632f55SGrant Likely */ 659ca632f55SGrant Likely static void readwriter(struct pl022 *pl022) 660ca632f55SGrant Likely { 661ca632f55SGrant Likely 662ca632f55SGrant Likely /* 663ca632f55SGrant Likely * The FIFO depth is different between primecell variants. 664ca632f55SGrant Likely * I believe filling in too much in the FIFO might cause 665ca632f55SGrant Likely * errons in 8bit wide transfers on ARM variants (just 8 words 666ca632f55SGrant Likely * FIFO, means only 8x8 = 64 bits in FIFO) at least. 667ca632f55SGrant Likely * 668ca632f55SGrant Likely * To prevent this issue, the TX FIFO is only filled to the 669ca632f55SGrant Likely * unused RX FIFO fill length, regardless of what the TX 670ca632f55SGrant Likely * FIFO status flag indicates. 671ca632f55SGrant Likely */ 672ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 673ca632f55SGrant Likely "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 674ca632f55SGrant Likely __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 675ca632f55SGrant Likely 676ca632f55SGrant Likely /* Read as much as you can */ 677ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 678ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 679ca632f55SGrant Likely switch (pl022->read) { 680ca632f55SGrant Likely case READING_NULL: 681ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 682ca632f55SGrant Likely break; 683ca632f55SGrant Likely case READING_U8: 684ca632f55SGrant Likely *(u8 *) (pl022->rx) = 685ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 686ca632f55SGrant Likely break; 687ca632f55SGrant Likely case READING_U16: 688ca632f55SGrant Likely *(u16 *) (pl022->rx) = 689ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 690ca632f55SGrant Likely break; 691ca632f55SGrant Likely case READING_U32: 692ca632f55SGrant Likely *(u32 *) (pl022->rx) = 693ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 694ca632f55SGrant Likely break; 695ca632f55SGrant Likely } 696ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 697ca632f55SGrant Likely pl022->exp_fifo_level--; 698ca632f55SGrant Likely } 699ca632f55SGrant Likely /* 700ca632f55SGrant Likely * Write as much as possible up to the RX FIFO size 701ca632f55SGrant Likely */ 702ca632f55SGrant Likely while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 703ca632f55SGrant Likely && (pl022->tx < pl022->tx_end)) { 704ca632f55SGrant Likely switch (pl022->write) { 705ca632f55SGrant Likely case WRITING_NULL: 706ca632f55SGrant Likely writew(0x0, SSP_DR(pl022->virtbase)); 707ca632f55SGrant Likely break; 708ca632f55SGrant Likely case WRITING_U8: 709ca632f55SGrant Likely writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 710ca632f55SGrant Likely break; 711ca632f55SGrant Likely case WRITING_U16: 712ca632f55SGrant Likely writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 713ca632f55SGrant Likely break; 714ca632f55SGrant Likely case WRITING_U32: 715ca632f55SGrant Likely writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 716ca632f55SGrant Likely break; 717ca632f55SGrant Likely } 718ca632f55SGrant Likely pl022->tx += (pl022->cur_chip->n_bytes); 719ca632f55SGrant Likely pl022->exp_fifo_level++; 720ca632f55SGrant Likely /* 721ca632f55SGrant Likely * This inner reader takes care of things appearing in the RX 722ca632f55SGrant Likely * FIFO as we're transmitting. This will happen a lot since the 723ca632f55SGrant Likely * clock starts running when you put things into the TX FIFO, 724ca632f55SGrant Likely * and then things are continuously clocked into the RX FIFO. 725ca632f55SGrant Likely */ 726ca632f55SGrant Likely while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 727ca632f55SGrant Likely && (pl022->rx < pl022->rx_end)) { 728ca632f55SGrant Likely switch (pl022->read) { 729ca632f55SGrant Likely case READING_NULL: 730ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)); 731ca632f55SGrant Likely break; 732ca632f55SGrant Likely case READING_U8: 733ca632f55SGrant Likely *(u8 *) (pl022->rx) = 734ca632f55SGrant Likely readw(SSP_DR(pl022->virtbase)) & 0xFFU; 735ca632f55SGrant Likely break; 736ca632f55SGrant Likely case READING_U16: 737ca632f55SGrant Likely *(u16 *) (pl022->rx) = 738ca632f55SGrant Likely (u16) readw(SSP_DR(pl022->virtbase)); 739ca632f55SGrant Likely break; 740ca632f55SGrant Likely case READING_U32: 741ca632f55SGrant Likely *(u32 *) (pl022->rx) = 742ca632f55SGrant Likely readl(SSP_DR(pl022->virtbase)); 743ca632f55SGrant Likely break; 744ca632f55SGrant Likely } 745ca632f55SGrant Likely pl022->rx += (pl022->cur_chip->n_bytes); 746ca632f55SGrant Likely pl022->exp_fifo_level--; 747ca632f55SGrant Likely } 748ca632f55SGrant Likely } 749ca632f55SGrant Likely /* 750ca632f55SGrant Likely * When we exit here the TX FIFO should be full and the RX FIFO 751ca632f55SGrant Likely * should be empty 752ca632f55SGrant Likely */ 753ca632f55SGrant Likely } 754ca632f55SGrant Likely 755ca632f55SGrant Likely 756ca632f55SGrant Likely /** 757ca632f55SGrant Likely * next_transfer - Move to the Next transfer in the current spi message 758ca632f55SGrant Likely * @pl022: SSP driver private data structure 759ca632f55SGrant Likely * 760ca632f55SGrant Likely * This function moves though the linked list of spi transfers in the 761ca632f55SGrant Likely * current spi message and returns with the state of current spi 762ca632f55SGrant Likely * message i.e whether its last transfer is done(STATE_DONE) or 763ca632f55SGrant Likely * Next transfer is ready(STATE_RUNNING) 764ca632f55SGrant Likely */ 765ca632f55SGrant Likely static void *next_transfer(struct pl022 *pl022) 766ca632f55SGrant Likely { 767ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 768ca632f55SGrant Likely struct spi_transfer *trans = pl022->cur_transfer; 769ca632f55SGrant Likely 770ca632f55SGrant Likely /* Move to next transfer */ 771ca632f55SGrant Likely if (trans->transfer_list.next != &msg->transfers) { 772ca632f55SGrant Likely pl022->cur_transfer = 773ca632f55SGrant Likely list_entry(trans->transfer_list.next, 774ca632f55SGrant Likely struct spi_transfer, transfer_list); 775ca632f55SGrant Likely return STATE_RUNNING; 776ca632f55SGrant Likely } 777ca632f55SGrant Likely return STATE_DONE; 778ca632f55SGrant Likely } 779ca632f55SGrant Likely 780ca632f55SGrant Likely /* 781ca632f55SGrant Likely * This DMA functionality is only compiled in if we have 782ca632f55SGrant Likely * access to the generic DMA devices/DMA engine. 783ca632f55SGrant Likely */ 784ca632f55SGrant Likely #ifdef CONFIG_DMA_ENGINE 785ca632f55SGrant Likely static void unmap_free_dma_scatter(struct pl022 *pl022) 786ca632f55SGrant Likely { 787ca632f55SGrant Likely /* Unmap and free the SG tables */ 788ca632f55SGrant Likely dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 789ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 790ca632f55SGrant Likely dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 791ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 792ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 793ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 794ca632f55SGrant Likely } 795ca632f55SGrant Likely 796ca632f55SGrant Likely static void dma_callback(void *data) 797ca632f55SGrant Likely { 798ca632f55SGrant Likely struct pl022 *pl022 = data; 799ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 800ca632f55SGrant Likely 801ca632f55SGrant Likely BUG_ON(!pl022->sgt_rx.sgl); 802ca632f55SGrant Likely 803ca632f55SGrant Likely #ifdef VERBOSE_DEBUG 804ca632f55SGrant Likely /* 805ca632f55SGrant Likely * Optionally dump out buffers to inspect contents, this is 806ca632f55SGrant Likely * good if you want to convince yourself that the loopback 807ca632f55SGrant Likely * read/write contents are the same, when adopting to a new 808ca632f55SGrant Likely * DMA engine. 809ca632f55SGrant Likely */ 810ca632f55SGrant Likely { 811ca632f55SGrant Likely struct scatterlist *sg; 812ca632f55SGrant Likely unsigned int i; 813ca632f55SGrant Likely 814ca632f55SGrant Likely dma_sync_sg_for_cpu(&pl022->adev->dev, 815ca632f55SGrant Likely pl022->sgt_rx.sgl, 816ca632f55SGrant Likely pl022->sgt_rx.nents, 817ca632f55SGrant Likely DMA_FROM_DEVICE); 818ca632f55SGrant Likely 819ca632f55SGrant Likely for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 820ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 821ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI RX: ", 822ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 823ca632f55SGrant Likely 16, 824ca632f55SGrant Likely 1, 825ca632f55SGrant Likely sg_virt(sg), 826ca632f55SGrant Likely sg_dma_len(sg), 827ca632f55SGrant Likely 1); 828ca632f55SGrant Likely } 829ca632f55SGrant Likely for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 830ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 831ca632f55SGrant Likely print_hex_dump(KERN_ERR, "SPI TX: ", 832ca632f55SGrant Likely DUMP_PREFIX_OFFSET, 833ca632f55SGrant Likely 16, 834ca632f55SGrant Likely 1, 835ca632f55SGrant Likely sg_virt(sg), 836ca632f55SGrant Likely sg_dma_len(sg), 837ca632f55SGrant Likely 1); 838ca632f55SGrant Likely } 839ca632f55SGrant Likely } 840ca632f55SGrant Likely #endif 841ca632f55SGrant Likely 842ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 843ca632f55SGrant Likely 844ca632f55SGrant Likely /* Update total bytes transferred */ 845ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 846ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 847ca632f55SGrant Likely pl022->cur_chip-> 848ca632f55SGrant Likely cs_control(SSP_CHIP_DESELECT); 849ca632f55SGrant Likely 850ca632f55SGrant Likely /* Move to next transfer */ 851ca632f55SGrant Likely msg->state = next_transfer(pl022); 852ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 853ca632f55SGrant Likely } 854ca632f55SGrant Likely 855ca632f55SGrant Likely static void setup_dma_scatter(struct pl022 *pl022, 856ca632f55SGrant Likely void *buffer, 857ca632f55SGrant Likely unsigned int length, 858ca632f55SGrant Likely struct sg_table *sgtab) 859ca632f55SGrant Likely { 860ca632f55SGrant Likely struct scatterlist *sg; 861ca632f55SGrant Likely int bytesleft = length; 862ca632f55SGrant Likely void *bufp = buffer; 863ca632f55SGrant Likely int mapbytes; 864ca632f55SGrant Likely int i; 865ca632f55SGrant Likely 866ca632f55SGrant Likely if (buffer) { 867ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 868ca632f55SGrant Likely /* 869ca632f55SGrant Likely * If there are less bytes left than what fits 870ca632f55SGrant Likely * in the current page (plus page alignment offset) 871ca632f55SGrant Likely * we just feed in this, else we stuff in as much 872ca632f55SGrant Likely * as we can. 873ca632f55SGrant Likely */ 874ca632f55SGrant Likely if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 875ca632f55SGrant Likely mapbytes = bytesleft; 876ca632f55SGrant Likely else 877ca632f55SGrant Likely mapbytes = PAGE_SIZE - offset_in_page(bufp); 878ca632f55SGrant Likely sg_set_page(sg, virt_to_page(bufp), 879ca632f55SGrant Likely mapbytes, offset_in_page(bufp)); 880ca632f55SGrant Likely bufp += mapbytes; 881ca632f55SGrant Likely bytesleft -= mapbytes; 882ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 883ca632f55SGrant Likely "set RX/TX target page @ %p, %d bytes, %d left\n", 884ca632f55SGrant Likely bufp, mapbytes, bytesleft); 885ca632f55SGrant Likely } 886ca632f55SGrant Likely } else { 887ca632f55SGrant Likely /* Map the dummy buffer on every page */ 888ca632f55SGrant Likely for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 889ca632f55SGrant Likely if (bytesleft < PAGE_SIZE) 890ca632f55SGrant Likely mapbytes = bytesleft; 891ca632f55SGrant Likely else 892ca632f55SGrant Likely mapbytes = PAGE_SIZE; 893ca632f55SGrant Likely sg_set_page(sg, virt_to_page(pl022->dummypage), 894ca632f55SGrant Likely mapbytes, 0); 895ca632f55SGrant Likely bytesleft -= mapbytes; 896ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 897ca632f55SGrant Likely "set RX/TX to dummy page %d bytes, %d left\n", 898ca632f55SGrant Likely mapbytes, bytesleft); 899ca632f55SGrant Likely 900ca632f55SGrant Likely } 901ca632f55SGrant Likely } 902ca632f55SGrant Likely BUG_ON(bytesleft); 903ca632f55SGrant Likely } 904ca632f55SGrant Likely 905ca632f55SGrant Likely /** 906ca632f55SGrant Likely * configure_dma - configures the channels for the next transfer 907ca632f55SGrant Likely * @pl022: SSP driver's private data structure 908ca632f55SGrant Likely */ 909ca632f55SGrant Likely static int configure_dma(struct pl022 *pl022) 910ca632f55SGrant Likely { 911ca632f55SGrant Likely struct dma_slave_config rx_conf = { 912ca632f55SGrant Likely .src_addr = SSP_DR(pl022->phybase), 913ca632f55SGrant Likely .direction = DMA_FROM_DEVICE, 914ca632f55SGrant Likely }; 915ca632f55SGrant Likely struct dma_slave_config tx_conf = { 916ca632f55SGrant Likely .dst_addr = SSP_DR(pl022->phybase), 917ca632f55SGrant Likely .direction = DMA_TO_DEVICE, 918ca632f55SGrant Likely }; 919ca632f55SGrant Likely unsigned int pages; 920ca632f55SGrant Likely int ret; 921ca632f55SGrant Likely int rx_sglen, tx_sglen; 922ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 923ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 924ca632f55SGrant Likely struct dma_async_tx_descriptor *rxdesc; 925ca632f55SGrant Likely struct dma_async_tx_descriptor *txdesc; 926ca632f55SGrant Likely 927ca632f55SGrant Likely /* Check that the channels are available */ 928ca632f55SGrant Likely if (!rxchan || !txchan) 929ca632f55SGrant Likely return -ENODEV; 930ca632f55SGrant Likely 931083be3f0SLinus Walleij /* 932083be3f0SLinus Walleij * If supplied, the DMA burstsize should equal the FIFO trigger level. 933083be3f0SLinus Walleij * Notice that the DMA engine uses one-to-one mapping. Since we can 934083be3f0SLinus Walleij * not trigger on 2 elements this needs explicit mapping rather than 935083be3f0SLinus Walleij * calculation. 936083be3f0SLinus Walleij */ 937083be3f0SLinus Walleij switch (pl022->rx_lev_trig) { 938083be3f0SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 939083be3f0SLinus Walleij rx_conf.src_maxburst = 1; 940083be3f0SLinus Walleij break; 941083be3f0SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 942083be3f0SLinus Walleij rx_conf.src_maxburst = 4; 943083be3f0SLinus Walleij break; 944083be3f0SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 945083be3f0SLinus Walleij rx_conf.src_maxburst = 8; 946083be3f0SLinus Walleij break; 947083be3f0SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 948083be3f0SLinus Walleij rx_conf.src_maxburst = 16; 949083be3f0SLinus Walleij break; 950083be3f0SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 951083be3f0SLinus Walleij rx_conf.src_maxburst = 32; 952083be3f0SLinus Walleij break; 953083be3f0SLinus Walleij default: 954083be3f0SLinus Walleij rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 955083be3f0SLinus Walleij break; 956083be3f0SLinus Walleij } 957083be3f0SLinus Walleij 958083be3f0SLinus Walleij switch (pl022->tx_lev_trig) { 959083be3f0SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 960083be3f0SLinus Walleij tx_conf.dst_maxburst = 1; 961083be3f0SLinus Walleij break; 962083be3f0SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 963083be3f0SLinus Walleij tx_conf.dst_maxburst = 4; 964083be3f0SLinus Walleij break; 965083be3f0SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 966083be3f0SLinus Walleij tx_conf.dst_maxburst = 8; 967083be3f0SLinus Walleij break; 968083be3f0SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 969083be3f0SLinus Walleij tx_conf.dst_maxburst = 16; 970083be3f0SLinus Walleij break; 971083be3f0SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 972083be3f0SLinus Walleij tx_conf.dst_maxburst = 32; 973083be3f0SLinus Walleij break; 974083be3f0SLinus Walleij default: 975083be3f0SLinus Walleij tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 976083be3f0SLinus Walleij break; 977083be3f0SLinus Walleij } 978083be3f0SLinus Walleij 979ca632f55SGrant Likely switch (pl022->read) { 980ca632f55SGrant Likely case READING_NULL: 981ca632f55SGrant Likely /* Use the same as for writing */ 982ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 983ca632f55SGrant Likely break; 984ca632f55SGrant Likely case READING_U8: 985ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 986ca632f55SGrant Likely break; 987ca632f55SGrant Likely case READING_U16: 988ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 989ca632f55SGrant Likely break; 990ca632f55SGrant Likely case READING_U32: 991ca632f55SGrant Likely rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 992ca632f55SGrant Likely break; 993ca632f55SGrant Likely } 994ca632f55SGrant Likely 995ca632f55SGrant Likely switch (pl022->write) { 996ca632f55SGrant Likely case WRITING_NULL: 997ca632f55SGrant Likely /* Use the same as for reading */ 998ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 999ca632f55SGrant Likely break; 1000ca632f55SGrant Likely case WRITING_U8: 1001ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1002ca632f55SGrant Likely break; 1003ca632f55SGrant Likely case WRITING_U16: 1004ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1005ca632f55SGrant Likely break; 1006ca632f55SGrant Likely case WRITING_U32: 1007ca632f55SGrant Likely tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1008ca632f55SGrant Likely break; 1009ca632f55SGrant Likely } 1010ca632f55SGrant Likely 1011ca632f55SGrant Likely /* SPI pecularity: we need to read and write the same width */ 1012ca632f55SGrant Likely if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1013ca632f55SGrant Likely rx_conf.src_addr_width = tx_conf.dst_addr_width; 1014ca632f55SGrant Likely if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1015ca632f55SGrant Likely tx_conf.dst_addr_width = rx_conf.src_addr_width; 1016ca632f55SGrant Likely BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1017ca632f55SGrant Likely 1018ca632f55SGrant Likely dmaengine_slave_config(rxchan, &rx_conf); 1019ca632f55SGrant Likely dmaengine_slave_config(txchan, &tx_conf); 1020ca632f55SGrant Likely 1021ca632f55SGrant Likely /* Create sglists for the transfers */ 1022ca632f55SGrant Likely pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; 1023ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1024ca632f55SGrant Likely 1025ca632f55SGrant Likely ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); 1026ca632f55SGrant Likely if (ret) 1027ca632f55SGrant Likely goto err_alloc_rx_sg; 1028ca632f55SGrant Likely 1029ca632f55SGrant Likely ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); 1030ca632f55SGrant Likely if (ret) 1031ca632f55SGrant Likely goto err_alloc_tx_sg; 1032ca632f55SGrant Likely 1033ca632f55SGrant Likely /* Fill in the scatterlists for the RX+TX buffers */ 1034ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->rx, 1035ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_rx); 1036ca632f55SGrant Likely setup_dma_scatter(pl022, pl022->tx, 1037ca632f55SGrant Likely pl022->cur_transfer->len, &pl022->sgt_tx); 1038ca632f55SGrant Likely 1039ca632f55SGrant Likely /* Map DMA buffers */ 1040ca632f55SGrant Likely rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1041ca632f55SGrant Likely pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1042ca632f55SGrant Likely if (!rx_sglen) 1043ca632f55SGrant Likely goto err_rx_sgmap; 1044ca632f55SGrant Likely 1045ca632f55SGrant Likely tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1046ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1047ca632f55SGrant Likely if (!tx_sglen) 1048ca632f55SGrant Likely goto err_tx_sgmap; 1049ca632f55SGrant Likely 1050ca632f55SGrant Likely /* Send both scatterlists */ 1051ca632f55SGrant Likely rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1052ca632f55SGrant Likely pl022->sgt_rx.sgl, 1053ca632f55SGrant Likely rx_sglen, 1054ca632f55SGrant Likely DMA_FROM_DEVICE, 1055ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1056ca632f55SGrant Likely if (!rxdesc) 1057ca632f55SGrant Likely goto err_rxdesc; 1058ca632f55SGrant Likely 1059ca632f55SGrant Likely txdesc = txchan->device->device_prep_slave_sg(txchan, 1060ca632f55SGrant Likely pl022->sgt_tx.sgl, 1061ca632f55SGrant Likely tx_sglen, 1062ca632f55SGrant Likely DMA_TO_DEVICE, 1063ca632f55SGrant Likely DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1064ca632f55SGrant Likely if (!txdesc) 1065ca632f55SGrant Likely goto err_txdesc; 1066ca632f55SGrant Likely 1067ca632f55SGrant Likely /* Put the callback on the RX transfer only, that should finish last */ 1068ca632f55SGrant Likely rxdesc->callback = dma_callback; 1069ca632f55SGrant Likely rxdesc->callback_param = pl022; 1070ca632f55SGrant Likely 1071ca632f55SGrant Likely /* Submit and fire RX and TX with TX last so we're ready to read! */ 1072ca632f55SGrant Likely dmaengine_submit(rxdesc); 1073ca632f55SGrant Likely dmaengine_submit(txdesc); 1074ca632f55SGrant Likely dma_async_issue_pending(rxchan); 1075ca632f55SGrant Likely dma_async_issue_pending(txchan); 1076ca632f55SGrant Likely 1077ca632f55SGrant Likely return 0; 1078ca632f55SGrant Likely 1079ca632f55SGrant Likely err_txdesc: 1080ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1081ca632f55SGrant Likely err_rxdesc: 1082ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1083ca632f55SGrant Likely dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1084ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_TO_DEVICE); 1085ca632f55SGrant Likely err_tx_sgmap: 1086ca632f55SGrant Likely dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1087ca632f55SGrant Likely pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1088ca632f55SGrant Likely err_rx_sgmap: 1089ca632f55SGrant Likely sg_free_table(&pl022->sgt_tx); 1090ca632f55SGrant Likely err_alloc_tx_sg: 1091ca632f55SGrant Likely sg_free_table(&pl022->sgt_rx); 1092ca632f55SGrant Likely err_alloc_rx_sg: 1093ca632f55SGrant Likely return -ENOMEM; 1094ca632f55SGrant Likely } 1095ca632f55SGrant Likely 1096ca632f55SGrant Likely static int __init pl022_dma_probe(struct pl022 *pl022) 1097ca632f55SGrant Likely { 1098ca632f55SGrant Likely dma_cap_mask_t mask; 1099ca632f55SGrant Likely 1100ca632f55SGrant Likely /* Try to acquire a generic DMA engine slave channel */ 1101ca632f55SGrant Likely dma_cap_zero(mask); 1102ca632f55SGrant Likely dma_cap_set(DMA_SLAVE, mask); 1103ca632f55SGrant Likely /* 1104ca632f55SGrant Likely * We need both RX and TX channels to do DMA, else do none 1105ca632f55SGrant Likely * of them. 1106ca632f55SGrant Likely */ 1107ca632f55SGrant Likely pl022->dma_rx_channel = dma_request_channel(mask, 1108ca632f55SGrant Likely pl022->master_info->dma_filter, 1109ca632f55SGrant Likely pl022->master_info->dma_rx_param); 1110ca632f55SGrant Likely if (!pl022->dma_rx_channel) { 1111ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1112ca632f55SGrant Likely goto err_no_rxchan; 1113ca632f55SGrant Likely } 1114ca632f55SGrant Likely 1115ca632f55SGrant Likely pl022->dma_tx_channel = dma_request_channel(mask, 1116ca632f55SGrant Likely pl022->master_info->dma_filter, 1117ca632f55SGrant Likely pl022->master_info->dma_tx_param); 1118ca632f55SGrant Likely if (!pl022->dma_tx_channel) { 1119ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1120ca632f55SGrant Likely goto err_no_txchan; 1121ca632f55SGrant Likely } 1122ca632f55SGrant Likely 1123ca632f55SGrant Likely pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1124ca632f55SGrant Likely if (!pl022->dummypage) { 1125ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1126ca632f55SGrant Likely goto err_no_dummypage; 1127ca632f55SGrant Likely } 1128ca632f55SGrant Likely 1129ca632f55SGrant Likely dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1130ca632f55SGrant Likely dma_chan_name(pl022->dma_rx_channel), 1131ca632f55SGrant Likely dma_chan_name(pl022->dma_tx_channel)); 1132ca632f55SGrant Likely 1133ca632f55SGrant Likely return 0; 1134ca632f55SGrant Likely 1135ca632f55SGrant Likely err_no_dummypage: 1136ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1137ca632f55SGrant Likely err_no_txchan: 1138ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1139ca632f55SGrant Likely pl022->dma_rx_channel = NULL; 1140ca632f55SGrant Likely err_no_rxchan: 1141ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1142ca632f55SGrant Likely "Failed to work in dma mode, work without dma!\n"); 1143ca632f55SGrant Likely return -ENODEV; 1144ca632f55SGrant Likely } 1145ca632f55SGrant Likely 1146ca632f55SGrant Likely static void terminate_dma(struct pl022 *pl022) 1147ca632f55SGrant Likely { 1148ca632f55SGrant Likely struct dma_chan *rxchan = pl022->dma_rx_channel; 1149ca632f55SGrant Likely struct dma_chan *txchan = pl022->dma_tx_channel; 1150ca632f55SGrant Likely 1151ca632f55SGrant Likely dmaengine_terminate_all(rxchan); 1152ca632f55SGrant Likely dmaengine_terminate_all(txchan); 1153ca632f55SGrant Likely unmap_free_dma_scatter(pl022); 1154ca632f55SGrant Likely } 1155ca632f55SGrant Likely 1156ca632f55SGrant Likely static void pl022_dma_remove(struct pl022 *pl022) 1157ca632f55SGrant Likely { 1158ca632f55SGrant Likely if (pl022->busy) 1159ca632f55SGrant Likely terminate_dma(pl022); 1160ca632f55SGrant Likely if (pl022->dma_tx_channel) 1161ca632f55SGrant Likely dma_release_channel(pl022->dma_tx_channel); 1162ca632f55SGrant Likely if (pl022->dma_rx_channel) 1163ca632f55SGrant Likely dma_release_channel(pl022->dma_rx_channel); 1164ca632f55SGrant Likely kfree(pl022->dummypage); 1165ca632f55SGrant Likely } 1166ca632f55SGrant Likely 1167ca632f55SGrant Likely #else 1168ca632f55SGrant Likely static inline int configure_dma(struct pl022 *pl022) 1169ca632f55SGrant Likely { 1170ca632f55SGrant Likely return -ENODEV; 1171ca632f55SGrant Likely } 1172ca632f55SGrant Likely 1173ca632f55SGrant Likely static inline int pl022_dma_probe(struct pl022 *pl022) 1174ca632f55SGrant Likely { 1175ca632f55SGrant Likely return 0; 1176ca632f55SGrant Likely } 1177ca632f55SGrant Likely 1178ca632f55SGrant Likely static inline void pl022_dma_remove(struct pl022 *pl022) 1179ca632f55SGrant Likely { 1180ca632f55SGrant Likely } 1181ca632f55SGrant Likely #endif 1182ca632f55SGrant Likely 1183ca632f55SGrant Likely /** 1184ca632f55SGrant Likely * pl022_interrupt_handler - Interrupt handler for SSP controller 1185ca632f55SGrant Likely * 1186ca632f55SGrant Likely * This function handles interrupts generated for an interrupt based transfer. 1187ca632f55SGrant Likely * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1188ca632f55SGrant Likely * current message's state as STATE_ERROR and schedule the tasklet 1189ca632f55SGrant Likely * pump_transfers which will do the postprocessing of the current message by 1190ca632f55SGrant Likely * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1191ca632f55SGrant Likely * more data, and writes data in TX FIFO till it is not full. If we complete 1192ca632f55SGrant Likely * the transfer we move to the next transfer and schedule the tasklet. 1193ca632f55SGrant Likely */ 1194ca632f55SGrant Likely static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1195ca632f55SGrant Likely { 1196ca632f55SGrant Likely struct pl022 *pl022 = dev_id; 1197ca632f55SGrant Likely struct spi_message *msg = pl022->cur_msg; 1198ca632f55SGrant Likely u16 irq_status = 0; 1199ca632f55SGrant Likely u16 flag = 0; 1200ca632f55SGrant Likely 1201ca632f55SGrant Likely if (unlikely(!msg)) { 1202ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1203ca632f55SGrant Likely "bad message state in interrupt handler"); 1204ca632f55SGrant Likely /* Never fail */ 1205ca632f55SGrant Likely return IRQ_HANDLED; 1206ca632f55SGrant Likely } 1207ca632f55SGrant Likely 1208ca632f55SGrant Likely /* Read the Interrupt Status Register */ 1209ca632f55SGrant Likely irq_status = readw(SSP_MIS(pl022->virtbase)); 1210ca632f55SGrant Likely 1211ca632f55SGrant Likely if (unlikely(!irq_status)) 1212ca632f55SGrant Likely return IRQ_NONE; 1213ca632f55SGrant Likely 1214ca632f55SGrant Likely /* 1215ca632f55SGrant Likely * This handles the FIFO interrupts, the timeout 1216ca632f55SGrant Likely * interrupts are flatly ignored, they cannot be 1217ca632f55SGrant Likely * trusted. 1218ca632f55SGrant Likely */ 1219ca632f55SGrant Likely if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1220ca632f55SGrant Likely /* 1221ca632f55SGrant Likely * Overrun interrupt - bail out since our Data has been 1222ca632f55SGrant Likely * corrupted 1223ca632f55SGrant Likely */ 1224ca632f55SGrant Likely dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1225ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1226ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1227ca632f55SGrant Likely "RXFIFO is full\n"); 1228ca632f55SGrant Likely if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1229ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1230ca632f55SGrant Likely "TXFIFO is full\n"); 1231ca632f55SGrant Likely 1232ca632f55SGrant Likely /* 1233ca632f55SGrant Likely * Disable and clear interrupts, disable SSP, 1234ca632f55SGrant Likely * mark message with bad status so it can be 1235ca632f55SGrant Likely * retried. 1236ca632f55SGrant Likely */ 1237ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1238ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1239ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1240ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & 1241ca632f55SGrant Likely (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1242ca632f55SGrant Likely msg->state = STATE_ERROR; 1243ca632f55SGrant Likely 1244ca632f55SGrant Likely /* Schedule message queue handler */ 1245ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1246ca632f55SGrant Likely return IRQ_HANDLED; 1247ca632f55SGrant Likely } 1248ca632f55SGrant Likely 1249ca632f55SGrant Likely readwriter(pl022); 1250ca632f55SGrant Likely 1251ca632f55SGrant Likely if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1252ca632f55SGrant Likely flag = 1; 1253ca632f55SGrant Likely /* Disable Transmit interrupt */ 1254ca632f55SGrant Likely writew(readw(SSP_IMSC(pl022->virtbase)) & 1255ca632f55SGrant Likely (~SSP_IMSC_MASK_TXIM), 1256ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1257ca632f55SGrant Likely } 1258ca632f55SGrant Likely 1259ca632f55SGrant Likely /* 1260ca632f55SGrant Likely * Since all transactions must write as much as shall be read, 1261ca632f55SGrant Likely * we can conclude the entire transaction once RX is complete. 1262ca632f55SGrant Likely * At this point, all TX will always be finished. 1263ca632f55SGrant Likely */ 1264ca632f55SGrant Likely if (pl022->rx >= pl022->rx_end) { 1265ca632f55SGrant Likely writew(DISABLE_ALL_INTERRUPTS, 1266ca632f55SGrant Likely SSP_IMSC(pl022->virtbase)); 1267ca632f55SGrant Likely writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1268ca632f55SGrant Likely if (unlikely(pl022->rx > pl022->rx_end)) { 1269ca632f55SGrant Likely dev_warn(&pl022->adev->dev, "read %u surplus " 1270ca632f55SGrant Likely "bytes (did you request an odd " 1271ca632f55SGrant Likely "number of bytes on a 16bit bus?)\n", 1272ca632f55SGrant Likely (u32) (pl022->rx - pl022->rx_end)); 1273ca632f55SGrant Likely } 1274ca632f55SGrant Likely /* Update total bytes transferred */ 1275ca632f55SGrant Likely msg->actual_length += pl022->cur_transfer->len; 1276ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1277ca632f55SGrant Likely pl022->cur_chip-> 1278ca632f55SGrant Likely cs_control(SSP_CHIP_DESELECT); 1279ca632f55SGrant Likely /* Move to next transfer */ 1280ca632f55SGrant Likely msg->state = next_transfer(pl022); 1281ca632f55SGrant Likely tasklet_schedule(&pl022->pump_transfers); 1282ca632f55SGrant Likely return IRQ_HANDLED; 1283ca632f55SGrant Likely } 1284ca632f55SGrant Likely 1285ca632f55SGrant Likely return IRQ_HANDLED; 1286ca632f55SGrant Likely } 1287ca632f55SGrant Likely 1288ca632f55SGrant Likely /** 1289ca632f55SGrant Likely * This sets up the pointers to memory for the next message to 1290ca632f55SGrant Likely * send out on the SPI bus. 1291ca632f55SGrant Likely */ 1292ca632f55SGrant Likely static int set_up_next_transfer(struct pl022 *pl022, 1293ca632f55SGrant Likely struct spi_transfer *transfer) 1294ca632f55SGrant Likely { 1295ca632f55SGrant Likely int residue; 1296ca632f55SGrant Likely 1297ca632f55SGrant Likely /* Sanity check the message for this bus width */ 1298ca632f55SGrant Likely residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1299ca632f55SGrant Likely if (unlikely(residue != 0)) { 1300ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1301ca632f55SGrant Likely "message of %u bytes to transmit but the current " 1302ca632f55SGrant Likely "chip bus has a data width of %u bytes!\n", 1303ca632f55SGrant Likely pl022->cur_transfer->len, 1304ca632f55SGrant Likely pl022->cur_chip->n_bytes); 1305ca632f55SGrant Likely dev_err(&pl022->adev->dev, "skipping this message\n"); 1306ca632f55SGrant Likely return -EIO; 1307ca632f55SGrant Likely } 1308ca632f55SGrant Likely pl022->tx = (void *)transfer->tx_buf; 1309ca632f55SGrant Likely pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1310ca632f55SGrant Likely pl022->rx = (void *)transfer->rx_buf; 1311ca632f55SGrant Likely pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1312ca632f55SGrant Likely pl022->write = 1313ca632f55SGrant Likely pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1314ca632f55SGrant Likely pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1315ca632f55SGrant Likely return 0; 1316ca632f55SGrant Likely } 1317ca632f55SGrant Likely 1318ca632f55SGrant Likely /** 1319ca632f55SGrant Likely * pump_transfers - Tasklet function which schedules next transfer 1320ca632f55SGrant Likely * when running in interrupt or DMA transfer mode. 1321ca632f55SGrant Likely * @data: SSP driver private data structure 1322ca632f55SGrant Likely * 1323ca632f55SGrant Likely */ 1324ca632f55SGrant Likely static void pump_transfers(unsigned long data) 1325ca632f55SGrant Likely { 1326ca632f55SGrant Likely struct pl022 *pl022 = (struct pl022 *) data; 1327ca632f55SGrant Likely struct spi_message *message = NULL; 1328ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1329ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1330ca632f55SGrant Likely 1331ca632f55SGrant Likely /* Get current state information */ 1332ca632f55SGrant Likely message = pl022->cur_msg; 1333ca632f55SGrant Likely transfer = pl022->cur_transfer; 1334ca632f55SGrant Likely 1335ca632f55SGrant Likely /* Handle for abort */ 1336ca632f55SGrant Likely if (message->state == STATE_ERROR) { 1337ca632f55SGrant Likely message->status = -EIO; 1338ca632f55SGrant Likely giveback(pl022); 1339ca632f55SGrant Likely return; 1340ca632f55SGrant Likely } 1341ca632f55SGrant Likely 1342ca632f55SGrant Likely /* Handle end of message */ 1343ca632f55SGrant Likely if (message->state == STATE_DONE) { 1344ca632f55SGrant Likely message->status = 0; 1345ca632f55SGrant Likely giveback(pl022); 1346ca632f55SGrant Likely return; 1347ca632f55SGrant Likely } 1348ca632f55SGrant Likely 1349ca632f55SGrant Likely /* Delay if requested at end of transfer before CS change */ 1350ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1351ca632f55SGrant Likely previous = list_entry(transfer->transfer_list.prev, 1352ca632f55SGrant Likely struct spi_transfer, 1353ca632f55SGrant Likely transfer_list); 1354ca632f55SGrant Likely if (previous->delay_usecs) 1355ca632f55SGrant Likely /* 1356ca632f55SGrant Likely * FIXME: This runs in interrupt context. 1357ca632f55SGrant Likely * Is this really smart? 1358ca632f55SGrant Likely */ 1359ca632f55SGrant Likely udelay(previous->delay_usecs); 1360ca632f55SGrant Likely 1361ca632f55SGrant Likely /* Drop chip select only if cs_change is requested */ 1362ca632f55SGrant Likely if (previous->cs_change) 1363ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1364ca632f55SGrant Likely } else { 1365ca632f55SGrant Likely /* STATE_START */ 1366ca632f55SGrant Likely message->state = STATE_RUNNING; 1367ca632f55SGrant Likely } 1368ca632f55SGrant Likely 1369ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1370ca632f55SGrant Likely message->state = STATE_ERROR; 1371ca632f55SGrant Likely message->status = -EIO; 1372ca632f55SGrant Likely giveback(pl022); 1373ca632f55SGrant Likely return; 1374ca632f55SGrant Likely } 1375ca632f55SGrant Likely /* Flush the FIFOs and let's go! */ 1376ca632f55SGrant Likely flush(pl022); 1377ca632f55SGrant Likely 1378ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1379ca632f55SGrant Likely if (configure_dma(pl022)) { 1380ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1381ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1382ca632f55SGrant Likely goto err_config_dma; 1383ca632f55SGrant Likely } 1384ca632f55SGrant Likely return; 1385ca632f55SGrant Likely } 1386ca632f55SGrant Likely 1387ca632f55SGrant Likely err_config_dma: 1388ca632f55SGrant Likely writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 1389ca632f55SGrant Likely } 1390ca632f55SGrant Likely 1391ca632f55SGrant Likely static void do_interrupt_dma_transfer(struct pl022 *pl022) 1392ca632f55SGrant Likely { 1393ca632f55SGrant Likely u32 irqflags = ENABLE_ALL_INTERRUPTS; 1394ca632f55SGrant Likely 1395ca632f55SGrant Likely /* Enable target chip */ 1396ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1397ca632f55SGrant Likely if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1398ca632f55SGrant Likely /* Error path */ 1399ca632f55SGrant Likely pl022->cur_msg->state = STATE_ERROR; 1400ca632f55SGrant Likely pl022->cur_msg->status = -EIO; 1401ca632f55SGrant Likely giveback(pl022); 1402ca632f55SGrant Likely return; 1403ca632f55SGrant Likely } 1404ca632f55SGrant Likely /* If we're using DMA, set up DMA here */ 1405ca632f55SGrant Likely if (pl022->cur_chip->enable_dma) { 1406ca632f55SGrant Likely /* Configure DMA transfer */ 1407ca632f55SGrant Likely if (configure_dma(pl022)) { 1408ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1409ca632f55SGrant Likely "configuration of DMA failed, fall back to interrupt mode\n"); 1410ca632f55SGrant Likely goto err_config_dma; 1411ca632f55SGrant Likely } 1412ca632f55SGrant Likely /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1413ca632f55SGrant Likely irqflags = DISABLE_ALL_INTERRUPTS; 1414ca632f55SGrant Likely } 1415ca632f55SGrant Likely err_config_dma: 1416ca632f55SGrant Likely /* Enable SSP, turn on interrupts */ 1417ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1418ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1419ca632f55SGrant Likely writew(irqflags, SSP_IMSC(pl022->virtbase)); 1420ca632f55SGrant Likely } 1421ca632f55SGrant Likely 1422ca632f55SGrant Likely static void do_polling_transfer(struct pl022 *pl022) 1423ca632f55SGrant Likely { 1424ca632f55SGrant Likely struct spi_message *message = NULL; 1425ca632f55SGrant Likely struct spi_transfer *transfer = NULL; 1426ca632f55SGrant Likely struct spi_transfer *previous = NULL; 1427ca632f55SGrant Likely struct chip_data *chip; 1428ca632f55SGrant Likely unsigned long time, timeout; 1429ca632f55SGrant Likely 1430ca632f55SGrant Likely chip = pl022->cur_chip; 1431ca632f55SGrant Likely message = pl022->cur_msg; 1432ca632f55SGrant Likely 1433ca632f55SGrant Likely while (message->state != STATE_DONE) { 1434ca632f55SGrant Likely /* Handle for abort */ 1435ca632f55SGrant Likely if (message->state == STATE_ERROR) 1436ca632f55SGrant Likely break; 1437ca632f55SGrant Likely transfer = pl022->cur_transfer; 1438ca632f55SGrant Likely 1439ca632f55SGrant Likely /* Delay if requested at end of transfer */ 1440ca632f55SGrant Likely if (message->state == STATE_RUNNING) { 1441ca632f55SGrant Likely previous = 1442ca632f55SGrant Likely list_entry(transfer->transfer_list.prev, 1443ca632f55SGrant Likely struct spi_transfer, transfer_list); 1444ca632f55SGrant Likely if (previous->delay_usecs) 1445ca632f55SGrant Likely udelay(previous->delay_usecs); 1446ca632f55SGrant Likely if (previous->cs_change) 1447ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1448ca632f55SGrant Likely } else { 1449ca632f55SGrant Likely /* STATE_START */ 1450ca632f55SGrant Likely message->state = STATE_RUNNING; 1451ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1452ca632f55SGrant Likely } 1453ca632f55SGrant Likely 1454ca632f55SGrant Likely /* Configuration Changing Per Transfer */ 1455ca632f55SGrant Likely if (set_up_next_transfer(pl022, transfer)) { 1456ca632f55SGrant Likely /* Error path */ 1457ca632f55SGrant Likely message->state = STATE_ERROR; 1458ca632f55SGrant Likely break; 1459ca632f55SGrant Likely } 1460ca632f55SGrant Likely /* Flush FIFOs and enable SSP */ 1461ca632f55SGrant Likely flush(pl022); 1462ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1463ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 1464ca632f55SGrant Likely 1465ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1466ca632f55SGrant Likely 1467ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1468ca632f55SGrant Likely while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1469ca632f55SGrant Likely time = jiffies; 1470ca632f55SGrant Likely readwriter(pl022); 1471ca632f55SGrant Likely if (time_after(time, timeout)) { 1472ca632f55SGrant Likely dev_warn(&pl022->adev->dev, 1473ca632f55SGrant Likely "%s: timeout!\n", __func__); 1474ca632f55SGrant Likely message->state = STATE_ERROR; 1475ca632f55SGrant Likely goto out; 1476ca632f55SGrant Likely } 1477ca632f55SGrant Likely cpu_relax(); 1478ca632f55SGrant Likely } 1479ca632f55SGrant Likely 1480ca632f55SGrant Likely /* Update total byte transferred */ 1481ca632f55SGrant Likely message->actual_length += pl022->cur_transfer->len; 1482ca632f55SGrant Likely if (pl022->cur_transfer->cs_change) 1483ca632f55SGrant Likely pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1484ca632f55SGrant Likely /* Move to next transfer */ 1485ca632f55SGrant Likely message->state = next_transfer(pl022); 1486ca632f55SGrant Likely } 1487ca632f55SGrant Likely out: 1488ca632f55SGrant Likely /* Handle end of message */ 1489ca632f55SGrant Likely if (message->state == STATE_DONE) 1490ca632f55SGrant Likely message->status = 0; 1491ca632f55SGrant Likely else 1492ca632f55SGrant Likely message->status = -EIO; 1493ca632f55SGrant Likely 1494ca632f55SGrant Likely giveback(pl022); 1495ca632f55SGrant Likely return; 1496ca632f55SGrant Likely } 1497ca632f55SGrant Likely 1498ca632f55SGrant Likely /** 1499ca632f55SGrant Likely * pump_messages - Workqueue function which processes spi message queue 1500ca632f55SGrant Likely * @data: pointer to private data of SSP driver 1501ca632f55SGrant Likely * 1502ca632f55SGrant Likely * This function checks if there is any spi message in the queue that 1503ca632f55SGrant Likely * needs processing and delegate control to appropriate function 1504ca632f55SGrant Likely * do_polling_transfer()/do_interrupt_dma_transfer() 1505ca632f55SGrant Likely * based on the kind of the transfer 1506ca632f55SGrant Likely * 1507ca632f55SGrant Likely */ 1508ca632f55SGrant Likely static void pump_messages(struct work_struct *work) 1509ca632f55SGrant Likely { 1510ca632f55SGrant Likely struct pl022 *pl022 = 1511ca632f55SGrant Likely container_of(work, struct pl022, pump_messages); 1512ca632f55SGrant Likely unsigned long flags; 1513ca632f55SGrant Likely 1514ca632f55SGrant Likely /* Lock queue and check for queue work */ 1515ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1516ca632f55SGrant Likely if (list_empty(&pl022->queue) || !pl022->running) { 1517ca632f55SGrant Likely pl022->busy = false; 1518ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1519ca632f55SGrant Likely return; 1520ca632f55SGrant Likely } 1521ca632f55SGrant Likely /* Make sure we are not already running a message */ 1522ca632f55SGrant Likely if (pl022->cur_msg) { 1523ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1524ca632f55SGrant Likely return; 1525ca632f55SGrant Likely } 1526ca632f55SGrant Likely /* Extract head of queue */ 1527ca632f55SGrant Likely pl022->cur_msg = 1528ca632f55SGrant Likely list_entry(pl022->queue.next, struct spi_message, queue); 1529ca632f55SGrant Likely 1530ca632f55SGrant Likely list_del_init(&pl022->cur_msg->queue); 1531ca632f55SGrant Likely pl022->busy = true; 1532ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1533ca632f55SGrant Likely 1534ca632f55SGrant Likely /* Initial message state */ 1535ca632f55SGrant Likely pl022->cur_msg->state = STATE_START; 1536ca632f55SGrant Likely pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, 1537ca632f55SGrant Likely struct spi_transfer, 1538ca632f55SGrant Likely transfer_list); 1539ca632f55SGrant Likely 1540ca632f55SGrant Likely /* Setup the SPI using the per chip configuration */ 1541ca632f55SGrant Likely pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); 1542ca632f55SGrant Likely /* 1543ca632f55SGrant Likely * We enable the core voltage and clocks here, then the clocks 1544ca632f55SGrant Likely * and core will be disabled when giveback() is called in each method 1545ca632f55SGrant Likely * (poll/interrupt/DMA) 1546ca632f55SGrant Likely */ 1547bcda6ff8SRabin Vincent pm_runtime_get_sync(&pl022->adev->dev); 1548ca632f55SGrant Likely amba_vcore_enable(pl022->adev); 1549ca632f55SGrant Likely amba_pclk_enable(pl022->adev); 1550ca632f55SGrant Likely clk_enable(pl022->clk); 1551ca632f55SGrant Likely restore_state(pl022); 1552ca632f55SGrant Likely flush(pl022); 1553ca632f55SGrant Likely 1554ca632f55SGrant Likely if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1555ca632f55SGrant Likely do_polling_transfer(pl022); 1556ca632f55SGrant Likely else 1557ca632f55SGrant Likely do_interrupt_dma_transfer(pl022); 1558ca632f55SGrant Likely } 1559ca632f55SGrant Likely 1560ca632f55SGrant Likely 1561ca632f55SGrant Likely static int __init init_queue(struct pl022 *pl022) 1562ca632f55SGrant Likely { 1563ca632f55SGrant Likely INIT_LIST_HEAD(&pl022->queue); 1564ca632f55SGrant Likely spin_lock_init(&pl022->queue_lock); 1565ca632f55SGrant Likely 1566ca632f55SGrant Likely pl022->running = false; 1567ca632f55SGrant Likely pl022->busy = false; 1568ca632f55SGrant Likely 1569ca632f55SGrant Likely tasklet_init(&pl022->pump_transfers, 1570ca632f55SGrant Likely pump_transfers, (unsigned long)pl022); 1571ca632f55SGrant Likely 1572ca632f55SGrant Likely INIT_WORK(&pl022->pump_messages, pump_messages); 1573ca632f55SGrant Likely pl022->workqueue = create_singlethread_workqueue( 1574ca632f55SGrant Likely dev_name(pl022->master->dev.parent)); 1575ca632f55SGrant Likely if (pl022->workqueue == NULL) 1576ca632f55SGrant Likely return -EBUSY; 1577ca632f55SGrant Likely 1578ca632f55SGrant Likely return 0; 1579ca632f55SGrant Likely } 1580ca632f55SGrant Likely 1581ca632f55SGrant Likely 1582ca632f55SGrant Likely static int start_queue(struct pl022 *pl022) 1583ca632f55SGrant Likely { 1584ca632f55SGrant Likely unsigned long flags; 1585ca632f55SGrant Likely 1586ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1587ca632f55SGrant Likely 1588ca632f55SGrant Likely if (pl022->running || pl022->busy) { 1589ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1590ca632f55SGrant Likely return -EBUSY; 1591ca632f55SGrant Likely } 1592ca632f55SGrant Likely 1593ca632f55SGrant Likely pl022->running = true; 1594ca632f55SGrant Likely pl022->cur_msg = NULL; 1595ca632f55SGrant Likely pl022->cur_transfer = NULL; 1596ca632f55SGrant Likely pl022->cur_chip = NULL; 1597ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1598ca632f55SGrant Likely 1599ca632f55SGrant Likely queue_work(pl022->workqueue, &pl022->pump_messages); 1600ca632f55SGrant Likely 1601ca632f55SGrant Likely return 0; 1602ca632f55SGrant Likely } 1603ca632f55SGrant Likely 1604ca632f55SGrant Likely 1605ca632f55SGrant Likely static int stop_queue(struct pl022 *pl022) 1606ca632f55SGrant Likely { 1607ca632f55SGrant Likely unsigned long flags; 1608ca632f55SGrant Likely unsigned limit = 500; 1609ca632f55SGrant Likely int status = 0; 1610ca632f55SGrant Likely 1611ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1612ca632f55SGrant Likely 1613ca632f55SGrant Likely /* This is a bit lame, but is optimized for the common execution path. 1614ca632f55SGrant Likely * A wait_queue on the pl022->busy could be used, but then the common 1615ca632f55SGrant Likely * execution path (pump_messages) would be required to call wake_up or 1616ca632f55SGrant Likely * friends on every SPI message. Do this instead */ 1617ca632f55SGrant Likely while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { 1618ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1619ca632f55SGrant Likely msleep(10); 1620ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1621ca632f55SGrant Likely } 1622ca632f55SGrant Likely 1623ca632f55SGrant Likely if (!list_empty(&pl022->queue) || pl022->busy) 1624ca632f55SGrant Likely status = -EBUSY; 1625ca632f55SGrant Likely else 1626ca632f55SGrant Likely pl022->running = false; 1627ca632f55SGrant Likely 1628ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1629ca632f55SGrant Likely 1630ca632f55SGrant Likely return status; 1631ca632f55SGrant Likely } 1632ca632f55SGrant Likely 1633ca632f55SGrant Likely static int destroy_queue(struct pl022 *pl022) 1634ca632f55SGrant Likely { 1635ca632f55SGrant Likely int status; 1636ca632f55SGrant Likely 1637ca632f55SGrant Likely status = stop_queue(pl022); 1638ca632f55SGrant Likely /* we are unloading the module or failing to load (only two calls 1639ca632f55SGrant Likely * to this routine), and neither call can handle a return value. 1640ca632f55SGrant Likely * However, destroy_workqueue calls flush_workqueue, and that will 1641ca632f55SGrant Likely * block until all work is done. If the reason that stop_queue 1642ca632f55SGrant Likely * timed out is that the work will never finish, then it does no 1643ca632f55SGrant Likely * good to call destroy_workqueue, so return anyway. */ 1644ca632f55SGrant Likely if (status != 0) 1645ca632f55SGrant Likely return status; 1646ca632f55SGrant Likely 1647ca632f55SGrant Likely destroy_workqueue(pl022->workqueue); 1648ca632f55SGrant Likely 1649ca632f55SGrant Likely return 0; 1650ca632f55SGrant Likely } 1651ca632f55SGrant Likely 1652ca632f55SGrant Likely static int verify_controller_parameters(struct pl022 *pl022, 1653ca632f55SGrant Likely struct pl022_config_chip const *chip_info) 1654ca632f55SGrant Likely { 1655ca632f55SGrant Likely if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1656ca632f55SGrant Likely || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1657ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1658ca632f55SGrant Likely "interface is configured incorrectly\n"); 1659ca632f55SGrant Likely return -EINVAL; 1660ca632f55SGrant Likely } 1661ca632f55SGrant Likely if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1662ca632f55SGrant Likely (!pl022->vendor->unidir)) { 1663ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1664ca632f55SGrant Likely "unidirectional mode not supported in this " 1665ca632f55SGrant Likely "hardware version\n"); 1666ca632f55SGrant Likely return -EINVAL; 1667ca632f55SGrant Likely } 1668ca632f55SGrant Likely if ((chip_info->hierarchy != SSP_MASTER) 1669ca632f55SGrant Likely && (chip_info->hierarchy != SSP_SLAVE)) { 1670ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1671ca632f55SGrant Likely "hierarchy is configured incorrectly\n"); 1672ca632f55SGrant Likely return -EINVAL; 1673ca632f55SGrant Likely } 1674ca632f55SGrant Likely if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1675ca632f55SGrant Likely && (chip_info->com_mode != DMA_TRANSFER) 1676ca632f55SGrant Likely && (chip_info->com_mode != POLLING_TRANSFER)) { 1677ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1678ca632f55SGrant Likely "Communication mode is configured incorrectly\n"); 1679ca632f55SGrant Likely return -EINVAL; 1680ca632f55SGrant Likely } 1681*78b2b911SLinus Walleij switch (chip_info->rx_lev_trig) { 1682*78b2b911SLinus Walleij case SSP_RX_1_OR_MORE_ELEM: 1683*78b2b911SLinus Walleij case SSP_RX_4_OR_MORE_ELEM: 1684*78b2b911SLinus Walleij case SSP_RX_8_OR_MORE_ELEM: 1685*78b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 1686*78b2b911SLinus Walleij break; 1687*78b2b911SLinus Walleij case SSP_RX_16_OR_MORE_ELEM: 1688*78b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1689ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1690ca632f55SGrant Likely "RX FIFO Trigger Level is configured incorrectly\n"); 1691ca632f55SGrant Likely return -EINVAL; 1692ca632f55SGrant Likely } 1693*78b2b911SLinus Walleij break; 1694*78b2b911SLinus Walleij case SSP_RX_32_OR_MORE_ELEM: 1695*78b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 1696*78b2b911SLinus Walleij dev_err(&pl022->adev->dev, 1697*78b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 1698*78b2b911SLinus Walleij return -EINVAL; 1699*78b2b911SLinus Walleij } 1700*78b2b911SLinus Walleij break; 1701*78b2b911SLinus Walleij default: 1702*78b2b911SLinus Walleij dev_err(&pl022->adev->dev, 1703*78b2b911SLinus Walleij "RX FIFO Trigger Level is configured incorrectly\n"); 1704*78b2b911SLinus Walleij return -EINVAL; 1705*78b2b911SLinus Walleij break; 1706*78b2b911SLinus Walleij } 1707*78b2b911SLinus Walleij switch (chip_info->tx_lev_trig) { 1708*78b2b911SLinus Walleij case SSP_TX_1_OR_MORE_EMPTY_LOC: 1709*78b2b911SLinus Walleij case SSP_TX_4_OR_MORE_EMPTY_LOC: 1710*78b2b911SLinus Walleij case SSP_TX_8_OR_MORE_EMPTY_LOC: 1711*78b2b911SLinus Walleij /* These are always OK, all variants can handle this */ 1712*78b2b911SLinus Walleij break; 1713*78b2b911SLinus Walleij case SSP_TX_16_OR_MORE_EMPTY_LOC: 1714*78b2b911SLinus Walleij if (pl022->vendor->fifodepth < 16) { 1715ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1716ca632f55SGrant Likely "TX FIFO Trigger Level is configured incorrectly\n"); 1717ca632f55SGrant Likely return -EINVAL; 1718ca632f55SGrant Likely } 1719*78b2b911SLinus Walleij break; 1720*78b2b911SLinus Walleij case SSP_TX_32_OR_MORE_EMPTY_LOC: 1721*78b2b911SLinus Walleij if (pl022->vendor->fifodepth < 32) { 1722*78b2b911SLinus Walleij dev_err(&pl022->adev->dev, 1723*78b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 1724*78b2b911SLinus Walleij return -EINVAL; 1725*78b2b911SLinus Walleij } 1726*78b2b911SLinus Walleij break; 1727*78b2b911SLinus Walleij default: 1728*78b2b911SLinus Walleij dev_err(&pl022->adev->dev, 1729*78b2b911SLinus Walleij "TX FIFO Trigger Level is configured incorrectly\n"); 1730*78b2b911SLinus Walleij return -EINVAL; 1731*78b2b911SLinus Walleij break; 1732*78b2b911SLinus Walleij } 1733ca632f55SGrant Likely if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1734ca632f55SGrant Likely if ((chip_info->ctrl_len < SSP_BITS_4) 1735ca632f55SGrant Likely || (chip_info->ctrl_len > SSP_BITS_32)) { 1736ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1737ca632f55SGrant Likely "CTRL LEN is configured incorrectly\n"); 1738ca632f55SGrant Likely return -EINVAL; 1739ca632f55SGrant Likely } 1740ca632f55SGrant Likely if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1741ca632f55SGrant Likely && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1742ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1743ca632f55SGrant Likely "Wait State is configured incorrectly\n"); 1744ca632f55SGrant Likely return -EINVAL; 1745ca632f55SGrant Likely } 1746ca632f55SGrant Likely /* Half duplex is only available in the ST Micro version */ 1747ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 1748ca632f55SGrant Likely if ((chip_info->duplex != 1749ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1750ca632f55SGrant Likely && (chip_info->duplex != 1751ca632f55SGrant Likely SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1752ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1753ca632f55SGrant Likely "Microwire duplex mode is configured incorrectly\n"); 1754ca632f55SGrant Likely return -EINVAL; 1755ca632f55SGrant Likely } 1756ca632f55SGrant Likely } else { 1757ca632f55SGrant Likely if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1758ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1759ca632f55SGrant Likely "Microwire half duplex mode requested," 1760ca632f55SGrant Likely " but this is only available in the" 1761ca632f55SGrant Likely " ST version of PL022\n"); 1762ca632f55SGrant Likely return -EINVAL; 1763ca632f55SGrant Likely } 1764ca632f55SGrant Likely } 1765ca632f55SGrant Likely return 0; 1766ca632f55SGrant Likely } 1767ca632f55SGrant Likely 1768ca632f55SGrant Likely /** 1769ca632f55SGrant Likely * pl022_transfer - transfer function registered to SPI master framework 1770ca632f55SGrant Likely * @spi: spi device which is requesting transfer 1771ca632f55SGrant Likely * @msg: spi message which is to handled is queued to driver queue 1772ca632f55SGrant Likely * 1773ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1774ca632f55SGrant Likely * controller. It will queue the spi_message in the queue of driver if 1775ca632f55SGrant Likely * the queue is not stopped and return. 1776ca632f55SGrant Likely */ 1777ca632f55SGrant Likely static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) 1778ca632f55SGrant Likely { 1779ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1780ca632f55SGrant Likely unsigned long flags; 1781ca632f55SGrant Likely 1782ca632f55SGrant Likely spin_lock_irqsave(&pl022->queue_lock, flags); 1783ca632f55SGrant Likely 1784ca632f55SGrant Likely if (!pl022->running) { 1785ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1786ca632f55SGrant Likely return -ESHUTDOWN; 1787ca632f55SGrant Likely } 1788ca632f55SGrant Likely msg->actual_length = 0; 1789ca632f55SGrant Likely msg->status = -EINPROGRESS; 1790ca632f55SGrant Likely msg->state = STATE_START; 1791ca632f55SGrant Likely 1792ca632f55SGrant Likely list_add_tail(&msg->queue, &pl022->queue); 1793ca632f55SGrant Likely if (pl022->running && !pl022->busy) 1794ca632f55SGrant Likely queue_work(pl022->workqueue, &pl022->pump_messages); 1795ca632f55SGrant Likely 1796ca632f55SGrant Likely spin_unlock_irqrestore(&pl022->queue_lock, flags); 1797ca632f55SGrant Likely return 0; 1798ca632f55SGrant Likely } 1799ca632f55SGrant Likely 1800ca632f55SGrant Likely static int calculate_effective_freq(struct pl022 *pl022, 1801ca632f55SGrant Likely int freq, 1802ca632f55SGrant Likely struct ssp_clock_params *clk_freq) 1803ca632f55SGrant Likely { 1804ca632f55SGrant Likely /* Lets calculate the frequency parameters */ 1805ca632f55SGrant Likely u16 cpsdvsr = 2; 1806ca632f55SGrant Likely u16 scr = 0; 1807ca632f55SGrant Likely bool freq_found = false; 1808ca632f55SGrant Likely u32 rate; 1809ca632f55SGrant Likely u32 max_tclk; 1810ca632f55SGrant Likely u32 min_tclk; 1811ca632f55SGrant Likely 1812ca632f55SGrant Likely rate = clk_get_rate(pl022->clk); 1813ca632f55SGrant Likely /* cpsdvscr = 2 & scr 0 */ 1814ca632f55SGrant Likely max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); 1815ca632f55SGrant Likely /* cpsdvsr = 254 & scr = 255 */ 1816ca632f55SGrant Likely min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); 1817ca632f55SGrant Likely 1818ca632f55SGrant Likely if ((freq <= max_tclk) && (freq >= min_tclk)) { 1819ca632f55SGrant Likely while (cpsdvsr <= CPSDVR_MAX && !freq_found) { 1820ca632f55SGrant Likely while (scr <= SCR_MAX && !freq_found) { 1821ca632f55SGrant Likely if ((rate / 1822ca632f55SGrant Likely (cpsdvsr * (1 + scr))) > freq) 1823ca632f55SGrant Likely scr += 1; 1824ca632f55SGrant Likely else { 1825ca632f55SGrant Likely /* 1826ca632f55SGrant Likely * This bool is made true when 1827ca632f55SGrant Likely * effective frequency >= 1828ca632f55SGrant Likely * target frequency is found 1829ca632f55SGrant Likely */ 1830ca632f55SGrant Likely freq_found = true; 1831ca632f55SGrant Likely if ((rate / 1832ca632f55SGrant Likely (cpsdvsr * (1 + scr))) != freq) { 1833ca632f55SGrant Likely if (scr == SCR_MIN) { 1834ca632f55SGrant Likely cpsdvsr -= 2; 1835ca632f55SGrant Likely scr = SCR_MAX; 1836ca632f55SGrant Likely } else 1837ca632f55SGrant Likely scr -= 1; 1838ca632f55SGrant Likely } 1839ca632f55SGrant Likely } 1840ca632f55SGrant Likely } 1841ca632f55SGrant Likely if (!freq_found) { 1842ca632f55SGrant Likely cpsdvsr += 2; 1843ca632f55SGrant Likely scr = SCR_MIN; 1844ca632f55SGrant Likely } 1845ca632f55SGrant Likely } 1846ca632f55SGrant Likely if (cpsdvsr != 0) { 1847ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1848ca632f55SGrant Likely "SSP Effective Frequency is %u\n", 1849ca632f55SGrant Likely (rate / (cpsdvsr * (1 + scr)))); 1850ca632f55SGrant Likely clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); 1851ca632f55SGrant Likely clk_freq->scr = (u8) (scr & 0xFF); 1852ca632f55SGrant Likely dev_dbg(&pl022->adev->dev, 1853ca632f55SGrant Likely "SSP cpsdvsr = %d, scr = %d\n", 1854ca632f55SGrant Likely clk_freq->cpsdvsr, clk_freq->scr); 1855ca632f55SGrant Likely } 1856ca632f55SGrant Likely } else { 1857ca632f55SGrant Likely dev_err(&pl022->adev->dev, 1858ca632f55SGrant Likely "controller data is incorrect: out of range frequency"); 1859ca632f55SGrant Likely return -EINVAL; 1860ca632f55SGrant Likely } 1861ca632f55SGrant Likely return 0; 1862ca632f55SGrant Likely } 1863ca632f55SGrant Likely 1864ca632f55SGrant Likely 1865ca632f55SGrant Likely /* 1866ca632f55SGrant Likely * A piece of default chip info unless the platform 1867ca632f55SGrant Likely * supplies it. 1868ca632f55SGrant Likely */ 1869ca632f55SGrant Likely static const struct pl022_config_chip pl022_default_chip_info = { 1870ca632f55SGrant Likely .com_mode = POLLING_TRANSFER, 1871ca632f55SGrant Likely .iface = SSP_INTERFACE_MOTOROLA_SPI, 1872ca632f55SGrant Likely .hierarchy = SSP_SLAVE, 1873ca632f55SGrant Likely .slave_tx_disable = DO_NOT_DRIVE_TX, 1874ca632f55SGrant Likely .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1875ca632f55SGrant Likely .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1876ca632f55SGrant Likely .ctrl_len = SSP_BITS_8, 1877ca632f55SGrant Likely .wait_state = SSP_MWIRE_WAIT_ZERO, 1878ca632f55SGrant Likely .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1879ca632f55SGrant Likely .cs_control = null_cs_control, 1880ca632f55SGrant Likely }; 1881ca632f55SGrant Likely 1882ca632f55SGrant Likely 1883ca632f55SGrant Likely /** 1884ca632f55SGrant Likely * pl022_setup - setup function registered to SPI master framework 1885ca632f55SGrant Likely * @spi: spi device which is requesting setup 1886ca632f55SGrant Likely * 1887ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 1888ca632f55SGrant Likely * controller. If it is the first time when setup is called by this device, 1889ca632f55SGrant Likely * this function will initialize the runtime state for this chip and save 1890ca632f55SGrant Likely * the same in the device structure. Else it will update the runtime info 1891ca632f55SGrant Likely * with the updated chip info. Nothing is really being written to the 1892ca632f55SGrant Likely * controller hardware here, that is not done until the actual transfer 1893ca632f55SGrant Likely * commence. 1894ca632f55SGrant Likely */ 1895ca632f55SGrant Likely static int pl022_setup(struct spi_device *spi) 1896ca632f55SGrant Likely { 1897ca632f55SGrant Likely struct pl022_config_chip const *chip_info; 1898ca632f55SGrant Likely struct chip_data *chip; 1899ca632f55SGrant Likely struct ssp_clock_params clk_freq = {0, }; 1900ca632f55SGrant Likely int status = 0; 1901ca632f55SGrant Likely struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1902ca632f55SGrant Likely unsigned int bits = spi->bits_per_word; 1903ca632f55SGrant Likely u32 tmp; 1904ca632f55SGrant Likely 1905ca632f55SGrant Likely if (!spi->max_speed_hz) 1906ca632f55SGrant Likely return -EINVAL; 1907ca632f55SGrant Likely 1908ca632f55SGrant Likely /* Get controller_state if one is supplied */ 1909ca632f55SGrant Likely chip = spi_get_ctldata(spi); 1910ca632f55SGrant Likely 1911ca632f55SGrant Likely if (chip == NULL) { 1912ca632f55SGrant Likely chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1913ca632f55SGrant Likely if (!chip) { 1914ca632f55SGrant Likely dev_err(&spi->dev, 1915ca632f55SGrant Likely "cannot allocate controller state\n"); 1916ca632f55SGrant Likely return -ENOMEM; 1917ca632f55SGrant Likely } 1918ca632f55SGrant Likely dev_dbg(&spi->dev, 1919ca632f55SGrant Likely "allocated memory for controller's runtime state\n"); 1920ca632f55SGrant Likely } 1921ca632f55SGrant Likely 1922ca632f55SGrant Likely /* Get controller data if one is supplied */ 1923ca632f55SGrant Likely chip_info = spi->controller_data; 1924ca632f55SGrant Likely 1925ca632f55SGrant Likely if (chip_info == NULL) { 1926ca632f55SGrant Likely chip_info = &pl022_default_chip_info; 1927ca632f55SGrant Likely /* spi_board_info.controller_data not is supplied */ 1928ca632f55SGrant Likely dev_dbg(&spi->dev, 1929ca632f55SGrant Likely "using default controller_data settings\n"); 1930ca632f55SGrant Likely } else 1931ca632f55SGrant Likely dev_dbg(&spi->dev, 1932ca632f55SGrant Likely "using user supplied controller_data settings\n"); 1933ca632f55SGrant Likely 1934ca632f55SGrant Likely /* 1935ca632f55SGrant Likely * We can override with custom divisors, else we use the board 1936ca632f55SGrant Likely * frequency setting 1937ca632f55SGrant Likely */ 1938ca632f55SGrant Likely if ((0 == chip_info->clk_freq.cpsdvsr) 1939ca632f55SGrant Likely && (0 == chip_info->clk_freq.scr)) { 1940ca632f55SGrant Likely status = calculate_effective_freq(pl022, 1941ca632f55SGrant Likely spi->max_speed_hz, 1942ca632f55SGrant Likely &clk_freq); 1943ca632f55SGrant Likely if (status < 0) 1944ca632f55SGrant Likely goto err_config_params; 1945ca632f55SGrant Likely } else { 1946ca632f55SGrant Likely memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1947ca632f55SGrant Likely if ((clk_freq.cpsdvsr % 2) != 0) 1948ca632f55SGrant Likely clk_freq.cpsdvsr = 1949ca632f55SGrant Likely clk_freq.cpsdvsr - 1; 1950ca632f55SGrant Likely } 1951ca632f55SGrant Likely if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1952ca632f55SGrant Likely || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1953ca632f55SGrant Likely dev_err(&spi->dev, 1954ca632f55SGrant Likely "cpsdvsr is configured incorrectly\n"); 1955ca632f55SGrant Likely goto err_config_params; 1956ca632f55SGrant Likely } 1957ca632f55SGrant Likely 1958ca632f55SGrant Likely 1959ca632f55SGrant Likely status = verify_controller_parameters(pl022, chip_info); 1960ca632f55SGrant Likely if (status) { 1961ca632f55SGrant Likely dev_err(&spi->dev, "controller data is incorrect"); 1962ca632f55SGrant Likely goto err_config_params; 1963ca632f55SGrant Likely } 1964ca632f55SGrant Likely 1965083be3f0SLinus Walleij pl022->rx_lev_trig = chip_info->rx_lev_trig; 1966083be3f0SLinus Walleij pl022->tx_lev_trig = chip_info->tx_lev_trig; 1967083be3f0SLinus Walleij 1968ca632f55SGrant Likely /* Now set controller state based on controller data */ 1969ca632f55SGrant Likely chip->xfer_type = chip_info->com_mode; 1970ca632f55SGrant Likely if (!chip_info->cs_control) { 1971ca632f55SGrant Likely chip->cs_control = null_cs_control; 1972ca632f55SGrant Likely dev_warn(&spi->dev, 1973ca632f55SGrant Likely "chip select function is NULL for this chip\n"); 1974ca632f55SGrant Likely } else 1975ca632f55SGrant Likely chip->cs_control = chip_info->cs_control; 1976ca632f55SGrant Likely 1977ca632f55SGrant Likely if (bits <= 3) { 1978ca632f55SGrant Likely /* PL022 doesn't support less than 4-bits */ 1979ca632f55SGrant Likely status = -ENOTSUPP; 1980ca632f55SGrant Likely goto err_config_params; 1981ca632f55SGrant Likely } else if (bits <= 8) { 1982ca632f55SGrant Likely dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1983ca632f55SGrant Likely chip->n_bytes = 1; 1984ca632f55SGrant Likely chip->read = READING_U8; 1985ca632f55SGrant Likely chip->write = WRITING_U8; 1986ca632f55SGrant Likely } else if (bits <= 16) { 1987ca632f55SGrant Likely dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1988ca632f55SGrant Likely chip->n_bytes = 2; 1989ca632f55SGrant Likely chip->read = READING_U16; 1990ca632f55SGrant Likely chip->write = WRITING_U16; 1991ca632f55SGrant Likely } else { 1992ca632f55SGrant Likely if (pl022->vendor->max_bpw >= 32) { 1993ca632f55SGrant Likely dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1994ca632f55SGrant Likely chip->n_bytes = 4; 1995ca632f55SGrant Likely chip->read = READING_U32; 1996ca632f55SGrant Likely chip->write = WRITING_U32; 1997ca632f55SGrant Likely } else { 1998ca632f55SGrant Likely dev_err(&spi->dev, 1999ca632f55SGrant Likely "illegal data size for this controller!\n"); 2000ca632f55SGrant Likely dev_err(&spi->dev, 2001ca632f55SGrant Likely "a standard pl022 can only handle " 2002ca632f55SGrant Likely "1 <= n <= 16 bit words\n"); 2003ca632f55SGrant Likely status = -ENOTSUPP; 2004ca632f55SGrant Likely goto err_config_params; 2005ca632f55SGrant Likely } 2006ca632f55SGrant Likely } 2007ca632f55SGrant Likely 2008ca632f55SGrant Likely /* Now Initialize all register settings required for this chip */ 2009ca632f55SGrant Likely chip->cr0 = 0; 2010ca632f55SGrant Likely chip->cr1 = 0; 2011ca632f55SGrant Likely chip->dmacr = 0; 2012ca632f55SGrant Likely chip->cpsr = 0; 2013ca632f55SGrant Likely if ((chip_info->com_mode == DMA_TRANSFER) 2014ca632f55SGrant Likely && ((pl022->master_info)->enable_dma)) { 2015ca632f55SGrant Likely chip->enable_dma = true; 2016ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 2017ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2018ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 2019ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2020ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 2021ca632f55SGrant Likely } else { 2022ca632f55SGrant Likely chip->enable_dma = false; 2023ca632f55SGrant Likely dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 2024ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2025ca632f55SGrant Likely SSP_DMACR_MASK_RXDMAE, 0); 2026ca632f55SGrant Likely SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2027ca632f55SGrant Likely SSP_DMACR_MASK_TXDMAE, 1); 2028ca632f55SGrant Likely } 2029ca632f55SGrant Likely 2030ca632f55SGrant Likely chip->cpsr = clk_freq.cpsdvsr; 2031ca632f55SGrant Likely 2032ca632f55SGrant Likely /* Special setup for the ST micro extended control registers */ 2033ca632f55SGrant Likely if (pl022->vendor->extended_cr) { 2034ca632f55SGrant Likely u32 etx; 2035ca632f55SGrant Likely 2036ca632f55SGrant Likely if (pl022->vendor->pl023) { 2037ca632f55SGrant Likely /* These bits are only in the PL023 */ 2038ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2039ca632f55SGrant Likely SSP_CR1_MASK_FBCLKDEL_ST, 13); 2040ca632f55SGrant Likely } else { 2041ca632f55SGrant Likely /* These bits are in the PL022 but not PL023 */ 2042ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2043ca632f55SGrant Likely SSP_CR0_MASK_HALFDUP_ST, 5); 2044ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2045ca632f55SGrant Likely SSP_CR0_MASK_CSS_ST, 16); 2046ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2047ca632f55SGrant Likely SSP_CR0_MASK_FRF_ST, 21); 2048ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2049ca632f55SGrant Likely SSP_CR1_MASK_MWAIT_ST, 6); 2050ca632f55SGrant Likely } 2051ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2052ca632f55SGrant Likely SSP_CR0_MASK_DSS_ST, 0); 2053ca632f55SGrant Likely 2054ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) { 2055ca632f55SGrant Likely tmp = SSP_RX_LSB; 2056ca632f55SGrant Likely etx = SSP_TX_LSB; 2057ca632f55SGrant Likely } else { 2058ca632f55SGrant Likely tmp = SSP_RX_MSB; 2059ca632f55SGrant Likely etx = SSP_TX_MSB; 2060ca632f55SGrant Likely } 2061ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2062ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2063ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2064ca632f55SGrant Likely SSP_CR1_MASK_RXIFLSEL_ST, 7); 2065ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2066ca632f55SGrant Likely SSP_CR1_MASK_TXIFLSEL_ST, 10); 2067ca632f55SGrant Likely } else { 2068ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, bits - 1, 2069ca632f55SGrant Likely SSP_CR0_MASK_DSS, 0); 2070ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2071ca632f55SGrant Likely SSP_CR0_MASK_FRF, 4); 2072ca632f55SGrant Likely } 2073ca632f55SGrant Likely 2074ca632f55SGrant Likely /* Stuff that is common for all versions */ 2075ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 2076ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_HIGH; 2077ca632f55SGrant Likely else 2078ca632f55SGrant Likely tmp = SSP_CLK_POL_IDLE_LOW; 2079ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2080ca632f55SGrant Likely 2081ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 2082ca632f55SGrant Likely tmp = SSP_CLK_SECOND_EDGE; 2083ca632f55SGrant Likely else 2084ca632f55SGrant Likely tmp = SSP_CLK_FIRST_EDGE; 2085ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2086ca632f55SGrant Likely 2087ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2088ca632f55SGrant Likely /* Loopback is available on all versions except PL023 */ 2089ca632f55SGrant Likely if (pl022->vendor->loopback) { 2090ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 2091ca632f55SGrant Likely tmp = LOOPBACK_ENABLED; 2092ca632f55SGrant Likely else 2093ca632f55SGrant Likely tmp = LOOPBACK_DISABLED; 2094ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2095ca632f55SGrant Likely } 2096ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2097ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2098ca632f55SGrant Likely SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); 2099ca632f55SGrant Likely 2100ca632f55SGrant Likely /* Save controller_state */ 2101ca632f55SGrant Likely spi_set_ctldata(spi, chip); 2102ca632f55SGrant Likely return status; 2103ca632f55SGrant Likely err_config_params: 2104ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2105ca632f55SGrant Likely kfree(chip); 2106ca632f55SGrant Likely return status; 2107ca632f55SGrant Likely } 2108ca632f55SGrant Likely 2109ca632f55SGrant Likely /** 2110ca632f55SGrant Likely * pl022_cleanup - cleanup function registered to SPI master framework 2111ca632f55SGrant Likely * @spi: spi device which is requesting cleanup 2112ca632f55SGrant Likely * 2113ca632f55SGrant Likely * This function is registered to the SPI framework for this SPI master 2114ca632f55SGrant Likely * controller. It will free the runtime state of chip. 2115ca632f55SGrant Likely */ 2116ca632f55SGrant Likely static void pl022_cleanup(struct spi_device *spi) 2117ca632f55SGrant Likely { 2118ca632f55SGrant Likely struct chip_data *chip = spi_get_ctldata(spi); 2119ca632f55SGrant Likely 2120ca632f55SGrant Likely spi_set_ctldata(spi, NULL); 2121ca632f55SGrant Likely kfree(chip); 2122ca632f55SGrant Likely } 2123ca632f55SGrant Likely 2124ca632f55SGrant Likely 2125ca632f55SGrant Likely static int __devinit 2126ca632f55SGrant Likely pl022_probe(struct amba_device *adev, const struct amba_id *id) 2127ca632f55SGrant Likely { 2128ca632f55SGrant Likely struct device *dev = &adev->dev; 2129ca632f55SGrant Likely struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2130ca632f55SGrant Likely struct spi_master *master; 2131ca632f55SGrant Likely struct pl022 *pl022 = NULL; /*Data for this driver */ 2132ca632f55SGrant Likely int status = 0; 2133ca632f55SGrant Likely 2134ca632f55SGrant Likely dev_info(&adev->dev, 2135ca632f55SGrant Likely "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2136ca632f55SGrant Likely if (platform_info == NULL) { 2137ca632f55SGrant Likely dev_err(&adev->dev, "probe - no platform data supplied\n"); 2138ca632f55SGrant Likely status = -ENODEV; 2139ca632f55SGrant Likely goto err_no_pdata; 2140ca632f55SGrant Likely } 2141ca632f55SGrant Likely 2142ca632f55SGrant Likely /* Allocate master with space for data */ 2143ca632f55SGrant Likely master = spi_alloc_master(dev, sizeof(struct pl022)); 2144ca632f55SGrant Likely if (master == NULL) { 2145ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2146ca632f55SGrant Likely status = -ENOMEM; 2147ca632f55SGrant Likely goto err_no_master; 2148ca632f55SGrant Likely } 2149ca632f55SGrant Likely 2150ca632f55SGrant Likely pl022 = spi_master_get_devdata(master); 2151ca632f55SGrant Likely pl022->master = master; 2152ca632f55SGrant Likely pl022->master_info = platform_info; 2153ca632f55SGrant Likely pl022->adev = adev; 2154ca632f55SGrant Likely pl022->vendor = id->data; 2155ca632f55SGrant Likely 2156ca632f55SGrant Likely /* 2157ca632f55SGrant Likely * Bus Number Which has been Assigned to this SSP controller 2158ca632f55SGrant Likely * on this board 2159ca632f55SGrant Likely */ 2160ca632f55SGrant Likely master->bus_num = platform_info->bus_id; 2161ca632f55SGrant Likely master->num_chipselect = platform_info->num_chipselect; 2162ca632f55SGrant Likely master->cleanup = pl022_cleanup; 2163ca632f55SGrant Likely master->setup = pl022_setup; 2164ca632f55SGrant Likely master->transfer = pl022_transfer; 2165ca632f55SGrant Likely 2166ca632f55SGrant Likely /* 2167ca632f55SGrant Likely * Supports mode 0-3, loopback, and active low CS. Transfers are 2168ca632f55SGrant Likely * always MS bit first on the original pl022. 2169ca632f55SGrant Likely */ 2170ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2171ca632f55SGrant Likely if (pl022->vendor->extended_cr) 2172ca632f55SGrant Likely master->mode_bits |= SPI_LSB_FIRST; 2173ca632f55SGrant Likely 2174ca632f55SGrant Likely dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2175ca632f55SGrant Likely 2176ca632f55SGrant Likely status = amba_request_regions(adev, NULL); 2177ca632f55SGrant Likely if (status) 2178ca632f55SGrant Likely goto err_no_ioregion; 2179ca632f55SGrant Likely 2180ca632f55SGrant Likely pl022->phybase = adev->res.start; 2181ca632f55SGrant Likely pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2182ca632f55SGrant Likely if (pl022->virtbase == NULL) { 2183ca632f55SGrant Likely status = -ENOMEM; 2184ca632f55SGrant Likely goto err_no_ioremap; 2185ca632f55SGrant Likely } 2186ca632f55SGrant Likely printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2187ca632f55SGrant Likely adev->res.start, pl022->virtbase); 2188bcda6ff8SRabin Vincent pm_runtime_enable(dev); 2189bcda6ff8SRabin Vincent pm_runtime_resume(dev); 2190ca632f55SGrant Likely 2191ca632f55SGrant Likely pl022->clk = clk_get(&adev->dev, NULL); 2192ca632f55SGrant Likely if (IS_ERR(pl022->clk)) { 2193ca632f55SGrant Likely status = PTR_ERR(pl022->clk); 2194ca632f55SGrant Likely dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2195ca632f55SGrant Likely goto err_no_clk; 2196ca632f55SGrant Likely } 2197ca632f55SGrant Likely 2198ca632f55SGrant Likely /* Disable SSP */ 2199ca632f55SGrant Likely writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2200ca632f55SGrant Likely SSP_CR1(pl022->virtbase)); 2201ca632f55SGrant Likely load_ssp_default_config(pl022); 2202ca632f55SGrant Likely 2203ca632f55SGrant Likely status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2204ca632f55SGrant Likely pl022); 2205ca632f55SGrant Likely if (status < 0) { 2206ca632f55SGrant Likely dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2207ca632f55SGrant Likely goto err_no_irq; 2208ca632f55SGrant Likely } 2209ca632f55SGrant Likely 2210ca632f55SGrant Likely /* Get DMA channels */ 2211ca632f55SGrant Likely if (platform_info->enable_dma) { 2212ca632f55SGrant Likely status = pl022_dma_probe(pl022); 2213ca632f55SGrant Likely if (status != 0) 2214ca632f55SGrant Likely platform_info->enable_dma = 0; 2215ca632f55SGrant Likely } 2216ca632f55SGrant Likely 2217ca632f55SGrant Likely /* Initialize and start queue */ 2218ca632f55SGrant Likely status = init_queue(pl022); 2219ca632f55SGrant Likely if (status != 0) { 2220ca632f55SGrant Likely dev_err(&adev->dev, "probe - problem initializing queue\n"); 2221ca632f55SGrant Likely goto err_init_queue; 2222ca632f55SGrant Likely } 2223ca632f55SGrant Likely status = start_queue(pl022); 2224ca632f55SGrant Likely if (status != 0) { 2225ca632f55SGrant Likely dev_err(&adev->dev, "probe - problem starting queue\n"); 2226ca632f55SGrant Likely goto err_start_queue; 2227ca632f55SGrant Likely } 2228ca632f55SGrant Likely /* Register with the SPI framework */ 2229ca632f55SGrant Likely amba_set_drvdata(adev, pl022); 2230ca632f55SGrant Likely status = spi_register_master(master); 2231ca632f55SGrant Likely if (status != 0) { 2232ca632f55SGrant Likely dev_err(&adev->dev, 2233ca632f55SGrant Likely "probe - problem registering spi master\n"); 2234ca632f55SGrant Likely goto err_spi_register; 2235ca632f55SGrant Likely } 2236ca632f55SGrant Likely dev_dbg(dev, "probe succeeded\n"); 2237ca632f55SGrant Likely /* 2238ca632f55SGrant Likely * Disable the silicon block pclk and any voltage domain and just 2239ca632f55SGrant Likely * power it up and clock it when it's needed 2240ca632f55SGrant Likely */ 2241ca632f55SGrant Likely amba_pclk_disable(adev); 2242ca632f55SGrant Likely amba_vcore_disable(adev); 2243ca632f55SGrant Likely return 0; 2244ca632f55SGrant Likely 2245ca632f55SGrant Likely err_spi_register: 2246ca632f55SGrant Likely err_start_queue: 2247ca632f55SGrant Likely err_init_queue: 2248ca632f55SGrant Likely destroy_queue(pl022); 2249ca632f55SGrant Likely pl022_dma_remove(pl022); 2250ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2251bcda6ff8SRabin Vincent pm_runtime_disable(&adev->dev); 2252ca632f55SGrant Likely err_no_irq: 2253ca632f55SGrant Likely clk_put(pl022->clk); 2254ca632f55SGrant Likely err_no_clk: 2255ca632f55SGrant Likely iounmap(pl022->virtbase); 2256ca632f55SGrant Likely err_no_ioremap: 2257ca632f55SGrant Likely amba_release_regions(adev); 2258ca632f55SGrant Likely err_no_ioregion: 2259ca632f55SGrant Likely spi_master_put(master); 2260ca632f55SGrant Likely err_no_master: 2261ca632f55SGrant Likely err_no_pdata: 2262ca632f55SGrant Likely return status; 2263ca632f55SGrant Likely } 2264ca632f55SGrant Likely 2265ca632f55SGrant Likely static int __devexit 2266ca632f55SGrant Likely pl022_remove(struct amba_device *adev) 2267ca632f55SGrant Likely { 2268ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 2269ca632f55SGrant Likely int status = 0; 2270ca632f55SGrant Likely if (!pl022) 2271ca632f55SGrant Likely return 0; 2272ca632f55SGrant Likely 2273ca632f55SGrant Likely /* Remove the queue */ 2274ca632f55SGrant Likely status = destroy_queue(pl022); 2275ca632f55SGrant Likely if (status != 0) { 2276ca632f55SGrant Likely dev_err(&adev->dev, 2277ca632f55SGrant Likely "queue remove failed (%d)\n", status); 2278ca632f55SGrant Likely return status; 2279ca632f55SGrant Likely } 2280ca632f55SGrant Likely load_ssp_default_config(pl022); 2281ca632f55SGrant Likely pl022_dma_remove(pl022); 2282ca632f55SGrant Likely free_irq(adev->irq[0], pl022); 2283ca632f55SGrant Likely clk_disable(pl022->clk); 2284ca632f55SGrant Likely clk_put(pl022->clk); 2285ca632f55SGrant Likely iounmap(pl022->virtbase); 2286ca632f55SGrant Likely amba_release_regions(adev); 2287ca632f55SGrant Likely tasklet_disable(&pl022->pump_transfers); 2288ca632f55SGrant Likely spi_unregister_master(pl022->master); 2289ca632f55SGrant Likely spi_master_put(pl022->master); 2290ca632f55SGrant Likely amba_set_drvdata(adev, NULL); 2291ca632f55SGrant Likely dev_dbg(&adev->dev, "remove succeeded\n"); 2292ca632f55SGrant Likely return 0; 2293ca632f55SGrant Likely } 2294ca632f55SGrant Likely 2295ca632f55SGrant Likely #ifdef CONFIG_PM 2296ca632f55SGrant Likely static int pl022_suspend(struct amba_device *adev, pm_message_t state) 2297ca632f55SGrant Likely { 2298ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 2299ca632f55SGrant Likely int status = 0; 2300ca632f55SGrant Likely 2301ca632f55SGrant Likely status = stop_queue(pl022); 2302ca632f55SGrant Likely if (status) { 2303ca632f55SGrant Likely dev_warn(&adev->dev, "suspend cannot stop queue\n"); 2304ca632f55SGrant Likely return status; 2305ca632f55SGrant Likely } 2306ca632f55SGrant Likely 2307ca632f55SGrant Likely amba_vcore_enable(adev); 2308ca632f55SGrant Likely amba_pclk_enable(adev); 2309ca632f55SGrant Likely load_ssp_default_config(pl022); 2310ca632f55SGrant Likely amba_pclk_disable(adev); 2311ca632f55SGrant Likely amba_vcore_disable(adev); 2312ca632f55SGrant Likely dev_dbg(&adev->dev, "suspended\n"); 2313ca632f55SGrant Likely return 0; 2314ca632f55SGrant Likely } 2315ca632f55SGrant Likely 2316ca632f55SGrant Likely static int pl022_resume(struct amba_device *adev) 2317ca632f55SGrant Likely { 2318ca632f55SGrant Likely struct pl022 *pl022 = amba_get_drvdata(adev); 2319ca632f55SGrant Likely int status = 0; 2320ca632f55SGrant Likely 2321ca632f55SGrant Likely /* Start the queue running */ 2322ca632f55SGrant Likely status = start_queue(pl022); 2323ca632f55SGrant Likely if (status) 2324ca632f55SGrant Likely dev_err(&adev->dev, "problem starting queue (%d)\n", status); 2325ca632f55SGrant Likely else 2326ca632f55SGrant Likely dev_dbg(&adev->dev, "resumed\n"); 2327ca632f55SGrant Likely 2328ca632f55SGrant Likely return status; 2329ca632f55SGrant Likely } 2330ca632f55SGrant Likely #else 2331ca632f55SGrant Likely #define pl022_suspend NULL 2332ca632f55SGrant Likely #define pl022_resume NULL 2333ca632f55SGrant Likely #endif /* CONFIG_PM */ 2334ca632f55SGrant Likely 2335ca632f55SGrant Likely static struct vendor_data vendor_arm = { 2336ca632f55SGrant Likely .fifodepth = 8, 2337ca632f55SGrant Likely .max_bpw = 16, 2338ca632f55SGrant Likely .unidir = false, 2339ca632f55SGrant Likely .extended_cr = false, 2340ca632f55SGrant Likely .pl023 = false, 2341ca632f55SGrant Likely .loopback = true, 2342ca632f55SGrant Likely }; 2343ca632f55SGrant Likely 2344ca632f55SGrant Likely 2345ca632f55SGrant Likely static struct vendor_data vendor_st = { 2346ca632f55SGrant Likely .fifodepth = 32, 2347ca632f55SGrant Likely .max_bpw = 32, 2348ca632f55SGrant Likely .unidir = false, 2349ca632f55SGrant Likely .extended_cr = true, 2350ca632f55SGrant Likely .pl023 = false, 2351ca632f55SGrant Likely .loopback = true, 2352ca632f55SGrant Likely }; 2353ca632f55SGrant Likely 2354ca632f55SGrant Likely static struct vendor_data vendor_st_pl023 = { 2355ca632f55SGrant Likely .fifodepth = 32, 2356ca632f55SGrant Likely .max_bpw = 32, 2357ca632f55SGrant Likely .unidir = false, 2358ca632f55SGrant Likely .extended_cr = true, 2359ca632f55SGrant Likely .pl023 = true, 2360ca632f55SGrant Likely .loopback = false, 2361ca632f55SGrant Likely }; 2362ca632f55SGrant Likely 2363ca632f55SGrant Likely static struct vendor_data vendor_db5500_pl023 = { 2364ca632f55SGrant Likely .fifodepth = 32, 2365ca632f55SGrant Likely .max_bpw = 32, 2366ca632f55SGrant Likely .unidir = false, 2367ca632f55SGrant Likely .extended_cr = true, 2368ca632f55SGrant Likely .pl023 = true, 2369ca632f55SGrant Likely .loopback = true, 2370ca632f55SGrant Likely }; 2371ca632f55SGrant Likely 2372ca632f55SGrant Likely static struct amba_id pl022_ids[] = { 2373ca632f55SGrant Likely { 2374ca632f55SGrant Likely /* 2375ca632f55SGrant Likely * ARM PL022 variant, this has a 16bit wide 2376ca632f55SGrant Likely * and 8 locations deep TX/RX FIFO 2377ca632f55SGrant Likely */ 2378ca632f55SGrant Likely .id = 0x00041022, 2379ca632f55SGrant Likely .mask = 0x000fffff, 2380ca632f55SGrant Likely .data = &vendor_arm, 2381ca632f55SGrant Likely }, 2382ca632f55SGrant Likely { 2383ca632f55SGrant Likely /* 2384ca632f55SGrant Likely * ST Micro derivative, this has 32bit wide 2385ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO 2386ca632f55SGrant Likely */ 2387ca632f55SGrant Likely .id = 0x01080022, 2388ca632f55SGrant Likely .mask = 0xffffffff, 2389ca632f55SGrant Likely .data = &vendor_st, 2390ca632f55SGrant Likely }, 2391ca632f55SGrant Likely { 2392ca632f55SGrant Likely /* 2393ca632f55SGrant Likely * ST-Ericsson derivative "PL023" (this is not 2394ca632f55SGrant Likely * an official ARM number), this is a PL022 SSP block 2395ca632f55SGrant Likely * stripped to SPI mode only, it has 32bit wide 2396ca632f55SGrant Likely * and 32 locations deep TX/RX FIFO but no extended 2397ca632f55SGrant Likely * CR0/CR1 register 2398ca632f55SGrant Likely */ 2399ca632f55SGrant Likely .id = 0x00080023, 2400ca632f55SGrant Likely .mask = 0xffffffff, 2401ca632f55SGrant Likely .data = &vendor_st_pl023, 2402ca632f55SGrant Likely }, 2403ca632f55SGrant Likely { 2404ca632f55SGrant Likely .id = 0x10080023, 2405ca632f55SGrant Likely .mask = 0xffffffff, 2406ca632f55SGrant Likely .data = &vendor_db5500_pl023, 2407ca632f55SGrant Likely }, 2408ca632f55SGrant Likely { 0, 0 }, 2409ca632f55SGrant Likely }; 2410ca632f55SGrant Likely 2411ca632f55SGrant Likely static struct amba_driver pl022_driver = { 2412ca632f55SGrant Likely .drv = { 2413ca632f55SGrant Likely .name = "ssp-pl022", 2414ca632f55SGrant Likely }, 2415ca632f55SGrant Likely .id_table = pl022_ids, 2416ca632f55SGrant Likely .probe = pl022_probe, 2417ca632f55SGrant Likely .remove = __devexit_p(pl022_remove), 2418ca632f55SGrant Likely .suspend = pl022_suspend, 2419ca632f55SGrant Likely .resume = pl022_resume, 2420ca632f55SGrant Likely }; 2421ca632f55SGrant Likely 2422ca632f55SGrant Likely 2423ca632f55SGrant Likely static int __init pl022_init(void) 2424ca632f55SGrant Likely { 2425ca632f55SGrant Likely return amba_driver_register(&pl022_driver); 2426ca632f55SGrant Likely } 2427ca632f55SGrant Likely 2428ca632f55SGrant Likely subsys_initcall(pl022_init); 2429ca632f55SGrant Likely 2430ca632f55SGrant Likely static void __exit pl022_exit(void) 2431ca632f55SGrant Likely { 2432ca632f55SGrant Likely amba_driver_unregister(&pl022_driver); 2433ca632f55SGrant Likely } 2434ca632f55SGrant Likely 2435ca632f55SGrant Likely module_exit(pl022_exit); 2436ca632f55SGrant Likely 2437ca632f55SGrant Likely MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2438ca632f55SGrant Likely MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2439ca632f55SGrant Likely MODULE_LICENSE("GPL"); 2440