1ca632f55SGrant Likely /*
2ca632f55SGrant Likely * MicroWire interface driver for OMAP
3ca632f55SGrant Likely *
4ca632f55SGrant Likely * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
5ca632f55SGrant Likely *
6ca632f55SGrant Likely * Ported to 2.6 OMAP uwire interface.
7ca632f55SGrant Likely * Copyright (C) 2004 Texas Instruments.
8ca632f55SGrant Likely *
9ca632f55SGrant Likely * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
10ca632f55SGrant Likely *
11ca632f55SGrant Likely * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12ca632f55SGrant Likely * Copyright (C) 2006 Nokia
13ca632f55SGrant Likely *
14ca632f55SGrant Likely * Many updates by Imre Deak <imre.deak@nokia.com>
15ca632f55SGrant Likely *
16ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify it
17ca632f55SGrant Likely * under the terms of the GNU General Public License as published by the
18ca632f55SGrant Likely * Free Software Foundation; either version 2 of the License, or (at your
19ca632f55SGrant Likely * option) any later version.
20ca632f55SGrant Likely *
21ca632f55SGrant Likely * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22ca632f55SGrant Likely * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23ca632f55SGrant Likely * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24ca632f55SGrant Likely * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25ca632f55SGrant Likely * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26ca632f55SGrant Likely * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27ca632f55SGrant Likely * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28ca632f55SGrant Likely * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29ca632f55SGrant Likely * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30ca632f55SGrant Likely * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31ca632f55SGrant Likely */
32ca632f55SGrant Likely #include <linux/kernel.h>
33ca632f55SGrant Likely #include <linux/init.h>
34ca632f55SGrant Likely #include <linux/delay.h>
35ca632f55SGrant Likely #include <linux/platform_device.h>
36ca632f55SGrant Likely #include <linux/interrupt.h>
37ca632f55SGrant Likely #include <linux/err.h>
38ca632f55SGrant Likely #include <linux/clk.h>
39ca632f55SGrant Likely #include <linux/slab.h>
401820a8fcSMark Brown #include <linux/device.h>
41ca632f55SGrant Likely
42ca632f55SGrant Likely #include <linux/spi/spi.h>
43ca632f55SGrant Likely #include <linux/spi/spi_bitbang.h>
44d7614de4SPaul Gortmaker #include <linux/module.h>
45ec17a7f2SSachin Kamat #include <linux/io.h>
46ca632f55SGrant Likely
47ca632f55SGrant Likely #include <asm/mach-types.h>
4858d37dc1SArnd Bergmann #include <linux/soc/ti/omap1-io.h>
4958d37dc1SArnd Bergmann #include <linux/soc/ti/omap1-soc.h>
5058d37dc1SArnd Bergmann #include <linux/soc/ti/omap1-mux.h>
51ca632f55SGrant Likely
52ca632f55SGrant Likely /* FIXME address is now a platform device resource,
53ca632f55SGrant Likely * and irqs should show there too...
54ca632f55SGrant Likely */
55ca632f55SGrant Likely #define UWIRE_BASE_PHYS 0xFFFB3000
56ca632f55SGrant Likely
57ca632f55SGrant Likely /* uWire Registers: */
58ca632f55SGrant Likely #define UWIRE_IO_SIZE 0x20
59ca632f55SGrant Likely #define UWIRE_TDR 0x00
60ca632f55SGrant Likely #define UWIRE_RDR 0x00
61ca632f55SGrant Likely #define UWIRE_CSR 0x01
62ca632f55SGrant Likely #define UWIRE_SR1 0x02
63ca632f55SGrant Likely #define UWIRE_SR2 0x03
64ca632f55SGrant Likely #define UWIRE_SR3 0x04
65ca632f55SGrant Likely #define UWIRE_SR4 0x05
66ca632f55SGrant Likely #define UWIRE_SR5 0x06
67ca632f55SGrant Likely
68ca632f55SGrant Likely /* CSR bits */
69ca632f55SGrant Likely #define RDRB (1 << 15)
70ca632f55SGrant Likely #define CSRB (1 << 14)
71ca632f55SGrant Likely #define START (1 << 13)
72ca632f55SGrant Likely #define CS_CMD (1 << 12)
73ca632f55SGrant Likely
74ca632f55SGrant Likely /* SR1 or SR2 bits */
75ca632f55SGrant Likely #define UWIRE_READ_FALLING_EDGE 0x0001
76ca632f55SGrant Likely #define UWIRE_READ_RISING_EDGE 0x0000
77ca632f55SGrant Likely #define UWIRE_WRITE_FALLING_EDGE 0x0000
78ca632f55SGrant Likely #define UWIRE_WRITE_RISING_EDGE 0x0002
79ca632f55SGrant Likely #define UWIRE_CS_ACTIVE_LOW 0x0000
80ca632f55SGrant Likely #define UWIRE_CS_ACTIVE_HIGH 0x0004
81ca632f55SGrant Likely #define UWIRE_FREQ_DIV_2 0x0000
82ca632f55SGrant Likely #define UWIRE_FREQ_DIV_4 0x0008
83ca632f55SGrant Likely #define UWIRE_FREQ_DIV_8 0x0010
84ca632f55SGrant Likely #define UWIRE_CHK_READY 0x0020
85ca632f55SGrant Likely #define UWIRE_CLK_INVERTED 0x0040
86ca632f55SGrant Likely
87ca632f55SGrant Likely
88ca632f55SGrant Likely struct uwire_spi {
89ca632f55SGrant Likely struct spi_bitbang bitbang;
90ca632f55SGrant Likely struct clk *ck;
91ca632f55SGrant Likely };
92ca632f55SGrant Likely
93ca632f55SGrant Likely struct uwire_state {
94ca632f55SGrant Likely unsigned div1_idx;
95ca632f55SGrant Likely };
96ca632f55SGrant Likely
97ca632f55SGrant Likely /* REVISIT compile time constant for idx_shift? */
98ca632f55SGrant Likely /*
99ca632f55SGrant Likely * Or, put it in a structure which is used throughout the driver;
100ca632f55SGrant Likely * that avoids having to issue two loads for each bit of static data.
101ca632f55SGrant Likely */
1028825acd7SArnd Bergmann static unsigned int uwire_idx_shift = 2;
103ca632f55SGrant Likely static void __iomem *uwire_base;
104ca632f55SGrant Likely
uwire_write_reg(int idx,u16 val)105ca632f55SGrant Likely static inline void uwire_write_reg(int idx, u16 val)
106ca632f55SGrant Likely {
107ca632f55SGrant Likely __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
108ca632f55SGrant Likely }
109ca632f55SGrant Likely
uwire_read_reg(int idx)110ca632f55SGrant Likely static inline u16 uwire_read_reg(int idx)
111ca632f55SGrant Likely {
112ca632f55SGrant Likely return __raw_readw(uwire_base + (idx << uwire_idx_shift));
113ca632f55SGrant Likely }
114ca632f55SGrant Likely
omap_uwire_configure_mode(u8 cs,unsigned long flags)115ca632f55SGrant Likely static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
116ca632f55SGrant Likely {
117ca632f55SGrant Likely u16 w, val = 0;
118ca632f55SGrant Likely int shift, reg;
119ca632f55SGrant Likely
120ca632f55SGrant Likely if (flags & UWIRE_CLK_INVERTED)
121ca632f55SGrant Likely val ^= 0x03;
122ca632f55SGrant Likely val = flags & 0x3f;
123ca632f55SGrant Likely if (cs & 1)
124ca632f55SGrant Likely shift = 6;
125ca632f55SGrant Likely else
126ca632f55SGrant Likely shift = 0;
127ca632f55SGrant Likely if (cs <= 1)
128ca632f55SGrant Likely reg = UWIRE_SR1;
129ca632f55SGrant Likely else
130ca632f55SGrant Likely reg = UWIRE_SR2;
131ca632f55SGrant Likely
132ca632f55SGrant Likely w = uwire_read_reg(reg);
133ca632f55SGrant Likely w &= ~(0x3f << shift);
134ca632f55SGrant Likely w |= val << shift;
135ca632f55SGrant Likely uwire_write_reg(reg, w);
136ca632f55SGrant Likely }
137ca632f55SGrant Likely
wait_uwire_csr_flag(u16 mask,u16 val,int might_not_catch)138ca632f55SGrant Likely static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
139ca632f55SGrant Likely {
140ca632f55SGrant Likely u16 w;
141ca632f55SGrant Likely int c = 0;
142ca632f55SGrant Likely unsigned long max_jiffies = jiffies + HZ;
143ca632f55SGrant Likely
144ca632f55SGrant Likely for (;;) {
145ca632f55SGrant Likely w = uwire_read_reg(UWIRE_CSR);
146ca632f55SGrant Likely if ((w & mask) == val)
147ca632f55SGrant Likely break;
148ca632f55SGrant Likely if (time_after(jiffies, max_jiffies)) {
149ca632f55SGrant Likely printk(KERN_ERR "%s: timeout. reg=%#06x "
150ca632f55SGrant Likely "mask=%#06x val=%#06x\n",
151ca632f55SGrant Likely __func__, w, mask, val);
152ca632f55SGrant Likely return -1;
153ca632f55SGrant Likely }
154ca632f55SGrant Likely c++;
155ca632f55SGrant Likely if (might_not_catch && c > 64)
156ca632f55SGrant Likely break;
157ca632f55SGrant Likely }
158ca632f55SGrant Likely return 0;
159ca632f55SGrant Likely }
160ca632f55SGrant Likely
uwire_set_clk1_div(int div1_idx)161ca632f55SGrant Likely static void uwire_set_clk1_div(int div1_idx)
162ca632f55SGrant Likely {
163ca632f55SGrant Likely u16 w;
164ca632f55SGrant Likely
165ca632f55SGrant Likely w = uwire_read_reg(UWIRE_SR3);
166ca632f55SGrant Likely w &= ~(0x03 << 1);
167ca632f55SGrant Likely w |= div1_idx << 1;
168ca632f55SGrant Likely uwire_write_reg(UWIRE_SR3, w);
169ca632f55SGrant Likely }
170ca632f55SGrant Likely
uwire_chipselect(struct spi_device * spi,int value)171ca632f55SGrant Likely static void uwire_chipselect(struct spi_device *spi, int value)
172ca632f55SGrant Likely {
173ca632f55SGrant Likely struct uwire_state *ust = spi->controller_state;
174ca632f55SGrant Likely u16 w;
175ca632f55SGrant Likely int old_cs;
176ca632f55SGrant Likely
177ca632f55SGrant Likely
178ca632f55SGrant Likely BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
179ca632f55SGrant Likely
180ca632f55SGrant Likely w = uwire_read_reg(UWIRE_CSR);
181ca632f55SGrant Likely old_cs = (w >> 10) & 0x03;
1829e264f3fSAmit Kumar Mahapatra via Alsa-devel if (value == BITBANG_CS_INACTIVE || old_cs != spi_get_chipselect(spi, 0)) {
183ca632f55SGrant Likely /* Deselect this CS, or the previous CS */
184ca632f55SGrant Likely w &= ~CS_CMD;
185ca632f55SGrant Likely uwire_write_reg(UWIRE_CSR, w);
186ca632f55SGrant Likely }
187ca632f55SGrant Likely /* activate specfied chipselect */
188ca632f55SGrant Likely if (value == BITBANG_CS_ACTIVE) {
189ca632f55SGrant Likely uwire_set_clk1_div(ust->div1_idx);
190ca632f55SGrant Likely /* invert clock? */
191ca632f55SGrant Likely if (spi->mode & SPI_CPOL)
192ca632f55SGrant Likely uwire_write_reg(UWIRE_SR4, 1);
193ca632f55SGrant Likely else
194ca632f55SGrant Likely uwire_write_reg(UWIRE_SR4, 0);
195ca632f55SGrant Likely
1969e264f3fSAmit Kumar Mahapatra via Alsa-devel w = spi_get_chipselect(spi, 0) << 10;
197ca632f55SGrant Likely w |= CS_CMD;
198ca632f55SGrant Likely uwire_write_reg(UWIRE_CSR, w);
199ca632f55SGrant Likely }
200ca632f55SGrant Likely }
201ca632f55SGrant Likely
uwire_txrx(struct spi_device * spi,struct spi_transfer * t)202ca632f55SGrant Likely static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
203ca632f55SGrant Likely {
204ca632f55SGrant Likely unsigned len = t->len;
205160f8d06SJarkko Nikula unsigned bits = t->bits_per_word;
206ca632f55SGrant Likely unsigned bytes;
207ca632f55SGrant Likely u16 val, w;
208ca632f55SGrant Likely int status = 0;
209ca632f55SGrant Likely
210ca632f55SGrant Likely if (!t->tx_buf && !t->rx_buf)
211ca632f55SGrant Likely return 0;
212ca632f55SGrant Likely
2139e264f3fSAmit Kumar Mahapatra via Alsa-devel w = spi_get_chipselect(spi, 0) << 10;
214ca632f55SGrant Likely w |= CS_CMD;
215ca632f55SGrant Likely
216ca632f55SGrant Likely if (t->tx_buf) {
217ca632f55SGrant Likely const u8 *buf = t->tx_buf;
218ca632f55SGrant Likely
219ca632f55SGrant Likely /* NOTE: DMA could be used for TX transfers */
220ca632f55SGrant Likely
221ca632f55SGrant Likely /* write one or two bytes at a time */
222ca632f55SGrant Likely while (len >= 1) {
223ca632f55SGrant Likely /* tx bit 15 is first sent; we byteswap multibyte words
224ca632f55SGrant Likely * (msb-first) on the way out from memory.
225ca632f55SGrant Likely */
226ca632f55SGrant Likely val = *buf++;
227ca632f55SGrant Likely if (bits > 8) {
228ca632f55SGrant Likely bytes = 2;
229ca632f55SGrant Likely val |= *buf++ << 8;
230ca632f55SGrant Likely } else
231ca632f55SGrant Likely bytes = 1;
232ca632f55SGrant Likely val <<= 16 - bits;
233ca632f55SGrant Likely
234ca632f55SGrant Likely #ifdef VERBOSE
235ca632f55SGrant Likely pr_debug("%s: write-%d =%04x\n",
236ca632f55SGrant Likely dev_name(&spi->dev), bits, val);
237ca632f55SGrant Likely #endif
238ca632f55SGrant Likely if (wait_uwire_csr_flag(CSRB, 0, 0))
239ca632f55SGrant Likely goto eio;
240ca632f55SGrant Likely
241ca632f55SGrant Likely uwire_write_reg(UWIRE_TDR, val);
242ca632f55SGrant Likely
243ca632f55SGrant Likely /* start write */
244ca632f55SGrant Likely val = START | w | (bits << 5);
245ca632f55SGrant Likely
246ca632f55SGrant Likely uwire_write_reg(UWIRE_CSR, val);
247ca632f55SGrant Likely len -= bytes;
248ca632f55SGrant Likely
249ca632f55SGrant Likely /* Wait till write actually starts.
250ca632f55SGrant Likely * This is needed with MPU clock 60+ MHz.
251ca632f55SGrant Likely * REVISIT: we may not have time to catch it...
252ca632f55SGrant Likely */
253ca632f55SGrant Likely if (wait_uwire_csr_flag(CSRB, CSRB, 1))
254ca632f55SGrant Likely goto eio;
255ca632f55SGrant Likely
256ca632f55SGrant Likely status += bytes;
257ca632f55SGrant Likely }
258ca632f55SGrant Likely
259ca632f55SGrant Likely /* REVISIT: save this for later to get more i/o overlap */
260ca632f55SGrant Likely if (wait_uwire_csr_flag(CSRB, 0, 0))
261ca632f55SGrant Likely goto eio;
262ca632f55SGrant Likely
263ca632f55SGrant Likely } else if (t->rx_buf) {
264ca632f55SGrant Likely u8 *buf = t->rx_buf;
265ca632f55SGrant Likely
266ca632f55SGrant Likely /* read one or two bytes at a time */
267ca632f55SGrant Likely while (len) {
268ca632f55SGrant Likely if (bits > 8) {
269ca632f55SGrant Likely bytes = 2;
270ca632f55SGrant Likely } else
271ca632f55SGrant Likely bytes = 1;
272ca632f55SGrant Likely
273ca632f55SGrant Likely /* start read */
274ca632f55SGrant Likely val = START | w | (bits << 0);
275ca632f55SGrant Likely uwire_write_reg(UWIRE_CSR, val);
276ca632f55SGrant Likely len -= bytes;
277ca632f55SGrant Likely
278ca632f55SGrant Likely /* Wait till read actually starts */
279ca632f55SGrant Likely (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
280ca632f55SGrant Likely
281ca632f55SGrant Likely if (wait_uwire_csr_flag(RDRB | CSRB,
282ca632f55SGrant Likely RDRB, 0))
283ca632f55SGrant Likely goto eio;
284ca632f55SGrant Likely
285ca632f55SGrant Likely /* rx bit 0 is last received; multibyte words will
286ca632f55SGrant Likely * be properly byteswapped on the way to memory.
287ca632f55SGrant Likely */
288ca632f55SGrant Likely val = uwire_read_reg(UWIRE_RDR);
289ca632f55SGrant Likely val &= (1 << bits) - 1;
290ca632f55SGrant Likely *buf++ = (u8) val;
291ca632f55SGrant Likely if (bytes == 2)
292ca632f55SGrant Likely *buf++ = val >> 8;
293ca632f55SGrant Likely status += bytes;
294ca632f55SGrant Likely #ifdef VERBOSE
295ca632f55SGrant Likely pr_debug("%s: read-%d =%04x\n",
296ca632f55SGrant Likely dev_name(&spi->dev), bits, val);
297ca632f55SGrant Likely #endif
298ca632f55SGrant Likely
299ca632f55SGrant Likely }
300ca632f55SGrant Likely }
301ca632f55SGrant Likely return status;
302ca632f55SGrant Likely eio:
303ca632f55SGrant Likely return -EIO;
304ca632f55SGrant Likely }
305ca632f55SGrant Likely
uwire_setup_transfer(struct spi_device * spi,struct spi_transfer * t)306ca632f55SGrant Likely static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
307ca632f55SGrant Likely {
308ca632f55SGrant Likely struct uwire_state *ust = spi->controller_state;
309ca632f55SGrant Likely struct uwire_spi *uwire;
310ca632f55SGrant Likely unsigned flags = 0;
311ca632f55SGrant Likely unsigned hz;
312ca632f55SGrant Likely unsigned long rate;
313ca632f55SGrant Likely int div1_idx;
314ca632f55SGrant Likely int div1;
315ca632f55SGrant Likely int div2;
316ca632f55SGrant Likely int status;
317ca632f55SGrant Likely
318ca632f55SGrant Likely uwire = spi_master_get_devdata(spi->master);
319ca632f55SGrant Likely
320ca632f55SGrant Likely /* mode 0..3, clock inverted separately;
321ca632f55SGrant Likely * standard nCS signaling;
322ca632f55SGrant Likely * don't treat DI=high as "not ready"
323ca632f55SGrant Likely */
324ca632f55SGrant Likely if (spi->mode & SPI_CS_HIGH)
325ca632f55SGrant Likely flags |= UWIRE_CS_ACTIVE_HIGH;
326ca632f55SGrant Likely
327ca632f55SGrant Likely if (spi->mode & SPI_CPOL)
328ca632f55SGrant Likely flags |= UWIRE_CLK_INVERTED;
329ca632f55SGrant Likely
330fdb217a3SAndy Shevchenko switch (spi->mode & SPI_MODE_X_MASK) {
331ca632f55SGrant Likely case SPI_MODE_0:
332ca632f55SGrant Likely case SPI_MODE_3:
333ca632f55SGrant Likely flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
334ca632f55SGrant Likely break;
335ca632f55SGrant Likely case SPI_MODE_1:
336ca632f55SGrant Likely case SPI_MODE_2:
337ca632f55SGrant Likely flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
338ca632f55SGrant Likely break;
339ca632f55SGrant Likely }
340ca632f55SGrant Likely
341ca632f55SGrant Likely /* assume it's already enabled */
342ca632f55SGrant Likely rate = clk_get_rate(uwire->ck);
343ca632f55SGrant Likely
344160f8d06SJarkko Nikula if (t != NULL)
345ca632f55SGrant Likely hz = t->speed_hz;
346160f8d06SJarkko Nikula else
347160f8d06SJarkko Nikula hz = spi->max_speed_hz;
348ca632f55SGrant Likely
349ca632f55SGrant Likely if (!hz) {
350ca632f55SGrant Likely pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
351ca632f55SGrant Likely status = -EINVAL;
352ca632f55SGrant Likely goto done;
353ca632f55SGrant Likely }
354ca632f55SGrant Likely
355ca632f55SGrant Likely /* F_INT = mpu_xor_clk / DIV1 */
356ca632f55SGrant Likely for (div1_idx = 0; div1_idx < 4; div1_idx++) {
357ca632f55SGrant Likely switch (div1_idx) {
358ca632f55SGrant Likely case 0:
359ca632f55SGrant Likely div1 = 2;
360ca632f55SGrant Likely break;
361ca632f55SGrant Likely case 1:
362ca632f55SGrant Likely div1 = 4;
363ca632f55SGrant Likely break;
364ca632f55SGrant Likely case 2:
365ca632f55SGrant Likely div1 = 7;
366ca632f55SGrant Likely break;
367ca632f55SGrant Likely default:
368ca632f55SGrant Likely case 3:
369ca632f55SGrant Likely div1 = 10;
370ca632f55SGrant Likely break;
371ca632f55SGrant Likely }
372ca632f55SGrant Likely div2 = (rate / div1 + hz - 1) / hz;
373ca632f55SGrant Likely if (div2 <= 8)
374ca632f55SGrant Likely break;
375ca632f55SGrant Likely }
376ca632f55SGrant Likely if (div1_idx == 4) {
377ca632f55SGrant Likely pr_debug("%s: lowest clock %ld, need %d\n",
378ca632f55SGrant Likely dev_name(&spi->dev), rate / 10 / 8, hz);
379ca632f55SGrant Likely status = -EDOM;
380ca632f55SGrant Likely goto done;
381ca632f55SGrant Likely }
382ca632f55SGrant Likely
383ca632f55SGrant Likely /* we have to cache this and reset in uwire_chipselect as this is a
384ca632f55SGrant Likely * global parameter and another uwire device can change it under
385ca632f55SGrant Likely * us */
386ca632f55SGrant Likely ust->div1_idx = div1_idx;
387ca632f55SGrant Likely uwire_set_clk1_div(div1_idx);
388ca632f55SGrant Likely
389ca632f55SGrant Likely rate /= div1;
390ca632f55SGrant Likely
391ca632f55SGrant Likely switch (div2) {
392ca632f55SGrant Likely case 0:
393ca632f55SGrant Likely case 1:
394ca632f55SGrant Likely case 2:
395ca632f55SGrant Likely flags |= UWIRE_FREQ_DIV_2;
396ca632f55SGrant Likely rate /= 2;
397ca632f55SGrant Likely break;
398ca632f55SGrant Likely case 3:
399ca632f55SGrant Likely case 4:
400ca632f55SGrant Likely flags |= UWIRE_FREQ_DIV_4;
401ca632f55SGrant Likely rate /= 4;
402ca632f55SGrant Likely break;
403ca632f55SGrant Likely case 5:
404ca632f55SGrant Likely case 6:
405ca632f55SGrant Likely case 7:
406ca632f55SGrant Likely case 8:
407ca632f55SGrant Likely flags |= UWIRE_FREQ_DIV_8;
408ca632f55SGrant Likely rate /= 8;
409ca632f55SGrant Likely break;
410ca632f55SGrant Likely }
4119e264f3fSAmit Kumar Mahapatra via Alsa-devel omap_uwire_configure_mode(spi_get_chipselect(spi, 0), flags);
412ca632f55SGrant Likely pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
413ca632f55SGrant Likely __func__, flags,
414ca632f55SGrant Likely clk_get_rate(uwire->ck) / 1000,
415ca632f55SGrant Likely rate / 1000);
416ca632f55SGrant Likely status = 0;
417ca632f55SGrant Likely done:
418ca632f55SGrant Likely return status;
419ca632f55SGrant Likely }
420ca632f55SGrant Likely
uwire_setup(struct spi_device * spi)421ca632f55SGrant Likely static int uwire_setup(struct spi_device *spi)
422ca632f55SGrant Likely {
423ca632f55SGrant Likely struct uwire_state *ust = spi->controller_state;
4242ec6f20bSLukas Wunner bool initial_setup = false;
4252ec6f20bSLukas Wunner int status;
426ca632f55SGrant Likely
427ca632f55SGrant Likely if (ust == NULL) {
428ca632f55SGrant Likely ust = kzalloc(sizeof(*ust), GFP_KERNEL);
429ca632f55SGrant Likely if (ust == NULL)
430ca632f55SGrant Likely return -ENOMEM;
431ca632f55SGrant Likely spi->controller_state = ust;
4322ec6f20bSLukas Wunner initial_setup = true;
433ca632f55SGrant Likely }
434ca632f55SGrant Likely
4352ec6f20bSLukas Wunner status = uwire_setup_transfer(spi, NULL);
4362ec6f20bSLukas Wunner if (status && initial_setup)
4372ec6f20bSLukas Wunner kfree(ust);
4382ec6f20bSLukas Wunner
4392ec6f20bSLukas Wunner return status;
440ca632f55SGrant Likely }
441ca632f55SGrant Likely
uwire_cleanup(struct spi_device * spi)442ca632f55SGrant Likely static void uwire_cleanup(struct spi_device *spi)
443ca632f55SGrant Likely {
444ca632f55SGrant Likely kfree(spi->controller_state);
445ca632f55SGrant Likely }
446ca632f55SGrant Likely
uwire_off(struct uwire_spi * uwire)447ca632f55SGrant Likely static void uwire_off(struct uwire_spi *uwire)
448ca632f55SGrant Likely {
449ca632f55SGrant Likely uwire_write_reg(UWIRE_SR3, 0);
450badfae42SQing Zhang clk_disable_unprepare(uwire->ck);
451ca632f55SGrant Likely spi_master_put(uwire->bitbang.master);
452ca632f55SGrant Likely }
453ca632f55SGrant Likely
uwire_probe(struct platform_device * pdev)4542deff8d6SGrant Likely static int uwire_probe(struct platform_device *pdev)
455ca632f55SGrant Likely {
456ca632f55SGrant Likely struct spi_master *master;
457ca632f55SGrant Likely struct uwire_spi *uwire;
458ca632f55SGrant Likely int status;
459ca632f55SGrant Likely
46019bae51bSZhiqi Song master = spi_alloc_master(&pdev->dev, sizeof(*uwire));
461ca632f55SGrant Likely if (!master)
462ca632f55SGrant Likely return -ENODEV;
463ca632f55SGrant Likely
464ca632f55SGrant Likely uwire = spi_master_get_devdata(master);
465ca632f55SGrant Likely
466b3f6a575SHimangi Saraogi uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
467ca632f55SGrant Likely if (!uwire_base) {
468ca632f55SGrant Likely dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
469ca632f55SGrant Likely spi_master_put(master);
470ca632f55SGrant Likely return -ENOMEM;
471ca632f55SGrant Likely }
472ca632f55SGrant Likely
47324b5a82cSJingoo Han platform_set_drvdata(pdev, uwire);
474ca632f55SGrant Likely
475b3f6a575SHimangi Saraogi uwire->ck = devm_clk_get(&pdev->dev, "fck");
476ca632f55SGrant Likely if (IS_ERR(uwire->ck)) {
477ca632f55SGrant Likely status = PTR_ERR(uwire->ck);
478ca632f55SGrant Likely dev_dbg(&pdev->dev, "no functional clock?\n");
479ca632f55SGrant Likely spi_master_put(master);
480ca632f55SGrant Likely return status;
481ca632f55SGrant Likely }
482badfae42SQing Zhang clk_prepare_enable(uwire->ck);
483ca632f55SGrant Likely
484ca632f55SGrant Likely uwire_write_reg(UWIRE_SR3, 1);
485ca632f55SGrant Likely
486ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */
487ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
488790fc55aSAxel Lin master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
489*7a2b552cSAndy Shevchenko master->flags = SPI_CONTROLLER_HALF_DUPLEX;
490ca632f55SGrant Likely
491ca632f55SGrant Likely master->bus_num = 2; /* "official" */
492ca632f55SGrant Likely master->num_chipselect = 4;
493ca632f55SGrant Likely master->setup = uwire_setup;
494ca632f55SGrant Likely master->cleanup = uwire_cleanup;
495ca632f55SGrant Likely
496ca632f55SGrant Likely uwire->bitbang.master = master;
497ca632f55SGrant Likely uwire->bitbang.chipselect = uwire_chipselect;
498ca632f55SGrant Likely uwire->bitbang.setup_transfer = uwire_setup_transfer;
499ca632f55SGrant Likely uwire->bitbang.txrx_bufs = uwire_txrx;
500ca632f55SGrant Likely
501ca632f55SGrant Likely status = spi_bitbang_start(&uwire->bitbang);
502ca632f55SGrant Likely if (status < 0) {
503ca632f55SGrant Likely uwire_off(uwire);
504ca632f55SGrant Likely }
505ca632f55SGrant Likely return status;
506ca632f55SGrant Likely }
507ca632f55SGrant Likely
uwire_remove(struct platform_device * pdev)508c43bdb3aSUwe Kleine-König static void uwire_remove(struct platform_device *pdev)
509ca632f55SGrant Likely {
51024b5a82cSJingoo Han struct uwire_spi *uwire = platform_get_drvdata(pdev);
511ca632f55SGrant Likely
512ca632f55SGrant Likely // FIXME remove all child devices, somewhere ...
513ca632f55SGrant Likely
514d9721ae1SAxel Lin spi_bitbang_stop(&uwire->bitbang);
515ca632f55SGrant Likely uwire_off(uwire);
516ca632f55SGrant Likely }
517ca632f55SGrant Likely
518ca632f55SGrant Likely /* work with hotplug and coldplug */
519ca632f55SGrant Likely MODULE_ALIAS("platform:omap_uwire");
520ca632f55SGrant Likely
521ca632f55SGrant Likely static struct platform_driver uwire_driver = {
522ca632f55SGrant Likely .driver = {
523ca632f55SGrant Likely .name = "omap_uwire",
524ca632f55SGrant Likely },
52593e9c900SWolfram Sang .probe = uwire_probe,
526c43bdb3aSUwe Kleine-König .remove_new = uwire_remove,
527ca632f55SGrant Likely // suspend ... unuse ck
528ca632f55SGrant Likely // resume ... use ck
529ca632f55SGrant Likely };
530ca632f55SGrant Likely
omap_uwire_init(void)531ca632f55SGrant Likely static int __init omap_uwire_init(void)
532ca632f55SGrant Likely {
53393e9c900SWolfram Sang return platform_driver_register(&uwire_driver);
534ca632f55SGrant Likely }
535ca632f55SGrant Likely
omap_uwire_exit(void)536ca632f55SGrant Likely static void __exit omap_uwire_exit(void)
537ca632f55SGrant Likely {
538ca632f55SGrant Likely platform_driver_unregister(&uwire_driver);
539ca632f55SGrant Likely }
540ca632f55SGrant Likely
541ca632f55SGrant Likely subsys_initcall(omap_uwire_init);
542ca632f55SGrant Likely module_exit(omap_uwire_exit);
543ca632f55SGrant Likely
544ca632f55SGrant Likely MODULE_LICENSE("GPL");
545ca632f55SGrant Likely
546