1 /* 2 * Driver for the Diolan DLN-2 USB-SPI adapter 3 * 4 * Copyright (c) 2014 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation, version 2. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/mfd/dln2.h> 15 #include <linux/spi/spi.h> 16 #include <linux/pm_runtime.h> 17 #include <asm/unaligned.h> 18 19 #define DLN2_SPI_MODULE_ID 0x02 20 #define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID) 21 22 /* SPI commands */ 23 #define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00) 24 #define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11) 25 #define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12) 26 #define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13) 27 #define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14) 28 #define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15) 29 #define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16) 30 #define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17) 31 #define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18) 32 #define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19) 33 #define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A) 34 #define DLN2_SPI_READ DLN2_SPI_CMD(0x1B) 35 #define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C) 36 #define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20) 37 #define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21) 38 #define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22) 39 #define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23) 40 #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24) 41 #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25) 42 #define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26) 43 #define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27) 44 #define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28) 45 #define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B) 46 #define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C) 47 #define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D) 48 #define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E) 49 #define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F) 50 #define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30) 51 #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31) 52 #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32) 53 #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33) 54 #define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34) 55 #define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35) 56 #define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36) 57 #define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37) 58 #define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38) 59 #define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39) 60 #define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A) 61 #define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40) 62 #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41) 63 #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42) 64 #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43) 65 #define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44) 66 #define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45) 67 #define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46) 68 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47) 69 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48) 70 #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49) 71 #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A) 72 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B) 73 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C) 74 75 #define DLN2_SPI_MAX_XFER_SIZE 256 76 #define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16) 77 #define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0) 78 #define DLN2_TRANSFERS_WAIT_COMPLETE 1 79 #define DLN2_TRANSFERS_CANCEL 0 80 #define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000 81 82 struct dln2_spi { 83 struct platform_device *pdev; 84 struct spi_master *master; 85 u8 port; 86 87 /* 88 * This buffer will be used mainly for read/write operations. Since 89 * they're quite large, we cannot use the stack. Protection is not 90 * needed because all SPI communication is serialized by the SPI core. 91 */ 92 void *buf; 93 94 u8 bpw; 95 u32 speed; 96 u16 mode; 97 u8 cs; 98 }; 99 100 /* 101 * Enable/Disable SPI module. The disable command will wait for transfers to 102 * complete first. 103 */ 104 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable) 105 { 106 int ret; 107 u16 cmd; 108 struct { 109 u8 port; 110 u8 wait_for_completion; 111 } tx; 112 unsigned len = sizeof(tx); 113 114 tx.port = dln2->port; 115 116 if (enable) { 117 cmd = DLN2_SPI_ENABLE; 118 len -= sizeof(tx.wait_for_completion); 119 } else { 120 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE; 121 cmd = DLN2_SPI_DISABLE; 122 } 123 124 ret = dln2_transfer_tx(dln2->pdev, cmd, &tx, len); 125 if (ret < 0) 126 return ret; 127 128 return 0; 129 } 130 131 /* 132 * Select/unselect multiple CS lines. The selected lines will be automatically 133 * toggled LOW/HIGH by the board firmware during transfers, provided they're 134 * enabled first. 135 * 136 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation 137 * will toggle the lines LOW/HIGH automatically. 138 */ 139 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) 140 { 141 struct { 142 u8 port; 143 u8 cs; 144 } tx; 145 146 tx.port = dln2->port; 147 148 /* 149 * According to Diolan docs, "a slave device can be selected by changing 150 * the corresponding bit value to 0". The rest must be set to 1. Hence 151 * the bitwise NOT in front. 152 */ 153 tx.cs = ~cs_mask; 154 155 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx)); 156 } 157 158 /* 159 * Select one CS line. The other lines will be un-selected. 160 */ 161 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs) 162 { 163 return dln2_spi_cs_set(dln2, BIT(cs)); 164 } 165 166 /* 167 * Enable/disable CS lines for usage. The module has to be disabled first. 168 */ 169 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) 170 { 171 struct { 172 u8 port; 173 u8 cs; 174 } tx; 175 u16 cmd; 176 177 tx.port = dln2->port; 178 tx.cs = cs_mask; 179 cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE; 180 181 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx)); 182 } 183 184 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable) 185 { 186 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0); 187 188 return dln2_spi_cs_enable(dln2, cs_mask, enable); 189 } 190 191 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num) 192 { 193 int ret; 194 struct { 195 u8 port; 196 } tx; 197 struct { 198 __le16 cs_count; 199 } rx; 200 unsigned rx_len = sizeof(rx); 201 202 tx.port = dln2->port; 203 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx), 204 &rx, &rx_len); 205 if (ret < 0) 206 return ret; 207 if (rx_len < sizeof(rx)) 208 return -EPROTO; 209 210 *cs_num = le16_to_cpu(rx.cs_count); 211 212 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num); 213 214 return 0; 215 } 216 217 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq) 218 { 219 int ret; 220 struct { 221 u8 port; 222 } tx; 223 struct { 224 __le32 speed; 225 } rx; 226 unsigned rx_len = sizeof(rx); 227 228 tx.port = dln2->port; 229 230 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len); 231 if (ret < 0) 232 return ret; 233 if (rx_len < sizeof(rx)) 234 return -EPROTO; 235 236 *freq = le32_to_cpu(rx.speed); 237 238 return 0; 239 } 240 241 /* 242 * Get bus min/max frequencies. 243 */ 244 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax) 245 { 246 int ret; 247 248 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin); 249 if (ret < 0) 250 return ret; 251 252 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax); 253 if (ret < 0) 254 return ret; 255 256 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n", 257 *fmin, *fmax); 258 259 return 0; 260 } 261 262 /* 263 * Set the bus speed. The module will automatically round down to the closest 264 * available frequency and returns it. The module has to be disabled first. 265 */ 266 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed) 267 { 268 int ret; 269 struct { 270 u8 port; 271 __le32 speed; 272 } __packed tx; 273 struct { 274 __le32 speed; 275 } rx; 276 int rx_len = sizeof(rx); 277 278 tx.port = dln2->port; 279 tx.speed = cpu_to_le32(speed); 280 281 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx), 282 &rx, &rx_len); 283 if (ret < 0) 284 return ret; 285 if (rx_len < sizeof(rx)) 286 return -EPROTO; 287 288 return 0; 289 } 290 291 /* 292 * Change CPOL & CPHA. The module has to be disabled first. 293 */ 294 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode) 295 { 296 struct { 297 u8 port; 298 u8 mode; 299 } tx; 300 301 tx.port = dln2->port; 302 tx.mode = mode; 303 304 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx)); 305 } 306 307 /* 308 * Change frame size. The module has to be disabled first. 309 */ 310 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw) 311 { 312 struct { 313 u8 port; 314 u8 bpw; 315 } tx; 316 317 tx.port = dln2->port; 318 tx.bpw = bpw; 319 320 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE, 321 &tx, sizeof(tx)); 322 } 323 324 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2, 325 u32 *bpw_mask) 326 { 327 int ret; 328 struct { 329 u8 port; 330 } tx; 331 struct { 332 u8 count; 333 u8 frame_sizes[36]; 334 } *rx = dln2->buf; 335 unsigned rx_len = sizeof(*rx); 336 int i; 337 338 tx.port = dln2->port; 339 340 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES, 341 &tx, sizeof(tx), rx, &rx_len); 342 if (ret < 0) 343 return ret; 344 if (rx_len < sizeof(*rx)) 345 return -EPROTO; 346 if (rx->count > ARRAY_SIZE(rx->frame_sizes)) 347 return -EPROTO; 348 349 *bpw_mask = 0; 350 for (i = 0; i < rx->count; i++) 351 *bpw_mask |= BIT(rx->frame_sizes[i] - 1); 352 353 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask); 354 355 return 0; 356 } 357 358 /* 359 * Copy the data to DLN2 buffer and change the byte order to LE, requested by 360 * DLN2 module. SPI core makes sure that the data length is a multiple of word 361 * size. 362 */ 363 static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw) 364 { 365 #ifdef __LITTLE_ENDIAN 366 memcpy(dln2_buf, src, len); 367 #else 368 if (bpw <= 8) { 369 memcpy(dln2_buf, src, len); 370 } else if (bpw <= 16) { 371 __le16 *d = (__le16 *)dln2_buf; 372 u16 *s = (u16 *)src; 373 374 len = len / 2; 375 while (len--) 376 *d++ = cpu_to_le16p(s++); 377 } else { 378 __le32 *d = (__le32 *)dln2_buf; 379 u32 *s = (u32 *)src; 380 381 len = len / 4; 382 while (len--) 383 *d++ = cpu_to_le32p(s++); 384 } 385 #endif 386 387 return 0; 388 } 389 390 /* 391 * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2 392 * buffer is LE ordered. SPI core makes sure that the data length is a multiple 393 * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make 394 * sure we avoid unaligned accesses for 32 bit case. 395 */ 396 static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw) 397 { 398 #ifdef __LITTLE_ENDIAN 399 memcpy(dest, dln2_buf, len); 400 #else 401 if (bpw <= 8) { 402 memcpy(dest, dln2_buf, len); 403 } else if (bpw <= 16) { 404 u16 *d = (u16 *)dest; 405 __le16 *s = (__le16 *)dln2_buf; 406 407 len = len / 2; 408 while (len--) 409 *d++ = le16_to_cpup(s++); 410 } else { 411 u32 *d = (u32 *)dest; 412 __le32 *s = (__le32 *)dln2_buf; 413 414 len = len / 4; 415 while (len--) 416 *d++ = get_unaligned_le32(s++); 417 } 418 #endif 419 420 return 0; 421 } 422 423 /* 424 * Perform one write operation. 425 */ 426 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data, 427 u16 data_len, u8 attr) 428 { 429 struct { 430 u8 port; 431 __le16 size; 432 u8 attr; 433 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 434 } __packed *tx = dln2->buf; 435 unsigned tx_len; 436 437 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE); 438 439 if (data_len > DLN2_SPI_MAX_XFER_SIZE) 440 return -EINVAL; 441 442 tx->port = dln2->port; 443 tx->size = cpu_to_le16(data_len); 444 tx->attr = attr; 445 446 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw); 447 448 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE; 449 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len); 450 } 451 452 /* 453 * Perform one read operation. 454 */ 455 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data, 456 u16 data_len, u8 attr) 457 { 458 int ret; 459 struct { 460 u8 port; 461 __le16 size; 462 u8 attr; 463 } __packed tx; 464 struct { 465 __le16 size; 466 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 467 } __packed *rx = dln2->buf; 468 unsigned rx_len = sizeof(*rx); 469 470 BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE); 471 472 if (data_len > DLN2_SPI_MAX_XFER_SIZE) 473 return -EINVAL; 474 475 tx.port = dln2->port; 476 tx.size = cpu_to_le16(data_len); 477 tx.attr = attr; 478 479 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx), 480 rx, &rx_len); 481 if (ret < 0) 482 return ret; 483 if (rx_len < sizeof(rx->size) + data_len) 484 return -EPROTO; 485 if (le16_to_cpu(rx->size) != data_len) 486 return -EPROTO; 487 488 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw); 489 490 return 0; 491 } 492 493 /* 494 * Perform one write & read operation. 495 */ 496 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data, 497 u8 *rx_data, u16 data_len, u8 attr) 498 { 499 int ret; 500 struct { 501 u8 port; 502 __le16 size; 503 u8 attr; 504 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 505 } __packed *tx; 506 struct { 507 __le16 size; 508 u8 buf[DLN2_SPI_MAX_XFER_SIZE]; 509 } __packed *rx; 510 unsigned tx_len, rx_len; 511 512 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE || 513 sizeof(*rx) > DLN2_SPI_BUF_SIZE); 514 515 if (data_len > DLN2_SPI_MAX_XFER_SIZE) 516 return -EINVAL; 517 518 /* 519 * Since this is a pseudo full-duplex communication, we're perfectly 520 * safe to use the same buffer for both tx and rx. When DLN2 sends the 521 * response back, with the rx data, we don't need the tx buffer anymore. 522 */ 523 tx = dln2->buf; 524 rx = dln2->buf; 525 526 tx->port = dln2->port; 527 tx->size = cpu_to_le16(data_len); 528 tx->attr = attr; 529 530 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw); 531 532 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE; 533 rx_len = sizeof(*rx); 534 535 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len, 536 rx, &rx_len); 537 if (ret < 0) 538 return ret; 539 if (rx_len < sizeof(rx->size) + data_len) 540 return -EPROTO; 541 if (le16_to_cpu(rx->size) != data_len) 542 return -EPROTO; 543 544 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw); 545 546 return 0; 547 } 548 549 /* 550 * Read/Write wrapper. It will automatically split an operation into multiple 551 * single ones due to device buffer constraints. 552 */ 553 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data, 554 u8 *rx_data, u16 data_len, u8 attr) { 555 int ret; 556 u16 len; 557 u8 temp_attr; 558 u16 remaining = data_len; 559 u16 offset; 560 561 do { 562 if (remaining > DLN2_SPI_MAX_XFER_SIZE) { 563 len = DLN2_SPI_MAX_XFER_SIZE; 564 temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW; 565 } else { 566 len = remaining; 567 temp_attr = attr; 568 } 569 570 offset = data_len - remaining; 571 572 if (tx_data && rx_data) { 573 ret = dln2_spi_read_write_one(dln2, 574 tx_data + offset, 575 rx_data + offset, 576 len, temp_attr); 577 } else if (tx_data) { 578 ret = dln2_spi_write_one(dln2, 579 tx_data + offset, 580 len, temp_attr); 581 } else if (rx_data) { 582 ret = dln2_spi_read_one(dln2, 583 rx_data + offset, 584 len, temp_attr); 585 } else { 586 return -EINVAL; 587 } 588 589 if (ret < 0) 590 return ret; 591 592 remaining -= len; 593 } while (remaining); 594 595 return 0; 596 } 597 598 static int dln2_spi_prepare_message(struct spi_master *master, 599 struct spi_message *message) 600 { 601 int ret; 602 struct dln2_spi *dln2 = spi_master_get_devdata(master); 603 struct spi_device *spi = message->spi; 604 605 if (dln2->cs != spi->chip_select) { 606 ret = dln2_spi_cs_set_one(dln2, spi->chip_select); 607 if (ret < 0) 608 return ret; 609 610 dln2->cs = spi->chip_select; 611 } 612 613 return 0; 614 } 615 616 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed, 617 u8 bpw, u8 mode) 618 { 619 int ret; 620 bool bus_setup_change; 621 622 bus_setup_change = dln2->speed != speed || dln2->mode != mode || 623 dln2->bpw != bpw; 624 625 if (!bus_setup_change) 626 return 0; 627 628 ret = dln2_spi_enable(dln2, false); 629 if (ret < 0) 630 return ret; 631 632 if (dln2->speed != speed) { 633 ret = dln2_spi_set_speed(dln2, speed); 634 if (ret < 0) 635 return ret; 636 637 dln2->speed = speed; 638 } 639 640 if (dln2->mode != mode) { 641 ret = dln2_spi_set_mode(dln2, mode & 0x3); 642 if (ret < 0) 643 return ret; 644 645 dln2->mode = mode; 646 } 647 648 if (dln2->bpw != bpw) { 649 ret = dln2_spi_set_bpw(dln2, bpw); 650 if (ret < 0) 651 return ret; 652 653 dln2->bpw = bpw; 654 } 655 656 ret = dln2_spi_enable(dln2, true); 657 if (ret < 0) 658 return ret; 659 660 return 0; 661 } 662 663 static int dln2_spi_transfer_one(struct spi_master *master, 664 struct spi_device *spi, 665 struct spi_transfer *xfer) 666 { 667 struct dln2_spi *dln2 = spi_master_get_devdata(master); 668 int status; 669 u8 attr = 0; 670 671 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz, 672 xfer->bits_per_word, 673 spi->mode); 674 if (status < 0) { 675 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n"); 676 return status; 677 } 678 679 if (!xfer->cs_change && !spi_transfer_is_last(master, xfer)) 680 attr = DLN2_SPI_ATTR_LEAVE_SS_LOW; 681 682 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf, 683 xfer->len, attr); 684 if (status < 0) 685 dev_err(&dln2->pdev->dev, "write/read failed!\n"); 686 687 return status; 688 } 689 690 static int dln2_spi_probe(struct platform_device *pdev) 691 { 692 struct spi_master *master; 693 struct dln2_spi *dln2; 694 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev); 695 int ret; 696 697 master = spi_alloc_master(&pdev->dev, sizeof(*dln2)); 698 if (!master) 699 return -ENOMEM; 700 701 platform_set_drvdata(pdev, master); 702 703 dln2 = spi_master_get_devdata(master); 704 705 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL); 706 if (!dln2->buf) { 707 ret = -ENOMEM; 708 goto exit_free_master; 709 } 710 711 dln2->master = master; 712 dln2->pdev = pdev; 713 dln2->port = pdata->port; 714 /* cs/mode can never be 0xff, so the first transfer will set them */ 715 dln2->cs = 0xff; 716 dln2->mode = 0xff; 717 718 /* disable SPI module before continuing with the setup */ 719 ret = dln2_spi_enable(dln2, false); 720 if (ret < 0) { 721 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 722 goto exit_free_master; 723 } 724 725 ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect); 726 if (ret < 0) { 727 dev_err(&pdev->dev, "Failed to get number of CS pins\n"); 728 goto exit_free_master; 729 } 730 731 ret = dln2_spi_get_speed_range(dln2, 732 &master->min_speed_hz, 733 &master->max_speed_hz); 734 if (ret < 0) { 735 dev_err(&pdev->dev, "Failed to read bus min/max freqs\n"); 736 goto exit_free_master; 737 } 738 739 ret = dln2_spi_get_supported_frame_sizes(dln2, 740 &master->bits_per_word_mask); 741 if (ret < 0) { 742 dev_err(&pdev->dev, "Failed to read supported frame sizes\n"); 743 goto exit_free_master; 744 } 745 746 ret = dln2_spi_cs_enable_all(dln2, true); 747 if (ret < 0) { 748 dev_err(&pdev->dev, "Failed to enable CS pins\n"); 749 goto exit_free_master; 750 } 751 752 master->bus_num = -1; 753 master->mode_bits = SPI_CPOL | SPI_CPHA; 754 master->prepare_message = dln2_spi_prepare_message; 755 master->transfer_one = dln2_spi_transfer_one; 756 master->auto_runtime_pm = true; 757 758 /* enable SPI module, we're good to go */ 759 ret = dln2_spi_enable(dln2, true); 760 if (ret < 0) { 761 dev_err(&pdev->dev, "Failed to enable SPI module\n"); 762 goto exit_free_master; 763 } 764 765 pm_runtime_set_autosuspend_delay(&pdev->dev, 766 DLN2_RPM_AUTOSUSPEND_TIMEOUT); 767 pm_runtime_use_autosuspend(&pdev->dev); 768 pm_runtime_set_active(&pdev->dev); 769 pm_runtime_enable(&pdev->dev); 770 771 ret = devm_spi_register_master(&pdev->dev, master); 772 if (ret < 0) { 773 dev_err(&pdev->dev, "Failed to register master\n"); 774 goto exit_register; 775 } 776 777 return ret; 778 779 exit_register: 780 pm_runtime_disable(&pdev->dev); 781 pm_runtime_set_suspended(&pdev->dev); 782 783 if (dln2_spi_enable(dln2, false) < 0) 784 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 785 exit_free_master: 786 spi_master_put(master); 787 788 return ret; 789 } 790 791 static int dln2_spi_remove(struct platform_device *pdev) 792 { 793 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 794 struct dln2_spi *dln2 = spi_master_get_devdata(master); 795 796 pm_runtime_disable(&pdev->dev); 797 798 if (dln2_spi_enable(dln2, false) < 0) 799 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 800 801 return 0; 802 } 803 804 #ifdef CONFIG_PM_SLEEP 805 static int dln2_spi_suspend(struct device *dev) 806 { 807 int ret; 808 struct spi_master *master = dev_get_drvdata(dev); 809 struct dln2_spi *dln2 = spi_master_get_devdata(master); 810 811 ret = spi_master_suspend(master); 812 if (ret < 0) 813 return ret; 814 815 if (!pm_runtime_suspended(dev)) { 816 ret = dln2_spi_enable(dln2, false); 817 if (ret < 0) 818 return ret; 819 } 820 821 /* 822 * USB power may be cut off during sleep. Resetting the following 823 * parameters will force the board to be set up before first transfer. 824 */ 825 dln2->cs = 0xff; 826 dln2->speed = 0; 827 dln2->bpw = 0; 828 dln2->mode = 0xff; 829 830 return 0; 831 } 832 833 static int dln2_spi_resume(struct device *dev) 834 { 835 int ret; 836 struct spi_master *master = dev_get_drvdata(dev); 837 struct dln2_spi *dln2 = spi_master_get_devdata(master); 838 839 if (!pm_runtime_suspended(dev)) { 840 ret = dln2_spi_cs_enable_all(dln2, true); 841 if (ret < 0) 842 return ret; 843 844 ret = dln2_spi_enable(dln2, true); 845 if (ret < 0) 846 return ret; 847 } 848 849 return spi_master_resume(master); 850 } 851 #endif /* CONFIG_PM_SLEEP */ 852 853 #ifdef CONFIG_PM_RUNTIME 854 static int dln2_spi_runtime_suspend(struct device *dev) 855 { 856 struct spi_master *master = dev_get_drvdata(dev); 857 struct dln2_spi *dln2 = spi_master_get_devdata(master); 858 859 return dln2_spi_enable(dln2, false); 860 } 861 862 static int dln2_spi_runtime_resume(struct device *dev) 863 { 864 struct spi_master *master = dev_get_drvdata(dev); 865 struct dln2_spi *dln2 = spi_master_get_devdata(master); 866 867 return dln2_spi_enable(dln2, true); 868 } 869 #endif /* CONFIG_PM_RUNTIME */ 870 871 static const struct dev_pm_ops dln2_spi_pm = { 872 SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume) 873 SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend, 874 dln2_spi_runtime_resume, NULL) 875 }; 876 877 static struct platform_driver spi_dln2_driver = { 878 .driver = { 879 .name = "dln2-spi", 880 .pm = &dln2_spi_pm, 881 }, 882 .probe = dln2_spi_probe, 883 .remove = dln2_spi_remove, 884 }; 885 module_platform_driver(spi_dln2_driver); 886 887 MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface"); 888 MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>"); 889 MODULE_LICENSE("GPL v2"); 890 MODULE_ALIAS("platform:dln2-spi"); 891