1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * Copyright (C) 2009 Texas Instruments. 3ca632f55SGrant Likely * Copyright (C) 2010 EF Johnson Technologies 4ca632f55SGrant Likely * 5ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 6ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 7ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 8ca632f55SGrant Likely * (at your option) any later version. 9ca632f55SGrant Likely * 10ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 11ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 12ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ca632f55SGrant Likely * GNU General Public License for more details. 14ca632f55SGrant Likely */ 15ca632f55SGrant Likely 16ca632f55SGrant Likely #include <linux/interrupt.h> 17ca632f55SGrant Likely #include <linux/io.h> 18ca632f55SGrant Likely #include <linux/gpio.h> 19ca632f55SGrant Likely #include <linux/module.h> 20ca632f55SGrant Likely #include <linux/delay.h> 21ca632f55SGrant Likely #include <linux/platform_device.h> 22ca632f55SGrant Likely #include <linux/err.h> 23ca632f55SGrant Likely #include <linux/clk.h> 24048177ceSMatt Porter #include <linux/dmaengine.h> 25ca632f55SGrant Likely #include <linux/dma-mapping.h> 26048177ceSMatt Porter #include <linux/edma.h> 27aae7147dSMurali Karicheri #include <linux/of.h> 28aae7147dSMurali Karicheri #include <linux/of_device.h> 29a88e34eaSMurali Karicheri #include <linux/of_gpio.h> 30ca632f55SGrant Likely #include <linux/spi/spi.h> 31ca632f55SGrant Likely #include <linux/spi/spi_bitbang.h> 32ca632f55SGrant Likely #include <linux/slab.h> 33ca632f55SGrant Likely 34ec2a0833SArnd Bergmann #include <linux/platform_data/spi-davinci.h> 35ca632f55SGrant Likely 36ca632f55SGrant Likely #define SPI_NO_RESOURCE ((resource_size_t)-1) 37ca632f55SGrant Likely 38ca632f55SGrant Likely #define CS_DEFAULT 0xFF 39ca632f55SGrant Likely 40ca632f55SGrant Likely #define SPIFMT_PHASE_MASK BIT(16) 41ca632f55SGrant Likely #define SPIFMT_POLARITY_MASK BIT(17) 42ca632f55SGrant Likely #define SPIFMT_DISTIMER_MASK BIT(18) 43ca632f55SGrant Likely #define SPIFMT_SHIFTDIR_MASK BIT(20) 44ca632f55SGrant Likely #define SPIFMT_WAITENA_MASK BIT(21) 45ca632f55SGrant Likely #define SPIFMT_PARITYENA_MASK BIT(22) 46ca632f55SGrant Likely #define SPIFMT_ODD_PARITY_MASK BIT(23) 47ca632f55SGrant Likely #define SPIFMT_WDELAY_MASK 0x3f000000u 48ca632f55SGrant Likely #define SPIFMT_WDELAY_SHIFT 24 49ca632f55SGrant Likely #define SPIFMT_PRESCALE_SHIFT 8 50ca632f55SGrant Likely 51ca632f55SGrant Likely /* SPIPC0 */ 52ca632f55SGrant Likely #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ 53ca632f55SGrant Likely #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ 54ca632f55SGrant Likely #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 55ca632f55SGrant Likely #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ 56ca632f55SGrant Likely 57ca632f55SGrant Likely #define SPIINT_MASKALL 0x0101035F 58ca632f55SGrant Likely #define SPIINT_MASKINT 0x0000015F 59ca632f55SGrant Likely #define SPI_INTLVL_1 0x000001FF 60ca632f55SGrant Likely #define SPI_INTLVL_0 0x00000000 61ca632f55SGrant Likely 62ca632f55SGrant Likely /* SPIDAT1 (upper 16 bit defines) */ 63ca632f55SGrant Likely #define SPIDAT1_CSHOLD_MASK BIT(12) 64365a7bb3SMurali Karicheri #define SPIDAT1_WDEL BIT(10) 65ca632f55SGrant Likely 66ca632f55SGrant Likely /* SPIGCR1 */ 67ca632f55SGrant Likely #define SPIGCR1_CLKMOD_MASK BIT(1) 68ca632f55SGrant Likely #define SPIGCR1_MASTER_MASK BIT(0) 69ca632f55SGrant Likely #define SPIGCR1_POWERDOWN_MASK BIT(8) 70ca632f55SGrant Likely #define SPIGCR1_LOOPBACK_MASK BIT(16) 71ca632f55SGrant Likely #define SPIGCR1_SPIENA_MASK BIT(24) 72ca632f55SGrant Likely 73ca632f55SGrant Likely /* SPIBUF */ 74ca632f55SGrant Likely #define SPIBUF_TXFULL_MASK BIT(29) 75ca632f55SGrant Likely #define SPIBUF_RXEMPTY_MASK BIT(31) 76ca632f55SGrant Likely 77ca632f55SGrant Likely /* SPIDELAY */ 78ca632f55SGrant Likely #define SPIDELAY_C2TDELAY_SHIFT 24 79ca632f55SGrant Likely #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) 80ca632f55SGrant Likely #define SPIDELAY_T2CDELAY_SHIFT 16 81ca632f55SGrant Likely #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) 82ca632f55SGrant Likely #define SPIDELAY_T2EDELAY_SHIFT 8 83ca632f55SGrant Likely #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) 84ca632f55SGrant Likely #define SPIDELAY_C2EDELAY_SHIFT 0 85ca632f55SGrant Likely #define SPIDELAY_C2EDELAY_MASK 0xFF 86ca632f55SGrant Likely 87ca632f55SGrant Likely /* Error Masks */ 88ca632f55SGrant Likely #define SPIFLG_DLEN_ERR_MASK BIT(0) 89ca632f55SGrant Likely #define SPIFLG_TIMEOUT_MASK BIT(1) 90ca632f55SGrant Likely #define SPIFLG_PARERR_MASK BIT(2) 91ca632f55SGrant Likely #define SPIFLG_DESYNC_MASK BIT(3) 92ca632f55SGrant Likely #define SPIFLG_BITERR_MASK BIT(4) 93ca632f55SGrant Likely #define SPIFLG_OVRRUN_MASK BIT(6) 94ca632f55SGrant Likely #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) 95ca632f55SGrant Likely #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ 96ca632f55SGrant Likely | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ 97ca632f55SGrant Likely | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ 98ca632f55SGrant Likely | SPIFLG_OVRRUN_MASK) 99ca632f55SGrant Likely 100ca632f55SGrant Likely #define SPIINT_DMA_REQ_EN BIT(16) 101ca632f55SGrant Likely 102ca632f55SGrant Likely /* SPI Controller registers */ 103ca632f55SGrant Likely #define SPIGCR0 0x00 104ca632f55SGrant Likely #define SPIGCR1 0x04 105ca632f55SGrant Likely #define SPIINT 0x08 106ca632f55SGrant Likely #define SPILVL 0x0c 107ca632f55SGrant Likely #define SPIFLG 0x10 108ca632f55SGrant Likely #define SPIPC0 0x14 109ca632f55SGrant Likely #define SPIDAT1 0x3c 110ca632f55SGrant Likely #define SPIBUF 0x40 111ca632f55SGrant Likely #define SPIDELAY 0x48 112ca632f55SGrant Likely #define SPIDEF 0x4c 113ca632f55SGrant Likely #define SPIFMT0 0x50 114ca632f55SGrant Likely 115ca632f55SGrant Likely /* SPI Controller driver's private data. */ 116ca632f55SGrant Likely struct davinci_spi { 117ca632f55SGrant Likely struct spi_bitbang bitbang; 118ca632f55SGrant Likely struct clk *clk; 119ca632f55SGrant Likely 120ca632f55SGrant Likely u8 version; 121ca632f55SGrant Likely resource_size_t pbase; 122ca632f55SGrant Likely void __iomem *base; 123ca632f55SGrant Likely u32 irq; 124ca632f55SGrant Likely struct completion done; 125ca632f55SGrant Likely 126ca632f55SGrant Likely const void *tx; 127ca632f55SGrant Likely void *rx; 128ca632f55SGrant Likely int rcount; 129ca632f55SGrant Likely int wcount; 130048177ceSMatt Porter 131048177ceSMatt Porter struct dma_chan *dma_rx; 132048177ceSMatt Porter struct dma_chan *dma_tx; 133048177ceSMatt Porter int dma_rx_chnum; 134048177ceSMatt Porter int dma_tx_chnum; 135048177ceSMatt Porter 136aae7147dSMurali Karicheri struct davinci_spi_platform_data pdata; 137ca632f55SGrant Likely 138ca632f55SGrant Likely void (*get_rx)(u32 rx_data, struct davinci_spi *); 139ca632f55SGrant Likely u32 (*get_tx)(struct davinci_spi *); 140ca632f55SGrant Likely 1417480e755SMurali Karicheri u8 *bytes_per_word; 142fa466c91SFranklin S Cooper Jr 143fa466c91SFranklin S Cooper Jr u8 prescaler_limit; 144ca632f55SGrant Likely }; 145ca632f55SGrant Likely 146ca632f55SGrant Likely static struct davinci_spi_config davinci_spi_default_cfg; 147ca632f55SGrant Likely 148ca632f55SGrant Likely static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) 149ca632f55SGrant Likely { 150ca632f55SGrant Likely if (dspi->rx) { 151ca632f55SGrant Likely u8 *rx = dspi->rx; 152ca632f55SGrant Likely *rx++ = (u8)data; 153ca632f55SGrant Likely dspi->rx = rx; 154ca632f55SGrant Likely } 155ca632f55SGrant Likely } 156ca632f55SGrant Likely 157ca632f55SGrant Likely static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) 158ca632f55SGrant Likely { 159ca632f55SGrant Likely if (dspi->rx) { 160ca632f55SGrant Likely u16 *rx = dspi->rx; 161ca632f55SGrant Likely *rx++ = (u16)data; 162ca632f55SGrant Likely dspi->rx = rx; 163ca632f55SGrant Likely } 164ca632f55SGrant Likely } 165ca632f55SGrant Likely 166ca632f55SGrant Likely static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) 167ca632f55SGrant Likely { 168ca632f55SGrant Likely u32 data = 0; 169859c3377SJingoo Han 170ca632f55SGrant Likely if (dspi->tx) { 171ca632f55SGrant Likely const u8 *tx = dspi->tx; 172859c3377SJingoo Han 173ca632f55SGrant Likely data = *tx++; 174ca632f55SGrant Likely dspi->tx = tx; 175ca632f55SGrant Likely } 176ca632f55SGrant Likely return data; 177ca632f55SGrant Likely } 178ca632f55SGrant Likely 179ca632f55SGrant Likely static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) 180ca632f55SGrant Likely { 181ca632f55SGrant Likely u32 data = 0; 182859c3377SJingoo Han 183ca632f55SGrant Likely if (dspi->tx) { 184ca632f55SGrant Likely const u16 *tx = dspi->tx; 185859c3377SJingoo Han 186ca632f55SGrant Likely data = *tx++; 187ca632f55SGrant Likely dspi->tx = tx; 188ca632f55SGrant Likely } 189ca632f55SGrant Likely return data; 190ca632f55SGrant Likely } 191ca632f55SGrant Likely 192ca632f55SGrant Likely static inline void set_io_bits(void __iomem *addr, u32 bits) 193ca632f55SGrant Likely { 194ca632f55SGrant Likely u32 v = ioread32(addr); 195ca632f55SGrant Likely 196ca632f55SGrant Likely v |= bits; 197ca632f55SGrant Likely iowrite32(v, addr); 198ca632f55SGrant Likely } 199ca632f55SGrant Likely 200ca632f55SGrant Likely static inline void clear_io_bits(void __iomem *addr, u32 bits) 201ca632f55SGrant Likely { 202ca632f55SGrant Likely u32 v = ioread32(addr); 203ca632f55SGrant Likely 204ca632f55SGrant Likely v &= ~bits; 205ca632f55SGrant Likely iowrite32(v, addr); 206ca632f55SGrant Likely } 207ca632f55SGrant Likely 208ca632f55SGrant Likely /* 209ca632f55SGrant Likely * Interface to control the chip select signal 210ca632f55SGrant Likely */ 211ca632f55SGrant Likely static void davinci_spi_chipselect(struct spi_device *spi, int value) 212ca632f55SGrant Likely { 213ca632f55SGrant Likely struct davinci_spi *dspi; 214ca632f55SGrant Likely struct davinci_spi_platform_data *pdata; 215365a7bb3SMurali Karicheri struct davinci_spi_config *spicfg = spi->controller_data; 216ca632f55SGrant Likely u8 chip_sel = spi->chip_select; 217ca632f55SGrant Likely u16 spidat1 = CS_DEFAULT; 218ca632f55SGrant Likely 219ca632f55SGrant Likely dspi = spi_master_get_devdata(spi->master); 220aae7147dSMurali Karicheri pdata = &dspi->pdata; 221ca632f55SGrant Likely 222365a7bb3SMurali Karicheri /* program delay transfers if tx_delay is non zero */ 223365a7bb3SMurali Karicheri if (spicfg->wdelay) 224365a7bb3SMurali Karicheri spidat1 |= SPIDAT1_WDEL; 225365a7bb3SMurali Karicheri 226ca632f55SGrant Likely /* 227ca632f55SGrant Likely * Board specific chip select logic decides the polarity and cs 228ca632f55SGrant Likely * line for the controller 229ca632f55SGrant Likely */ 2308cae0424SLuis de Bethencourt if (spi->cs_gpio >= 0) { 231ca632f55SGrant Likely if (value == BITBANG_CS_ACTIVE) 2328cae0424SLuis de Bethencourt gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH); 233ca632f55SGrant Likely else 2348cae0424SLuis de Bethencourt gpio_set_value(spi->cs_gpio, 2358cae0424SLuis de Bethencourt !(spi->mode & SPI_CS_HIGH)); 236ca632f55SGrant Likely } else { 237ca632f55SGrant Likely if (value == BITBANG_CS_ACTIVE) { 238ca632f55SGrant Likely spidat1 |= SPIDAT1_CSHOLD_MASK; 239ca632f55SGrant Likely spidat1 &= ~(0x1 << chip_sel); 240ca632f55SGrant Likely } 241365a7bb3SMurali Karicheri } 242ca632f55SGrant Likely 243ca632f55SGrant Likely iowrite16(spidat1, dspi->base + SPIDAT1 + 2); 244ca632f55SGrant Likely } 245ca632f55SGrant Likely 246ca632f55SGrant Likely /** 247ca632f55SGrant Likely * davinci_spi_get_prescale - Calculates the correct prescale value 248ca632f55SGrant Likely * @maxspeed_hz: the maximum rate the SPI clock can run at 249ca632f55SGrant Likely * 250ca632f55SGrant Likely * This function calculates the prescale value that generates a clock rate 251ca632f55SGrant Likely * less than or equal to the specified maximum. 252ca632f55SGrant Likely * 253bba732d8SFranklin S Cooper Jr * Returns: calculated prescale value for easy programming into SPI registers 254ca632f55SGrant Likely * or negative error number if valid prescalar cannot be updated. 255ca632f55SGrant Likely */ 256ca632f55SGrant Likely static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, 257ca632f55SGrant Likely u32 max_speed_hz) 258ca632f55SGrant Likely { 259ca632f55SGrant Likely int ret; 260ca632f55SGrant Likely 261bba732d8SFranklin S Cooper Jr /* Subtract 1 to match what will be programmed into SPI register. */ 262bba732d8SFranklin S Cooper Jr ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1; 263ca632f55SGrant Likely 264fa466c91SFranklin S Cooper Jr if (ret < dspi->prescaler_limit || ret > 255) 265ca632f55SGrant Likely return -EINVAL; 266ca632f55SGrant Likely 267bba732d8SFranklin S Cooper Jr return ret; 268ca632f55SGrant Likely } 269ca632f55SGrant Likely 270ca632f55SGrant Likely /** 271ca632f55SGrant Likely * davinci_spi_setup_transfer - This functions will determine transfer method 272ca632f55SGrant Likely * @spi: spi device on which data transfer to be done 273ca632f55SGrant Likely * @t: spi transfer in which transfer info is filled 274ca632f55SGrant Likely * 275ca632f55SGrant Likely * This function determines data transfer method (8/16/32 bit transfer). 276ca632f55SGrant Likely * It will also set the SPI Clock Control register according to 277ca632f55SGrant Likely * SPI slave device freq. 278ca632f55SGrant Likely */ 279ca632f55SGrant Likely static int davinci_spi_setup_transfer(struct spi_device *spi, 280ca632f55SGrant Likely struct spi_transfer *t) 281ca632f55SGrant Likely { 282ca632f55SGrant Likely 283ca632f55SGrant Likely struct davinci_spi *dspi; 284ca632f55SGrant Likely struct davinci_spi_config *spicfg; 285ca632f55SGrant Likely u8 bits_per_word = 0; 28632ea3944SSachin Kamat u32 hz = 0, spifmt = 0; 28732ea3944SSachin Kamat int prescale; 288ca632f55SGrant Likely 289ca632f55SGrant Likely dspi = spi_master_get_devdata(spi->master); 290365a7bb3SMurali Karicheri spicfg = spi->controller_data; 291ca632f55SGrant Likely if (!spicfg) 292ca632f55SGrant Likely spicfg = &davinci_spi_default_cfg; 293ca632f55SGrant Likely 294ca632f55SGrant Likely if (t) { 295ca632f55SGrant Likely bits_per_word = t->bits_per_word; 296ca632f55SGrant Likely hz = t->speed_hz; 297ca632f55SGrant Likely } 298ca632f55SGrant Likely 299ca632f55SGrant Likely /* if bits_per_word is not set then set it default */ 300ca632f55SGrant Likely if (!bits_per_word) 301ca632f55SGrant Likely bits_per_word = spi->bits_per_word; 302ca632f55SGrant Likely 303ca632f55SGrant Likely /* 304ca632f55SGrant Likely * Assign function pointer to appropriate transfer method 305ca632f55SGrant Likely * 8bit, 16bit or 32bit transfer 306ca632f55SGrant Likely */ 30724778be2SStephen Warren if (bits_per_word <= 8) { 308ca632f55SGrant Likely dspi->get_rx = davinci_spi_rx_buf_u8; 309ca632f55SGrant Likely dspi->get_tx = davinci_spi_tx_buf_u8; 310ca632f55SGrant Likely dspi->bytes_per_word[spi->chip_select] = 1; 31124778be2SStephen Warren } else { 312ca632f55SGrant Likely dspi->get_rx = davinci_spi_rx_buf_u16; 313ca632f55SGrant Likely dspi->get_tx = davinci_spi_tx_buf_u16; 314ca632f55SGrant Likely dspi->bytes_per_word[spi->chip_select] = 2; 31524778be2SStephen Warren } 316ca632f55SGrant Likely 317ca632f55SGrant Likely if (!hz) 318ca632f55SGrant Likely hz = spi->max_speed_hz; 319ca632f55SGrant Likely 320ca632f55SGrant Likely /* Set up SPIFMTn register, unique to this chipselect. */ 321ca632f55SGrant Likely 322ca632f55SGrant Likely prescale = davinci_spi_get_prescale(dspi, hz); 323ca632f55SGrant Likely if (prescale < 0) 324ca632f55SGrant Likely return prescale; 325ca632f55SGrant Likely 326ca632f55SGrant Likely spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); 327ca632f55SGrant Likely 328ca632f55SGrant Likely if (spi->mode & SPI_LSB_FIRST) 329ca632f55SGrant Likely spifmt |= SPIFMT_SHIFTDIR_MASK; 330ca632f55SGrant Likely 331ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 332ca632f55SGrant Likely spifmt |= SPIFMT_POLARITY_MASK; 333ca632f55SGrant Likely 334ca632f55SGrant Likely if (!(spi->mode & SPI_CPHA)) 335ca632f55SGrant Likely spifmt |= SPIFMT_PHASE_MASK; 336ca632f55SGrant Likely 337ca632f55SGrant Likely /* 338365a7bb3SMurali Karicheri * Assume wdelay is used only on SPI peripherals that has this field 339365a7bb3SMurali Karicheri * in SPIFMTn register and when it's configured from board file or DT. 340365a7bb3SMurali Karicheri */ 341365a7bb3SMurali Karicheri if (spicfg->wdelay) 342365a7bb3SMurali Karicheri spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) 343365a7bb3SMurali Karicheri & SPIFMT_WDELAY_MASK); 344365a7bb3SMurali Karicheri 345365a7bb3SMurali Karicheri /* 346ca632f55SGrant Likely * Version 1 hardware supports two basic SPI modes: 347ca632f55SGrant Likely * - Standard SPI mode uses 4 pins, with chipselect 348ca632f55SGrant Likely * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) 349ca632f55SGrant Likely * (distinct from SPI_3WIRE, with just one data wire; 350ca632f55SGrant Likely * or similar variants without MOSI or without MISO) 351ca632f55SGrant Likely * 352ca632f55SGrant Likely * Version 2 hardware supports an optional handshaking signal, 353ca632f55SGrant Likely * so it can support two more modes: 354ca632f55SGrant Likely * - 5 pin SPI variant is standard SPI plus SPI_READY 355ca632f55SGrant Likely * - 4 pin with enable is (SPI_READY | SPI_NO_CS) 356ca632f55SGrant Likely */ 357ca632f55SGrant Likely 358ca632f55SGrant Likely if (dspi->version == SPI_VERSION_2) { 359ca632f55SGrant Likely 360ca632f55SGrant Likely u32 delay = 0; 361ca632f55SGrant Likely 362ca632f55SGrant Likely if (spicfg->odd_parity) 363ca632f55SGrant Likely spifmt |= SPIFMT_ODD_PARITY_MASK; 364ca632f55SGrant Likely 365ca632f55SGrant Likely if (spicfg->parity_enable) 366ca632f55SGrant Likely spifmt |= SPIFMT_PARITYENA_MASK; 367ca632f55SGrant Likely 368ca632f55SGrant Likely if (spicfg->timer_disable) { 369ca632f55SGrant Likely spifmt |= SPIFMT_DISTIMER_MASK; 370ca632f55SGrant Likely } else { 371ca632f55SGrant Likely delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) 372ca632f55SGrant Likely & SPIDELAY_C2TDELAY_MASK; 373ca632f55SGrant Likely delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) 374ca632f55SGrant Likely & SPIDELAY_T2CDELAY_MASK; 375ca632f55SGrant Likely } 376ca632f55SGrant Likely 377ca632f55SGrant Likely if (spi->mode & SPI_READY) { 378ca632f55SGrant Likely spifmt |= SPIFMT_WAITENA_MASK; 379ca632f55SGrant Likely delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) 380ca632f55SGrant Likely & SPIDELAY_T2EDELAY_MASK; 381ca632f55SGrant Likely delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) 382ca632f55SGrant Likely & SPIDELAY_C2EDELAY_MASK; 383ca632f55SGrant Likely } 384ca632f55SGrant Likely 385ca632f55SGrant Likely iowrite32(delay, dspi->base + SPIDELAY); 386ca632f55SGrant Likely } 387ca632f55SGrant Likely 388ca632f55SGrant Likely iowrite32(spifmt, dspi->base + SPIFMT0); 389ca632f55SGrant Likely 390ca632f55SGrant Likely return 0; 391ca632f55SGrant Likely } 392ca632f55SGrant Likely 393365a7bb3SMurali Karicheri static int davinci_spi_of_setup(struct spi_device *spi) 394365a7bb3SMurali Karicheri { 395365a7bb3SMurali Karicheri struct davinci_spi_config *spicfg = spi->controller_data; 396365a7bb3SMurali Karicheri struct device_node *np = spi->dev.of_node; 397365a7bb3SMurali Karicheri u32 prop; 398365a7bb3SMurali Karicheri 399365a7bb3SMurali Karicheri if (spicfg == NULL && np) { 400365a7bb3SMurali Karicheri spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL); 401365a7bb3SMurali Karicheri if (!spicfg) 402365a7bb3SMurali Karicheri return -ENOMEM; 403365a7bb3SMurali Karicheri *spicfg = davinci_spi_default_cfg; 404365a7bb3SMurali Karicheri /* override with dt configured values */ 405365a7bb3SMurali Karicheri if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) 406365a7bb3SMurali Karicheri spicfg->wdelay = (u8)prop; 407365a7bb3SMurali Karicheri spi->controller_data = spicfg; 408365a7bb3SMurali Karicheri } 409365a7bb3SMurali Karicheri 410365a7bb3SMurali Karicheri return 0; 411365a7bb3SMurali Karicheri } 412365a7bb3SMurali Karicheri 413ca632f55SGrant Likely /** 414ca632f55SGrant Likely * davinci_spi_setup - This functions will set default transfer method 415ca632f55SGrant Likely * @spi: spi device on which data transfer to be done 416ca632f55SGrant Likely * 417ca632f55SGrant Likely * This functions sets the default transfer method. 418ca632f55SGrant Likely */ 419ca632f55SGrant Likely static int davinci_spi_setup(struct spi_device *spi) 420ca632f55SGrant Likely { 421ca632f55SGrant Likely int retval = 0; 422ca632f55SGrant Likely struct davinci_spi *dspi; 423ca632f55SGrant Likely struct davinci_spi_platform_data *pdata; 424a88e34eaSMurali Karicheri struct spi_master *master = spi->master; 425a88e34eaSMurali Karicheri struct device_node *np = spi->dev.of_node; 426a88e34eaSMurali Karicheri bool internal_cs = true; 427ca632f55SGrant Likely 428ca632f55SGrant Likely dspi = spi_master_get_devdata(spi->master); 429aae7147dSMurali Karicheri pdata = &dspi->pdata; 430ca632f55SGrant Likely 431ca632f55SGrant Likely if (!(spi->mode & SPI_NO_CS)) { 432a88e34eaSMurali Karicheri if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { 4338936decdSGrygorii Strashko retval = gpio_direction_output( 4348936decdSGrygorii Strashko spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 435a88e34eaSMurali Karicheri internal_cs = false; 436a88e34eaSMurali Karicheri } else if (pdata->chip_sel && 437a88e34eaSMurali Karicheri spi->chip_select < pdata->num_chipselect && 438a88e34eaSMurali Karicheri pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { 439c0600140SGrygorii Strashko spi->cs_gpio = pdata->chip_sel[spi->chip_select]; 4408936decdSGrygorii Strashko retval = gpio_direction_output( 4418936decdSGrygorii Strashko spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 442a88e34eaSMurali Karicheri internal_cs = false; 443a88e34eaSMurali Karicheri } 444a88e34eaSMurali Karicheri 445c0600140SGrygorii Strashko if (retval) { 446c0600140SGrygorii Strashko dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", 447c0600140SGrygorii Strashko spi->cs_gpio, retval); 448c0600140SGrygorii Strashko return retval; 449c0600140SGrygorii Strashko } 450c0600140SGrygorii Strashko 451a88e34eaSMurali Karicheri if (internal_cs) 452a88e34eaSMurali Karicheri set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 4533f2dad99SGrygorii Strashko } 454ca632f55SGrant Likely 455ca632f55SGrant Likely if (spi->mode & SPI_READY) 456ca632f55SGrant Likely set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 457ca632f55SGrant Likely 458ca632f55SGrant Likely if (spi->mode & SPI_LOOP) 459ca632f55SGrant Likely set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 460ca632f55SGrant Likely else 461ca632f55SGrant Likely clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 462ca632f55SGrant Likely 463365a7bb3SMurali Karicheri return davinci_spi_of_setup(spi); 464365a7bb3SMurali Karicheri } 465365a7bb3SMurali Karicheri 466365a7bb3SMurali Karicheri static void davinci_spi_cleanup(struct spi_device *spi) 467365a7bb3SMurali Karicheri { 468365a7bb3SMurali Karicheri struct davinci_spi_config *spicfg = spi->controller_data; 469365a7bb3SMurali Karicheri 470365a7bb3SMurali Karicheri spi->controller_data = NULL; 471365a7bb3SMurali Karicheri if (spi->dev.of_node) 472365a7bb3SMurali Karicheri kfree(spicfg); 473ca632f55SGrant Likely } 474ca632f55SGrant Likely 475ca632f55SGrant Likely static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) 476ca632f55SGrant Likely { 477ca632f55SGrant Likely struct device *sdev = dspi->bitbang.master->dev.parent; 478ca632f55SGrant Likely 479ca632f55SGrant Likely if (int_status & SPIFLG_TIMEOUT_MASK) { 480ca632f55SGrant Likely dev_dbg(sdev, "SPI Time-out Error\n"); 481ca632f55SGrant Likely return -ETIMEDOUT; 482ca632f55SGrant Likely } 483ca632f55SGrant Likely if (int_status & SPIFLG_DESYNC_MASK) { 484ca632f55SGrant Likely dev_dbg(sdev, "SPI Desynchronization Error\n"); 485ca632f55SGrant Likely return -EIO; 486ca632f55SGrant Likely } 487ca632f55SGrant Likely if (int_status & SPIFLG_BITERR_MASK) { 488ca632f55SGrant Likely dev_dbg(sdev, "SPI Bit error\n"); 489ca632f55SGrant Likely return -EIO; 490ca632f55SGrant Likely } 491ca632f55SGrant Likely 492ca632f55SGrant Likely if (dspi->version == SPI_VERSION_2) { 493ca632f55SGrant Likely if (int_status & SPIFLG_DLEN_ERR_MASK) { 494ca632f55SGrant Likely dev_dbg(sdev, "SPI Data Length Error\n"); 495ca632f55SGrant Likely return -EIO; 496ca632f55SGrant Likely } 497ca632f55SGrant Likely if (int_status & SPIFLG_PARERR_MASK) { 498ca632f55SGrant Likely dev_dbg(sdev, "SPI Parity Error\n"); 499ca632f55SGrant Likely return -EIO; 500ca632f55SGrant Likely } 501ca632f55SGrant Likely if (int_status & SPIFLG_OVRRUN_MASK) { 502ca632f55SGrant Likely dev_dbg(sdev, "SPI Data Overrun error\n"); 503ca632f55SGrant Likely return -EIO; 504ca632f55SGrant Likely } 505ca632f55SGrant Likely if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { 506ca632f55SGrant Likely dev_dbg(sdev, "SPI Buffer Init Active\n"); 507ca632f55SGrant Likely return -EBUSY; 508ca632f55SGrant Likely } 509ca632f55SGrant Likely } 510ca632f55SGrant Likely 511ca632f55SGrant Likely return 0; 512ca632f55SGrant Likely } 513ca632f55SGrant Likely 514ca632f55SGrant Likely /** 515ca632f55SGrant Likely * davinci_spi_process_events - check for and handle any SPI controller events 516ca632f55SGrant Likely * @dspi: the controller data 517ca632f55SGrant Likely * 518ca632f55SGrant Likely * This function will check the SPIFLG register and handle any events that are 519ca632f55SGrant Likely * detected there 520ca632f55SGrant Likely */ 521ca632f55SGrant Likely static int davinci_spi_process_events(struct davinci_spi *dspi) 522ca632f55SGrant Likely { 523ca632f55SGrant Likely u32 buf, status, errors = 0, spidat1; 524ca632f55SGrant Likely 525ca632f55SGrant Likely buf = ioread32(dspi->base + SPIBUF); 526ca632f55SGrant Likely 527ca632f55SGrant Likely if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { 528ca632f55SGrant Likely dspi->get_rx(buf & 0xFFFF, dspi); 529ca632f55SGrant Likely dspi->rcount--; 530ca632f55SGrant Likely } 531ca632f55SGrant Likely 532ca632f55SGrant Likely status = ioread32(dspi->base + SPIFLG); 533ca632f55SGrant Likely 534ca632f55SGrant Likely if (unlikely(status & SPIFLG_ERROR_MASK)) { 535ca632f55SGrant Likely errors = status & SPIFLG_ERROR_MASK; 536ca632f55SGrant Likely goto out; 537ca632f55SGrant Likely } 538ca632f55SGrant Likely 539ca632f55SGrant Likely if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { 540ca632f55SGrant Likely spidat1 = ioread32(dspi->base + SPIDAT1); 541ca632f55SGrant Likely dspi->wcount--; 542ca632f55SGrant Likely spidat1 &= ~0xFFFF; 543ca632f55SGrant Likely spidat1 |= 0xFFFF & dspi->get_tx(dspi); 544ca632f55SGrant Likely iowrite32(spidat1, dspi->base + SPIDAT1); 545ca632f55SGrant Likely } 546ca632f55SGrant Likely 547ca632f55SGrant Likely out: 548ca632f55SGrant Likely return errors; 549ca632f55SGrant Likely } 550ca632f55SGrant Likely 551048177ceSMatt Porter static void davinci_spi_dma_rx_callback(void *data) 552ca632f55SGrant Likely { 553048177ceSMatt Porter struct davinci_spi *dspi = (struct davinci_spi *)data; 554ca632f55SGrant Likely 555ca632f55SGrant Likely dspi->rcount = 0; 556048177ceSMatt Porter 557048177ceSMatt Porter if (!dspi->wcount && !dspi->rcount) 558048177ceSMatt Porter complete(&dspi->done); 559ca632f55SGrant Likely } 560ca632f55SGrant Likely 561048177ceSMatt Porter static void davinci_spi_dma_tx_callback(void *data) 562048177ceSMatt Porter { 563048177ceSMatt Porter struct davinci_spi *dspi = (struct davinci_spi *)data; 564048177ceSMatt Porter 565048177ceSMatt Porter dspi->wcount = 0; 566048177ceSMatt Porter 567048177ceSMatt Porter if (!dspi->wcount && !dspi->rcount) 568ca632f55SGrant Likely complete(&dspi->done); 569ca632f55SGrant Likely } 570ca632f55SGrant Likely 571ca632f55SGrant Likely /** 572ca632f55SGrant Likely * davinci_spi_bufs - functions which will handle transfer data 573ca632f55SGrant Likely * @spi: spi device on which data transfer to be done 574ca632f55SGrant Likely * @t: spi transfer in which transfer info is filled 575ca632f55SGrant Likely * 576ca632f55SGrant Likely * This function will put data to be transferred into data register 577ca632f55SGrant Likely * of SPI controller and then wait until the completion will be marked 578ca632f55SGrant Likely * by the IRQ Handler. 579ca632f55SGrant Likely */ 580ca632f55SGrant Likely static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) 581ca632f55SGrant Likely { 582ca632f55SGrant Likely struct davinci_spi *dspi; 583048177ceSMatt Porter int data_type, ret = -ENOMEM; 584ca632f55SGrant Likely u32 tx_data, spidat1; 585ca632f55SGrant Likely u32 errors = 0; 586ca632f55SGrant Likely struct davinci_spi_config *spicfg; 587ca632f55SGrant Likely struct davinci_spi_platform_data *pdata; 588ca632f55SGrant Likely unsigned uninitialized_var(rx_buf_count); 589048177ceSMatt Porter void *dummy_buf = NULL; 590048177ceSMatt Porter struct scatterlist sg_rx, sg_tx; 591ca632f55SGrant Likely 592ca632f55SGrant Likely dspi = spi_master_get_devdata(spi->master); 593aae7147dSMurali Karicheri pdata = &dspi->pdata; 594ca632f55SGrant Likely spicfg = (struct davinci_spi_config *)spi->controller_data; 595ca632f55SGrant Likely if (!spicfg) 596ca632f55SGrant Likely spicfg = &davinci_spi_default_cfg; 597ca632f55SGrant Likely 598ca632f55SGrant Likely /* convert len to words based on bits_per_word */ 599ca632f55SGrant Likely data_type = dspi->bytes_per_word[spi->chip_select]; 600ca632f55SGrant Likely 601ca632f55SGrant Likely dspi->tx = t->tx_buf; 602ca632f55SGrant Likely dspi->rx = t->rx_buf; 603ca632f55SGrant Likely dspi->wcount = t->len / data_type; 604ca632f55SGrant Likely dspi->rcount = dspi->wcount; 605ca632f55SGrant Likely 606ca632f55SGrant Likely spidat1 = ioread32(dspi->base + SPIDAT1); 607ca632f55SGrant Likely 608ca632f55SGrant Likely clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 609ca632f55SGrant Likely set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 610ca632f55SGrant Likely 61116735d02SWolfram Sang reinit_completion(&dspi->done); 612ca632f55SGrant Likely 613ca632f55SGrant Likely if (spicfg->io_type == SPI_IO_TYPE_INTR) 614ca632f55SGrant Likely set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 615ca632f55SGrant Likely 616ca632f55SGrant Likely if (spicfg->io_type != SPI_IO_TYPE_DMA) { 617ca632f55SGrant Likely /* start the transfer */ 618ca632f55SGrant Likely dspi->wcount--; 619ca632f55SGrant Likely tx_data = dspi->get_tx(dspi); 620ca632f55SGrant Likely spidat1 &= 0xFFFF0000; 621ca632f55SGrant Likely spidat1 |= tx_data & 0xFFFF; 622ca632f55SGrant Likely iowrite32(spidat1, dspi->base + SPIDAT1); 623ca632f55SGrant Likely } else { 624048177ceSMatt Porter struct dma_slave_config dma_rx_conf = { 625048177ceSMatt Porter .direction = DMA_DEV_TO_MEM, 626048177ceSMatt Porter .src_addr = (unsigned long)dspi->pbase + SPIBUF, 627048177ceSMatt Porter .src_addr_width = data_type, 628048177ceSMatt Porter .src_maxburst = 1, 629048177ceSMatt Porter }; 630048177ceSMatt Porter struct dma_slave_config dma_tx_conf = { 631048177ceSMatt Porter .direction = DMA_MEM_TO_DEV, 632048177ceSMatt Porter .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, 633048177ceSMatt Porter .dst_addr_width = data_type, 634048177ceSMatt Porter .dst_maxburst = 1, 635048177ceSMatt Porter }; 636048177ceSMatt Porter struct dma_async_tx_descriptor *rxdesc; 637048177ceSMatt Porter struct dma_async_tx_descriptor *txdesc; 638048177ceSMatt Porter void *buf; 639ca632f55SGrant Likely 640048177ceSMatt Porter dummy_buf = kzalloc(t->len, GFP_KERNEL); 641048177ceSMatt Porter if (!dummy_buf) 642048177ceSMatt Porter goto err_alloc_dummy_buf; 643ca632f55SGrant Likely 644048177ceSMatt Porter dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); 645048177ceSMatt Porter dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); 646ca632f55SGrant Likely 647048177ceSMatt Porter sg_init_table(&sg_rx, 1); 648048177ceSMatt Porter if (!t->rx_buf) 649048177ceSMatt Porter buf = dummy_buf; 650ca632f55SGrant Likely else 651048177ceSMatt Porter buf = t->rx_buf; 652048177ceSMatt Porter t->rx_dma = dma_map_single(&spi->dev, buf, 653048177ceSMatt Porter t->len, DMA_FROM_DEVICE); 654048177ceSMatt Porter if (!t->rx_dma) { 655048177ceSMatt Porter ret = -EFAULT; 656048177ceSMatt Porter goto err_rx_map; 657ca632f55SGrant Likely } 658048177ceSMatt Porter sg_dma_address(&sg_rx) = t->rx_dma; 659048177ceSMatt Porter sg_dma_len(&sg_rx) = t->len; 660ca632f55SGrant Likely 661048177ceSMatt Porter sg_init_table(&sg_tx, 1); 662048177ceSMatt Porter if (!t->tx_buf) 663048177ceSMatt Porter buf = dummy_buf; 664048177ceSMatt Porter else 665048177ceSMatt Porter buf = (void *)t->tx_buf; 666048177ceSMatt Porter t->tx_dma = dma_map_single(&spi->dev, buf, 66789c66ee8SChristian Eggers t->len, DMA_TO_DEVICE); 668048177ceSMatt Porter if (!t->tx_dma) { 669048177ceSMatt Porter ret = -EFAULT; 670048177ceSMatt Porter goto err_tx_map; 671ca632f55SGrant Likely } 672048177ceSMatt Porter sg_dma_address(&sg_tx) = t->tx_dma; 673048177ceSMatt Porter sg_dma_len(&sg_tx) = t->len; 674ca632f55SGrant Likely 675048177ceSMatt Porter rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, 676048177ceSMatt Porter &sg_rx, 1, DMA_DEV_TO_MEM, 677048177ceSMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 678048177ceSMatt Porter if (!rxdesc) 679048177ceSMatt Porter goto err_desc; 680048177ceSMatt Porter 681048177ceSMatt Porter txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, 682048177ceSMatt Porter &sg_tx, 1, DMA_MEM_TO_DEV, 683048177ceSMatt Porter DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 684048177ceSMatt Porter if (!txdesc) 685048177ceSMatt Porter goto err_desc; 686048177ceSMatt Porter 687048177ceSMatt Porter rxdesc->callback = davinci_spi_dma_rx_callback; 688048177ceSMatt Porter rxdesc->callback_param = (void *)dspi; 689048177ceSMatt Porter txdesc->callback = davinci_spi_dma_tx_callback; 690048177ceSMatt Porter txdesc->callback_param = (void *)dspi; 691ca632f55SGrant Likely 692ca632f55SGrant Likely if (pdata->cshold_bug) 693ca632f55SGrant Likely iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); 694ca632f55SGrant Likely 695048177ceSMatt Porter dmaengine_submit(rxdesc); 696048177ceSMatt Porter dmaengine_submit(txdesc); 697048177ceSMatt Porter 698048177ceSMatt Porter dma_async_issue_pending(dspi->dma_rx); 699048177ceSMatt Porter dma_async_issue_pending(dspi->dma_tx); 700048177ceSMatt Porter 701ca632f55SGrant Likely set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 702ca632f55SGrant Likely } 703ca632f55SGrant Likely 704ca632f55SGrant Likely /* Wait for the transfer to complete */ 705ca632f55SGrant Likely if (spicfg->io_type != SPI_IO_TYPE_POLL) { 706*7f3ac71aSSekhar Nori if (wait_for_completion_timeout(&dspi->done, HZ) == 0) 707*7f3ac71aSSekhar Nori errors = SPIFLG_TIMEOUT_MASK; 708ca632f55SGrant Likely } else { 709ca632f55SGrant Likely while (dspi->rcount > 0 || dspi->wcount > 0) { 710ca632f55SGrant Likely errors = davinci_spi_process_events(dspi); 711ca632f55SGrant Likely if (errors) 712ca632f55SGrant Likely break; 713ca632f55SGrant Likely cpu_relax(); 714ca632f55SGrant Likely } 715ca632f55SGrant Likely } 716ca632f55SGrant Likely 717ca632f55SGrant Likely clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); 718ca632f55SGrant Likely if (spicfg->io_type == SPI_IO_TYPE_DMA) { 719ca632f55SGrant Likely clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 720048177ceSMatt Porter 721048177ceSMatt Porter dma_unmap_single(&spi->dev, t->rx_dma, 722048177ceSMatt Porter t->len, DMA_FROM_DEVICE); 723048177ceSMatt Porter dma_unmap_single(&spi->dev, t->tx_dma, 724048177ceSMatt Porter t->len, DMA_TO_DEVICE); 725048177ceSMatt Porter kfree(dummy_buf); 726ca632f55SGrant Likely } 727ca632f55SGrant Likely 728ca632f55SGrant Likely clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 729ca632f55SGrant Likely set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 730ca632f55SGrant Likely 731ca632f55SGrant Likely /* 732ca632f55SGrant Likely * Check for bit error, desync error,parity error,timeout error and 733ca632f55SGrant Likely * receive overflow errors 734ca632f55SGrant Likely */ 735ca632f55SGrant Likely if (errors) { 736ca632f55SGrant Likely ret = davinci_spi_check_error(dspi, errors); 737ca632f55SGrant Likely WARN(!ret, "%s: error reported but no error found!\n", 738ca632f55SGrant Likely dev_name(&spi->dev)); 739ca632f55SGrant Likely return ret; 740ca632f55SGrant Likely } 741ca632f55SGrant Likely 742ca632f55SGrant Likely if (dspi->rcount != 0 || dspi->wcount != 0) { 743048177ceSMatt Porter dev_err(&spi->dev, "SPI data transfer error\n"); 744ca632f55SGrant Likely return -EIO; 745ca632f55SGrant Likely } 746ca632f55SGrant Likely 747ca632f55SGrant Likely return t->len; 748048177ceSMatt Porter 749048177ceSMatt Porter err_desc: 750048177ceSMatt Porter dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); 751048177ceSMatt Porter err_tx_map: 752048177ceSMatt Porter dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); 753048177ceSMatt Porter err_rx_map: 754048177ceSMatt Porter kfree(dummy_buf); 755048177ceSMatt Porter err_alloc_dummy_buf: 756048177ceSMatt Porter return ret; 757ca632f55SGrant Likely } 758ca632f55SGrant Likely 759ca632f55SGrant Likely /** 76032310aafSMurali Karicheri * dummy_thread_fn - dummy thread function 76132310aafSMurali Karicheri * @irq: IRQ number for this SPI Master 76232310aafSMurali Karicheri * @context_data: structure for SPI Master controller davinci_spi 76332310aafSMurali Karicheri * 76432310aafSMurali Karicheri * This is to satisfy the request_threaded_irq() API so that the irq 76532310aafSMurali Karicheri * handler is called in interrupt context. 76632310aafSMurali Karicheri */ 76732310aafSMurali Karicheri static irqreturn_t dummy_thread_fn(s32 irq, void *data) 76832310aafSMurali Karicheri { 76932310aafSMurali Karicheri return IRQ_HANDLED; 77032310aafSMurali Karicheri } 77132310aafSMurali Karicheri 77232310aafSMurali Karicheri /** 773ca632f55SGrant Likely * davinci_spi_irq - Interrupt handler for SPI Master Controller 774ca632f55SGrant Likely * @irq: IRQ number for this SPI Master 775ca632f55SGrant Likely * @context_data: structure for SPI Master controller davinci_spi 776ca632f55SGrant Likely * 777ca632f55SGrant Likely * ISR will determine that interrupt arrives either for READ or WRITE command. 778ca632f55SGrant Likely * According to command it will do the appropriate action. It will check 779ca632f55SGrant Likely * transfer length and if it is not zero then dispatch transfer command again. 780ca632f55SGrant Likely * If transfer length is zero then it will indicate the COMPLETION so that 781ca632f55SGrant Likely * davinci_spi_bufs function can go ahead. 782ca632f55SGrant Likely */ 783ca632f55SGrant Likely static irqreturn_t davinci_spi_irq(s32 irq, void *data) 784ca632f55SGrant Likely { 785ca632f55SGrant Likely struct davinci_spi *dspi = data; 786ca632f55SGrant Likely int status; 787ca632f55SGrant Likely 788ca632f55SGrant Likely status = davinci_spi_process_events(dspi); 789ca632f55SGrant Likely if (unlikely(status != 0)) 790ca632f55SGrant Likely clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 791ca632f55SGrant Likely 792ca632f55SGrant Likely if ((!dspi->rcount && !dspi->wcount) || status) 793ca632f55SGrant Likely complete(&dspi->done); 794ca632f55SGrant Likely 795ca632f55SGrant Likely return IRQ_HANDLED; 796ca632f55SGrant Likely } 797ca632f55SGrant Likely 798ca632f55SGrant Likely static int davinci_spi_request_dma(struct davinci_spi *dspi) 799ca632f55SGrant Likely { 800048177ceSMatt Porter dma_cap_mask_t mask; 801048177ceSMatt Porter struct device *sdev = dspi->bitbang.master->dev.parent; 802ca632f55SGrant Likely int r; 803ca632f55SGrant Likely 804048177ceSMatt Porter dma_cap_zero(mask); 805048177ceSMatt Porter dma_cap_set(DMA_SLAVE, mask); 806048177ceSMatt Porter 807048177ceSMatt Porter dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, 808048177ceSMatt Porter &dspi->dma_rx_chnum); 809048177ceSMatt Porter if (!dspi->dma_rx) { 810048177ceSMatt Porter dev_err(sdev, "request RX DMA channel failed\n"); 811048177ceSMatt Porter r = -ENODEV; 812ca632f55SGrant Likely goto rx_dma_failed; 813ca632f55SGrant Likely } 814ca632f55SGrant Likely 815048177ceSMatt Porter dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, 816048177ceSMatt Porter &dspi->dma_tx_chnum); 817048177ceSMatt Porter if (!dspi->dma_tx) { 818048177ceSMatt Porter dev_err(sdev, "request TX DMA channel failed\n"); 819048177ceSMatt Porter r = -ENODEV; 820ca632f55SGrant Likely goto tx_dma_failed; 821ca632f55SGrant Likely } 822ca632f55SGrant Likely 823ca632f55SGrant Likely return 0; 824048177ceSMatt Porter 825ca632f55SGrant Likely tx_dma_failed: 826048177ceSMatt Porter dma_release_channel(dspi->dma_rx); 827ca632f55SGrant Likely rx_dma_failed: 828ca632f55SGrant Likely return r; 829ca632f55SGrant Likely } 830ca632f55SGrant Likely 831aae7147dSMurali Karicheri #if defined(CONFIG_OF) 832fa466c91SFranklin S Cooper Jr 833fa466c91SFranklin S Cooper Jr /* OF SPI data structure */ 834fa466c91SFranklin S Cooper Jr struct davinci_spi_of_data { 835fa466c91SFranklin S Cooper Jr u8 version; 836fa466c91SFranklin S Cooper Jr u8 prescaler_limit; 837fa466c91SFranklin S Cooper Jr }; 838fa466c91SFranklin S Cooper Jr 839fa466c91SFranklin S Cooper Jr static const struct davinci_spi_of_data dm6441_spi_data = { 840fa466c91SFranklin S Cooper Jr .version = SPI_VERSION_1, 841fa466c91SFranklin S Cooper Jr .prescaler_limit = 2, 842fa466c91SFranklin S Cooper Jr }; 843fa466c91SFranklin S Cooper Jr 844fa466c91SFranklin S Cooper Jr static const struct davinci_spi_of_data da830_spi_data = { 845fa466c91SFranklin S Cooper Jr .version = SPI_VERSION_2, 846fa466c91SFranklin S Cooper Jr .prescaler_limit = 2, 847fa466c91SFranklin S Cooper Jr }; 848fa466c91SFranklin S Cooper Jr 849fa466c91SFranklin S Cooper Jr static const struct davinci_spi_of_data keystone_spi_data = { 850fa466c91SFranklin S Cooper Jr .version = SPI_VERSION_1, 851fa466c91SFranklin S Cooper Jr .prescaler_limit = 0, 852fa466c91SFranklin S Cooper Jr }; 853fa466c91SFranklin S Cooper Jr 854aae7147dSMurali Karicheri static const struct of_device_id davinci_spi_of_match[] = { 855aae7147dSMurali Karicheri { 856804413f2SManjunathappa, Prakash .compatible = "ti,dm6441-spi", 857fa466c91SFranklin S Cooper Jr .data = &dm6441_spi_data, 858aae7147dSMurali Karicheri }, 859aae7147dSMurali Karicheri { 860804413f2SManjunathappa, Prakash .compatible = "ti,da830-spi", 861fa466c91SFranklin S Cooper Jr .data = &da830_spi_data, 862fa466c91SFranklin S Cooper Jr }, 863fa466c91SFranklin S Cooper Jr { 864fa466c91SFranklin S Cooper Jr .compatible = "ti,keystone-spi", 865fa466c91SFranklin S Cooper Jr .data = &keystone_spi_data, 866aae7147dSMurali Karicheri }, 867aae7147dSMurali Karicheri { }, 868aae7147dSMurali Karicheri }; 8690d2d0cc5SManjunathappa, Prakash MODULE_DEVICE_TABLE(of, davinci_spi_of_match); 870aae7147dSMurali Karicheri 871aae7147dSMurali Karicheri /** 872aae7147dSMurali Karicheri * spi_davinci_get_pdata - Get platform data from DTS binding 873aae7147dSMurali Karicheri * @pdev: ptr to platform data 874aae7147dSMurali Karicheri * @dspi: ptr to driver data 875aae7147dSMurali Karicheri * 876aae7147dSMurali Karicheri * Parses and populates pdata in dspi from device tree bindings. 877aae7147dSMurali Karicheri * 878aae7147dSMurali Karicheri * NOTE: Not all platform data params are supported currently. 879aae7147dSMurali Karicheri */ 880aae7147dSMurali Karicheri static int spi_davinci_get_pdata(struct platform_device *pdev, 881aae7147dSMurali Karicheri struct davinci_spi *dspi) 882aae7147dSMurali Karicheri { 883aae7147dSMurali Karicheri struct device_node *node = pdev->dev.of_node; 884fa466c91SFranklin S Cooper Jr struct davinci_spi_of_data *spi_data; 885aae7147dSMurali Karicheri struct davinci_spi_platform_data *pdata; 886aae7147dSMurali Karicheri unsigned int num_cs, intr_line = 0; 887aae7147dSMurali Karicheri const struct of_device_id *match; 888aae7147dSMurali Karicheri 889aae7147dSMurali Karicheri pdata = &dspi->pdata; 890aae7147dSMurali Karicheri 891b53b34f0SAxel Lin match = of_match_device(davinci_spi_of_match, &pdev->dev); 892aae7147dSMurali Karicheri if (!match) 893aae7147dSMurali Karicheri return -ENODEV; 894aae7147dSMurali Karicheri 895fa466c91SFranklin S Cooper Jr spi_data = (struct davinci_spi_of_data *)match->data; 896aae7147dSMurali Karicheri 897fa466c91SFranklin S Cooper Jr pdata->version = spi_data->version; 898fa466c91SFranklin S Cooper Jr pdata->prescaler_limit = spi_data->prescaler_limit; 899aae7147dSMurali Karicheri /* 900aae7147dSMurali Karicheri * default num_cs is 1 and all chipsel are internal to the chip 901a88e34eaSMurali Karicheri * indicated by chip_sel being NULL or cs_gpios being NULL or 902a88e34eaSMurali Karicheri * set to -ENOENT. num-cs includes internal as well as gpios. 903aae7147dSMurali Karicheri * indicated by chip_sel being NULL. GPIO based CS is not 904aae7147dSMurali Karicheri * supported yet in DT bindings. 905aae7147dSMurali Karicheri */ 906aae7147dSMurali Karicheri num_cs = 1; 907aae7147dSMurali Karicheri of_property_read_u32(node, "num-cs", &num_cs); 908aae7147dSMurali Karicheri pdata->num_chipselect = num_cs; 909aae7147dSMurali Karicheri of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); 910aae7147dSMurali Karicheri pdata->intr_line = intr_line; 911aae7147dSMurali Karicheri return 0; 912aae7147dSMurali Karicheri } 913aae7147dSMurali Karicheri #else 914aae7147dSMurali Karicheri static struct davinci_spi_platform_data 915aae7147dSMurali Karicheri *spi_davinci_get_pdata(struct platform_device *pdev, 916aae7147dSMurali Karicheri struct davinci_spi *dspi) 917aae7147dSMurali Karicheri { 918aae7147dSMurali Karicheri return -ENODEV; 919aae7147dSMurali Karicheri } 920aae7147dSMurali Karicheri #endif 921aae7147dSMurali Karicheri 922ca632f55SGrant Likely /** 923ca632f55SGrant Likely * davinci_spi_probe - probe function for SPI Master Controller 924ca632f55SGrant Likely * @pdev: platform_device structure which contains plateform specific data 925ca632f55SGrant Likely * 926ca632f55SGrant Likely * According to Linux Device Model this function will be invoked by Linux 927ca632f55SGrant Likely * with platform_device struct which contains the device specific info. 928ca632f55SGrant Likely * This function will map the SPI controller's memory, register IRQ, 929ca632f55SGrant Likely * Reset SPI controller and setting its registers to default value. 930ca632f55SGrant Likely * It will invoke spi_bitbang_start to create work queue so that client driver 931ca632f55SGrant Likely * can register transfer method to work queue. 932ca632f55SGrant Likely */ 933fd4a319bSGrant Likely static int davinci_spi_probe(struct platform_device *pdev) 934ca632f55SGrant Likely { 935ca632f55SGrant Likely struct spi_master *master; 936ca632f55SGrant Likely struct davinci_spi *dspi; 937ca632f55SGrant Likely struct davinci_spi_platform_data *pdata; 9385b3bb596SJingoo Han struct resource *r; 939ca632f55SGrant Likely resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 940ca632f55SGrant Likely resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 941c0600140SGrygorii Strashko int ret = 0; 942ca632f55SGrant Likely u32 spipc0; 943ca632f55SGrant Likely 944ca632f55SGrant Likely master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); 945ca632f55SGrant Likely if (master == NULL) { 946ca632f55SGrant Likely ret = -ENOMEM; 947ca632f55SGrant Likely goto err; 948ca632f55SGrant Likely } 949ca632f55SGrant Likely 95024b5a82cSJingoo Han platform_set_drvdata(pdev, master); 951ca632f55SGrant Likely 952ca632f55SGrant Likely dspi = spi_master_get_devdata(master); 953ca632f55SGrant Likely 9548074cf06SJingoo Han if (dev_get_platdata(&pdev->dev)) { 9558074cf06SJingoo Han pdata = dev_get_platdata(&pdev->dev); 956aae7147dSMurali Karicheri dspi->pdata = *pdata; 957aae7147dSMurali Karicheri } else { 958aae7147dSMurali Karicheri /* update dspi pdata with that from the DT */ 959aae7147dSMurali Karicheri ret = spi_davinci_get_pdata(pdev, dspi); 960aae7147dSMurali Karicheri if (ret < 0) 961aae7147dSMurali Karicheri goto free_master; 962aae7147dSMurali Karicheri } 963aae7147dSMurali Karicheri 964aae7147dSMurali Karicheri /* pdata in dspi is now updated and point pdata to that */ 965aae7147dSMurali Karicheri pdata = &dspi->pdata; 966aae7147dSMurali Karicheri 9677480e755SMurali Karicheri dspi->bytes_per_word = devm_kzalloc(&pdev->dev, 9687480e755SMurali Karicheri sizeof(*dspi->bytes_per_word) * 9697480e755SMurali Karicheri pdata->num_chipselect, GFP_KERNEL); 9707480e755SMurali Karicheri if (dspi->bytes_per_word == NULL) { 9717480e755SMurali Karicheri ret = -ENOMEM; 9727480e755SMurali Karicheri goto free_master; 9737480e755SMurali Karicheri } 9747480e755SMurali Karicheri 975ca632f55SGrant Likely r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 976ca632f55SGrant Likely if (r == NULL) { 977ca632f55SGrant Likely ret = -ENOENT; 978ca632f55SGrant Likely goto free_master; 979ca632f55SGrant Likely } 980ca632f55SGrant Likely 981ca632f55SGrant Likely dspi->pbase = r->start; 982ca632f55SGrant Likely 9835b3bb596SJingoo Han dspi->base = devm_ioremap_resource(&pdev->dev, r); 9845b3bb596SJingoo Han if (IS_ERR(dspi->base)) { 9855b3bb596SJingoo Han ret = PTR_ERR(dspi->base); 986ca632f55SGrant Likely goto free_master; 987ca632f55SGrant Likely } 988ca632f55SGrant Likely 9898494cdeaSAndrzej Hajda ret = platform_get_irq(pdev, 0); 9908494cdeaSAndrzej Hajda if (ret == 0) 991ca632f55SGrant Likely ret = -EINVAL; 9928494cdeaSAndrzej Hajda if (ret < 0) 9935b3bb596SJingoo Han goto free_master; 9948494cdeaSAndrzej Hajda dspi->irq = ret; 995ca632f55SGrant Likely 9965b3bb596SJingoo Han ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, 9975b3bb596SJingoo Han dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); 998ca632f55SGrant Likely if (ret) 9995b3bb596SJingoo Han goto free_master; 1000ca632f55SGrant Likely 100194c69f76SAxel Lin dspi->bitbang.master = master; 1002ca632f55SGrant Likely 10035b3bb596SJingoo Han dspi->clk = devm_clk_get(&pdev->dev, NULL); 1004ca632f55SGrant Likely if (IS_ERR(dspi->clk)) { 1005ca632f55SGrant Likely ret = -ENODEV; 10065b3bb596SJingoo Han goto free_master; 1007ca632f55SGrant Likely } 1008aae7147dSMurali Karicheri clk_prepare_enable(dspi->clk); 1009ca632f55SGrant Likely 1010aae7147dSMurali Karicheri master->dev.of_node = pdev->dev.of_node; 1011ca632f55SGrant Likely master->bus_num = pdev->id; 1012ca632f55SGrant Likely master->num_chipselect = pdata->num_chipselect; 101324778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); 1014ca632f55SGrant Likely master->setup = davinci_spi_setup; 1015365a7bb3SMurali Karicheri master->cleanup = davinci_spi_cleanup; 1016ca632f55SGrant Likely 1017ca632f55SGrant Likely dspi->bitbang.chipselect = davinci_spi_chipselect; 1018ca632f55SGrant Likely dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; 1019fa466c91SFranklin S Cooper Jr dspi->prescaler_limit = pdata->prescaler_limit; 1020ca632f55SGrant Likely dspi->version = pdata->version; 1021ca632f55SGrant Likely 1022ca632f55SGrant Likely dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; 1023ca632f55SGrant Likely if (dspi->version == SPI_VERSION_2) 1024ca632f55SGrant Likely dspi->bitbang.flags |= SPI_READY; 1025ca632f55SGrant Likely 10268936decdSGrygorii Strashko if (pdev->dev.of_node) { 10278936decdSGrygorii Strashko int i; 10288936decdSGrygorii Strashko 10298936decdSGrygorii Strashko for (i = 0; i < pdata->num_chipselect; i++) { 10308936decdSGrygorii Strashko int cs_gpio = of_get_named_gpio(pdev->dev.of_node, 10318936decdSGrygorii Strashko "cs-gpios", i); 10328936decdSGrygorii Strashko 10338936decdSGrygorii Strashko if (cs_gpio == -EPROBE_DEFER) { 10348936decdSGrygorii Strashko ret = cs_gpio; 10358936decdSGrygorii Strashko goto free_clk; 10368936decdSGrygorii Strashko } 10378936decdSGrygorii Strashko 10388936decdSGrygorii Strashko if (gpio_is_valid(cs_gpio)) { 10398936decdSGrygorii Strashko ret = devm_gpio_request(&pdev->dev, cs_gpio, 10408936decdSGrygorii Strashko dev_name(&pdev->dev)); 10418936decdSGrygorii Strashko if (ret) 10428936decdSGrygorii Strashko goto free_clk; 10438936decdSGrygorii Strashko } 10448936decdSGrygorii Strashko } 10458936decdSGrygorii Strashko } 10468936decdSGrygorii Strashko 1047ca632f55SGrant Likely r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1048ca632f55SGrant Likely if (r) 1049ca632f55SGrant Likely dma_rx_chan = r->start; 1050ca632f55SGrant Likely r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1051ca632f55SGrant Likely if (r) 1052ca632f55SGrant Likely dma_tx_chan = r->start; 1053ca632f55SGrant Likely 1054ca632f55SGrant Likely dspi->bitbang.txrx_bufs = davinci_spi_bufs; 1055ca632f55SGrant Likely if (dma_rx_chan != SPI_NO_RESOURCE && 1056ca632f55SGrant Likely dma_tx_chan != SPI_NO_RESOURCE) { 1057048177ceSMatt Porter dspi->dma_rx_chnum = dma_rx_chan; 1058048177ceSMatt Porter dspi->dma_tx_chnum = dma_tx_chan; 1059ca632f55SGrant Likely 1060ca632f55SGrant Likely ret = davinci_spi_request_dma(dspi); 1061ca632f55SGrant Likely if (ret) 1062ca632f55SGrant Likely goto free_clk; 1063ca632f55SGrant Likely 1064ca632f55SGrant Likely dev_info(&pdev->dev, "DMA: supported\n"); 1065859c3377SJingoo Han dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n", 1066859c3377SJingoo Han &dma_rx_chan, &dma_tx_chan, 1067ca632f55SGrant Likely pdata->dma_event_q); 1068ca632f55SGrant Likely } 1069ca632f55SGrant Likely 1070ca632f55SGrant Likely dspi->get_rx = davinci_spi_rx_buf_u8; 1071ca632f55SGrant Likely dspi->get_tx = davinci_spi_tx_buf_u8; 1072ca632f55SGrant Likely 1073ca632f55SGrant Likely init_completion(&dspi->done); 1074ca632f55SGrant Likely 1075ca632f55SGrant Likely /* Reset In/OUT SPI module */ 1076ca632f55SGrant Likely iowrite32(0, dspi->base + SPIGCR0); 1077ca632f55SGrant Likely udelay(100); 1078ca632f55SGrant Likely iowrite32(1, dspi->base + SPIGCR0); 1079ca632f55SGrant Likely 1080ca632f55SGrant Likely /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ 1081ca632f55SGrant Likely spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; 1082ca632f55SGrant Likely iowrite32(spipc0, dspi->base + SPIPC0); 1083ca632f55SGrant Likely 1084ca632f55SGrant Likely if (pdata->intr_line) 1085ca632f55SGrant Likely iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); 1086ca632f55SGrant Likely else 1087ca632f55SGrant Likely iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); 1088ca632f55SGrant Likely 1089ca632f55SGrant Likely iowrite32(CS_DEFAULT, dspi->base + SPIDEF); 1090ca632f55SGrant Likely 1091ca632f55SGrant Likely /* master mode default */ 1092ca632f55SGrant Likely set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); 1093ca632f55SGrant Likely set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); 1094ca632f55SGrant Likely set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 1095ca632f55SGrant Likely 1096ca632f55SGrant Likely ret = spi_bitbang_start(&dspi->bitbang); 1097ca632f55SGrant Likely if (ret) 1098ca632f55SGrant Likely goto free_dma; 1099ca632f55SGrant Likely 1100ca632f55SGrant Likely dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); 1101ca632f55SGrant Likely 1102ca632f55SGrant Likely return ret; 1103ca632f55SGrant Likely 1104ca632f55SGrant Likely free_dma: 1105048177ceSMatt Porter dma_release_channel(dspi->dma_rx); 1106048177ceSMatt Porter dma_release_channel(dspi->dma_tx); 1107ca632f55SGrant Likely free_clk: 1108aae7147dSMurali Karicheri clk_disable_unprepare(dspi->clk); 1109ca632f55SGrant Likely free_master: 111094c69f76SAxel Lin spi_master_put(master); 1111ca632f55SGrant Likely err: 1112ca632f55SGrant Likely return ret; 1113ca632f55SGrant Likely } 1114ca632f55SGrant Likely 1115ca632f55SGrant Likely /** 1116ca632f55SGrant Likely * davinci_spi_remove - remove function for SPI Master Controller 1117ca632f55SGrant Likely * @pdev: platform_device structure which contains plateform specific data 1118ca632f55SGrant Likely * 1119ca632f55SGrant Likely * This function will do the reverse action of davinci_spi_probe function 1120ca632f55SGrant Likely * It will free the IRQ and SPI controller's memory region. 1121ca632f55SGrant Likely * It will also call spi_bitbang_stop to destroy the work queue which was 1122ca632f55SGrant Likely * created by spi_bitbang_start. 1123ca632f55SGrant Likely */ 1124fd4a319bSGrant Likely static int davinci_spi_remove(struct platform_device *pdev) 1125ca632f55SGrant Likely { 1126ca632f55SGrant Likely struct davinci_spi *dspi; 1127ca632f55SGrant Likely struct spi_master *master; 1128ca632f55SGrant Likely 112924b5a82cSJingoo Han master = platform_get_drvdata(pdev); 1130ca632f55SGrant Likely dspi = spi_master_get_devdata(master); 1131ca632f55SGrant Likely 1132ca632f55SGrant Likely spi_bitbang_stop(&dspi->bitbang); 1133ca632f55SGrant Likely 1134aae7147dSMurali Karicheri clk_disable_unprepare(dspi->clk); 113594c69f76SAxel Lin spi_master_put(master); 1136ca632f55SGrant Likely 1137ca632f55SGrant Likely return 0; 1138ca632f55SGrant Likely } 1139ca632f55SGrant Likely 1140ca632f55SGrant Likely static struct platform_driver davinci_spi_driver = { 1141ca632f55SGrant Likely .driver = { 1142ca632f55SGrant Likely .name = "spi_davinci", 1143b53b34f0SAxel Lin .of_match_table = of_match_ptr(davinci_spi_of_match), 1144ca632f55SGrant Likely }, 1145940ab889SGrant Likely .probe = davinci_spi_probe, 1146fd4a319bSGrant Likely .remove = davinci_spi_remove, 1147ca632f55SGrant Likely }; 1148940ab889SGrant Likely module_platform_driver(davinci_spi_driver); 1149ca632f55SGrant Likely 1150ca632f55SGrant Likely MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); 1151ca632f55SGrant Likely MODULE_LICENSE("GPL"); 1152