1 /* 2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers 3 * 4 * the driver does not rely on the native chipselects at all 5 * but only uses the gpio type chipselects 6 * 7 * Based on: spi-bcm2835.c 8 * 9 * Copyright (C) 2015 Martin Sperl 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/completion.h> 24 #include <linux/delay.h> 25 #include <linux/err.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_device.h> 33 #include <linux/of_gpio.h> 34 #include <linux/of_irq.h> 35 #include <linux/regmap.h> 36 #include <linux/spi/spi.h> 37 #include <linux/spinlock.h> 38 39 /* 40 * spi register defines 41 * 42 * note there is garbage in the "official" documentation, 43 * so some data is taken from the file: 44 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h 45 * inside of: 46 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz 47 */ 48 49 /* SPI register offsets */ 50 #define BCM2835_AUX_SPI_CNTL0 0x00 51 #define BCM2835_AUX_SPI_CNTL1 0x04 52 #define BCM2835_AUX_SPI_STAT 0x08 53 #define BCM2835_AUX_SPI_PEEK 0x0C 54 #define BCM2835_AUX_SPI_IO 0x20 55 #define BCM2835_AUX_SPI_TXHOLD 0x30 56 57 /* Bitfields in CNTL0 */ 58 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 59 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF 60 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 61 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 62 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 63 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 64 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 65 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 66 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 67 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 68 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 69 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 70 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 71 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 72 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F 73 74 /* Bitfields in CNTL1 */ 75 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 76 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 77 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 78 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 79 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 80 81 /* Bitfields in STAT */ 82 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 83 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 84 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 85 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 86 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 87 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 88 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 89 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F 90 91 /* timeout values */ 92 #define BCM2835_AUX_SPI_POLLING_LIMIT_US 30 93 #define BCM2835_AUX_SPI_POLLING_JIFFIES 2 94 95 struct bcm2835aux_spi { 96 void __iomem *regs; 97 struct clk *clk; 98 int irq; 99 u32 cntl[2]; 100 const u8 *tx_buf; 101 u8 *rx_buf; 102 int tx_len; 103 int rx_len; 104 int pending; 105 }; 106 107 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) 108 { 109 return readl(bs->regs + reg); 110 } 111 112 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, 113 u32 val) 114 { 115 writel(val, bs->regs + reg); 116 } 117 118 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) 119 { 120 u32 data; 121 int count = min(bs->rx_len, 3); 122 123 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); 124 if (bs->rx_buf) { 125 switch (count) { 126 case 3: 127 *bs->rx_buf++ = (data >> 16) & 0xff; 128 /* fallthrough */ 129 case 2: 130 *bs->rx_buf++ = (data >> 8) & 0xff; 131 /* fallthrough */ 132 case 1: 133 *bs->rx_buf++ = (data >> 0) & 0xff; 134 /* fallthrough - no default */ 135 } 136 } 137 bs->rx_len -= count; 138 bs->pending -= count; 139 } 140 141 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) 142 { 143 u32 data; 144 u8 byte; 145 int count; 146 int i; 147 148 /* gather up to 3 bytes to write to the FIFO */ 149 count = min(bs->tx_len, 3); 150 data = 0; 151 for (i = 0; i < count; i++) { 152 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 153 data |= byte << (8 * (2 - i)); 154 } 155 156 /* and set the variable bit-length */ 157 data |= (count * 8) << 24; 158 159 /* and decrement length */ 160 bs->tx_len -= count; 161 bs->pending += count; 162 163 /* write to the correct TX-register */ 164 if (bs->tx_len) 165 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); 166 else 167 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); 168 } 169 170 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) 171 { 172 /* disable spi clearing fifo and interrupts */ 173 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); 174 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, 175 BCM2835_AUX_SPI_CNTL0_CLEARFIFO); 176 } 177 178 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) 179 { 180 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); 181 182 /* check if we have data to read */ 183 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL); 184 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT)) 185 bcm2835aux_rd_fifo(bs); 186 187 /* check if we have data to write */ 188 while (bs->tx_len && 189 (bs->pending < 12) && 190 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 191 BCM2835_AUX_SPI_STAT_TX_FULL))) { 192 bcm2835aux_wr_fifo(bs); 193 } 194 } 195 196 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) 197 { 198 struct spi_master *master = dev_id; 199 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 200 201 /* IRQ may be shared, so return if our interrupts are disabled */ 202 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & 203 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) 204 return IRQ_NONE; 205 206 /* do common fifo handling */ 207 bcm2835aux_spi_transfer_helper(bs); 208 209 if (!bs->tx_len) { 210 /* disable tx fifo empty interrupt */ 211 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 212 BCM2835_AUX_SPI_CNTL1_IDLE); 213 } 214 215 /* and if rx_len is 0 then disable interrupts and wake up completion */ 216 if (!bs->rx_len) { 217 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 218 complete(&master->xfer_completion); 219 } 220 221 return IRQ_HANDLED; 222 } 223 224 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 225 struct spi_device *spi, 226 struct spi_transfer *tfr) 227 { 228 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 229 230 /* enable interrupts */ 231 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 232 BCM2835_AUX_SPI_CNTL1_TXEMPTY | 233 BCM2835_AUX_SPI_CNTL1_IDLE); 234 235 /* and wait for finish... */ 236 return 1; 237 } 238 239 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 240 struct spi_device *spi, 241 struct spi_transfer *tfr) 242 { 243 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 244 245 /* fill in registers and fifos before enabling interrupts */ 246 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 247 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 248 249 /* fill in tx fifo with data before enabling interrupts */ 250 while ((bs->tx_len) && 251 (bs->pending < 12) && 252 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 253 BCM2835_AUX_SPI_STAT_TX_FULL))) { 254 bcm2835aux_wr_fifo(bs); 255 } 256 257 /* now run the interrupt mode */ 258 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 259 } 260 261 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, 262 struct spi_device *spi, 263 struct spi_transfer *tfr) 264 { 265 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 266 unsigned long timeout; 267 268 /* configure spi */ 269 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 270 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 271 272 /* set the timeout */ 273 timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES; 274 275 /* loop until finished the transfer */ 276 while (bs->rx_len) { 277 278 /* do common fifo handling */ 279 bcm2835aux_spi_transfer_helper(bs); 280 281 /* there is still data pending to read check the timeout */ 282 if (bs->rx_len && time_after(jiffies, timeout)) { 283 dev_dbg_ratelimited(&spi->dev, 284 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 285 jiffies - timeout, 286 bs->tx_len, bs->rx_len); 287 /* forward to interrupt handler */ 288 return __bcm2835aux_spi_transfer_one_irq(master, 289 spi, tfr); 290 } 291 } 292 293 /* and return without waiting for completion */ 294 return 0; 295 } 296 297 static int bcm2835aux_spi_transfer_one(struct spi_master *master, 298 struct spi_device *spi, 299 struct spi_transfer *tfr) 300 { 301 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 302 unsigned long spi_hz, clk_hz, speed; 303 unsigned long spi_used_hz; 304 305 /* calculate the registers to handle 306 * 307 * note that we use the variable data mode, which 308 * is not optimal for longer transfers as we waste registers 309 * resulting (potentially) in more interrupts when transferring 310 * more than 12 bytes 311 */ 312 313 /* set clock */ 314 spi_hz = tfr->speed_hz; 315 clk_hz = clk_get_rate(bs->clk); 316 317 if (spi_hz >= clk_hz / 2) { 318 speed = 0; 319 } else if (spi_hz) { 320 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; 321 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) 322 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 323 } else { /* the slowest we can go */ 324 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 325 } 326 /* mask out old speed from previous spi_transfer */ 327 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); 328 /* set the new speed */ 329 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; 330 331 spi_used_hz = clk_hz / (2 * (speed + 1)); 332 333 /* set transmit buffers and length */ 334 bs->tx_buf = tfr->tx_buf; 335 bs->rx_buf = tfr->rx_buf; 336 bs->tx_len = tfr->len; 337 bs->rx_len = tfr->len; 338 bs->pending = 0; 339 340 /* Calculate the estimated time in us the transfer runs. Note that 341 * there are are 2 idle clocks cycles after each chunk getting 342 * transferred - in our case the chunk size is 3 bytes, so we 343 * approximate this by 9 cycles/byte. This is used to find the number 344 * of Hz per byte per polling limit. E.g., we can transfer 1 byte in 345 * 30 µs per 300,000 Hz of bus clock. 346 */ 347 #define HZ_PER_BYTE ((9 * 1000000) / BCM2835_AUX_SPI_POLLING_LIMIT_US) 348 /* run in polling mode for short transfers */ 349 if (tfr->len < spi_used_hz / HZ_PER_BYTE) 350 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); 351 352 /* run in interrupt mode for all others */ 353 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 354 #undef HZ_PER_BYTE 355 } 356 357 static int bcm2835aux_spi_prepare_message(struct spi_master *master, 358 struct spi_message *msg) 359 { 360 struct spi_device *spi = msg->spi; 361 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 362 363 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | 364 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | 365 BCM2835_AUX_SPI_CNTL0_MSBF_OUT; 366 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; 367 368 /* handle all the modes */ 369 if (spi->mode & SPI_CPOL) { 370 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; 371 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; 372 } else { 373 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; 374 } 375 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 376 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 377 378 return 0; 379 } 380 381 static int bcm2835aux_spi_unprepare_message(struct spi_master *master, 382 struct spi_message *msg) 383 { 384 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 385 386 bcm2835aux_spi_reset_hw(bs); 387 388 return 0; 389 } 390 391 static void bcm2835aux_spi_handle_err(struct spi_master *master, 392 struct spi_message *msg) 393 { 394 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 395 396 bcm2835aux_spi_reset_hw(bs); 397 } 398 399 static int bcm2835aux_spi_setup(struct spi_device *spi) 400 { 401 int ret; 402 403 /* sanity check for native cs */ 404 if (spi->mode & SPI_NO_CS) 405 return 0; 406 if (gpio_is_valid(spi->cs_gpio)) { 407 /* with gpio-cs set the GPIO to the correct level 408 * and as output (in case the dt has the gpio not configured 409 * as output but native cs) 410 */ 411 ret = gpio_direction_output(spi->cs_gpio, 412 (spi->mode & SPI_CS_HIGH) ? 0 : 1); 413 if (ret) 414 dev_err(&spi->dev, 415 "could not set gpio %i as output: %i\n", 416 spi->cs_gpio, ret); 417 418 return ret; 419 } 420 421 /* for dt-backwards compatibility: only support native on CS0 422 * known things not supported with broken native CS: 423 * * multiple chip-selects: cs0-cs2 are all 424 * simultaniously asserted whenever there is a transfer 425 * this even includes SPI_NO_CS 426 * * SPI_CS_HIGH: cs are always asserted low 427 * * cs_change: cs is deasserted after each spi_transfer 428 * * cs_delay_usec: cs is always deasserted one SCK cycle 429 * after the last transfer 430 * probably more... 431 */ 432 dev_warn(&spi->dev, 433 "Native CS is not supported - please configure cs-gpio in device-tree\n"); 434 435 if (spi->chip_select == 0) 436 return 0; 437 438 dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); 439 440 return -EINVAL; 441 } 442 443 static int bcm2835aux_spi_probe(struct platform_device *pdev) 444 { 445 struct spi_master *master; 446 struct bcm2835aux_spi *bs; 447 struct resource *res; 448 unsigned long clk_hz; 449 int err; 450 451 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 452 if (!master) { 453 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 454 return -ENOMEM; 455 } 456 457 platform_set_drvdata(pdev, master); 458 master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); 459 master->bits_per_word_mask = SPI_BPW_MASK(8); 460 /* even though the driver never officially supported native CS 461 * allow a single native CS for legacy DT support purposes when 462 * no cs-gpio is configured. 463 * Known limitations for native cs are: 464 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted 465 * whenever there is a transfer - this even includes SPI_NO_CS 466 * * SPI_CS_HIGH: is ignores - cs are always asserted low 467 * * cs_change: cs is deasserted after each spi_transfer 468 * * cs_delay_usec: cs is always deasserted one SCK cycle after 469 * a spi_transfer 470 */ 471 master->num_chipselect = 1; 472 master->setup = bcm2835aux_spi_setup; 473 master->transfer_one = bcm2835aux_spi_transfer_one; 474 master->handle_err = bcm2835aux_spi_handle_err; 475 master->prepare_message = bcm2835aux_spi_prepare_message; 476 master->unprepare_message = bcm2835aux_spi_unprepare_message; 477 master->dev.of_node = pdev->dev.of_node; 478 479 bs = spi_master_get_devdata(master); 480 481 /* the main area */ 482 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 483 bs->regs = devm_ioremap_resource(&pdev->dev, res); 484 if (IS_ERR(bs->regs)) { 485 err = PTR_ERR(bs->regs); 486 goto out_master_put; 487 } 488 489 bs->clk = devm_clk_get(&pdev->dev, NULL); 490 if (IS_ERR(bs->clk)) { 491 err = PTR_ERR(bs->clk); 492 dev_err(&pdev->dev, "could not get clk: %d\n", err); 493 goto out_master_put; 494 } 495 496 bs->irq = platform_get_irq(pdev, 0); 497 if (bs->irq <= 0) { 498 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 499 err = bs->irq ? bs->irq : -ENODEV; 500 goto out_master_put; 501 } 502 503 /* this also enables the HW block */ 504 err = clk_prepare_enable(bs->clk); 505 if (err) { 506 dev_err(&pdev->dev, "could not prepare clock: %d\n", err); 507 goto out_master_put; 508 } 509 510 /* just checking if the clock returns a sane value */ 511 clk_hz = clk_get_rate(bs->clk); 512 if (!clk_hz) { 513 dev_err(&pdev->dev, "clock returns 0 Hz\n"); 514 err = -ENODEV; 515 goto out_clk_disable; 516 } 517 518 /* reset SPI-HW block */ 519 bcm2835aux_spi_reset_hw(bs); 520 521 err = devm_request_irq(&pdev->dev, bs->irq, 522 bcm2835aux_spi_interrupt, 523 IRQF_SHARED, 524 dev_name(&pdev->dev), master); 525 if (err) { 526 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 527 goto out_clk_disable; 528 } 529 530 err = devm_spi_register_master(&pdev->dev, master); 531 if (err) { 532 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 533 goto out_clk_disable; 534 } 535 536 return 0; 537 538 out_clk_disable: 539 clk_disable_unprepare(bs->clk); 540 out_master_put: 541 spi_master_put(master); 542 return err; 543 } 544 545 static int bcm2835aux_spi_remove(struct platform_device *pdev) 546 { 547 struct spi_master *master = platform_get_drvdata(pdev); 548 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 549 550 bcm2835aux_spi_reset_hw(bs); 551 552 /* disable the HW block by releasing the clock */ 553 clk_disable_unprepare(bs->clk); 554 555 return 0; 556 } 557 558 static const struct of_device_id bcm2835aux_spi_match[] = { 559 { .compatible = "brcm,bcm2835-aux-spi", }, 560 {} 561 }; 562 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); 563 564 static struct platform_driver bcm2835aux_spi_driver = { 565 .driver = { 566 .name = "spi-bcm2835aux", 567 .of_match_table = bcm2835aux_spi_match, 568 }, 569 .probe = bcm2835aux_spi_probe, 570 .remove = bcm2835aux_spi_remove, 571 }; 572 module_platform_driver(bcm2835aux_spi_driver); 573 574 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); 575 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); 576 MODULE_LICENSE("GPL"); 577