1 /* 2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers 3 * 4 * the driver does not rely on the native chipselects at all 5 * but only uses the gpio type chipselects 6 * 7 * Based on: spi-bcm2835.c 8 * 9 * Copyright (C) 2015 Martin Sperl 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/completion.h> 24 #include <linux/debugfs.h> 25 #include <linux/delay.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/kernel.h> 30 #include <linux/module.h> 31 #include <linux/of.h> 32 #include <linux/of_address.h> 33 #include <linux/of_device.h> 34 #include <linux/of_gpio.h> 35 #include <linux/of_irq.h> 36 #include <linux/regmap.h> 37 #include <linux/spi/spi.h> 38 #include <linux/spinlock.h> 39 40 /* define polling limits */ 41 unsigned int polling_limit_us = 30; 42 module_param(polling_limit_us, uint, 0664); 43 MODULE_PARM_DESC(polling_limit_us, 44 "time in us to run a transfer in polling mode - if zero no polling is used\n"); 45 46 /* 47 * spi register defines 48 * 49 * note there is garbage in the "official" documentation, 50 * so some data is taken from the file: 51 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h 52 * inside of: 53 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz 54 */ 55 56 /* SPI register offsets */ 57 #define BCM2835_AUX_SPI_CNTL0 0x00 58 #define BCM2835_AUX_SPI_CNTL1 0x04 59 #define BCM2835_AUX_SPI_STAT 0x08 60 #define BCM2835_AUX_SPI_PEEK 0x0C 61 #define BCM2835_AUX_SPI_IO 0x20 62 #define BCM2835_AUX_SPI_TXHOLD 0x30 63 64 /* Bitfields in CNTL0 */ 65 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 66 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF 67 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 68 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 69 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 70 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 71 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 72 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 73 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 74 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 75 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 76 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 77 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 78 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 79 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F 80 81 /* Bitfields in CNTL1 */ 82 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 83 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 84 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 85 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 86 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 87 88 /* Bitfields in STAT */ 89 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 90 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 91 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 92 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 93 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 94 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 95 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 96 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F 97 98 struct bcm2835aux_spi { 99 void __iomem *regs; 100 struct clk *clk; 101 int irq; 102 u32 cntl[2]; 103 const u8 *tx_buf; 104 u8 *rx_buf; 105 int tx_len; 106 int rx_len; 107 int pending; 108 109 u64 count_transfer_polling; 110 u64 count_transfer_irq; 111 u64 count_transfer_irq_after_poll; 112 113 struct dentry *debugfs_dir; 114 }; 115 116 #if defined(CONFIG_DEBUG_FS) 117 static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, 118 const char *dname) 119 { 120 char name[64]; 121 struct dentry *dir; 122 123 /* get full name */ 124 snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); 125 126 /* the base directory */ 127 dir = debugfs_create_dir(name, NULL); 128 bs->debugfs_dir = dir; 129 130 /* the counters */ 131 debugfs_create_u64("count_transfer_polling", 0444, dir, 132 &bs->count_transfer_polling); 133 debugfs_create_u64("count_transfer_irq", 0444, dir, 134 &bs->count_transfer_irq); 135 debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir, 136 &bs->count_transfer_irq_after_poll); 137 } 138 139 static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) 140 { 141 debugfs_remove_recursive(bs->debugfs_dir); 142 bs->debugfs_dir = NULL; 143 } 144 #else 145 static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs) 146 { 147 } 148 149 static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) 150 { 151 } 152 #endif /* CONFIG_DEBUG_FS */ 153 154 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) 155 { 156 return readl(bs->regs + reg); 157 } 158 159 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, 160 u32 val) 161 { 162 writel(val, bs->regs + reg); 163 } 164 165 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) 166 { 167 u32 data; 168 int count = min(bs->rx_len, 3); 169 170 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); 171 if (bs->rx_buf) { 172 switch (count) { 173 case 3: 174 *bs->rx_buf++ = (data >> 16) & 0xff; 175 /* fallthrough */ 176 case 2: 177 *bs->rx_buf++ = (data >> 8) & 0xff; 178 /* fallthrough */ 179 case 1: 180 *bs->rx_buf++ = (data >> 0) & 0xff; 181 /* fallthrough - no default */ 182 } 183 } 184 bs->rx_len -= count; 185 bs->pending -= count; 186 } 187 188 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) 189 { 190 u32 data; 191 u8 byte; 192 int count; 193 int i; 194 195 /* gather up to 3 bytes to write to the FIFO */ 196 count = min(bs->tx_len, 3); 197 data = 0; 198 for (i = 0; i < count; i++) { 199 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 200 data |= byte << (8 * (2 - i)); 201 } 202 203 /* and set the variable bit-length */ 204 data |= (count * 8) << 24; 205 206 /* and decrement length */ 207 bs->tx_len -= count; 208 bs->pending += count; 209 210 /* write to the correct TX-register */ 211 if (bs->tx_len) 212 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); 213 else 214 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); 215 } 216 217 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) 218 { 219 /* disable spi clearing fifo and interrupts */ 220 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); 221 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, 222 BCM2835_AUX_SPI_CNTL0_CLEARFIFO); 223 } 224 225 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) 226 { 227 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); 228 229 /* check if we have data to read */ 230 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL); 231 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT)) 232 bcm2835aux_rd_fifo(bs); 233 234 /* check if we have data to write */ 235 while (bs->tx_len && 236 (bs->pending < 12) && 237 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 238 BCM2835_AUX_SPI_STAT_TX_FULL))) { 239 bcm2835aux_wr_fifo(bs); 240 } 241 } 242 243 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) 244 { 245 struct spi_master *master = dev_id; 246 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 247 248 /* IRQ may be shared, so return if our interrupts are disabled */ 249 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & 250 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) 251 return IRQ_NONE; 252 253 /* do common fifo handling */ 254 bcm2835aux_spi_transfer_helper(bs); 255 256 if (!bs->tx_len) { 257 /* disable tx fifo empty interrupt */ 258 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 259 BCM2835_AUX_SPI_CNTL1_IDLE); 260 } 261 262 /* and if rx_len is 0 then disable interrupts and wake up completion */ 263 if (!bs->rx_len) { 264 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 265 complete(&master->xfer_completion); 266 } 267 268 return IRQ_HANDLED; 269 } 270 271 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 272 struct spi_device *spi, 273 struct spi_transfer *tfr) 274 { 275 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 276 277 /* enable interrupts */ 278 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 279 BCM2835_AUX_SPI_CNTL1_TXEMPTY | 280 BCM2835_AUX_SPI_CNTL1_IDLE); 281 282 /* and wait for finish... */ 283 return 1; 284 } 285 286 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 287 struct spi_device *spi, 288 struct spi_transfer *tfr) 289 { 290 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 291 292 /* update statistics */ 293 bs->count_transfer_irq++; 294 295 /* fill in registers and fifos before enabling interrupts */ 296 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 297 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 298 299 /* fill in tx fifo with data before enabling interrupts */ 300 while ((bs->tx_len) && 301 (bs->pending < 12) && 302 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 303 BCM2835_AUX_SPI_STAT_TX_FULL))) { 304 bcm2835aux_wr_fifo(bs); 305 } 306 307 /* now run the interrupt mode */ 308 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 309 } 310 311 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, 312 struct spi_device *spi, 313 struct spi_transfer *tfr) 314 { 315 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 316 unsigned long timeout; 317 318 /* update statistics */ 319 bs->count_transfer_polling++; 320 321 /* configure spi */ 322 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 323 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 324 325 /* set the timeout to at least 2 jiffies */ 326 timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; 327 328 /* loop until finished the transfer */ 329 while (bs->rx_len) { 330 331 /* do common fifo handling */ 332 bcm2835aux_spi_transfer_helper(bs); 333 334 /* there is still data pending to read check the timeout */ 335 if (bs->rx_len && time_after(jiffies, timeout)) { 336 dev_dbg_ratelimited(&spi->dev, 337 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 338 jiffies - timeout, 339 bs->tx_len, bs->rx_len); 340 /* forward to interrupt handler */ 341 bs->count_transfer_irq_after_poll++; 342 return __bcm2835aux_spi_transfer_one_irq(master, 343 spi, tfr); 344 } 345 } 346 347 /* and return without waiting for completion */ 348 return 0; 349 } 350 351 static int bcm2835aux_spi_transfer_one(struct spi_master *master, 352 struct spi_device *spi, 353 struct spi_transfer *tfr) 354 { 355 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 356 unsigned long spi_hz, clk_hz, speed, spi_used_hz; 357 unsigned long hz_per_byte, byte_limit; 358 359 /* calculate the registers to handle 360 * 361 * note that we use the variable data mode, which 362 * is not optimal for longer transfers as we waste registers 363 * resulting (potentially) in more interrupts when transferring 364 * more than 12 bytes 365 */ 366 367 /* set clock */ 368 spi_hz = tfr->speed_hz; 369 clk_hz = clk_get_rate(bs->clk); 370 371 if (spi_hz >= clk_hz / 2) { 372 speed = 0; 373 } else if (spi_hz) { 374 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; 375 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) 376 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 377 } else { /* the slowest we can go */ 378 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 379 } 380 /* mask out old speed from previous spi_transfer */ 381 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); 382 /* set the new speed */ 383 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; 384 385 spi_used_hz = clk_hz / (2 * (speed + 1)); 386 387 /* set transmit buffers and length */ 388 bs->tx_buf = tfr->tx_buf; 389 bs->rx_buf = tfr->rx_buf; 390 bs->tx_len = tfr->len; 391 bs->rx_len = tfr->len; 392 bs->pending = 0; 393 394 /* Calculate the estimated time in us the transfer runs. Note that 395 * there are are 2 idle clocks cycles after each chunk getting 396 * transferred - in our case the chunk size is 3 bytes, so we 397 * approximate this by 9 cycles/byte. This is used to find the number 398 * of Hz per byte per polling limit. E.g., we can transfer 1 byte in 399 * 30 µs per 300,000 Hz of bus clock. 400 */ 401 hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; 402 byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1; 403 404 /* run in polling mode for short transfers */ 405 if (tfr->len < byte_limit) 406 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); 407 408 /* run in interrupt mode for all others */ 409 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 410 } 411 412 static int bcm2835aux_spi_prepare_message(struct spi_master *master, 413 struct spi_message *msg) 414 { 415 struct spi_device *spi = msg->spi; 416 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 417 418 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | 419 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | 420 BCM2835_AUX_SPI_CNTL0_MSBF_OUT; 421 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; 422 423 /* handle all the modes */ 424 if (spi->mode & SPI_CPOL) { 425 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; 426 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; 427 } else { 428 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; 429 } 430 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 431 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 432 433 return 0; 434 } 435 436 static int bcm2835aux_spi_unprepare_message(struct spi_master *master, 437 struct spi_message *msg) 438 { 439 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 440 441 bcm2835aux_spi_reset_hw(bs); 442 443 return 0; 444 } 445 446 static void bcm2835aux_spi_handle_err(struct spi_master *master, 447 struct spi_message *msg) 448 { 449 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 450 451 bcm2835aux_spi_reset_hw(bs); 452 } 453 454 static int bcm2835aux_spi_setup(struct spi_device *spi) 455 { 456 int ret; 457 458 /* sanity check for native cs */ 459 if (spi->mode & SPI_NO_CS) 460 return 0; 461 if (gpio_is_valid(spi->cs_gpio)) { 462 /* with gpio-cs set the GPIO to the correct level 463 * and as output (in case the dt has the gpio not configured 464 * as output but native cs) 465 */ 466 ret = gpio_direction_output(spi->cs_gpio, 467 (spi->mode & SPI_CS_HIGH) ? 0 : 1); 468 if (ret) 469 dev_err(&spi->dev, 470 "could not set gpio %i as output: %i\n", 471 spi->cs_gpio, ret); 472 473 return ret; 474 } 475 476 /* for dt-backwards compatibility: only support native on CS0 477 * known things not supported with broken native CS: 478 * * multiple chip-selects: cs0-cs2 are all 479 * simultaniously asserted whenever there is a transfer 480 * this even includes SPI_NO_CS 481 * * SPI_CS_HIGH: cs are always asserted low 482 * * cs_change: cs is deasserted after each spi_transfer 483 * * cs_delay_usec: cs is always deasserted one SCK cycle 484 * after the last transfer 485 * probably more... 486 */ 487 dev_warn(&spi->dev, 488 "Native CS is not supported - please configure cs-gpio in device-tree\n"); 489 490 if (spi->chip_select == 0) 491 return 0; 492 493 dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); 494 495 return -EINVAL; 496 } 497 498 static int bcm2835aux_spi_probe(struct platform_device *pdev) 499 { 500 struct spi_master *master; 501 struct bcm2835aux_spi *bs; 502 struct resource *res; 503 unsigned long clk_hz; 504 int err; 505 506 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 507 if (!master) { 508 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 509 return -ENOMEM; 510 } 511 512 platform_set_drvdata(pdev, master); 513 master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); 514 master->bits_per_word_mask = SPI_BPW_MASK(8); 515 /* even though the driver never officially supported native CS 516 * allow a single native CS for legacy DT support purposes when 517 * no cs-gpio is configured. 518 * Known limitations for native cs are: 519 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted 520 * whenever there is a transfer - this even includes SPI_NO_CS 521 * * SPI_CS_HIGH: is ignores - cs are always asserted low 522 * * cs_change: cs is deasserted after each spi_transfer 523 * * cs_delay_usec: cs is always deasserted one SCK cycle after 524 * a spi_transfer 525 */ 526 master->num_chipselect = 1; 527 master->setup = bcm2835aux_spi_setup; 528 master->transfer_one = bcm2835aux_spi_transfer_one; 529 master->handle_err = bcm2835aux_spi_handle_err; 530 master->prepare_message = bcm2835aux_spi_prepare_message; 531 master->unprepare_message = bcm2835aux_spi_unprepare_message; 532 master->dev.of_node = pdev->dev.of_node; 533 534 bs = spi_master_get_devdata(master); 535 536 /* the main area */ 537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 538 bs->regs = devm_ioremap_resource(&pdev->dev, res); 539 if (IS_ERR(bs->regs)) { 540 err = PTR_ERR(bs->regs); 541 goto out_master_put; 542 } 543 544 bs->clk = devm_clk_get(&pdev->dev, NULL); 545 if (IS_ERR(bs->clk)) { 546 err = PTR_ERR(bs->clk); 547 dev_err(&pdev->dev, "could not get clk: %d\n", err); 548 goto out_master_put; 549 } 550 551 bs->irq = platform_get_irq(pdev, 0); 552 if (bs->irq <= 0) { 553 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 554 err = bs->irq ? bs->irq : -ENODEV; 555 goto out_master_put; 556 } 557 558 /* this also enables the HW block */ 559 err = clk_prepare_enable(bs->clk); 560 if (err) { 561 dev_err(&pdev->dev, "could not prepare clock: %d\n", err); 562 goto out_master_put; 563 } 564 565 /* just checking if the clock returns a sane value */ 566 clk_hz = clk_get_rate(bs->clk); 567 if (!clk_hz) { 568 dev_err(&pdev->dev, "clock returns 0 Hz\n"); 569 err = -ENODEV; 570 goto out_clk_disable; 571 } 572 573 /* reset SPI-HW block */ 574 bcm2835aux_spi_reset_hw(bs); 575 576 err = devm_request_irq(&pdev->dev, bs->irq, 577 bcm2835aux_spi_interrupt, 578 IRQF_SHARED, 579 dev_name(&pdev->dev), master); 580 if (err) { 581 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 582 goto out_clk_disable; 583 } 584 585 err = devm_spi_register_master(&pdev->dev, master); 586 if (err) { 587 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 588 goto out_clk_disable; 589 } 590 591 bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev)); 592 593 return 0; 594 595 out_clk_disable: 596 clk_disable_unprepare(bs->clk); 597 out_master_put: 598 spi_master_put(master); 599 return err; 600 } 601 602 static int bcm2835aux_spi_remove(struct platform_device *pdev) 603 { 604 struct spi_master *master = platform_get_drvdata(pdev); 605 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 606 607 bcm2835aux_debugfs_remove(bs); 608 609 bcm2835aux_spi_reset_hw(bs); 610 611 /* disable the HW block by releasing the clock */ 612 clk_disable_unprepare(bs->clk); 613 614 return 0; 615 } 616 617 static const struct of_device_id bcm2835aux_spi_match[] = { 618 { .compatible = "brcm,bcm2835-aux-spi", }, 619 {} 620 }; 621 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); 622 623 static struct platform_driver bcm2835aux_spi_driver = { 624 .driver = { 625 .name = "spi-bcm2835aux", 626 .of_match_table = bcm2835aux_spi_match, 627 }, 628 .probe = bcm2835aux_spi_probe, 629 .remove = bcm2835aux_spi_remove, 630 }; 631 module_platform_driver(bcm2835aux_spi_driver); 632 633 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); 634 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); 635 MODULE_LICENSE("GPL"); 636