1 /* 2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers 3 * 4 * the driver does not rely on the native chipselects at all 5 * but only uses the gpio type chipselects 6 * 7 * Based on: spi-bcm2835.c 8 * 9 * Copyright (C) 2015 Martin Sperl 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/completion.h> 24 #include <linux/delay.h> 25 #include <linux/err.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_device.h> 33 #include <linux/of_gpio.h> 34 #include <linux/of_irq.h> 35 #include <linux/regmap.h> 36 #include <linux/spi/spi.h> 37 #include <linux/spinlock.h> 38 39 /* 40 * spi register defines 41 * 42 * note there is garbage in the "official" documentation, 43 * so some data is taken from the file: 44 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h 45 * inside of: 46 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz 47 */ 48 49 /* SPI register offsets */ 50 #define BCM2835_AUX_SPI_CNTL0 0x00 51 #define BCM2835_AUX_SPI_CNTL1 0x04 52 #define BCM2835_AUX_SPI_STAT 0x08 53 #define BCM2835_AUX_SPI_PEEK 0x0C 54 #define BCM2835_AUX_SPI_IO 0x20 55 #define BCM2835_AUX_SPI_TXHOLD 0x30 56 57 /* Bitfields in CNTL0 */ 58 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 59 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF 60 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 61 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 62 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 63 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 64 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 65 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 66 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 67 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 68 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 69 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 70 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 71 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 72 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F 73 74 /* Bitfields in CNTL1 */ 75 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 76 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 77 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 78 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 79 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 80 81 /* Bitfields in STAT */ 82 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 83 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 84 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 85 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 86 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 87 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 88 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 89 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F 90 91 /* timeout values */ 92 #define BCM2835_AUX_SPI_POLLING_LIMIT_US 30 93 #define BCM2835_AUX_SPI_POLLING_JIFFIES 2 94 95 struct bcm2835aux_spi { 96 void __iomem *regs; 97 struct clk *clk; 98 int irq; 99 u32 cntl[2]; 100 const u8 *tx_buf; 101 u8 *rx_buf; 102 int tx_len; 103 int rx_len; 104 int pending; 105 }; 106 107 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) 108 { 109 return readl(bs->regs + reg); 110 } 111 112 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, 113 u32 val) 114 { 115 writel(val, bs->regs + reg); 116 } 117 118 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) 119 { 120 u32 data; 121 int count = min(bs->rx_len, 3); 122 123 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); 124 if (bs->rx_buf) { 125 switch (count) { 126 case 4: 127 *bs->rx_buf++ = (data >> 24) & 0xff; 128 /* fallthrough */ 129 case 3: 130 *bs->rx_buf++ = (data >> 16) & 0xff; 131 /* fallthrough */ 132 case 2: 133 *bs->rx_buf++ = (data >> 8) & 0xff; 134 /* fallthrough */ 135 case 1: 136 *bs->rx_buf++ = (data >> 0) & 0xff; 137 /* fallthrough - no default */ 138 } 139 } 140 bs->rx_len -= count; 141 bs->pending -= count; 142 } 143 144 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) 145 { 146 u32 data; 147 u8 byte; 148 int count; 149 int i; 150 151 /* gather up to 3 bytes to write to the FIFO */ 152 count = min(bs->tx_len, 3); 153 data = 0; 154 for (i = 0; i < count; i++) { 155 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 156 data |= byte << (8 * (2 - i)); 157 } 158 159 /* and set the variable bit-length */ 160 data |= (count * 8) << 24; 161 162 /* and decrement length */ 163 bs->tx_len -= count; 164 bs->pending += count; 165 166 /* write to the correct TX-register */ 167 if (bs->tx_len) 168 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); 169 else 170 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); 171 } 172 173 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) 174 { 175 /* disable spi clearing fifo and interrupts */ 176 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); 177 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, 178 BCM2835_AUX_SPI_CNTL0_CLEARFIFO); 179 } 180 181 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) 182 { 183 /* check if we have data to read */ 184 while (bs->rx_len && 185 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 186 BCM2835_AUX_SPI_STAT_RX_EMPTY))) { 187 bcm2835aux_rd_fifo(bs); 188 } 189 190 /* check if we have data to write */ 191 while (bs->tx_len && 192 (bs->pending < 12) && 193 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 194 BCM2835_AUX_SPI_STAT_TX_FULL))) { 195 bcm2835aux_wr_fifo(bs); 196 } 197 198 /* and check if we have reached "done" */ 199 while (bs->rx_len && 200 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 201 BCM2835_AUX_SPI_STAT_BUSY))) { 202 bcm2835aux_rd_fifo(bs); 203 } 204 } 205 206 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) 207 { 208 struct spi_master *master = dev_id; 209 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 210 211 /* IRQ may be shared, so return if our interrupts are disabled */ 212 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & 213 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) 214 return IRQ_NONE; 215 216 /* do common fifo handling */ 217 bcm2835aux_spi_transfer_helper(bs); 218 219 if (!bs->tx_len) { 220 /* disable tx fifo empty interrupt */ 221 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 222 BCM2835_AUX_SPI_CNTL1_IDLE); 223 } 224 225 /* and if rx_len is 0 then disable interrupts and wake up completion */ 226 if (!bs->rx_len) { 227 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 228 complete(&master->xfer_completion); 229 } 230 231 return IRQ_HANDLED; 232 } 233 234 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 235 struct spi_device *spi, 236 struct spi_transfer *tfr) 237 { 238 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 239 240 /* enable interrupts */ 241 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 242 BCM2835_AUX_SPI_CNTL1_TXEMPTY | 243 BCM2835_AUX_SPI_CNTL1_IDLE); 244 245 /* and wait for finish... */ 246 return 1; 247 } 248 249 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 250 struct spi_device *spi, 251 struct spi_transfer *tfr) 252 { 253 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 254 255 /* fill in registers and fifos before enabling interrupts */ 256 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 257 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 258 259 /* fill in tx fifo with data before enabling interrupts */ 260 while ((bs->tx_len) && 261 (bs->pending < 12) && 262 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 263 BCM2835_AUX_SPI_STAT_TX_FULL))) { 264 bcm2835aux_wr_fifo(bs); 265 } 266 267 /* now run the interrupt mode */ 268 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 269 } 270 271 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, 272 struct spi_device *spi, 273 struct spi_transfer *tfr) 274 { 275 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 276 unsigned long timeout; 277 278 /* configure spi */ 279 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 280 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 281 282 /* set the timeout */ 283 timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES; 284 285 /* loop until finished the transfer */ 286 while (bs->rx_len) { 287 288 /* do common fifo handling */ 289 bcm2835aux_spi_transfer_helper(bs); 290 291 /* there is still data pending to read check the timeout */ 292 if (bs->rx_len && time_after(jiffies, timeout)) { 293 dev_dbg_ratelimited(&spi->dev, 294 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 295 jiffies - timeout, 296 bs->tx_len, bs->rx_len); 297 /* forward to interrupt handler */ 298 return __bcm2835aux_spi_transfer_one_irq(master, 299 spi, tfr); 300 } 301 } 302 303 /* and return without waiting for completion */ 304 return 0; 305 } 306 307 static int bcm2835aux_spi_transfer_one(struct spi_master *master, 308 struct spi_device *spi, 309 struct spi_transfer *tfr) 310 { 311 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 312 unsigned long spi_hz, clk_hz, speed; 313 unsigned long spi_used_hz; 314 315 /* calculate the registers to handle 316 * 317 * note that we use the variable data mode, which 318 * is not optimal for longer transfers as we waste registers 319 * resulting (potentially) in more interrupts when transferring 320 * more than 12 bytes 321 */ 322 323 /* set clock */ 324 spi_hz = tfr->speed_hz; 325 clk_hz = clk_get_rate(bs->clk); 326 327 if (spi_hz >= clk_hz / 2) { 328 speed = 0; 329 } else if (spi_hz) { 330 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; 331 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) 332 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 333 } else { /* the slowest we can go */ 334 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 335 } 336 /* mask out old speed from previous spi_transfer */ 337 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); 338 /* set the new speed */ 339 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; 340 341 spi_used_hz = clk_hz / (2 * (speed + 1)); 342 343 /* set transmit buffers and length */ 344 bs->tx_buf = tfr->tx_buf; 345 bs->rx_buf = tfr->rx_buf; 346 bs->tx_len = tfr->len; 347 bs->rx_len = tfr->len; 348 bs->pending = 0; 349 350 /* Calculate the estimated time in us the transfer runs. Note that 351 * there are are 2 idle clocks cycles after each chunk getting 352 * transferred - in our case the chunk size is 3 bytes, so we 353 * approximate this by 9 cycles/byte. This is used to find the number 354 * of Hz per byte per polling limit. E.g., we can transfer 1 byte in 355 * 30 µs per 300,000 Hz of bus clock. 356 */ 357 #define HZ_PER_BYTE ((9 * 1000000) / BCM2835_AUX_SPI_POLLING_LIMIT_US) 358 /* run in polling mode for short transfers */ 359 if (tfr->len < spi_used_hz / HZ_PER_BYTE) 360 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); 361 362 /* run in interrupt mode for all others */ 363 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 364 #undef HZ_PER_BYTE 365 } 366 367 static int bcm2835aux_spi_prepare_message(struct spi_master *master, 368 struct spi_message *msg) 369 { 370 struct spi_device *spi = msg->spi; 371 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 372 373 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | 374 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | 375 BCM2835_AUX_SPI_CNTL0_MSBF_OUT; 376 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; 377 378 /* handle all the modes */ 379 if (spi->mode & SPI_CPOL) { 380 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; 381 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; 382 } else { 383 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; 384 } 385 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 386 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 387 388 return 0; 389 } 390 391 static int bcm2835aux_spi_unprepare_message(struct spi_master *master, 392 struct spi_message *msg) 393 { 394 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 395 396 bcm2835aux_spi_reset_hw(bs); 397 398 return 0; 399 } 400 401 static void bcm2835aux_spi_handle_err(struct spi_master *master, 402 struct spi_message *msg) 403 { 404 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 405 406 bcm2835aux_spi_reset_hw(bs); 407 } 408 409 static int bcm2835aux_spi_probe(struct platform_device *pdev) 410 { 411 struct spi_master *master; 412 struct bcm2835aux_spi *bs; 413 struct resource *res; 414 unsigned long clk_hz; 415 int err; 416 417 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 418 if (!master) { 419 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 420 return -ENOMEM; 421 } 422 423 platform_set_drvdata(pdev, master); 424 master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); 425 master->bits_per_word_mask = SPI_BPW_MASK(8); 426 master->num_chipselect = -1; 427 master->transfer_one = bcm2835aux_spi_transfer_one; 428 master->handle_err = bcm2835aux_spi_handle_err; 429 master->prepare_message = bcm2835aux_spi_prepare_message; 430 master->unprepare_message = bcm2835aux_spi_unprepare_message; 431 master->dev.of_node = pdev->dev.of_node; 432 433 bs = spi_master_get_devdata(master); 434 435 /* the main area */ 436 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 437 bs->regs = devm_ioremap_resource(&pdev->dev, res); 438 if (IS_ERR(bs->regs)) { 439 err = PTR_ERR(bs->regs); 440 goto out_master_put; 441 } 442 443 bs->clk = devm_clk_get(&pdev->dev, NULL); 444 if (IS_ERR(bs->clk)) { 445 err = PTR_ERR(bs->clk); 446 dev_err(&pdev->dev, "could not get clk: %d\n", err); 447 goto out_master_put; 448 } 449 450 bs->irq = platform_get_irq(pdev, 0); 451 if (bs->irq <= 0) { 452 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 453 err = bs->irq ? bs->irq : -ENODEV; 454 goto out_master_put; 455 } 456 457 /* this also enables the HW block */ 458 err = clk_prepare_enable(bs->clk); 459 if (err) { 460 dev_err(&pdev->dev, "could not prepare clock: %d\n", err); 461 goto out_master_put; 462 } 463 464 /* just checking if the clock returns a sane value */ 465 clk_hz = clk_get_rate(bs->clk); 466 if (!clk_hz) { 467 dev_err(&pdev->dev, "clock returns 0 Hz\n"); 468 err = -ENODEV; 469 goto out_clk_disable; 470 } 471 472 /* reset SPI-HW block */ 473 bcm2835aux_spi_reset_hw(bs); 474 475 err = devm_request_irq(&pdev->dev, bs->irq, 476 bcm2835aux_spi_interrupt, 477 IRQF_SHARED, 478 dev_name(&pdev->dev), master); 479 if (err) { 480 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 481 goto out_clk_disable; 482 } 483 484 err = devm_spi_register_master(&pdev->dev, master); 485 if (err) { 486 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 487 goto out_clk_disable; 488 } 489 490 return 0; 491 492 out_clk_disable: 493 clk_disable_unprepare(bs->clk); 494 out_master_put: 495 spi_master_put(master); 496 return err; 497 } 498 499 static int bcm2835aux_spi_remove(struct platform_device *pdev) 500 { 501 struct spi_master *master = platform_get_drvdata(pdev); 502 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 503 504 bcm2835aux_spi_reset_hw(bs); 505 506 /* disable the HW block by releasing the clock */ 507 clk_disable_unprepare(bs->clk); 508 509 return 0; 510 } 511 512 static const struct of_device_id bcm2835aux_spi_match[] = { 513 { .compatible = "brcm,bcm2835-aux-spi", }, 514 {} 515 }; 516 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); 517 518 static struct platform_driver bcm2835aux_spi_driver = { 519 .driver = { 520 .name = "spi-bcm2835aux", 521 .of_match_table = bcm2835aux_spi_match, 522 }, 523 .probe = bcm2835aux_spi_probe, 524 .remove = bcm2835aux_spi_remove, 525 }; 526 module_platform_driver(bcm2835aux_spi_driver); 527 528 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); 529 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); 530 MODULE_LICENSE("GPL"); 531