1 /* 2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers 3 * 4 * the driver does not rely on the native chipselects at all 5 * but only uses the gpio type chipselects 6 * 7 * Based on: spi-bcm2835.c 8 * 9 * Copyright (C) 2015 Martin Sperl 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/completion.h> 24 #include <linux/delay.h> 25 #include <linux/err.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_device.h> 33 #include <linux/of_gpio.h> 34 #include <linux/of_irq.h> 35 #include <linux/regmap.h> 36 #include <linux/spi/spi.h> 37 #include <linux/spinlock.h> 38 39 /* define polling limits */ 40 unsigned int polling_limit_us = 30; 41 module_param(polling_limit_us, uint, 0664); 42 MODULE_PARM_DESC(polling_limit_us, 43 "time in us to run a transfer in polling mode - if zero no polling is used\n"); 44 45 /* 46 * spi register defines 47 * 48 * note there is garbage in the "official" documentation, 49 * so some data is taken from the file: 50 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h 51 * inside of: 52 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz 53 */ 54 55 /* SPI register offsets */ 56 #define BCM2835_AUX_SPI_CNTL0 0x00 57 #define BCM2835_AUX_SPI_CNTL1 0x04 58 #define BCM2835_AUX_SPI_STAT 0x08 59 #define BCM2835_AUX_SPI_PEEK 0x0C 60 #define BCM2835_AUX_SPI_IO 0x20 61 #define BCM2835_AUX_SPI_TXHOLD 0x30 62 63 /* Bitfields in CNTL0 */ 64 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 65 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF 66 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 67 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 68 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 69 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 70 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 71 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 72 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 73 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 74 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 75 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 76 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 77 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 78 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F 79 80 /* Bitfields in CNTL1 */ 81 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 82 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 83 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 84 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 85 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 86 87 /* Bitfields in STAT */ 88 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 89 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 90 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 91 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 92 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 93 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 94 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 95 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F 96 97 struct bcm2835aux_spi { 98 void __iomem *regs; 99 struct clk *clk; 100 int irq; 101 u32 cntl[2]; 102 const u8 *tx_buf; 103 u8 *rx_buf; 104 int tx_len; 105 int rx_len; 106 int pending; 107 }; 108 109 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) 110 { 111 return readl(bs->regs + reg); 112 } 113 114 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, 115 u32 val) 116 { 117 writel(val, bs->regs + reg); 118 } 119 120 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) 121 { 122 u32 data; 123 int count = min(bs->rx_len, 3); 124 125 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); 126 if (bs->rx_buf) { 127 switch (count) { 128 case 3: 129 *bs->rx_buf++ = (data >> 16) & 0xff; 130 /* fallthrough */ 131 case 2: 132 *bs->rx_buf++ = (data >> 8) & 0xff; 133 /* fallthrough */ 134 case 1: 135 *bs->rx_buf++ = (data >> 0) & 0xff; 136 /* fallthrough - no default */ 137 } 138 } 139 bs->rx_len -= count; 140 bs->pending -= count; 141 } 142 143 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) 144 { 145 u32 data; 146 u8 byte; 147 int count; 148 int i; 149 150 /* gather up to 3 bytes to write to the FIFO */ 151 count = min(bs->tx_len, 3); 152 data = 0; 153 for (i = 0; i < count; i++) { 154 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 155 data |= byte << (8 * (2 - i)); 156 } 157 158 /* and set the variable bit-length */ 159 data |= (count * 8) << 24; 160 161 /* and decrement length */ 162 bs->tx_len -= count; 163 bs->pending += count; 164 165 /* write to the correct TX-register */ 166 if (bs->tx_len) 167 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); 168 else 169 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); 170 } 171 172 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) 173 { 174 /* disable spi clearing fifo and interrupts */ 175 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); 176 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, 177 BCM2835_AUX_SPI_CNTL0_CLEARFIFO); 178 } 179 180 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) 181 { 182 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); 183 184 /* check if we have data to read */ 185 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL); 186 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT)) 187 bcm2835aux_rd_fifo(bs); 188 189 /* check if we have data to write */ 190 while (bs->tx_len && 191 (bs->pending < 12) && 192 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 193 BCM2835_AUX_SPI_STAT_TX_FULL))) { 194 bcm2835aux_wr_fifo(bs); 195 } 196 } 197 198 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) 199 { 200 struct spi_master *master = dev_id; 201 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 202 203 /* IRQ may be shared, so return if our interrupts are disabled */ 204 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & 205 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) 206 return IRQ_NONE; 207 208 /* do common fifo handling */ 209 bcm2835aux_spi_transfer_helper(bs); 210 211 if (!bs->tx_len) { 212 /* disable tx fifo empty interrupt */ 213 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 214 BCM2835_AUX_SPI_CNTL1_IDLE); 215 } 216 217 /* and if rx_len is 0 then disable interrupts and wake up completion */ 218 if (!bs->rx_len) { 219 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 220 complete(&master->xfer_completion); 221 } 222 223 return IRQ_HANDLED; 224 } 225 226 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 227 struct spi_device *spi, 228 struct spi_transfer *tfr) 229 { 230 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 231 232 /* enable interrupts */ 233 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | 234 BCM2835_AUX_SPI_CNTL1_TXEMPTY | 235 BCM2835_AUX_SPI_CNTL1_IDLE); 236 237 /* and wait for finish... */ 238 return 1; 239 } 240 241 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, 242 struct spi_device *spi, 243 struct spi_transfer *tfr) 244 { 245 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 246 247 /* fill in registers and fifos before enabling interrupts */ 248 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 249 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 250 251 /* fill in tx fifo with data before enabling interrupts */ 252 while ((bs->tx_len) && 253 (bs->pending < 12) && 254 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & 255 BCM2835_AUX_SPI_STAT_TX_FULL))) { 256 bcm2835aux_wr_fifo(bs); 257 } 258 259 /* now run the interrupt mode */ 260 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 261 } 262 263 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, 264 struct spi_device *spi, 265 struct spi_transfer *tfr) 266 { 267 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 268 unsigned long timeout; 269 270 /* configure spi */ 271 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 272 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 273 274 /* set the timeout to at least 2 jiffies */ 275 timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; 276 277 /* loop until finished the transfer */ 278 while (bs->rx_len) { 279 280 /* do common fifo handling */ 281 bcm2835aux_spi_transfer_helper(bs); 282 283 /* there is still data pending to read check the timeout */ 284 if (bs->rx_len && time_after(jiffies, timeout)) { 285 dev_dbg_ratelimited(&spi->dev, 286 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 287 jiffies - timeout, 288 bs->tx_len, bs->rx_len); 289 /* forward to interrupt handler */ 290 return __bcm2835aux_spi_transfer_one_irq(master, 291 spi, tfr); 292 } 293 } 294 295 /* and return without waiting for completion */ 296 return 0; 297 } 298 299 static int bcm2835aux_spi_transfer_one(struct spi_master *master, 300 struct spi_device *spi, 301 struct spi_transfer *tfr) 302 { 303 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 304 unsigned long spi_hz, clk_hz, speed, spi_used_hz; 305 unsigned long hz_per_byte, byte_limit; 306 307 /* calculate the registers to handle 308 * 309 * note that we use the variable data mode, which 310 * is not optimal for longer transfers as we waste registers 311 * resulting (potentially) in more interrupts when transferring 312 * more than 12 bytes 313 */ 314 315 /* set clock */ 316 spi_hz = tfr->speed_hz; 317 clk_hz = clk_get_rate(bs->clk); 318 319 if (spi_hz >= clk_hz / 2) { 320 speed = 0; 321 } else if (spi_hz) { 322 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; 323 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) 324 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 325 } else { /* the slowest we can go */ 326 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; 327 } 328 /* mask out old speed from previous spi_transfer */ 329 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); 330 /* set the new speed */ 331 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; 332 333 spi_used_hz = clk_hz / (2 * (speed + 1)); 334 335 /* set transmit buffers and length */ 336 bs->tx_buf = tfr->tx_buf; 337 bs->rx_buf = tfr->rx_buf; 338 bs->tx_len = tfr->len; 339 bs->rx_len = tfr->len; 340 bs->pending = 0; 341 342 /* Calculate the estimated time in us the transfer runs. Note that 343 * there are are 2 idle clocks cycles after each chunk getting 344 * transferred - in our case the chunk size is 3 bytes, so we 345 * approximate this by 9 cycles/byte. This is used to find the number 346 * of Hz per byte per polling limit. E.g., we can transfer 1 byte in 347 * 30 µs per 300,000 Hz of bus clock. 348 */ 349 hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; 350 byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1; 351 352 /* run in polling mode for short transfers */ 353 if (tfr->len < byte_limit) 354 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); 355 356 /* run in interrupt mode for all others */ 357 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); 358 } 359 360 static int bcm2835aux_spi_prepare_message(struct spi_master *master, 361 struct spi_message *msg) 362 { 363 struct spi_device *spi = msg->spi; 364 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 365 366 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | 367 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | 368 BCM2835_AUX_SPI_CNTL0_MSBF_OUT; 369 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; 370 371 /* handle all the modes */ 372 if (spi->mode & SPI_CPOL) { 373 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; 374 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; 375 } else { 376 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; 377 } 378 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); 379 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); 380 381 return 0; 382 } 383 384 static int bcm2835aux_spi_unprepare_message(struct spi_master *master, 385 struct spi_message *msg) 386 { 387 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 388 389 bcm2835aux_spi_reset_hw(bs); 390 391 return 0; 392 } 393 394 static void bcm2835aux_spi_handle_err(struct spi_master *master, 395 struct spi_message *msg) 396 { 397 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 398 399 bcm2835aux_spi_reset_hw(bs); 400 } 401 402 static int bcm2835aux_spi_setup(struct spi_device *spi) 403 { 404 int ret; 405 406 /* sanity check for native cs */ 407 if (spi->mode & SPI_NO_CS) 408 return 0; 409 if (gpio_is_valid(spi->cs_gpio)) { 410 /* with gpio-cs set the GPIO to the correct level 411 * and as output (in case the dt has the gpio not configured 412 * as output but native cs) 413 */ 414 ret = gpio_direction_output(spi->cs_gpio, 415 (spi->mode & SPI_CS_HIGH) ? 0 : 1); 416 if (ret) 417 dev_err(&spi->dev, 418 "could not set gpio %i as output: %i\n", 419 spi->cs_gpio, ret); 420 421 return ret; 422 } 423 424 /* for dt-backwards compatibility: only support native on CS0 425 * known things not supported with broken native CS: 426 * * multiple chip-selects: cs0-cs2 are all 427 * simultaniously asserted whenever there is a transfer 428 * this even includes SPI_NO_CS 429 * * SPI_CS_HIGH: cs are always asserted low 430 * * cs_change: cs is deasserted after each spi_transfer 431 * * cs_delay_usec: cs is always deasserted one SCK cycle 432 * after the last transfer 433 * probably more... 434 */ 435 dev_warn(&spi->dev, 436 "Native CS is not supported - please configure cs-gpio in device-tree\n"); 437 438 if (spi->chip_select == 0) 439 return 0; 440 441 dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); 442 443 return -EINVAL; 444 } 445 446 static int bcm2835aux_spi_probe(struct platform_device *pdev) 447 { 448 struct spi_master *master; 449 struct bcm2835aux_spi *bs; 450 struct resource *res; 451 unsigned long clk_hz; 452 int err; 453 454 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 455 if (!master) { 456 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 457 return -ENOMEM; 458 } 459 460 platform_set_drvdata(pdev, master); 461 master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); 462 master->bits_per_word_mask = SPI_BPW_MASK(8); 463 /* even though the driver never officially supported native CS 464 * allow a single native CS for legacy DT support purposes when 465 * no cs-gpio is configured. 466 * Known limitations for native cs are: 467 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted 468 * whenever there is a transfer - this even includes SPI_NO_CS 469 * * SPI_CS_HIGH: is ignores - cs are always asserted low 470 * * cs_change: cs is deasserted after each spi_transfer 471 * * cs_delay_usec: cs is always deasserted one SCK cycle after 472 * a spi_transfer 473 */ 474 master->num_chipselect = 1; 475 master->setup = bcm2835aux_spi_setup; 476 master->transfer_one = bcm2835aux_spi_transfer_one; 477 master->handle_err = bcm2835aux_spi_handle_err; 478 master->prepare_message = bcm2835aux_spi_prepare_message; 479 master->unprepare_message = bcm2835aux_spi_unprepare_message; 480 master->dev.of_node = pdev->dev.of_node; 481 482 bs = spi_master_get_devdata(master); 483 484 /* the main area */ 485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 486 bs->regs = devm_ioremap_resource(&pdev->dev, res); 487 if (IS_ERR(bs->regs)) { 488 err = PTR_ERR(bs->regs); 489 goto out_master_put; 490 } 491 492 bs->clk = devm_clk_get(&pdev->dev, NULL); 493 if (IS_ERR(bs->clk)) { 494 err = PTR_ERR(bs->clk); 495 dev_err(&pdev->dev, "could not get clk: %d\n", err); 496 goto out_master_put; 497 } 498 499 bs->irq = platform_get_irq(pdev, 0); 500 if (bs->irq <= 0) { 501 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 502 err = bs->irq ? bs->irq : -ENODEV; 503 goto out_master_put; 504 } 505 506 /* this also enables the HW block */ 507 err = clk_prepare_enable(bs->clk); 508 if (err) { 509 dev_err(&pdev->dev, "could not prepare clock: %d\n", err); 510 goto out_master_put; 511 } 512 513 /* just checking if the clock returns a sane value */ 514 clk_hz = clk_get_rate(bs->clk); 515 if (!clk_hz) { 516 dev_err(&pdev->dev, "clock returns 0 Hz\n"); 517 err = -ENODEV; 518 goto out_clk_disable; 519 } 520 521 /* reset SPI-HW block */ 522 bcm2835aux_spi_reset_hw(bs); 523 524 err = devm_request_irq(&pdev->dev, bs->irq, 525 bcm2835aux_spi_interrupt, 526 IRQF_SHARED, 527 dev_name(&pdev->dev), master); 528 if (err) { 529 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 530 goto out_clk_disable; 531 } 532 533 err = devm_spi_register_master(&pdev->dev, master); 534 if (err) { 535 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 536 goto out_clk_disable; 537 } 538 539 return 0; 540 541 out_clk_disable: 542 clk_disable_unprepare(bs->clk); 543 out_master_put: 544 spi_master_put(master); 545 return err; 546 } 547 548 static int bcm2835aux_spi_remove(struct platform_device *pdev) 549 { 550 struct spi_master *master = platform_get_drvdata(pdev); 551 struct bcm2835aux_spi *bs = spi_master_get_devdata(master); 552 553 bcm2835aux_spi_reset_hw(bs); 554 555 /* disable the HW block by releasing the clock */ 556 clk_disable_unprepare(bs->clk); 557 558 return 0; 559 } 560 561 static const struct of_device_id bcm2835aux_spi_match[] = { 562 { .compatible = "brcm,bcm2835-aux-spi", }, 563 {} 564 }; 565 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); 566 567 static struct platform_driver bcm2835aux_spi_driver = { 568 .driver = { 569 .name = "spi-bcm2835aux", 570 .of_match_table = bcm2835aux_spi_match, 571 }, 572 .probe = bcm2835aux_spi_probe, 573 .remove = bcm2835aux_spi_remove, 574 }; 575 module_platform_driver(bcm2835aux_spi_driver); 576 577 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); 578 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); 579 MODULE_LICENSE("GPL"); 580