1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/device.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/soc/mediatek/mtk-mmsys.h> 12 13 #include "../../gpu/drm/mediatek/mtk_drm_ddp.h" 14 #include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" 15 16 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 17 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 18 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 19 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c 20 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 21 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 22 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 23 #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 24 #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 25 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac 26 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 27 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 28 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 29 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 30 31 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 32 #define DISP_REG_CONFIG_OUT_SEL 0x04c 33 #define DISP_REG_CONFIG_DSI_SEL 0x050 34 #define DISP_REG_CONFIG_DPI_SEL 0x064 35 36 #define OVL0_MOUT_EN_COLOR0 0x1 37 #define OD_MOUT_EN_RDMA0 0x1 38 #define OD1_MOUT_EN_RDMA1 BIT(16) 39 #define UFOE_MOUT_EN_DSI0 0x1 40 #define COLOR0_SEL_IN_OVL0 0x1 41 #define OVL1_MOUT_EN_COLOR1 0x1 42 #define GAMMA_MOUT_EN_RDMA1 0x1 43 #define RDMA0_SOUT_DPI0 0x2 44 #define RDMA0_SOUT_DPI1 0x3 45 #define RDMA0_SOUT_DSI1 0x1 46 #define RDMA0_SOUT_DSI2 0x4 47 #define RDMA0_SOUT_DSI3 0x5 48 #define RDMA1_SOUT_DPI0 0x2 49 #define RDMA1_SOUT_DPI1 0x3 50 #define RDMA1_SOUT_DSI1 0x1 51 #define RDMA1_SOUT_DSI2 0x4 52 #define RDMA1_SOUT_DSI3 0x5 53 #define RDMA2_SOUT_DPI0 0x2 54 #define RDMA2_SOUT_DPI1 0x3 55 #define RDMA2_SOUT_DSI1 0x1 56 #define RDMA2_SOUT_DSI2 0x4 57 #define RDMA2_SOUT_DSI3 0x5 58 #define DPI0_SEL_IN_RDMA1 0x1 59 #define DPI0_SEL_IN_RDMA2 0x3 60 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) 61 #define DPI1_SEL_IN_RDMA2 (0x3 << 8) 62 #define DSI0_SEL_IN_RDMA1 0x1 63 #define DSI0_SEL_IN_RDMA2 0x4 64 #define DSI1_SEL_IN_RDMA1 0x1 65 #define DSI1_SEL_IN_RDMA2 0x4 66 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) 67 #define DSI2_SEL_IN_RDMA2 (0x4 << 16) 68 #define DSI3_SEL_IN_RDMA1 (0x1 << 16) 69 #define DSI3_SEL_IN_RDMA2 (0x4 << 16) 70 #define COLOR1_SEL_IN_OVL1 0x1 71 72 #define OVL_MOUT_EN_RDMA 0x1 73 #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 74 #define BLS_TO_DPI_RDMA1_TO_DSI 0x2 75 #define DSI_SEL_IN_BLS 0x0 76 #define DPI_SEL_IN_BLS 0x0 77 #define DSI_SEL_IN_RDMA 0x1 78 79 struct mtk_mmsys_driver_data { 80 const char *clk_driver; 81 }; 82 83 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 84 .clk_driver = "clk-mt8173-mm", 85 }; 86 87 static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, 88 enum mtk_ddp_comp_id next, 89 unsigned int *addr) 90 { 91 unsigned int value; 92 93 if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { 94 *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; 95 value = OVL0_MOUT_EN_COLOR0; 96 } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { 97 *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; 98 value = OVL_MOUT_EN_RDMA; 99 } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { 100 *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; 101 value = OD_MOUT_EN_RDMA0; 102 } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { 103 *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; 104 value = UFOE_MOUT_EN_DSI0; 105 } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { 106 *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; 107 value = OVL1_MOUT_EN_COLOR1; 108 } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { 109 *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; 110 value = GAMMA_MOUT_EN_RDMA1; 111 } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { 112 *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; 113 value = OD1_MOUT_EN_RDMA1; 114 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { 115 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 116 value = RDMA0_SOUT_DPI0; 117 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { 118 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 119 value = RDMA0_SOUT_DPI1; 120 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { 121 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 122 value = RDMA0_SOUT_DSI1; 123 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { 124 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 125 value = RDMA0_SOUT_DSI2; 126 } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { 127 *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; 128 value = RDMA0_SOUT_DSI3; 129 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { 130 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; 131 value = RDMA1_SOUT_DSI1; 132 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { 133 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; 134 value = RDMA1_SOUT_DSI2; 135 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { 136 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; 137 value = RDMA1_SOUT_DSI3; 138 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { 139 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; 140 value = RDMA1_SOUT_DPI0; 141 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { 142 *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; 143 value = RDMA1_SOUT_DPI1; 144 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { 145 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; 146 value = RDMA2_SOUT_DPI0; 147 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { 148 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; 149 value = RDMA2_SOUT_DPI1; 150 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { 151 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; 152 value = RDMA2_SOUT_DSI1; 153 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { 154 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; 155 value = RDMA2_SOUT_DSI2; 156 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { 157 *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; 158 value = RDMA2_SOUT_DSI3; 159 } else { 160 value = 0; 161 } 162 163 return value; 164 } 165 166 static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, 167 enum mtk_ddp_comp_id next, 168 unsigned int *addr) 169 { 170 unsigned int value; 171 172 if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { 173 *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; 174 value = COLOR0_SEL_IN_OVL0; 175 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { 176 *addr = DISP_REG_CONFIG_DPI_SEL_IN; 177 value = DPI0_SEL_IN_RDMA1; 178 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { 179 *addr = DISP_REG_CONFIG_DPI_SEL_IN; 180 value = DPI1_SEL_IN_RDMA1; 181 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { 182 *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 183 value = DSI0_SEL_IN_RDMA1; 184 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { 185 *addr = DISP_REG_CONFIG_DSIO_SEL_IN; 186 value = DSI1_SEL_IN_RDMA1; 187 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { 188 *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 189 value = DSI2_SEL_IN_RDMA1; 190 } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { 191 *addr = DISP_REG_CONFIG_DSIO_SEL_IN; 192 value = DSI3_SEL_IN_RDMA1; 193 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { 194 *addr = DISP_REG_CONFIG_DPI_SEL_IN; 195 value = DPI0_SEL_IN_RDMA2; 196 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { 197 *addr = DISP_REG_CONFIG_DPI_SEL_IN; 198 value = DPI1_SEL_IN_RDMA2; 199 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { 200 *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 201 value = DSI0_SEL_IN_RDMA2; 202 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { 203 *addr = DISP_REG_CONFIG_DSIO_SEL_IN; 204 value = DSI1_SEL_IN_RDMA2; 205 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { 206 *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 207 value = DSI2_SEL_IN_RDMA2; 208 } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { 209 *addr = DISP_REG_CONFIG_DSIE_SEL_IN; 210 value = DSI3_SEL_IN_RDMA2; 211 } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { 212 *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; 213 value = COLOR1_SEL_IN_OVL1; 214 } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { 215 *addr = DISP_REG_CONFIG_DSI_SEL; 216 value = DSI_SEL_IN_BLS; 217 } else { 218 value = 0; 219 } 220 221 return value; 222 } 223 224 static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, 225 enum mtk_ddp_comp_id cur, 226 enum mtk_ddp_comp_id next) 227 { 228 if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { 229 writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, 230 config_regs + DISP_REG_CONFIG_OUT_SEL); 231 } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { 232 writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, 233 config_regs + DISP_REG_CONFIG_OUT_SEL); 234 writel_relaxed(DSI_SEL_IN_RDMA, 235 config_regs + DISP_REG_CONFIG_DSI_SEL); 236 writel_relaxed(DPI_SEL_IN_BLS, 237 config_regs + DISP_REG_CONFIG_DPI_SEL); 238 } 239 } 240 241 void mtk_mmsys_ddp_connect(struct device *dev, 242 enum mtk_ddp_comp_id cur, 243 enum mtk_ddp_comp_id next) 244 { 245 void __iomem *config_regs = dev_get_drvdata(dev); 246 unsigned int addr, value, reg; 247 248 value = mtk_mmsys_ddp_mout_en(cur, next, &addr); 249 if (value) { 250 reg = readl_relaxed(config_regs + addr) | value; 251 writel_relaxed(reg, config_regs + addr); 252 } 253 254 mtk_mmsys_ddp_sout_sel(config_regs, cur, next); 255 256 value = mtk_mmsys_ddp_sel_in(cur, next, &addr); 257 if (value) { 258 reg = readl_relaxed(config_regs + addr) | value; 259 writel_relaxed(reg, config_regs + addr); 260 } 261 } 262 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); 263 264 void mtk_mmsys_ddp_disconnect(struct device *dev, 265 enum mtk_ddp_comp_id cur, 266 enum mtk_ddp_comp_id next) 267 { 268 void __iomem *config_regs = dev_get_drvdata(dev); 269 unsigned int addr, value, reg; 270 271 value = mtk_mmsys_ddp_mout_en(cur, next, &addr); 272 if (value) { 273 reg = readl_relaxed(config_regs + addr) & ~value; 274 writel_relaxed(reg, config_regs + addr); 275 } 276 277 value = mtk_mmsys_ddp_sel_in(cur, next, &addr); 278 if (value) { 279 reg = readl_relaxed(config_regs + addr) & ~value; 280 writel_relaxed(reg, config_regs + addr); 281 } 282 } 283 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); 284 285 static int mtk_mmsys_probe(struct platform_device *pdev) 286 { 287 const struct mtk_mmsys_driver_data *data; 288 struct device *dev = &pdev->dev; 289 struct platform_device *clks; 290 struct platform_device *drm; 291 void __iomem *config_regs; 292 struct resource *mem; 293 int ret; 294 295 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 296 config_regs = devm_ioremap_resource(dev, mem); 297 if (IS_ERR(config_regs)) { 298 ret = PTR_ERR(config_regs); 299 dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", 300 ret); 301 return ret; 302 } 303 304 platform_set_drvdata(pdev, config_regs); 305 306 data = of_device_get_match_data(&pdev->dev); 307 308 clks = platform_device_register_data(&pdev->dev, data->clk_driver, 309 PLATFORM_DEVID_AUTO, NULL, 0); 310 if (IS_ERR(clks)) 311 return PTR_ERR(clks); 312 313 drm = platform_device_register_data(&pdev->dev, "mediatek-drm", 314 PLATFORM_DEVID_AUTO, NULL, 0); 315 if (IS_ERR(drm)) 316 return PTR_ERR(drm); 317 318 return 0; 319 } 320 321 static const struct of_device_id of_match_mtk_mmsys[] = { 322 { 323 .compatible = "mediatek,mt8173-mmsys", 324 .data = &mt8173_mmsys_driver_data, 325 }, 326 { } 327 }; 328 329 static struct platform_driver mtk_mmsys_drv = { 330 .driver = { 331 .name = "mtk-mmsys", 332 .of_match_table = of_match_mtk_mmsys, 333 }, 334 .probe = mtk_mmsys_probe, 335 }; 336 337 builtin_platform_driver(mtk_mmsys_drv); 338