1b804923bSjason-jh.lin /* SPDX-License-Identifier: GPL-2.0-only */ 2b804923bSjason-jh.lin 3b804923bSjason-jh.lin #ifndef __SOC_MEDIATEK_MT8195_MMSYS_H 4b804923bSjason-jh.lin #define __SOC_MEDIATEK_MT8195_MMSYS_H 5b804923bSjason-jh.lin 6b804923bSjason-jh.lin #define MT8195_VDO0_OVL_MOUT_EN 0xf14 7b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) 9b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) 10b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) 11b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) 12b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) 13b804923bSjason-jh.lin 14b804923bSjason-jh.lin #define MT8195_VDO0_SEL_IN 0xf34 15b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) 16b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) 17b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) 18b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) 19b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) 20b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) 21b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) 22b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) 23b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) 24b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) 25b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) 26b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) 27b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) 28b804923bSjason-jh.lin #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) 29b804923bSjason-jh.lin #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) 30b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) 31b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) 32b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) 33b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) 34b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) 35b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) 36b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) 37b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) 38b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) 39b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) 40b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) 41b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) 42b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) 43b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) 44b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) 45b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) 46b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) 47b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) 48b804923bSjason-jh.lin 49b804923bSjason-jh.lin #define MT8195_VDO0_SEL_OUT 0xf38 50b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) 51b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) 52b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) 53b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) 54b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) 55b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) 56b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) 57b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) 58b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) 59b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) 60b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) 61b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) 62b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) 63b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) 64b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) 65b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) 66b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) 67b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) 68b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) 69b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) 70b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) 71b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) 72b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) 73b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) 74b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) 75b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) 76b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) 77b804923bSjason-jh.lin 787f0a38f4SNancy.Lin #define MT8195_VDO1_SW0_RST_B 0x1d0 793dd20b71SNancy.Lin #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 803dd20b71SNancy.Lin #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 813dd20b71SNancy.Lin #define MT8195_VDO1_HDR_TOP_CFG 0xd00 823dd20b71SNancy.Lin #define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 833dd20b71SNancy.Lin #define MT8195_VDO1_MIXER_IN1_PAD 0xd40 843dd20b71SNancy.Lin 8539170127SNancy.Lin #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 8639170127SNancy.Lin #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 8739170127SNancy.Lin 8839170127SNancy.Lin #define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 8939170127SNancy.Lin #define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 9039170127SNancy.Lin 9139170127SNancy.Lin #define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 9239170127SNancy.Lin #define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 9339170127SNancy.Lin 9439170127SNancy.Lin #define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 9539170127SNancy.Lin #define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 9639170127SNancy.Lin 9739170127SNancy.Lin #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 9839170127SNancy.Lin #define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2 9939170127SNancy.Lin #define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3 10039170127SNancy.Lin 10139170127SNancy.Lin #define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 10239170127SNancy.Lin #define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 10339170127SNancy.Lin 10439170127SNancy.Lin #define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 10539170127SNancy.Lin #define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 10639170127SNancy.Lin 10739170127SNancy.Lin #define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c 10839170127SNancy.Lin #define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 10939170127SNancy.Lin 11039170127SNancy.Lin #define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 11139170127SNancy.Lin #define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 11239170127SNancy.Lin 11339170127SNancy.Lin #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 11439170127SNancy.Lin #define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 11539170127SNancy.Lin 11639170127SNancy.Lin #define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c 11739170127SNancy.Lin #define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 11839170127SNancy.Lin 11939170127SNancy.Lin #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 12039170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN1_SEL 1 12139170127SNancy.Lin 12239170127SNancy.Lin #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 12339170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN2_SEL 1 12439170127SNancy.Lin 12539170127SNancy.Lin #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 12639170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN3_SEL 1 12739170127SNancy.Lin 12839170127SNancy.Lin #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c 12939170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN4_SEL 1 13039170127SNancy.Lin 13139170127SNancy.Lin #define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 13239170127SNancy.Lin #define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 13339170127SNancy.Lin 13439170127SNancy.Lin #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 13539170127SNancy.Lin #define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0 13639170127SNancy.Lin 13739170127SNancy.Lin #define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c 13839170127SNancy.Lin #define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0 13939170127SNancy.Lin 14039170127SNancy.Lin #define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 14139170127SNancy.Lin #define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0 14239170127SNancy.Lin 14339170127SNancy.Lin #define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 14439170127SNancy.Lin #define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0 14539170127SNancy.Lin 14639170127SNancy.Lin #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 14739170127SNancy.Lin #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 14839170127SNancy.Lin 149*dd4f373eSRoy-CW.Yeh /* VPPSYS1 */ 150*dd4f373eSRoy-CW.Yeh #define MT8195_VPP1_HW_DCM_1ST_DIS0 0x150 151*dd4f373eSRoy-CW.Yeh #define MT8195_VPP1_HW_DCM_1ST_DIS1 0x160 152*dd4f373eSRoy-CW.Yeh #define MT8195_VPP1_HW_DCM_2ND_DIS0 0x1a0 153*dd4f373eSRoy-CW.Yeh #define MT8195_VPP1_HW_DCM_2ND_DIS1 0x1b0 154*dd4f373eSRoy-CW.Yeh #define MT8195_SVPP2_BUF_BF_RSZ_SWITCH 0xf48 155*dd4f373eSRoy-CW.Yeh #define MT8195_SVPP3_BUF_BF_RSZ_SWITCH 0xf74 156*dd4f373eSRoy-CW.Yeh 157*dd4f373eSRoy-CW.Yeh /* VPPSYS1 HW DCM client*/ 158*dd4f373eSRoy-CW.Yeh #define MT8195_SVPP1_MDP_RSZ BIT(25) 159*dd4f373eSRoy-CW.Yeh #define MT8195_SVPP2_MDP_RSZ BIT(4) 160*dd4f373eSRoy-CW.Yeh #define MT8195_SVPP3_MDP_RSZ BIT(5) 161*dd4f373eSRoy-CW.Yeh 162b804923bSjason-jh.lin static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { 163b804923bSjason-jh.lin { 164b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 165b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, 166b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 167b804923bSjason-jh.lin }, { 168b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 169b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, 170b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 171b804923bSjason-jh.lin }, { 172b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, 173b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, 174b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 175b804923bSjason-jh.lin }, { 176b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, 177b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, 178b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 179b804923bSjason-jh.lin }, { 180b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 181b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, 182b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 183b804923bSjason-jh.lin }, { 184b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, 185b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, 186b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 187b804923bSjason-jh.lin }, { 188b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 189b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 190b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 191b804923bSjason-jh.lin }, { 192b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 193b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 194b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 195b804923bSjason-jh.lin }, { 196b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 197b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 198b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 199b804923bSjason-jh.lin }, { 2004e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 201b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 202b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 203b804923bSjason-jh.lin }, { 204b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 205b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 206b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE 207b804923bSjason-jh.lin }, { 208b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 209b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 210b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 211b804923bSjason-jh.lin }, { 212b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 213b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 214b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE 215b804923bSjason-jh.lin }, { 216b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 217b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 218b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 219b804923bSjason-jh.lin }, { 220b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 221b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 222b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 223b804923bSjason-jh.lin }, { 224b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 225b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 226b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 227b804923bSjason-jh.lin }, { 228b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 229b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 230b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 231b804923bSjason-jh.lin }, { 232b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 233b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 234b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 235b804923bSjason-jh.lin }, { 236b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 237b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 238b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 239b804923bSjason-jh.lin }, { 240b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 241b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 242b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 243b804923bSjason-jh.lin }, { 244b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 245b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 246b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 247b804923bSjason-jh.lin }, { 248b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 249b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 250b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 251b804923bSjason-jh.lin }, { 252b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 253b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 254b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT 255b804923bSjason-jh.lin }, { 256b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 257b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 258b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE 259b804923bSjason-jh.lin }, { 260b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 261b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 262b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 263b804923bSjason-jh.lin }, { 264b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 265b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 266b804923bSjason-jh.lin MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT 267b804923bSjason-jh.lin }, { 2684e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 269b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 270b804923bSjason-jh.lin MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 271b804923bSjason-jh.lin }, { 272b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 273b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 274b804923bSjason-jh.lin MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT 275b804923bSjason-jh.lin }, { 276b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 277b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 278b804923bSjason-jh.lin MT8195_SEL_IN_DSI1_FROM_VPP_MERGE 279b804923bSjason-jh.lin }, { 280b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 281b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 282b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 283b804923bSjason-jh.lin }, { 284b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 285b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 286b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE 287b804923bSjason-jh.lin }, { 288b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 289b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 290b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 291b804923bSjason-jh.lin }, { 292b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 293b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 294b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 295b804923bSjason-jh.lin }, { 296b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 297b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 298b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 299b804923bSjason-jh.lin }, { 300b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 301b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 302b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 303b804923bSjason-jh.lin }, { 304b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 305b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 306b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 307b804923bSjason-jh.lin }, { 308b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 309b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 310b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 311b804923bSjason-jh.lin }, { 312b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 313b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 314b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 315b804923bSjason-jh.lin }, { 316b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 317b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 318b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 319b804923bSjason-jh.lin }, { 320b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 321b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 322b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 323b804923bSjason-jh.lin }, { 324b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 325b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 326b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 327b804923bSjason-jh.lin }, { 328b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 329b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, 330b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 331b804923bSjason-jh.lin }, { 3324e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 333b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 334b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN 335b804923bSjason-jh.lin }, { 3364e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 337b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 338b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER0_TO_DSI0 339b804923bSjason-jh.lin }, { 340b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 341b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 342b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN 343b804923bSjason-jh.lin }, { 344b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 345b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 346b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE 347b804923bSjason-jh.lin }, { 348b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 349b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 350b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 351b804923bSjason-jh.lin }, { 352b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 353b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 354b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 355b804923bSjason-jh.lin }, { 356b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, 357b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 358b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 359b804923bSjason-jh.lin }, { 360b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 361b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 362b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 363b804923bSjason-jh.lin }, { 364b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 365b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 366b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 367b804923bSjason-jh.lin }, { 368b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 369b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 370b804923bSjason-jh.lin MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE 371b804923bSjason-jh.lin }, { 372b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 373b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 374b804923bSjason-jh.lin MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 375b804923bSjason-jh.lin }, { 376b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 377b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 378b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSI1 379b804923bSjason-jh.lin }, { 380b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 381b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 382b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 383b804923bSjason-jh.lin }, { 384b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 385b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 386b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 387b804923bSjason-jh.lin }, { 388b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 389b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 390b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 391b804923bSjason-jh.lin }, { 392b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 393b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 394b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 395b804923bSjason-jh.lin }, { 396b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 397b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 398b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 399b804923bSjason-jh.lin }, { 400b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 401b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 402b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN 403b804923bSjason-jh.lin }, { 404b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 405b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, 406b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN 407b804923bSjason-jh.lin }, { 408b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 409b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 410b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 411b804923bSjason-jh.lin }, { 412b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 413b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 414b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 415b804923bSjason-jh.lin }, { 416b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 417b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 418b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 419b804923bSjason-jh.lin }, { 420b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 421b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 422b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 423b804923bSjason-jh.lin }, { 424b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 425b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 426b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE 427b804923bSjason-jh.lin }, { 428b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 429b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 430b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 431b804923bSjason-jh.lin }, { 432b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 433b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 434b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 435b804923bSjason-jh.lin }, { 436b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 437b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 438b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 439b804923bSjason-jh.lin }, { 440b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 441b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 442b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 443b804923bSjason-jh.lin }, { 444b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 445b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 446b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 447b804923bSjason-jh.lin }, { 448b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 449b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 450b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE 451b804923bSjason-jh.lin } 452b804923bSjason-jh.lin }; 453b804923bSjason-jh.lin 45439170127SNancy.Lin static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = { 45539170127SNancy.Lin { 45639170127SNancy.Lin DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, 45739170127SNancy.Lin MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), 45839170127SNancy.Lin MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 45939170127SNancy.Lin }, { 46039170127SNancy.Lin DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, 46139170127SNancy.Lin MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), 46239170127SNancy.Lin MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 46339170127SNancy.Lin }, { 46439170127SNancy.Lin DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, 46539170127SNancy.Lin MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), 46639170127SNancy.Lin MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 46739170127SNancy.Lin }, { 46839170127SNancy.Lin DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 46939170127SNancy.Lin MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), 47039170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN1_SEL 47139170127SNancy.Lin }, { 47239170127SNancy.Lin DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 47339170127SNancy.Lin MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), 47439170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN2_SEL 47539170127SNancy.Lin }, { 47639170127SNancy.Lin DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 47739170127SNancy.Lin MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), 47839170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN3_SEL 47939170127SNancy.Lin }, { 48039170127SNancy.Lin DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 48139170127SNancy.Lin MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), 48239170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN4_SEL 48339170127SNancy.Lin }, { 48439170127SNancy.Lin DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 48539170127SNancy.Lin MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), 48639170127SNancy.Lin MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 48739170127SNancy.Lin }, { 48839170127SNancy.Lin DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 48939170127SNancy.Lin MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), 49039170127SNancy.Lin MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 49139170127SNancy.Lin }, { 49239170127SNancy.Lin DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 49339170127SNancy.Lin MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), 49439170127SNancy.Lin MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 49539170127SNancy.Lin }, { 49639170127SNancy.Lin DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 49739170127SNancy.Lin MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), 49839170127SNancy.Lin MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 49939170127SNancy.Lin }, { 50039170127SNancy.Lin DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 50139170127SNancy.Lin MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), 50239170127SNancy.Lin MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 50339170127SNancy.Lin }, { 50439170127SNancy.Lin DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 50539170127SNancy.Lin MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), 50639170127SNancy.Lin MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 50739170127SNancy.Lin }, { 50839170127SNancy.Lin DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 50939170127SNancy.Lin MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), 51039170127SNancy.Lin MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 51139170127SNancy.Lin }, { 51239170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 51339170127SNancy.Lin MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), 51439170127SNancy.Lin MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 51539170127SNancy.Lin }, { 51639170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 51739170127SNancy.Lin MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 51839170127SNancy.Lin MT8195_MERGE4_SOUT_TO_DPI1_SEL 51939170127SNancy.Lin }, { 52039170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 52139170127SNancy.Lin MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), 52239170127SNancy.Lin MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 52339170127SNancy.Lin }, { 52439170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 52539170127SNancy.Lin MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 52639170127SNancy.Lin MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 52739170127SNancy.Lin } 52839170127SNancy.Lin }; 529b804923bSjason-jh.lin #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ 530