1*886bdf9cSHuisong Li /* SPDX-License-Identifier: GPL-2.0+ */ 2*886bdf9cSHuisong Li /* Copyright (c) 2023 Hisilicon Limited. */ 3*886bdf9cSHuisong Li 4*886bdf9cSHuisong Li #ifndef __KUNPENG_HCCS_H__ 5*886bdf9cSHuisong Li #define __KUNPENG_HCCS_H__ 6*886bdf9cSHuisong Li 7*886bdf9cSHuisong Li /* 8*886bdf9cSHuisong Li * |--------------- Chip0 ---------------|---------------- ChipN -------------| 9*886bdf9cSHuisong Li * |--------Die0-------|--------DieN-------|--------Die0-------|-------DieN-------| 10*886bdf9cSHuisong Li * | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 | 11*886bdf9cSHuisong Li */ 12*886bdf9cSHuisong Li 13*886bdf9cSHuisong Li /* 14*886bdf9cSHuisong Li * This value cannot be 255, otherwise the loop of the multi-BD communication 15*886bdf9cSHuisong Li * case cannot end. 16*886bdf9cSHuisong Li */ 17*886bdf9cSHuisong Li #define HCCS_DIE_MAX_PORT_ID 254 18*886bdf9cSHuisong Li 19*886bdf9cSHuisong Li struct hccs_port_info { 20*886bdf9cSHuisong Li u8 port_id; 21*886bdf9cSHuisong Li u8 port_type; 22*886bdf9cSHuisong Li u8 lane_mode; 23*886bdf9cSHuisong Li bool enable; /* if the port is enabled */ 24*886bdf9cSHuisong Li struct hccs_die_info *die; /* point to the die the port is located */ 25*886bdf9cSHuisong Li }; 26*886bdf9cSHuisong Li 27*886bdf9cSHuisong Li struct hccs_die_info { 28*886bdf9cSHuisong Li u8 die_id; 29*886bdf9cSHuisong Li u8 port_num; 30*886bdf9cSHuisong Li u8 min_port_id; 31*886bdf9cSHuisong Li u8 max_port_id; 32*886bdf9cSHuisong Li struct hccs_port_info *ports; 33*886bdf9cSHuisong Li struct hccs_chip_info *chip; /* point to the chip the die is located */ 34*886bdf9cSHuisong Li }; 35*886bdf9cSHuisong Li 36*886bdf9cSHuisong Li struct hccs_chip_info { 37*886bdf9cSHuisong Li u8 chip_id; 38*886bdf9cSHuisong Li u8 die_num; 39*886bdf9cSHuisong Li struct hccs_die_info *dies; 40*886bdf9cSHuisong Li struct hccs_dev *hdev; 41*886bdf9cSHuisong Li }; 42*886bdf9cSHuisong Li 43*886bdf9cSHuisong Li struct hccs_mbox_client_info { 44*886bdf9cSHuisong Li struct mbox_client client; 45*886bdf9cSHuisong Li struct mbox_chan *mbox_chan; 46*886bdf9cSHuisong Li struct pcc_mbox_chan *pcc_chan; 47*886bdf9cSHuisong Li u64 deadline_us; 48*886bdf9cSHuisong Li void *pcc_comm_addr; 49*886bdf9cSHuisong Li }; 50*886bdf9cSHuisong Li 51*886bdf9cSHuisong Li struct hccs_dev { 52*886bdf9cSHuisong Li struct device *dev; 53*886bdf9cSHuisong Li struct acpi_device *acpi_dev; 54*886bdf9cSHuisong Li u64 caps; 55*886bdf9cSHuisong Li u8 chip_num; 56*886bdf9cSHuisong Li struct hccs_chip_info *chips; 57*886bdf9cSHuisong Li u8 chan_id; 58*886bdf9cSHuisong Li struct mutex lock; 59*886bdf9cSHuisong Li struct hccs_mbox_client_info cl_info; 60*886bdf9cSHuisong Li }; 61*886bdf9cSHuisong Li 62*886bdf9cSHuisong Li #define HCCS_SERDES_MODULE_CODE 0x32 63*886bdf9cSHuisong Li enum hccs_subcmd_type { 64*886bdf9cSHuisong Li HCCS_GET_CHIP_NUM = 0x1, 65*886bdf9cSHuisong Li HCCS_GET_DIE_NUM, 66*886bdf9cSHuisong Li HCCS_GET_DIE_INFO, 67*886bdf9cSHuisong Li HCCS_GET_DIE_PORT_INFO, 68*886bdf9cSHuisong Li HCCS_GET_DEV_CAP, 69*886bdf9cSHuisong Li HCCS_GET_PORT_LINK_STATUS, 70*886bdf9cSHuisong Li HCCS_GET_PORT_CRC_ERR_CNT, 71*886bdf9cSHuisong Li HCCS_GET_DIE_PORTS_LANE_STA, 72*886bdf9cSHuisong Li HCCS_GET_DIE_PORTS_LINK_STA, 73*886bdf9cSHuisong Li HCCS_GET_DIE_PORTS_CRC_ERR_CNT, 74*886bdf9cSHuisong Li HCCS_SUB_CMD_MAX = 255, 75*886bdf9cSHuisong Li }; 76*886bdf9cSHuisong Li 77*886bdf9cSHuisong Li struct hccs_die_num_req_param { 78*886bdf9cSHuisong Li u8 chip_id; 79*886bdf9cSHuisong Li }; 80*886bdf9cSHuisong Li 81*886bdf9cSHuisong Li struct hccs_die_info_req_param { 82*886bdf9cSHuisong Li u8 chip_id; 83*886bdf9cSHuisong Li u8 die_idx; 84*886bdf9cSHuisong Li }; 85*886bdf9cSHuisong Li 86*886bdf9cSHuisong Li struct hccs_die_info_rsp_data { 87*886bdf9cSHuisong Li u8 die_id; 88*886bdf9cSHuisong Li u8 port_num; 89*886bdf9cSHuisong Li u8 min_port_id; 90*886bdf9cSHuisong Li u8 max_port_id; 91*886bdf9cSHuisong Li }; 92*886bdf9cSHuisong Li 93*886bdf9cSHuisong Li struct hccs_port_attr { 94*886bdf9cSHuisong Li u8 port_id; 95*886bdf9cSHuisong Li u8 port_type; 96*886bdf9cSHuisong Li u8 lane_mode; 97*886bdf9cSHuisong Li u8 enable : 1; /* if the port is enabled */ 98*886bdf9cSHuisong Li u16 rsv[2]; 99*886bdf9cSHuisong Li }; 100*886bdf9cSHuisong Li 101*886bdf9cSHuisong Li /* 102*886bdf9cSHuisong Li * The common command request for getting the information of all HCCS port on 103*886bdf9cSHuisong Li * specified DIE. 104*886bdf9cSHuisong Li */ 105*886bdf9cSHuisong Li struct hccs_die_comm_req_param { 106*886bdf9cSHuisong Li u8 chip_id; 107*886bdf9cSHuisong Li u8 die_id; /* id in hardware */ 108*886bdf9cSHuisong Li }; 109*886bdf9cSHuisong Li 110*886bdf9cSHuisong Li struct hccs_req_head { 111*886bdf9cSHuisong Li u8 module_code; /* set to 0x32 for serdes */ 112*886bdf9cSHuisong Li u8 start_id; 113*886bdf9cSHuisong Li u8 rsv[2]; 114*886bdf9cSHuisong Li }; 115*886bdf9cSHuisong Li 116*886bdf9cSHuisong Li struct hccs_rsp_head { 117*886bdf9cSHuisong Li u8 data_len; 118*886bdf9cSHuisong Li u8 next_id; 119*886bdf9cSHuisong Li u8 rsv[2]; 120*886bdf9cSHuisong Li }; 121*886bdf9cSHuisong Li 122*886bdf9cSHuisong Li struct hccs_fw_inner_head { 123*886bdf9cSHuisong Li u8 retStatus; /* 0: success, other: failure */ 124*886bdf9cSHuisong Li u8 rsv[7]; 125*886bdf9cSHuisong Li }; 126*886bdf9cSHuisong Li 127*886bdf9cSHuisong Li #define HCCS_PCC_SHARE_MEM_BYTES 64 128*886bdf9cSHuisong Li #define HCCS_FW_INNER_HEAD_BYTES 8 129*886bdf9cSHuisong Li #define HCCS_RSP_HEAD_BYTES 4 130*886bdf9cSHuisong Li 131*886bdf9cSHuisong Li #define HCCS_MAX_RSP_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \ 132*886bdf9cSHuisong Li HCCS_FW_INNER_HEAD_BYTES - \ 133*886bdf9cSHuisong Li HCCS_RSP_HEAD_BYTES) 134*886bdf9cSHuisong Li #define HCCS_MAX_RSP_DATA_SIZE_MAX (HCCS_MAX_RSP_DATA_BYTES / 4) 135*886bdf9cSHuisong Li 136*886bdf9cSHuisong Li /* 137*886bdf9cSHuisong Li * Note: Actual available size of data field also depands on the PCC header 138*886bdf9cSHuisong Li * bytes of the specific type. Driver needs to copy the response data in the 139*886bdf9cSHuisong Li * communication space based on the real length. 140*886bdf9cSHuisong Li */ 141*886bdf9cSHuisong Li struct hccs_rsp_desc { 142*886bdf9cSHuisong Li struct hccs_fw_inner_head fw_inner_head; /* 8 Bytes */ 143*886bdf9cSHuisong Li struct hccs_rsp_head rsp_head; /* 4 Bytes */ 144*886bdf9cSHuisong Li u32 data[HCCS_MAX_RSP_DATA_SIZE_MAX]; 145*886bdf9cSHuisong Li }; 146*886bdf9cSHuisong Li 147*886bdf9cSHuisong Li #define HCCS_REQ_HEAD_BYTES 4 148*886bdf9cSHuisong Li #define HCCS_MAX_REQ_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \ 149*886bdf9cSHuisong Li HCCS_REQ_HEAD_BYTES) 150*886bdf9cSHuisong Li #define HCCS_MAX_REQ_DATA_SIZE_MAX (HCCS_MAX_REQ_DATA_BYTES / 4) 151*886bdf9cSHuisong Li 152*886bdf9cSHuisong Li /* 153*886bdf9cSHuisong Li * Note: Actual available size of data field also depands on the PCC header 154*886bdf9cSHuisong Li * bytes of the specific type. Driver needs to copy the request data to the 155*886bdf9cSHuisong Li * communication space based on the real length. 156*886bdf9cSHuisong Li */ 157*886bdf9cSHuisong Li struct hccs_req_desc { 158*886bdf9cSHuisong Li struct hccs_req_head req_head; /* 4 Bytes */ 159*886bdf9cSHuisong Li u32 data[HCCS_MAX_REQ_DATA_SIZE_MAX]; 160*886bdf9cSHuisong Li }; 161*886bdf9cSHuisong Li 162*886bdf9cSHuisong Li struct hccs_desc { 163*886bdf9cSHuisong Li union { 164*886bdf9cSHuisong Li struct hccs_req_desc req; 165*886bdf9cSHuisong Li struct hccs_rsp_desc rsp; 166*886bdf9cSHuisong Li }; 167*886bdf9cSHuisong Li }; 168*886bdf9cSHuisong Li 169*886bdf9cSHuisong Li #endif /* __KUNPENG_HCCS_H__ */ 170