146a2bb5aSSagar Dharia // SPDX-License-Identifier: GPL-2.0 246a2bb5aSSagar Dharia /* 346a2bb5aSSagar Dharia * Copyright (c) 2011-2017, The Linux Foundation 446a2bb5aSSagar Dharia */ 546a2bb5aSSagar Dharia 646a2bb5aSSagar Dharia #ifndef _DRIVERS_SLIMBUS_H 746a2bb5aSSagar Dharia #define _DRIVERS_SLIMBUS_H 846a2bb5aSSagar Dharia #include <linux/module.h> 946a2bb5aSSagar Dharia #include <linux/device.h> 1046a2bb5aSSagar Dharia #include <linux/mutex.h> 11afbdcc7cSSagar Dharia #include <linux/completion.h> 1246a2bb5aSSagar Dharia #include <linux/slimbus.h> 1346a2bb5aSSagar Dharia 14*ce96188bSSrinivas Kandagatla /* Standard values per SLIMbus spec needed by controllers and devices */ 15*ce96188bSSrinivas Kandagatla #define SLIM_CL_PER_SUPERFRAME 6144 16*ce96188bSSrinivas Kandagatla #define SLIM_CL_PER_SUPERFRAME_DIV8 (SLIM_CL_PER_SUPERFRAME >> 3) 17*ce96188bSSrinivas Kandagatla 18afbdcc7cSSagar Dharia /* SLIMbus message types. Related to interpretation of message code. */ 19afbdcc7cSSagar Dharia #define SLIM_MSG_MT_CORE 0x0 20afbdcc7cSSagar Dharia 21*ce96188bSSrinivas Kandagatla /* 22*ce96188bSSrinivas Kandagatla * SLIM Broadcast header format 23*ce96188bSSrinivas Kandagatla * BYTE 0: MT[7:5] RL[4:0] 24*ce96188bSSrinivas Kandagatla * BYTE 1: RSVD[7] MC[6:0] 25*ce96188bSSrinivas Kandagatla * BYTE 2: RSVD[7:6] DT[5:4] PI[3:0] 26*ce96188bSSrinivas Kandagatla */ 27*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MT_MASK GENMASK(2, 0) 28*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MT_SHIFT 5 29*ce96188bSSrinivas Kandagatla #define SLIM_MSG_RL_MASK GENMASK(4, 0) 30*ce96188bSSrinivas Kandagatla #define SLIM_MSG_RL_SHIFT 0 31*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MC_MASK GENMASK(6, 0) 32*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MC_SHIFT 0 33*ce96188bSSrinivas Kandagatla #define SLIM_MSG_DT_MASK GENMASK(1, 0) 34*ce96188bSSrinivas Kandagatla #define SLIM_MSG_DT_SHIFT 4 35*ce96188bSSrinivas Kandagatla 36*ce96188bSSrinivas Kandagatla #define SLIM_HEADER_GET_MT(b) ((b >> SLIM_MSG_MT_SHIFT) & SLIM_MSG_MT_MASK) 37*ce96188bSSrinivas Kandagatla #define SLIM_HEADER_GET_RL(b) ((b >> SLIM_MSG_RL_SHIFT) & SLIM_MSG_RL_MASK) 38*ce96188bSSrinivas Kandagatla #define SLIM_HEADER_GET_MC(b) ((b >> SLIM_MSG_MC_SHIFT) & SLIM_MSG_MC_MASK) 39*ce96188bSSrinivas Kandagatla #define SLIM_HEADER_GET_DT(b) ((b >> SLIM_MSG_DT_SHIFT) & SLIM_MSG_DT_MASK) 40*ce96188bSSrinivas Kandagatla 41*ce96188bSSrinivas Kandagatla /* Device management messages used by this framework */ 42*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MC_REPORT_PRESENT 0x1 43*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS 0x2 44*ce96188bSSrinivas Kandagatla #define SLIM_MSG_MC_REPORT_ABSENT 0xF 45*ce96188bSSrinivas Kandagatla 464b14e62aSSagar Dharia /* Clock pause Reconfiguration messages */ 474b14e62aSSagar Dharia #define SLIM_MSG_MC_BEGIN_RECONFIGURATION 0x40 484b14e62aSSagar Dharia #define SLIM_MSG_MC_NEXT_PAUSE_CLOCK 0x4A 494b14e62aSSagar Dharia #define SLIM_MSG_MC_RECONFIGURE_NOW 0x5F 504b14e62aSSagar Dharia 514b14e62aSSagar Dharia /* Clock pause values per SLIMbus spec */ 524b14e62aSSagar Dharia #define SLIM_CLK_FAST 0 534b14e62aSSagar Dharia #define SLIM_CLK_CONST_PHASE 1 544b14e62aSSagar Dharia #define SLIM_CLK_UNSPECIFIED 2 554b14e62aSSagar Dharia 56afbdcc7cSSagar Dharia /* Destination type Values */ 57afbdcc7cSSagar Dharia #define SLIM_MSG_DEST_LOGICALADDR 0 58afbdcc7cSSagar Dharia #define SLIM_MSG_DEST_ENUMADDR 1 59afbdcc7cSSagar Dharia #define SLIM_MSG_DEST_BROADCAST 3 60afbdcc7cSSagar Dharia 6146a2bb5aSSagar Dharia /* Standard values per SLIMbus spec needed by controllers and devices */ 6246a2bb5aSSagar Dharia #define SLIM_MAX_CLK_GEAR 10 6346a2bb5aSSagar Dharia #define SLIM_MIN_CLK_GEAR 1 6446a2bb5aSSagar Dharia 6546a2bb5aSSagar Dharia /* Manager's logical address is set to 0xFF per spec */ 6646a2bb5aSSagar Dharia #define SLIM_LA_MANAGER 0xFF 6746a2bb5aSSagar Dharia 68afbdcc7cSSagar Dharia #define SLIM_MAX_TIDS 256 6946a2bb5aSSagar Dharia /** 7046a2bb5aSSagar Dharia * struct slim_framer - Represents SLIMbus framer. 7146a2bb5aSSagar Dharia * Every controller may have multiple framers. There is 1 active framer device 7246a2bb5aSSagar Dharia * responsible for clocking the bus. 7346a2bb5aSSagar Dharia * Manager is responsible for framer hand-over. 7446a2bb5aSSagar Dharia * @dev: Driver model representation of the device. 7546a2bb5aSSagar Dharia * @e_addr: Enumeration address of the framer. 7646a2bb5aSSagar Dharia * @rootfreq: Root Frequency at which the framer can run. This is maximum 7746a2bb5aSSagar Dharia * frequency ('clock gear 10') at which the bus can operate. 7846a2bb5aSSagar Dharia * @superfreq: Superframes per root frequency. Every frame is 6144 bits. 7946a2bb5aSSagar Dharia */ 8046a2bb5aSSagar Dharia struct slim_framer { 8146a2bb5aSSagar Dharia struct device dev; 8246a2bb5aSSagar Dharia struct slim_eaddr e_addr; 8346a2bb5aSSagar Dharia int rootfreq; 8446a2bb5aSSagar Dharia int superfreq; 8546a2bb5aSSagar Dharia }; 8646a2bb5aSSagar Dharia 8746a2bb5aSSagar Dharia #define to_slim_framer(d) container_of(d, struct slim_framer, dev) 8846a2bb5aSSagar Dharia 8946a2bb5aSSagar Dharia /** 90afbdcc7cSSagar Dharia * struct slim_msg_txn - Message to be sent by the controller. 91afbdcc7cSSagar Dharia * This structure has packet header, 92afbdcc7cSSagar Dharia * payload and buffer to be filled (if any) 93afbdcc7cSSagar Dharia * @rl: Header field. remaining length. 94afbdcc7cSSagar Dharia * @mt: Header field. Message type. 95afbdcc7cSSagar Dharia * @mc: Header field. LSB is message code for type mt. 96afbdcc7cSSagar Dharia * @dt: Header field. Destination type. 97afbdcc7cSSagar Dharia * @ec: Element code. Used for elemental access APIs. 98afbdcc7cSSagar Dharia * @tid: Transaction ID. Used for messages expecting response. 99afbdcc7cSSagar Dharia * (relevant for message-codes involving read operation) 100afbdcc7cSSagar Dharia * @la: Logical address of the device this message is going to. 101afbdcc7cSSagar Dharia * (Not used when destination type is broadcast.) 102afbdcc7cSSagar Dharia * @msg: Elemental access message to be read/written 103afbdcc7cSSagar Dharia * @comp: completion if read/write is synchronous, used internally 104afbdcc7cSSagar Dharia * for tid based transactions. 105afbdcc7cSSagar Dharia */ 106afbdcc7cSSagar Dharia struct slim_msg_txn { 107afbdcc7cSSagar Dharia u8 rl; 108afbdcc7cSSagar Dharia u8 mt; 109afbdcc7cSSagar Dharia u8 mc; 110afbdcc7cSSagar Dharia u8 dt; 111afbdcc7cSSagar Dharia u16 ec; 112afbdcc7cSSagar Dharia u8 tid; 113afbdcc7cSSagar Dharia u8 la; 114afbdcc7cSSagar Dharia struct slim_val_inf *msg; 115afbdcc7cSSagar Dharia struct completion *comp; 116afbdcc7cSSagar Dharia }; 117afbdcc7cSSagar Dharia 118afbdcc7cSSagar Dharia /* Frequently used message transaction structures */ 119afbdcc7cSSagar Dharia #define DEFINE_SLIM_LDEST_TXN(name, mc, rl, la, msg) \ 120afbdcc7cSSagar Dharia struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_LOGICALADDR, 0,\ 121afbdcc7cSSagar Dharia 0, la, msg, } 1224b14e62aSSagar Dharia 1234b14e62aSSagar Dharia #define DEFINE_SLIM_BCAST_TXN(name, mc, rl, la, msg) \ 1244b14e62aSSagar Dharia struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_BROADCAST, 0,\ 1254b14e62aSSagar Dharia 0, la, msg, } 126*ce96188bSSrinivas Kandagatla 127*ce96188bSSrinivas Kandagatla #define DEFINE_SLIM_EDEST_TXN(name, mc, rl, la, msg) \ 128*ce96188bSSrinivas Kandagatla struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_ENUMADDR, 0,\ 129*ce96188bSSrinivas Kandagatla 0, la, msg, } 1304b14e62aSSagar Dharia /** 1314b14e62aSSagar Dharia * enum slim_clk_state: SLIMbus controller's clock state used internally for 1324b14e62aSSagar Dharia * maintaining current clock state. 1334b14e62aSSagar Dharia * @SLIM_CLK_ACTIVE: SLIMbus clock is active 1344b14e62aSSagar Dharia * @SLIM_CLK_ENTERING_PAUSE: SLIMbus clock pause sequence is being sent on the 1354b14e62aSSagar Dharia * bus. If this succeeds, state changes to SLIM_CLK_PAUSED. If the 1364b14e62aSSagar Dharia * transition fails, state changes back to SLIM_CLK_ACTIVE 1374b14e62aSSagar Dharia * @SLIM_CLK_PAUSED: SLIMbus controller clock has paused. 1384b14e62aSSagar Dharia */ 1394b14e62aSSagar Dharia enum slim_clk_state { 1404b14e62aSSagar Dharia SLIM_CLK_ACTIVE, 1414b14e62aSSagar Dharia SLIM_CLK_ENTERING_PAUSE, 1424b14e62aSSagar Dharia SLIM_CLK_PAUSED, 1434b14e62aSSagar Dharia }; 1444b14e62aSSagar Dharia 1454b14e62aSSagar Dharia /** 1464b14e62aSSagar Dharia * struct slim_sched: Framework uses this structure internally for scheduling. 1474b14e62aSSagar Dharia * @clk_state: Controller's clock state from enum slim_clk_state 1484b14e62aSSagar Dharia * @pause_comp: Signals completion of clock pause sequence. This is useful when 1494b14e62aSSagar Dharia * client tries to call SLIMbus transaction when controller is entering 1504b14e62aSSagar Dharia * clock pause. 1514b14e62aSSagar Dharia * @m_reconf: This mutex is held until current reconfiguration (data channel 1524b14e62aSSagar Dharia * scheduling, message bandwidth reservation) is done. Message APIs can 1534b14e62aSSagar Dharia * use the bus concurrently when this mutex is held since elemental access 1544b14e62aSSagar Dharia * messages can be sent on the bus when reconfiguration is in progress. 1554b14e62aSSagar Dharia */ 1564b14e62aSSagar Dharia struct slim_sched { 1574b14e62aSSagar Dharia enum slim_clk_state clk_state; 1584b14e62aSSagar Dharia struct completion pause_comp; 1594b14e62aSSagar Dharia struct mutex m_reconf; 1604b14e62aSSagar Dharia }; 1614b14e62aSSagar Dharia 162afbdcc7cSSagar Dharia /** 16346a2bb5aSSagar Dharia * struct slim_controller - Controls every instance of SLIMbus 16446a2bb5aSSagar Dharia * (similar to 'master' on SPI) 16546a2bb5aSSagar Dharia * @dev: Device interface to this driver 16646a2bb5aSSagar Dharia * @id: Board-specific number identifier for this controller/bus 16746a2bb5aSSagar Dharia * @name: Name for this controller 16846a2bb5aSSagar Dharia * @min_cg: Minimum clock gear supported by this controller (default value: 1) 16946a2bb5aSSagar Dharia * @max_cg: Maximum clock gear supported by this controller (default value: 10) 17046a2bb5aSSagar Dharia * @clkgear: Current clock gear in which this bus is running 17146a2bb5aSSagar Dharia * @laddr_ida: logical address id allocator 17246a2bb5aSSagar Dharia * @a_framer: Active framer which is clocking the bus managed by this controller 17346a2bb5aSSagar Dharia * @lock: Mutex protecting controller data structures 17446a2bb5aSSagar Dharia * @devices: Slim device list 17546a2bb5aSSagar Dharia * @tid_idr: tid id allocator 17646a2bb5aSSagar Dharia * @txn_lock: Lock to protect table of transactions 1774b14e62aSSagar Dharia * @sched: scheduler structure used by the controller 178afbdcc7cSSagar Dharia * @xfer_msg: Transfer a message on this controller (this can be a broadcast 179afbdcc7cSSagar Dharia * control/status message like data channel setup, or a unicast message 180afbdcc7cSSagar Dharia * like value element read/write. 18146a2bb5aSSagar Dharia * @set_laddr: Setup logical address at laddr for the slave with elemental 18246a2bb5aSSagar Dharia * address e_addr. Drivers implementing controller will be expected to 18346a2bb5aSSagar Dharia * send unicast message to this device with its logical address. 18446a2bb5aSSagar Dharia * @get_laddr: It is possible that controller needs to set fixed logical 18546a2bb5aSSagar Dharia * address table and get_laddr can be used in that case so that controller 18646a2bb5aSSagar Dharia * can do this assignment. Use case is when the master is on the remote 18746a2bb5aSSagar Dharia * processor side, who is resposible for allocating laddr. 1884b14e62aSSagar Dharia * @wakeup: This function pointer implements controller-specific procedure 1894b14e62aSSagar Dharia * to wake it up from clock-pause. Framework will call this to bring 1904b14e62aSSagar Dharia * the controller out of clock pause. 19146a2bb5aSSagar Dharia * 19246a2bb5aSSagar Dharia * 'Manager device' is responsible for device management, bandwidth 19346a2bb5aSSagar Dharia * allocation, channel setup, and port associations per channel. 19446a2bb5aSSagar Dharia * Device management means Logical address assignment/removal based on 19546a2bb5aSSagar Dharia * enumeration (report-present, report-absent) of a device. 19646a2bb5aSSagar Dharia * Bandwidth allocation is done dynamically by the manager based on active 19746a2bb5aSSagar Dharia * channels on the bus, message-bandwidth requests made by SLIMbus devices. 19846a2bb5aSSagar Dharia * Based on current bandwidth usage, manager chooses a frequency to run 19946a2bb5aSSagar Dharia * the bus at (in steps of 'clock-gear', 1 through 10, each clock gear 20046a2bb5aSSagar Dharia * representing twice the frequency than the previous gear). 20146a2bb5aSSagar Dharia * Manager is also responsible for entering (and exiting) low-power-mode 20246a2bb5aSSagar Dharia * (known as 'clock pause'). 20346a2bb5aSSagar Dharia * Manager can do handover of framer if there are multiple framers on the 20446a2bb5aSSagar Dharia * bus and a certain usecase warrants using certain framer to avoid keeping 20546a2bb5aSSagar Dharia * previous framer being powered-on. 20646a2bb5aSSagar Dharia * 20746a2bb5aSSagar Dharia * Controller here performs duties of the manager device, and 'interface 20846a2bb5aSSagar Dharia * device'. Interface device is responsible for monitoring the bus and 20946a2bb5aSSagar Dharia * reporting information such as loss-of-synchronization, data 21046a2bb5aSSagar Dharia * slot-collision. 21146a2bb5aSSagar Dharia */ 21246a2bb5aSSagar Dharia struct slim_controller { 21346a2bb5aSSagar Dharia struct device *dev; 21446a2bb5aSSagar Dharia unsigned int id; 21546a2bb5aSSagar Dharia char name[SLIMBUS_NAME_SIZE]; 21646a2bb5aSSagar Dharia int min_cg; 21746a2bb5aSSagar Dharia int max_cg; 21846a2bb5aSSagar Dharia int clkgear; 21946a2bb5aSSagar Dharia struct ida laddr_ida; 22046a2bb5aSSagar Dharia struct slim_framer *a_framer; 22146a2bb5aSSagar Dharia struct mutex lock; 22246a2bb5aSSagar Dharia struct list_head devices; 22346a2bb5aSSagar Dharia struct idr tid_idr; 22446a2bb5aSSagar Dharia spinlock_t txn_lock; 2254b14e62aSSagar Dharia struct slim_sched sched; 226afbdcc7cSSagar Dharia int (*xfer_msg)(struct slim_controller *ctrl, 227afbdcc7cSSagar Dharia struct slim_msg_txn *tx); 22846a2bb5aSSagar Dharia int (*set_laddr)(struct slim_controller *ctrl, 22946a2bb5aSSagar Dharia struct slim_eaddr *ea, u8 laddr); 23046a2bb5aSSagar Dharia int (*get_laddr)(struct slim_controller *ctrl, 23146a2bb5aSSagar Dharia struct slim_eaddr *ea, u8 *laddr); 2324b14e62aSSagar Dharia int (*wakeup)(struct slim_controller *ctrl); 23346a2bb5aSSagar Dharia }; 23446a2bb5aSSagar Dharia 23546a2bb5aSSagar Dharia int slim_device_report_present(struct slim_controller *ctrl, 23646a2bb5aSSagar Dharia struct slim_eaddr *e_addr, u8 *laddr); 23746a2bb5aSSagar Dharia void slim_report_absent(struct slim_device *sbdev); 23846a2bb5aSSagar Dharia int slim_register_controller(struct slim_controller *ctrl); 23946a2bb5aSSagar Dharia int slim_unregister_controller(struct slim_controller *ctrl); 240afbdcc7cSSagar Dharia void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 l); 241afbdcc7cSSagar Dharia int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn); 2424b14e62aSSagar Dharia int slim_ctrl_clk_pause(struct slim_controller *ctrl, bool wakeup, u8 restart); 24346a2bb5aSSagar Dharia 244afbdcc7cSSagar Dharia static inline bool slim_tid_txn(u8 mt, u8 mc) 245afbdcc7cSSagar Dharia { 246afbdcc7cSSagar Dharia return (mt == SLIM_MSG_MT_CORE && 247afbdcc7cSSagar Dharia (mc == SLIM_MSG_MC_REQUEST_INFORMATION || 248afbdcc7cSSagar Dharia mc == SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION || 249afbdcc7cSSagar Dharia mc == SLIM_MSG_MC_REQUEST_VALUE || 250afbdcc7cSSagar Dharia mc == SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION)); 251afbdcc7cSSagar Dharia } 252afbdcc7cSSagar Dharia 253afbdcc7cSSagar Dharia static inline bool slim_ec_txn(u8 mt, u8 mc) 254afbdcc7cSSagar Dharia { 255afbdcc7cSSagar Dharia return (mt == SLIM_MSG_MT_CORE && 256afbdcc7cSSagar Dharia ((mc >= SLIM_MSG_MC_REQUEST_INFORMATION && 257afbdcc7cSSagar Dharia mc <= SLIM_MSG_MC_REPORT_INFORMATION) || 258afbdcc7cSSagar Dharia (mc >= SLIM_MSG_MC_REQUEST_VALUE && 259afbdcc7cSSagar Dharia mc <= SLIM_MSG_MC_CHANGE_VALUE))); 260afbdcc7cSSagar Dharia } 26146a2bb5aSSagar Dharia #endif /* _LINUX_SLIMBUS_H */ 262