xref: /openbmc/linux/drivers/scsi/stex.c (revision e868d61272caa648214046a096e5a6bfc068dc8c)
1 /*
2  * SuperTrak EX Series Storage Controller driver for Linux
3  *
4  *	Copyright (C) 2005, 2006 Promise Technology Inc.
5  *
6  *	This program is free software; you can redistribute it and/or
7  *	modify it under the terms of the GNU General Public License
8  *	as published by the Free Software Foundation; either version
9  *	2 of the License, or (at your option) any later version.
10  *
11  *	Written By:
12  *		Ed Lin <promise_linux@promise.com>
13  *
14  */
15 
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/time.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/interrupt.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <asm/io.h>
28 #include <asm/irq.h>
29 #include <asm/byteorder.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_tcq.h>
35 
36 #define DRV_NAME "stex"
37 #define ST_DRIVER_VERSION "3.1.0.1"
38 #define ST_VER_MAJOR 		3
39 #define ST_VER_MINOR 		1
40 #define ST_OEM 			0
41 #define ST_BUILD_VER 		1
42 
43 enum {
44 	/* MU register offset */
45 	IMR0	= 0x10,	/* MU_INBOUND_MESSAGE_REG0 */
46 	IMR1	= 0x14,	/* MU_INBOUND_MESSAGE_REG1 */
47 	OMR0	= 0x18,	/* MU_OUTBOUND_MESSAGE_REG0 */
48 	OMR1	= 0x1c,	/* MU_OUTBOUND_MESSAGE_REG1 */
49 	IDBL	= 0x20,	/* MU_INBOUND_DOORBELL */
50 	IIS	= 0x24,	/* MU_INBOUND_INTERRUPT_STATUS */
51 	IIM	= 0x28,	/* MU_INBOUND_INTERRUPT_MASK */
52 	ODBL	= 0x2c,	/* MU_OUTBOUND_DOORBELL */
53 	OIS	= 0x30,	/* MU_OUTBOUND_INTERRUPT_STATUS */
54 	OIM	= 0x3c,	/* MU_OUTBOUND_INTERRUPT_MASK */
55 
56 	/* MU register value */
57 	MU_INBOUND_DOORBELL_HANDSHAKE		= 1,
58 	MU_INBOUND_DOORBELL_REQHEADCHANGED	= 2,
59 	MU_INBOUND_DOORBELL_STATUSTAILCHANGED	= 4,
60 	MU_INBOUND_DOORBELL_HMUSTOPPED		= 8,
61 	MU_INBOUND_DOORBELL_RESET		= 16,
62 
63 	MU_OUTBOUND_DOORBELL_HANDSHAKE		= 1,
64 	MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED	= 2,
65 	MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED	= 4,
66 	MU_OUTBOUND_DOORBELL_BUSCHANGE		= 8,
67 	MU_OUTBOUND_DOORBELL_HASEVENT		= 16,
68 
69 	/* MU status code */
70 	MU_STATE_STARTING			= 1,
71 	MU_STATE_FMU_READY_FOR_HANDSHAKE	= 2,
72 	MU_STATE_SEND_HANDSHAKE_FRAME		= 3,
73 	MU_STATE_STARTED			= 4,
74 	MU_STATE_RESETTING			= 5,
75 
76 	MU_MAX_DELAY				= 120,
77 	MU_HANDSHAKE_SIGNATURE			= 0x55aaaa55,
78 	MU_HANDSHAKE_SIGNATURE_HALF		= 0x5a5a0000,
79 	MU_HARD_RESET_WAIT			= 30000,
80 	HMU_PARTNER_TYPE			= 2,
81 
82 	/* firmware returned values */
83 	SRB_STATUS_SUCCESS			= 0x01,
84 	SRB_STATUS_ERROR			= 0x04,
85 	SRB_STATUS_BUSY				= 0x05,
86 	SRB_STATUS_INVALID_REQUEST		= 0x06,
87 	SRB_STATUS_SELECTION_TIMEOUT		= 0x0A,
88 	SRB_SEE_SENSE 				= 0x80,
89 
90 	/* task attribute */
91 	TASK_ATTRIBUTE_SIMPLE			= 0x0,
92 	TASK_ATTRIBUTE_HEADOFQUEUE		= 0x1,
93 	TASK_ATTRIBUTE_ORDERED			= 0x2,
94 	TASK_ATTRIBUTE_ACA			= 0x4,
95 
96 	/* request count, etc. */
97 	MU_MAX_REQUEST				= 32,
98 
99 	/* one message wasted, use MU_MAX_REQUEST+1
100 		to handle MU_MAX_REQUEST messages */
101 	MU_REQ_COUNT				= (MU_MAX_REQUEST + 1),
102 	MU_STATUS_COUNT				= (MU_MAX_REQUEST + 1),
103 
104 	STEX_CDB_LENGTH				= MAX_COMMAND_SIZE,
105 	REQ_VARIABLE_LEN			= 1024,
106 	STATUS_VAR_LEN				= 128,
107 	ST_CAN_QUEUE				= MU_MAX_REQUEST,
108 	ST_CMD_PER_LUN				= MU_MAX_REQUEST,
109 	ST_MAX_SG				= 32,
110 
111 	/* sg flags */
112 	SG_CF_EOT				= 0x80,	/* end of table */
113 	SG_CF_64B				= 0x40,	/* 64 bit item */
114 	SG_CF_HOST				= 0x20,	/* sg in host memory */
115 
116 	ST_MAX_ARRAY_SUPPORTED			= 16,
117 	ST_MAX_TARGET_NUM			= (ST_MAX_ARRAY_SUPPORTED+1),
118 	ST_MAX_LUN_PER_TARGET			= 16,
119 
120 	st_shasta				= 0,
121 	st_vsc					= 1,
122 	st_vsc1					= 2,
123 	st_yosemite				= 3,
124 
125 	PASSTHRU_REQ_TYPE			= 0x00000001,
126 	PASSTHRU_REQ_NO_WAKEUP			= 0x00000100,
127 	ST_INTERNAL_TIMEOUT			= 30,
128 
129 	ST_TO_CMD				= 0,
130 	ST_FROM_CMD				= 1,
131 
132 	/* vendor specific commands of Promise */
133 	MGT_CMD					= 0xd8,
134 	SINBAND_MGT_CMD				= 0xd9,
135 	ARRAY_CMD				= 0xe0,
136 	CONTROLLER_CMD				= 0xe1,
137 	DEBUGGING_CMD				= 0xe2,
138 	PASSTHRU_CMD				= 0xe3,
139 
140 	PASSTHRU_GET_ADAPTER			= 0x05,
141 	PASSTHRU_GET_DRVVER			= 0x10,
142 
143 	CTLR_CONFIG_CMD				= 0x03,
144 	CTLR_SHUTDOWN				= 0x0d,
145 
146 	CTLR_POWER_STATE_CHANGE			= 0x0e,
147 	CTLR_POWER_SAVING			= 0x01,
148 
149 	PASSTHRU_SIGNATURE			= 0x4e415041,
150 	MGT_CMD_SIGNATURE			= 0xba,
151 
152 	INQUIRY_EVPD				= 0x01,
153 
154 	ST_ADDITIONAL_MEM			= 0x200000,
155 };
156 
157 /* SCSI inquiry data */
158 typedef struct st_inq {
159 	u8 DeviceType			:5;
160 	u8 DeviceTypeQualifier		:3;
161 	u8 DeviceTypeModifier		:7;
162 	u8 RemovableMedia		:1;
163 	u8 Versions;
164 	u8 ResponseDataFormat		:4;
165 	u8 HiSupport			:1;
166 	u8 NormACA			:1;
167 	u8 ReservedBit			:1;
168 	u8 AERC				:1;
169 	u8 AdditionalLength;
170 	u8 Reserved[2];
171 	u8 SoftReset			:1;
172 	u8 CommandQueue			:1;
173 	u8 Reserved2			:1;
174 	u8 LinkedCommands		:1;
175 	u8 Synchronous			:1;
176 	u8 Wide16Bit			:1;
177 	u8 Wide32Bit			:1;
178 	u8 RelativeAddressing		:1;
179 	u8 VendorId[8];
180 	u8 ProductId[16];
181 	u8 ProductRevisionLevel[4];
182 	u8 VendorSpecific[20];
183 	u8 Reserved3[40];
184 } ST_INQ;
185 
186 struct st_sgitem {
187 	u8 ctrl;	/* SG_CF_xxx */
188 	u8 reserved[3];
189 	__le32 count;
190 	__le32 addr;
191 	__le32 addr_hi;
192 };
193 
194 struct st_sgtable {
195 	__le16 sg_count;
196 	__le16 max_sg_count;
197 	__le32 sz_in_byte;
198 	struct st_sgitem table[ST_MAX_SG];
199 };
200 
201 struct handshake_frame {
202 	__le32 rb_phy;		/* request payload queue physical address */
203 	__le32 rb_phy_hi;
204 	__le16 req_sz;		/* size of each request payload */
205 	__le16 req_cnt;		/* count of reqs the buffer can hold */
206 	__le16 status_sz;	/* size of each status payload */
207 	__le16 status_cnt;	/* count of status the buffer can hold */
208 	__le32 hosttime;	/* seconds from Jan 1, 1970 (GMT) */
209 	__le32 hosttime_hi;
210 	u8 partner_type;	/* who sends this frame */
211 	u8 reserved0[7];
212 	__le32 partner_ver_major;
213 	__le32 partner_ver_minor;
214 	__le32 partner_ver_oem;
215 	__le32 partner_ver_build;
216 	__le32 extra_offset;	/* NEW */
217 	__le32 extra_size;	/* NEW */
218 	u32 reserved1[2];
219 };
220 
221 struct req_msg {
222 	__le16 tag;
223 	u8 lun;
224 	u8 target;
225 	u8 task_attr;
226 	u8 task_manage;
227 	u8 prd_entry;
228 	u8 payload_sz;		/* payload size in 4-byte, not used */
229 	u8 cdb[STEX_CDB_LENGTH];
230 	u8 variable[REQ_VARIABLE_LEN];
231 };
232 
233 struct status_msg {
234 	__le16 tag;
235 	u8 lun;
236 	u8 target;
237 	u8 srb_status;
238 	u8 scsi_status;
239 	u8 reserved;
240 	u8 payload_sz;		/* payload size in 4-byte */
241 	u8 variable[STATUS_VAR_LEN];
242 };
243 
244 struct ver_info {
245 	u32 major;
246 	u32 minor;
247 	u32 oem;
248 	u32 build;
249 	u32 reserved[2];
250 };
251 
252 struct st_frame {
253 	u32 base[6];
254 	u32 rom_addr;
255 
256 	struct ver_info drv_ver;
257 	struct ver_info bios_ver;
258 
259 	u32 bus;
260 	u32 slot;
261 	u32 irq_level;
262 	u32 irq_vec;
263 	u32 id;
264 	u32 subid;
265 
266 	u32 dimm_size;
267 	u8 dimm_type;
268 	u8 reserved[3];
269 
270 	u32 channel;
271 	u32 reserved1;
272 };
273 
274 struct st_drvver {
275 	u32 major;
276 	u32 minor;
277 	u32 oem;
278 	u32 build;
279 	u32 signature[2];
280 	u8 console_id;
281 	u8 host_no;
282 	u8 reserved0[2];
283 	u32 reserved[3];
284 };
285 
286 #define MU_REQ_BUFFER_SIZE	(MU_REQ_COUNT * sizeof(struct req_msg))
287 #define MU_STATUS_BUFFER_SIZE	(MU_STATUS_COUNT * sizeof(struct status_msg))
288 #define MU_BUFFER_SIZE		(MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
289 #define STEX_EXTRA_SIZE		max(sizeof(struct st_frame), sizeof(ST_INQ))
290 #define STEX_BUFFER_SIZE	(MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
291 
292 struct st_ccb {
293 	struct req_msg *req;
294 	struct scsi_cmnd *cmd;
295 
296 	void *sense_buffer;
297 	unsigned int sense_bufflen;
298 	int sg_count;
299 
300 	u32 req_type;
301 	u8 srb_status;
302 	u8 scsi_status;
303 };
304 
305 struct st_hba {
306 	void __iomem *mmio_base;	/* iomapped PCI memory space */
307 	void *dma_mem;
308 	dma_addr_t dma_handle;
309 	size_t dma_size;
310 
311 	struct Scsi_Host *host;
312 	struct pci_dev *pdev;
313 
314 	u32 req_head;
315 	u32 req_tail;
316 	u32 status_head;
317 	u32 status_tail;
318 
319 	struct status_msg *status_buffer;
320 	void *copy_buffer; /* temp buffer for driver-handled commands */
321 	struct st_ccb ccb[MU_MAX_REQUEST];
322 	struct st_ccb *wait_ccb;
323 	wait_queue_head_t waitq;
324 
325 	unsigned int mu_status;
326 	int out_req_cnt;
327 
328 	unsigned int cardtype;
329 };
330 
331 static const char console_inq_page[] =
332 {
333 	0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
334 	0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,	/* "Promise " */
335 	0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,	/* "RAID Con" */
336 	0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,	/* "sole    " */
337 	0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,	/* "1.00    " */
338 	0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,	/* "SX/RSAF-" */
339 	0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,	/* "TE1.00  " */
340 	0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
341 };
342 
343 MODULE_AUTHOR("Ed Lin");
344 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
345 MODULE_LICENSE("GPL");
346 MODULE_VERSION(ST_DRIVER_VERSION);
347 
348 static void stex_gettime(__le32 *time)
349 {
350 	struct timeval tv;
351 	do_gettimeofday(&tv);
352 
353 	*time = cpu_to_le32(tv.tv_sec & 0xffffffff);
354 	*(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
355 }
356 
357 static struct status_msg *stex_get_status(struct st_hba *hba)
358 {
359 	struct status_msg *status =
360 		hba->status_buffer + hba->status_tail;
361 
362 	++hba->status_tail;
363 	hba->status_tail %= MU_STATUS_COUNT;
364 
365 	return status;
366 }
367 
368 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
369 {
370 	cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
371 
372 	cmd->sense_buffer[0] = 0x70;    /* fixed format, current */
373 	cmd->sense_buffer[2] = sk;
374 	cmd->sense_buffer[7] = 18 - 8;  /* additional sense length */
375 	cmd->sense_buffer[12] = asc;
376 	cmd->sense_buffer[13] = ascq;
377 }
378 
379 static void stex_invalid_field(struct scsi_cmnd *cmd,
380 			       void (*done)(struct scsi_cmnd *))
381 {
382 	/* "Invalid field in cbd" */
383 	stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
384 	done(cmd);
385 }
386 
387 static struct req_msg *stex_alloc_req(struct st_hba *hba)
388 {
389 	struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
390 		hba->req_head;
391 
392 	++hba->req_head;
393 	hba->req_head %= MU_REQ_COUNT;
394 
395 	return req;
396 }
397 
398 static int stex_map_sg(struct st_hba *hba,
399 	struct req_msg *req, struct st_ccb *ccb)
400 {
401 	struct pci_dev *pdev = hba->pdev;
402 	struct scsi_cmnd *cmd;
403 	dma_addr_t dma_handle;
404 	struct scatterlist *src;
405 	struct st_sgtable *dst;
406 	int i;
407 
408 	cmd = ccb->cmd;
409 	dst = (struct st_sgtable *)req->variable;
410 	dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
411 	dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
412 
413 	if (cmd->use_sg) {
414 		int n_elem;
415 
416 		src = (struct scatterlist *) cmd->request_buffer;
417 		n_elem = pci_map_sg(pdev, src,
418 			cmd->use_sg, cmd->sc_data_direction);
419 		if (n_elem <= 0)
420 			return -EIO;
421 
422 		ccb->sg_count = n_elem;
423 		dst->sg_count = cpu_to_le16((u16)n_elem);
424 
425 		for (i = 0; i < n_elem; i++, src++) {
426 			dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
427 			dst->table[i].addr =
428 				cpu_to_le32(sg_dma_address(src) & 0xffffffff);
429 			dst->table[i].addr_hi =
430 				cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
431 			dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
432 		}
433 		dst->table[--i].ctrl |= SG_CF_EOT;
434 		return 0;
435 	}
436 
437 	dma_handle = pci_map_single(pdev, cmd->request_buffer,
438 		cmd->request_bufflen, cmd->sc_data_direction);
439 	cmd->SCp.dma_handle = dma_handle;
440 
441 	ccb->sg_count = 1;
442 	dst->sg_count = cpu_to_le16(1);
443 	dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
444 	dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
445 	dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
446 	dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
447 
448 	return 0;
449 }
450 
451 static void stex_internal_copy(struct scsi_cmnd *cmd,
452 	const void *src, size_t *count, int sg_count, int direction)
453 {
454 	size_t lcount;
455 	size_t len;
456 	void *s, *d, *base = NULL;
457 	if (*count > cmd->request_bufflen)
458 		*count = cmd->request_bufflen;
459 	lcount = *count;
460 	while (lcount) {
461 		len = lcount;
462 		s = (void *)src;
463 		if (cmd->use_sg) {
464 			size_t offset = *count - lcount;
465 			s += offset;
466 			base = scsi_kmap_atomic_sg(cmd->request_buffer,
467 				sg_count, &offset, &len);
468 			if (base == NULL) {
469 				*count -= lcount;
470 				return;
471 			}
472 			d = base + offset;
473 		} else
474 			d = cmd->request_buffer;
475 
476 		if (direction == ST_TO_CMD)
477 			memcpy(d, s, len);
478 		else
479 			memcpy(s, d, len);
480 
481 		lcount -= len;
482 		if (cmd->use_sg)
483 			scsi_kunmap_atomic_sg(base);
484 	}
485 }
486 
487 static int stex_direct_copy(struct scsi_cmnd *cmd,
488 	const void *src, size_t count)
489 {
490 	struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
491 	size_t cp_len = count;
492 	int n_elem = 0;
493 
494 	if (cmd->use_sg) {
495 		n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
496 			cmd->use_sg, cmd->sc_data_direction);
497 		if (n_elem <= 0)
498 			return 0;
499 	}
500 
501 	stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
502 
503 	if (cmd->use_sg)
504 		pci_unmap_sg(hba->pdev, cmd->request_buffer,
505 			cmd->use_sg, cmd->sc_data_direction);
506 	return cp_len == count;
507 }
508 
509 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
510 {
511 	struct st_frame *p;
512 	size_t count = sizeof(struct st_frame);
513 
514 	p = hba->copy_buffer;
515 	stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
516 	memset(p->base, 0, sizeof(u32)*6);
517 	*(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
518 	p->rom_addr = 0;
519 
520 	p->drv_ver.major = ST_VER_MAJOR;
521 	p->drv_ver.minor = ST_VER_MINOR;
522 	p->drv_ver.oem = ST_OEM;
523 	p->drv_ver.build = ST_BUILD_VER;
524 
525 	p->bus = hba->pdev->bus->number;
526 	p->slot = hba->pdev->devfn;
527 	p->irq_level = 0;
528 	p->irq_vec = hba->pdev->irq;
529 	p->id = hba->pdev->vendor << 16 | hba->pdev->device;
530 	p->subid =
531 		hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
532 
533 	stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
534 }
535 
536 static void
537 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
538 {
539 	req->tag = cpu_to_le16(tag);
540 	req->task_attr = TASK_ATTRIBUTE_SIMPLE;
541 	req->task_manage = 0; /* not supported yet */
542 
543 	hba->ccb[tag].req = req;
544 	hba->out_req_cnt++;
545 
546 	writel(hba->req_head, hba->mmio_base + IMR0);
547 	writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
548 	readl(hba->mmio_base + IDBL); /* flush */
549 }
550 
551 static int
552 stex_slave_alloc(struct scsi_device *sdev)
553 {
554 	/* Cheat: usually extracted from Inquiry data */
555 	sdev->tagged_supported = 1;
556 
557 	scsi_activate_tcq(sdev, sdev->host->can_queue);
558 
559 	return 0;
560 }
561 
562 static int
563 stex_slave_config(struct scsi_device *sdev)
564 {
565 	sdev->use_10_for_rw = 1;
566 	sdev->use_10_for_ms = 1;
567 	sdev->timeout = 60 * HZ;
568 	sdev->tagged_supported = 1;
569 
570 	return 0;
571 }
572 
573 static void
574 stex_slave_destroy(struct scsi_device *sdev)
575 {
576 	scsi_deactivate_tcq(sdev, 1);
577 }
578 
579 static int
580 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
581 {
582 	struct st_hba *hba;
583 	struct Scsi_Host *host;
584 	unsigned int id,lun;
585 	struct req_msg *req;
586 	u16 tag;
587 	host = cmd->device->host;
588 	id = cmd->device->id;
589 	lun = cmd->device->channel; /* firmware lun issue work around */
590 	hba = (struct st_hba *) &host->hostdata[0];
591 
592 	switch (cmd->cmnd[0]) {
593 	case MODE_SENSE_10:
594 	{
595 		static char ms10_caching_page[12] =
596 			{ 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
597 		unsigned char page;
598 		page = cmd->cmnd[2] & 0x3f;
599 		if (page == 0x8 || page == 0x3f) {
600 			stex_direct_copy(cmd, ms10_caching_page,
601 					sizeof(ms10_caching_page));
602 			cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
603 			done(cmd);
604 		} else
605 			stex_invalid_field(cmd, done);
606 		return 0;
607 	}
608 	case INQUIRY:
609 		if (id != ST_MAX_ARRAY_SUPPORTED)
610 			break;
611 		if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
612 			stex_direct_copy(cmd, console_inq_page,
613 				sizeof(console_inq_page));
614 			cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
615 			done(cmd);
616 		} else
617 			stex_invalid_field(cmd, done);
618 		return 0;
619 	case PASSTHRU_CMD:
620 		if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
621 			struct st_drvver ver;
622 			ver.major = ST_VER_MAJOR;
623 			ver.minor = ST_VER_MINOR;
624 			ver.oem = ST_OEM;
625 			ver.build = ST_BUILD_VER;
626 			ver.signature[0] = PASSTHRU_SIGNATURE;
627 			ver.console_id = ST_MAX_ARRAY_SUPPORTED;
628 			ver.host_no = hba->host->host_no;
629 			cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
630 				DID_OK << 16 | COMMAND_COMPLETE << 8 :
631 				DID_ERROR << 16 | COMMAND_COMPLETE << 8;
632 			done(cmd);
633 			return 0;
634 		}
635 	default:
636 		break;
637 	}
638 
639 	cmd->scsi_done = done;
640 
641 	tag = cmd->request->tag;
642 
643 	if (unlikely(tag >= host->can_queue))
644 		return SCSI_MLQUEUE_HOST_BUSY;
645 
646 	req = stex_alloc_req(hba);
647 
648 	if (hba->cardtype == st_yosemite) {
649 		req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
650 		req->target = 0;
651 	} else {
652 		req->lun = lun;
653 		req->target = id;
654 	}
655 
656 	/* cdb */
657 	memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
658 
659 	hba->ccb[tag].cmd = cmd;
660 	hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
661 	hba->ccb[tag].sense_buffer = cmd->sense_buffer;
662 	hba->ccb[tag].req_type = 0;
663 
664 	if (cmd->sc_data_direction != DMA_NONE)
665 		stex_map_sg(hba, req, &hba->ccb[tag]);
666 
667 	stex_send_cmd(hba, req, tag);
668 	return 0;
669 }
670 
671 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
672 {
673 	if (cmd->sc_data_direction != DMA_NONE) {
674 		if (cmd->use_sg)
675 			pci_unmap_sg(hba->pdev, cmd->request_buffer,
676 				cmd->use_sg, cmd->sc_data_direction);
677 		else
678 			pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
679 				cmd->request_bufflen, cmd->sc_data_direction);
680 	}
681 }
682 
683 static void stex_scsi_done(struct st_ccb *ccb)
684 {
685 	struct scsi_cmnd *cmd = ccb->cmd;
686 	int result;
687 
688 	if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
689 		result = ccb->scsi_status;
690 		switch (ccb->scsi_status) {
691 		case SAM_STAT_GOOD:
692 			result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
693 			break;
694 		case SAM_STAT_CHECK_CONDITION:
695 			result |= DRIVER_SENSE << 24;
696 			break;
697 		case SAM_STAT_BUSY:
698 			result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
699 			break;
700 		default:
701 			result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
702 			break;
703 		}
704 	}
705 	else if (ccb->srb_status & SRB_SEE_SENSE)
706 		result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
707 	else switch (ccb->srb_status) {
708 		case SRB_STATUS_SELECTION_TIMEOUT:
709 			result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
710 			break;
711 		case SRB_STATUS_BUSY:
712 			result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
713 			break;
714 		case SRB_STATUS_INVALID_REQUEST:
715 		case SRB_STATUS_ERROR:
716 		default:
717 			result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
718 			break;
719 	}
720 
721 	cmd->result = result;
722 	cmd->scsi_done(cmd);
723 }
724 
725 static void stex_copy_data(struct st_ccb *ccb,
726 	struct status_msg *resp, unsigned int variable)
727 {
728 	size_t count = variable;
729 	if (resp->scsi_status != SAM_STAT_GOOD) {
730 		if (ccb->sense_buffer != NULL)
731 			memcpy(ccb->sense_buffer, resp->variable,
732 				min(variable, ccb->sense_bufflen));
733 		return;
734 	}
735 
736 	if (ccb->cmd == NULL)
737 		return;
738 	stex_internal_copy(ccb->cmd,
739 		resp->variable, &count, ccb->sg_count, ST_TO_CMD);
740 }
741 
742 static void stex_ys_commands(struct st_hba *hba,
743 	struct st_ccb *ccb, struct status_msg *resp)
744 {
745 	size_t count;
746 
747 	if (ccb->cmd->cmnd[0] == MGT_CMD &&
748 		resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
749 		ccb->cmd->request_bufflen =
750 			le32_to_cpu(*(__le32 *)&resp->variable[0]);
751 		return;
752 	}
753 
754 	if (resp->srb_status != 0)
755 		return;
756 
757 	/* determine inquiry command status by DeviceTypeQualifier */
758 	if (ccb->cmd->cmnd[0] == INQUIRY &&
759 		resp->scsi_status == SAM_STAT_GOOD) {
760 		ST_INQ *inq_data;
761 
762 		count = STEX_EXTRA_SIZE;
763 		stex_internal_copy(ccb->cmd, hba->copy_buffer,
764 			&count, ccb->sg_count, ST_FROM_CMD);
765 		inq_data = (ST_INQ *)hba->copy_buffer;
766 		if (inq_data->DeviceTypeQualifier != 0)
767 			ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
768 		else
769 			ccb->srb_status = SRB_STATUS_SUCCESS;
770 	} else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
771 		u8 *report_lun_data = (u8 *)hba->copy_buffer;
772 
773 		count = STEX_EXTRA_SIZE;
774 		stex_internal_copy(ccb->cmd, report_lun_data,
775 			&count, ccb->sg_count, ST_FROM_CMD);
776 		if (report_lun_data[2] || report_lun_data[3]) {
777 			report_lun_data[2] = 0x00;
778 			report_lun_data[3] = 0x08;
779 			stex_internal_copy(ccb->cmd, report_lun_data,
780 				&count, ccb->sg_count, ST_TO_CMD);
781 		}
782 	}
783 }
784 
785 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
786 {
787 	void __iomem *base = hba->mmio_base;
788 	struct status_msg *resp;
789 	struct st_ccb *ccb;
790 	unsigned int size;
791 	u16 tag;
792 
793 	if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
794 		return;
795 
796 	/* status payloads */
797 	hba->status_head = readl(base + OMR1);
798 	if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
799 		printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
800 			pci_name(hba->pdev));
801 		return;
802 	}
803 
804 	/*
805 	 * it's not a valid status payload if:
806 	 * 1. there are no pending requests(e.g. during init stage)
807 	 * 2. there are some pending requests, but the controller is in
808 	 *     reset status, and its type is not st_yosemite
809 	 * firmware of st_yosemite in reset status will return pending requests
810 	 * to driver, so we allow it to pass
811 	 */
812 	if (unlikely(hba->out_req_cnt <= 0 ||
813 			(hba->mu_status == MU_STATE_RESETTING &&
814 			 hba->cardtype != st_yosemite))) {
815 		hba->status_tail = hba->status_head;
816 		goto update_status;
817 	}
818 
819 	while (hba->status_tail != hba->status_head) {
820 		resp = stex_get_status(hba);
821 		tag = le16_to_cpu(resp->tag);
822 		if (unlikely(tag >= hba->host->can_queue)) {
823 			printk(KERN_WARNING DRV_NAME
824 				"(%s): invalid tag\n", pci_name(hba->pdev));
825 			continue;
826 		}
827 
828 		ccb = &hba->ccb[tag];
829 		if (hba->wait_ccb == ccb)
830 			hba->wait_ccb = NULL;
831 		if (unlikely(ccb->req == NULL)) {
832 			printk(KERN_WARNING DRV_NAME
833 				"(%s): lagging req\n", pci_name(hba->pdev));
834 			hba->out_req_cnt--;
835 			continue;
836 		}
837 
838 		size = resp->payload_sz * sizeof(u32); /* payload size */
839 		if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
840 			size > sizeof(*resp))) {
841 			printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
842 				pci_name(hba->pdev));
843 		} else {
844 			size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
845 			if (size)
846 				stex_copy_data(ccb, resp, size);
847 		}
848 
849 		ccb->srb_status = resp->srb_status;
850 		ccb->scsi_status = resp->scsi_status;
851 
852 		if (likely(ccb->cmd != NULL)) {
853 			if (hba->cardtype == st_yosemite)
854 				stex_ys_commands(hba, ccb, resp);
855 
856 			if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
857 				ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
858 				stex_controller_info(hba, ccb);
859 
860 			stex_unmap_sg(hba, ccb->cmd);
861 			stex_scsi_done(ccb);
862 			hba->out_req_cnt--;
863 		} else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
864 			hba->out_req_cnt--;
865 			if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
866 				ccb->req_type = 0;
867 				continue;
868 			}
869 			ccb->req_type = 0;
870 			if (waitqueue_active(&hba->waitq))
871 				wake_up(&hba->waitq);
872 		}
873 	}
874 
875 update_status:
876 	writel(hba->status_head, base + IMR1);
877 	readl(base + IMR1); /* flush */
878 }
879 
880 static irqreturn_t stex_intr(int irq, void *__hba)
881 {
882 	struct st_hba *hba = __hba;
883 	void __iomem *base = hba->mmio_base;
884 	u32 data;
885 	unsigned long flags;
886 	int handled = 0;
887 
888 	spin_lock_irqsave(hba->host->host_lock, flags);
889 
890 	data = readl(base + ODBL);
891 
892 	if (data && data != 0xffffffff) {
893 		/* clear the interrupt */
894 		writel(data, base + ODBL);
895 		readl(base + ODBL); /* flush */
896 		stex_mu_intr(hba, data);
897 		handled = 1;
898 	}
899 
900 	spin_unlock_irqrestore(hba->host->host_lock, flags);
901 
902 	return IRQ_RETVAL(handled);
903 }
904 
905 static int stex_handshake(struct st_hba *hba)
906 {
907 	void __iomem *base = hba->mmio_base;
908 	struct handshake_frame *h;
909 	dma_addr_t status_phys;
910 	u32 data;
911 	unsigned long before;
912 
913 	if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
914 		writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
915 		readl(base + IDBL);
916 		before = jiffies;
917 		while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
918 			if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
919 				printk(KERN_ERR DRV_NAME
920 					"(%s): no handshake signature\n",
921 					pci_name(hba->pdev));
922 				return -1;
923 			}
924 			rmb();
925 			msleep(1);
926 		}
927 	}
928 
929 	udelay(10);
930 
931 	data = readl(base + OMR1);
932 	if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
933 		data &= 0x0000ffff;
934 		if (hba->host->can_queue > data)
935 			hba->host->can_queue = data;
936 	}
937 
938 	h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
939 	h->rb_phy = cpu_to_le32(hba->dma_handle);
940 	h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
941 	h->req_sz = cpu_to_le16(sizeof(struct req_msg));
942 	h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
943 	h->status_sz = cpu_to_le16(sizeof(struct status_msg));
944 	h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
945 	stex_gettime(&h->hosttime);
946 	h->partner_type = HMU_PARTNER_TYPE;
947 	if (hba->dma_size > STEX_BUFFER_SIZE) {
948 		h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
949 		h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
950 	} else
951 		h->extra_offset = h->extra_size = 0;
952 
953 	status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
954 	writel(status_phys, base + IMR0);
955 	readl(base + IMR0);
956 	writel((status_phys >> 16) >> 16, base + IMR1);
957 	readl(base + IMR1);
958 
959 	writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
960 	readl(base + OMR0);
961 	writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
962 	readl(base + IDBL); /* flush */
963 
964 	udelay(10);
965 	before = jiffies;
966 	while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
967 		if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
968 			printk(KERN_ERR DRV_NAME
969 				"(%s): no signature after handshake frame\n",
970 				pci_name(hba->pdev));
971 			return -1;
972 		}
973 		rmb();
974 		msleep(1);
975 	}
976 
977 	writel(0, base + IMR0);
978 	readl(base + IMR0);
979 	writel(0, base + OMR0);
980 	readl(base + OMR0);
981 	writel(0, base + IMR1);
982 	readl(base + IMR1);
983 	writel(0, base + OMR1);
984 	readl(base + OMR1); /* flush */
985 	hba->mu_status = MU_STATE_STARTED;
986 	return 0;
987 }
988 
989 static int stex_abort(struct scsi_cmnd *cmd)
990 {
991 	struct Scsi_Host *host = cmd->device->host;
992 	struct st_hba *hba = (struct st_hba *)host->hostdata;
993 	u16 tag = cmd->request->tag;
994 	void __iomem *base;
995 	u32 data;
996 	int result = SUCCESS;
997 	unsigned long flags;
998 	base = hba->mmio_base;
999 	spin_lock_irqsave(host->host_lock, flags);
1000 	if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
1001 		hba->wait_ccb = &hba->ccb[tag];
1002 	else {
1003 		for (tag = 0; tag < host->can_queue; tag++)
1004 			if (hba->ccb[tag].cmd == cmd) {
1005 				hba->wait_ccb = &hba->ccb[tag];
1006 				break;
1007 			}
1008 		if (tag >= host->can_queue)
1009 			goto out;
1010 	}
1011 
1012 	data = readl(base + ODBL);
1013 	if (data == 0 || data == 0xffffffff)
1014 		goto fail_out;
1015 
1016 	writel(data, base + ODBL);
1017 	readl(base + ODBL); /* flush */
1018 
1019 	stex_mu_intr(hba, data);
1020 
1021 	if (hba->wait_ccb == NULL) {
1022 		printk(KERN_WARNING DRV_NAME
1023 			"(%s): lost interrupt\n", pci_name(hba->pdev));
1024 		goto out;
1025 	}
1026 
1027 fail_out:
1028 	stex_unmap_sg(hba, cmd);
1029 	hba->wait_ccb->req = NULL; /* nullify the req's future return */
1030 	hba->wait_ccb = NULL;
1031 	result = FAILED;
1032 out:
1033 	spin_unlock_irqrestore(host->host_lock, flags);
1034 	return result;
1035 }
1036 
1037 static void stex_hard_reset(struct st_hba *hba)
1038 {
1039 	struct pci_bus *bus;
1040 	int i;
1041 	u16 pci_cmd;
1042 	u8 pci_bctl;
1043 
1044 	for (i = 0; i < 16; i++)
1045 		pci_read_config_dword(hba->pdev, i * 4,
1046 			&hba->pdev->saved_config_space[i]);
1047 
1048 	/* Reset secondary bus. Our controller(MU/ATU) is the only device on
1049 	   secondary bus. Consult Intel 80331/3 developer's manual for detail */
1050 	bus = hba->pdev->bus;
1051 	pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1052 	pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1053 	pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1054 	msleep(1);
1055 	pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1056 	pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1057 
1058 	for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1059 		pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1060 		if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1061 			break;
1062 		msleep(1);
1063 	}
1064 
1065 	ssleep(5);
1066 	for (i = 0; i < 16; i++)
1067 		pci_write_config_dword(hba->pdev, i * 4,
1068 			hba->pdev->saved_config_space[i]);
1069 }
1070 
1071 static int stex_reset(struct scsi_cmnd *cmd)
1072 {
1073 	struct st_hba *hba;
1074 	unsigned long flags;
1075 	unsigned long before;
1076 	hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1077 
1078 	hba->mu_status = MU_STATE_RESETTING;
1079 
1080 	if (hba->cardtype == st_shasta)
1081 		stex_hard_reset(hba);
1082 
1083 	if (hba->cardtype != st_yosemite) {
1084 		if (stex_handshake(hba)) {
1085 			printk(KERN_WARNING DRV_NAME
1086 				"(%s): resetting: handshake failed\n",
1087 				pci_name(hba->pdev));
1088 			return FAILED;
1089 		}
1090 		spin_lock_irqsave(hba->host->host_lock, flags);
1091 		hba->req_head = 0;
1092 		hba->req_tail = 0;
1093 		hba->status_head = 0;
1094 		hba->status_tail = 0;
1095 		hba->out_req_cnt = 0;
1096 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1097 		return SUCCESS;
1098 	}
1099 
1100 	/* st_yosemite */
1101 	writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1102 	readl(hba->mmio_base + IDBL); /* flush */
1103 	before = jiffies;
1104 	while (hba->out_req_cnt > 0) {
1105 		if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1106 			printk(KERN_WARNING DRV_NAME
1107 				"(%s): reset timeout\n", pci_name(hba->pdev));
1108 			return FAILED;
1109 		}
1110 		msleep(1);
1111 	}
1112 
1113 	hba->mu_status = MU_STATE_STARTED;
1114 	return SUCCESS;
1115 }
1116 
1117 static int stex_biosparam(struct scsi_device *sdev,
1118 	struct block_device *bdev, sector_t capacity, int geom[])
1119 {
1120 	int heads = 255, sectors = 63;
1121 
1122 	if (capacity < 0x200000) {
1123 		heads = 64;
1124 		sectors = 32;
1125 	}
1126 
1127 	sector_div(capacity, heads * sectors);
1128 
1129 	geom[0] = heads;
1130 	geom[1] = sectors;
1131 	geom[2] = capacity;
1132 
1133 	return 0;
1134 }
1135 
1136 static struct scsi_host_template driver_template = {
1137 	.module				= THIS_MODULE,
1138 	.name				= DRV_NAME,
1139 	.proc_name			= DRV_NAME,
1140 	.bios_param			= stex_biosparam,
1141 	.queuecommand			= stex_queuecommand,
1142 	.slave_alloc			= stex_slave_alloc,
1143 	.slave_configure		= stex_slave_config,
1144 	.slave_destroy			= stex_slave_destroy,
1145 	.eh_abort_handler		= stex_abort,
1146 	.eh_host_reset_handler		= stex_reset,
1147 	.can_queue			= ST_CAN_QUEUE,
1148 	.this_id			= -1,
1149 	.sg_tablesize			= ST_MAX_SG,
1150 	.cmd_per_lun			= ST_CMD_PER_LUN,
1151 };
1152 
1153 static int stex_set_dma_mask(struct pci_dev * pdev)
1154 {
1155 	int ret;
1156 	if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1157 		&& !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1158 		return 0;
1159 	ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1160 	if (!ret)
1161 		ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1162 	return ret;
1163 }
1164 
1165 static int __devinit
1166 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1167 {
1168 	struct st_hba *hba;
1169 	struct Scsi_Host *host;
1170 	int err;
1171 
1172 	err = pci_enable_device(pdev);
1173 	if (err)
1174 		return err;
1175 
1176 	pci_set_master(pdev);
1177 
1178 	host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1179 
1180 	if (!host) {
1181 		printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1182 			pci_name(pdev));
1183 		err = -ENOMEM;
1184 		goto out_disable;
1185 	}
1186 
1187 	hba = (struct st_hba *)host->hostdata;
1188 	memset(hba, 0, sizeof(struct st_hba));
1189 
1190 	err = pci_request_regions(pdev, DRV_NAME);
1191 	if (err < 0) {
1192 		printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1193 			pci_name(pdev));
1194 		goto out_scsi_host_put;
1195 	}
1196 
1197 	hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1198 		pci_resource_len(pdev, 0));
1199 	if ( !hba->mmio_base) {
1200 		printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1201 			pci_name(pdev));
1202 		err = -ENOMEM;
1203 		goto out_release_regions;
1204 	}
1205 
1206 	err = stex_set_dma_mask(pdev);
1207 	if (err) {
1208 		printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1209 			pci_name(pdev));
1210 		goto out_iounmap;
1211 	}
1212 
1213 	hba->cardtype = (unsigned int) id->driver_data;
1214 	if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1215 		hba->cardtype = st_vsc1;
1216 	hba->dma_size = (hba->cardtype == st_vsc1) ?
1217 		(STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1218 	hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1219 		hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1220 	if (!hba->dma_mem) {
1221 		err = -ENOMEM;
1222 		printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1223 			pci_name(pdev));
1224 		goto out_iounmap;
1225 	}
1226 
1227 	hba->status_buffer =
1228 		(struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1229 	hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1230 	hba->mu_status = MU_STATE_STARTING;
1231 
1232 	/* firmware uses id/lun pair for a logical drive, but lun would be
1233 	   always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
1234 	   channel to map lun here */
1235 	host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
1236 	host->max_id = ST_MAX_TARGET_NUM;
1237 	host->max_lun = 1;
1238 	host->unique_id = host->host_no;
1239 	host->max_cmd_len = STEX_CDB_LENGTH;
1240 
1241 	hba->host = host;
1242 	hba->pdev = pdev;
1243 	init_waitqueue_head(&hba->waitq);
1244 
1245 	err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1246 	if (err) {
1247 		printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1248 			pci_name(pdev));
1249 		goto out_pci_free;
1250 	}
1251 
1252 	err = stex_handshake(hba);
1253 	if (err)
1254 		goto out_free_irq;
1255 
1256 	err = scsi_init_shared_tag_map(host, host->can_queue);
1257 	if (err) {
1258 		printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1259 			pci_name(pdev));
1260 		goto out_free_irq;
1261 	}
1262 
1263 	pci_set_drvdata(pdev, hba);
1264 
1265 	err = scsi_add_host(host, &pdev->dev);
1266 	if (err) {
1267 		printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1268 			pci_name(pdev));
1269 		goto out_free_irq;
1270 	}
1271 
1272 	scsi_scan_host(host);
1273 
1274 	return 0;
1275 
1276 out_free_irq:
1277 	free_irq(pdev->irq, hba);
1278 out_pci_free:
1279 	dma_free_coherent(&pdev->dev, hba->dma_size,
1280 			  hba->dma_mem, hba->dma_handle);
1281 out_iounmap:
1282 	iounmap(hba->mmio_base);
1283 out_release_regions:
1284 	pci_release_regions(pdev);
1285 out_scsi_host_put:
1286 	scsi_host_put(host);
1287 out_disable:
1288 	pci_disable_device(pdev);
1289 
1290 	return err;
1291 }
1292 
1293 static void stex_hba_stop(struct st_hba *hba)
1294 {
1295 	struct req_msg *req;
1296 	unsigned long flags;
1297 	unsigned long before;
1298 	u16 tag = 0;
1299 
1300 	spin_lock_irqsave(hba->host->host_lock, flags);
1301 	req = stex_alloc_req(hba);
1302 	memset(req->cdb, 0, STEX_CDB_LENGTH);
1303 
1304 	if (hba->cardtype == st_yosemite) {
1305 		req->cdb[0] = MGT_CMD;
1306 		req->cdb[1] = MGT_CMD_SIGNATURE;
1307 		req->cdb[2] = CTLR_CONFIG_CMD;
1308 		req->cdb[3] = CTLR_SHUTDOWN;
1309 	} else {
1310 		req->cdb[0] = CONTROLLER_CMD;
1311 		req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1312 		req->cdb[2] = CTLR_POWER_SAVING;
1313 	}
1314 
1315 	hba->ccb[tag].cmd = NULL;
1316 	hba->ccb[tag].sg_count = 0;
1317 	hba->ccb[tag].sense_bufflen = 0;
1318 	hba->ccb[tag].sense_buffer = NULL;
1319 	hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1320 
1321 	stex_send_cmd(hba, req, tag);
1322 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1323 
1324 	before = jiffies;
1325 	while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1326 		if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1327 			return;
1328 		msleep(10);
1329 	}
1330 }
1331 
1332 static void stex_hba_free(struct st_hba *hba)
1333 {
1334 	free_irq(hba->pdev->irq, hba);
1335 
1336 	iounmap(hba->mmio_base);
1337 
1338 	pci_release_regions(hba->pdev);
1339 
1340 	dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1341 			  hba->dma_mem, hba->dma_handle);
1342 }
1343 
1344 static void stex_remove(struct pci_dev *pdev)
1345 {
1346 	struct st_hba *hba = pci_get_drvdata(pdev);
1347 
1348 	scsi_remove_host(hba->host);
1349 
1350 	pci_set_drvdata(pdev, NULL);
1351 
1352 	stex_hba_stop(hba);
1353 
1354 	stex_hba_free(hba);
1355 
1356 	scsi_host_put(hba->host);
1357 
1358 	pci_disable_device(pdev);
1359 }
1360 
1361 static void stex_shutdown(struct pci_dev *pdev)
1362 {
1363 	struct st_hba *hba = pci_get_drvdata(pdev);
1364 
1365 	stex_hba_stop(hba);
1366 }
1367 
1368 static struct pci_device_id stex_pci_tbl[] = {
1369 	/* st_shasta */
1370 	{ 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1371 		st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1372 	{ 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1373 		st_shasta }, /* SuperTrak EX12350 */
1374 	{ 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1375 		st_shasta }, /* SuperTrak EX4350 */
1376 	{ 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1377 		st_shasta }, /* SuperTrak EX24350 */
1378 
1379 	/* st_vsc */
1380 	{ 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1381 
1382 	/* st_yosemite */
1383 	{ 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1384 		st_yosemite }, /* SuperTrak EX4650 */
1385 	{ 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1386 		st_yosemite }, /* SuperTrak EX4650o */
1387 	{ 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1388 		st_yosemite }, /* SuperTrak EX8650EL */
1389 	{ 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1390 		st_yosemite }, /* SuperTrak EX8650 */
1391 	{ 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1392 		st_yosemite }, /* SuperTrak EX8654 */
1393 	{ 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1394 		st_yosemite }, /* generic st_yosemite */
1395 	{ }	/* terminate list */
1396 };
1397 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1398 
1399 static struct pci_driver stex_pci_driver = {
1400 	.name		= DRV_NAME,
1401 	.id_table	= stex_pci_tbl,
1402 	.probe		= stex_probe,
1403 	.remove		= __devexit_p(stex_remove),
1404 	.shutdown	= stex_shutdown,
1405 };
1406 
1407 static int __init stex_init(void)
1408 {
1409 	printk(KERN_INFO DRV_NAME
1410 		": Promise SuperTrak EX Driver version: %s\n",
1411 		 ST_DRIVER_VERSION);
1412 
1413 	return pci_register_driver(&stex_pci_driver);
1414 }
1415 
1416 static void __exit stex_exit(void)
1417 {
1418 	pci_unregister_driver(&stex_pci_driver);
1419 }
1420 
1421 module_init(stex_init);
1422 module_exit(stex_exit);
1423