1*dfb99b05SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2*dfb99b05SThomas Gleixner /* Copyright 2014 Cisco Systems, Inc. All rights reserved. */ 3c8806b6cSNarsimhulu Musini 4c8806b6cSNarsimhulu Musini #ifndef __SNIC_STATS_H 5c8806b6cSNarsimhulu Musini #define __SNIC_STATS_H 6c8806b6cSNarsimhulu Musini 7c8806b6cSNarsimhulu Musini struct snic_io_stats { 8c8806b6cSNarsimhulu Musini atomic64_t active; /* Active IOs */ 9c8806b6cSNarsimhulu Musini atomic64_t max_active; /* Max # active IOs */ 10c8806b6cSNarsimhulu Musini atomic64_t max_sgl; /* Max # SGLs for any IO */ 11c8806b6cSNarsimhulu Musini atomic64_t max_time; /* Max time to process IO */ 12c8806b6cSNarsimhulu Musini atomic64_t max_qtime; /* Max time to Queue the IO */ 13c8806b6cSNarsimhulu Musini atomic64_t max_cmpl_time; /* Max time to complete the IO */ 14c8806b6cSNarsimhulu Musini atomic64_t sgl_cnt[SNIC_MAX_SG_DESC_CNT]; /* SGL Counters */ 15c8806b6cSNarsimhulu Musini atomic64_t max_io_sz; /* Max IO Size */ 16c8806b6cSNarsimhulu Musini atomic64_t compl; /* IO Completions */ 17c8806b6cSNarsimhulu Musini atomic64_t fail; /* IO Failures */ 18c8806b6cSNarsimhulu Musini atomic64_t req_null; /* req or req info is NULL */ 19c8806b6cSNarsimhulu Musini atomic64_t alloc_fail; /* Alloc Failures */ 20c8806b6cSNarsimhulu Musini atomic64_t sc_null; 21c8806b6cSNarsimhulu Musini atomic64_t io_not_found; /* IO Not Found */ 22c8806b6cSNarsimhulu Musini atomic64_t num_ios; /* Number of IOs */ 23c8806b6cSNarsimhulu Musini }; 24c8806b6cSNarsimhulu Musini 25c8806b6cSNarsimhulu Musini struct snic_abort_stats { 26c8806b6cSNarsimhulu Musini atomic64_t num; /* Abort counter */ 27c8806b6cSNarsimhulu Musini atomic64_t fail; /* Abort Failure Counter */ 28c8806b6cSNarsimhulu Musini atomic64_t drv_tmo; /* Abort Driver Timeouts */ 29c8806b6cSNarsimhulu Musini atomic64_t fw_tmo; /* Abort Firmware Timeouts */ 30c8806b6cSNarsimhulu Musini atomic64_t io_not_found;/* Abort IO Not Found */ 313f5c11a4SNarsimhulu Musini atomic64_t q_fail; /* Abort Queuing Failed */ 32c8806b6cSNarsimhulu Musini }; 33c8806b6cSNarsimhulu Musini 34c8806b6cSNarsimhulu Musini struct snic_reset_stats { 35c8806b6cSNarsimhulu Musini atomic64_t dev_resets; /* Device Reset Counter */ 36c8806b6cSNarsimhulu Musini atomic64_t dev_reset_fail; /* Device Reset Failures */ 37c8806b6cSNarsimhulu Musini atomic64_t dev_reset_aborts; /* Device Reset Aborts */ 38c8806b6cSNarsimhulu Musini atomic64_t dev_reset_tmo; /* Device Reset Timeout */ 39c8806b6cSNarsimhulu Musini atomic64_t dev_reset_terms; /* Device Reset terminate */ 40c8806b6cSNarsimhulu Musini atomic64_t hba_resets; /* hba/firmware resets */ 41c8806b6cSNarsimhulu Musini atomic64_t hba_reset_cmpl; /* hba/firmware reset completions */ 42c8806b6cSNarsimhulu Musini atomic64_t hba_reset_fail; /* hba/firmware failures */ 43c8806b6cSNarsimhulu Musini atomic64_t snic_resets; /* snic resets */ 44c8806b6cSNarsimhulu Musini atomic64_t snic_reset_compl; /* snic reset completions */ 45c8806b6cSNarsimhulu Musini atomic64_t snic_reset_fail; /* snic reset failures */ 46c8806b6cSNarsimhulu Musini }; 47c8806b6cSNarsimhulu Musini 48c8806b6cSNarsimhulu Musini struct snic_fw_stats { 49c8806b6cSNarsimhulu Musini atomic64_t actv_reqs; /* Active Requests */ 50c8806b6cSNarsimhulu Musini atomic64_t max_actv_reqs; /* Max Active Requests */ 51c8806b6cSNarsimhulu Musini atomic64_t out_of_res; /* Firmware Out Of Resources */ 52c8806b6cSNarsimhulu Musini atomic64_t io_errs; /* Firmware IO Firmware Errors */ 53c8806b6cSNarsimhulu Musini atomic64_t scsi_errs; /* Target hits check condition */ 54c8806b6cSNarsimhulu Musini }; 55c8806b6cSNarsimhulu Musini 56c8806b6cSNarsimhulu Musini struct snic_misc_stats { 57c8806b6cSNarsimhulu Musini u64 last_isr_time; 58c8806b6cSNarsimhulu Musini u64 last_ack_time; 593f5c11a4SNarsimhulu Musini atomic64_t ack_isr_cnt; 603f5c11a4SNarsimhulu Musini atomic64_t cmpl_isr_cnt; 613f5c11a4SNarsimhulu Musini atomic64_t errnotify_isr_cnt; 62c8806b6cSNarsimhulu Musini atomic64_t max_cq_ents; /* Max CQ Entries */ 63c8806b6cSNarsimhulu Musini atomic64_t data_cnt_mismat; /* Data Count Mismatch */ 64c8806b6cSNarsimhulu Musini atomic64_t io_tmo; 65c8806b6cSNarsimhulu Musini atomic64_t io_aborted; 66c8806b6cSNarsimhulu Musini atomic64_t sgl_inval; /* SGL Invalid */ 67c8806b6cSNarsimhulu Musini atomic64_t abts_wq_alloc_fail; /* Abort Path WQ desc alloc failure */ 68c8806b6cSNarsimhulu Musini atomic64_t devrst_wq_alloc_fail;/* Device Reset - WQ desc alloc fail */ 69c8806b6cSNarsimhulu Musini atomic64_t wq_alloc_fail; /* IO WQ desc alloc failure */ 70c8806b6cSNarsimhulu Musini atomic64_t no_icmnd_itmf_cmpls; 71c8806b6cSNarsimhulu Musini atomic64_t io_under_run; 72c8806b6cSNarsimhulu Musini atomic64_t qfull; 733f5c11a4SNarsimhulu Musini atomic64_t qsz_rampup; 743f5c11a4SNarsimhulu Musini atomic64_t qsz_rampdown; 753f5c11a4SNarsimhulu Musini atomic64_t last_qsz; 76c8806b6cSNarsimhulu Musini atomic64_t tgt_not_rdy; 77c8806b6cSNarsimhulu Musini }; 78c8806b6cSNarsimhulu Musini 79c8806b6cSNarsimhulu Musini struct snic_stats { 80c8806b6cSNarsimhulu Musini struct snic_io_stats io; 81c8806b6cSNarsimhulu Musini struct snic_abort_stats abts; 82c8806b6cSNarsimhulu Musini struct snic_reset_stats reset; 83c8806b6cSNarsimhulu Musini struct snic_fw_stats fw; 84c8806b6cSNarsimhulu Musini struct snic_misc_stats misc; 85c8806b6cSNarsimhulu Musini atomic64_t io_cmpl_skip; 86c8806b6cSNarsimhulu Musini }; 87c8806b6cSNarsimhulu Musini 88fd84ec20SGreg Kroah-Hartman void snic_stats_debugfs_init(struct snic *); 89c8806b6cSNarsimhulu Musini void snic_stats_debugfs_remove(struct snic *); 90c8806b6cSNarsimhulu Musini 91c8806b6cSNarsimhulu Musini /* Auxillary function to update active IO counter */ 92c8806b6cSNarsimhulu Musini static inline void snic_stats_update_active_ios(struct snic_stats * s_stats)93c8806b6cSNarsimhulu Musinisnic_stats_update_active_ios(struct snic_stats *s_stats) 94c8806b6cSNarsimhulu Musini { 95c8806b6cSNarsimhulu Musini struct snic_io_stats *io = &s_stats->io; 963f5c11a4SNarsimhulu Musini int nr_active_ios; 97c8806b6cSNarsimhulu Musini 983f5c11a4SNarsimhulu Musini nr_active_ios = atomic64_read(&io->active); 99c8806b6cSNarsimhulu Musini if (atomic64_read(&io->max_active) < nr_active_ios) 100c8806b6cSNarsimhulu Musini atomic64_set(&io->max_active, nr_active_ios); 101c8806b6cSNarsimhulu Musini 102c8806b6cSNarsimhulu Musini atomic64_inc(&io->num_ios); 103c8806b6cSNarsimhulu Musini } 104c8806b6cSNarsimhulu Musini 105c8806b6cSNarsimhulu Musini /* Auxillary function to update IO completion counter */ 106c8806b6cSNarsimhulu Musini static inline void snic_stats_update_io_cmpl(struct snic_stats * s_stats)107c8806b6cSNarsimhulu Musinisnic_stats_update_io_cmpl(struct snic_stats *s_stats) 108c8806b6cSNarsimhulu Musini { 109c8806b6cSNarsimhulu Musini atomic64_dec(&s_stats->io.active); 110c8806b6cSNarsimhulu Musini if (unlikely(atomic64_read(&s_stats->io_cmpl_skip))) 111c8806b6cSNarsimhulu Musini atomic64_dec(&s_stats->io_cmpl_skip); 112c8806b6cSNarsimhulu Musini else 113c8806b6cSNarsimhulu Musini atomic64_inc(&s_stats->io.compl); 114c8806b6cSNarsimhulu Musini } 115c8806b6cSNarsimhulu Musini #endif /* __SNIC_STATS_H */ 116