1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 1; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 51 52 /* 53 * CT6 CTX allocation cache 54 */ 55 static struct kmem_cache *ctx_cachep; 56 /* 57 * error level for logging 58 */ 59 uint ql_errlev = 0x8001; 60 61 int ql2xsecenable; 62 module_param(ql2xsecenable, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xsecenable, 64 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 65 66 static int ql2xenableclass2; 67 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 68 MODULE_PARM_DESC(ql2xenableclass2, 69 "Specify if Class 2 operations are supported from the very " 70 "beginning. Default is 0 - class 2 not supported."); 71 72 73 int ql2xlogintimeout = 20; 74 module_param(ql2xlogintimeout, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xlogintimeout, 76 "Login timeout value in seconds."); 77 78 int qlport_down_retry; 79 module_param(qlport_down_retry, int, S_IRUGO); 80 MODULE_PARM_DESC(qlport_down_retry, 81 "Maximum number of command retries to a port that returns " 82 "a PORT-DOWN status."); 83 84 int ql2xplogiabsentdevice; 85 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 86 MODULE_PARM_DESC(ql2xplogiabsentdevice, 87 "Option to enable PLOGI to devices that are not present after " 88 "a Fabric scan. This is needed for several broken switches. " 89 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 90 91 int ql2xloginretrycount; 92 module_param(ql2xloginretrycount, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xloginretrycount, 94 "Specify an alternate value for the NVRAM login retry count."); 95 96 int ql2xallocfwdump = 1; 97 module_param(ql2xallocfwdump, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xallocfwdump, 99 "Option to enable allocation of memory for a firmware dump " 100 "during HBA initialization. Memory allocation requirements " 101 "vary by ISP type. Default is 1 - allocate memory."); 102 103 int ql2xextended_error_logging; 104 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 105 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 MODULE_PARM_DESC(ql2xextended_error_logging, 107 "Option to enable extended error logging,\n" 108 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 109 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 110 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 111 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 112 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 113 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 114 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 115 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 116 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 117 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 118 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 119 "\t\t0x1e400000 - Preferred value for capturing essential " 120 "debug information (equivalent to old " 121 "ql2xextended_error_logging=1).\n" 122 "\t\tDo LOGICAL OR of the value to enable more than one level"); 123 124 int ql2xextended_error_logging_ktrace = 1; 125 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 126 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 127 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 128 129 int ql2xshiftctondsd = 6; 130 module_param(ql2xshiftctondsd, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xshiftctondsd, 132 "Set to control shifting of command type processing " 133 "based on total number of SG elements."); 134 135 int ql2xfdmienable = 1; 136 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 137 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 MODULE_PARM_DESC(ql2xfdmienable, 139 "Enables FDMI registrations. " 140 "0 - no FDMI registrations. " 141 "1 - provide FDMI registrations (default)."); 142 143 #define MAX_Q_DEPTH 64 144 static int ql2xmaxqdepth = MAX_Q_DEPTH; 145 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 146 MODULE_PARM_DESC(ql2xmaxqdepth, 147 "Maximum queue depth to set for each LUN. " 148 "Default is 64."); 149 150 int ql2xenabledif = 2; 151 module_param(ql2xenabledif, int, S_IRUGO); 152 MODULE_PARM_DESC(ql2xenabledif, 153 " Enable T10-CRC-DIF:\n" 154 " Default is 2.\n" 155 " 0 -- No DIF Support\n" 156 " 1 -- Enable DIF for all types\n" 157 " 2 -- Enable DIF for all types, except Type 0.\n"); 158 159 #if (IS_ENABLED(CONFIG_NVME_FC)) 160 int ql2xnvmeenable = 1; 161 #else 162 int ql2xnvmeenable; 163 #endif 164 module_param(ql2xnvmeenable, int, 0644); 165 MODULE_PARM_DESC(ql2xnvmeenable, 166 "Enables NVME support. " 167 "0 - no NVMe. Default is Y"); 168 169 int ql2xenablehba_err_chk = 2; 170 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xenablehba_err_chk, 172 " Enable T10-CRC-DIF Error isolation by HBA:\n" 173 " Default is 2.\n" 174 " 0 -- Error isolation disabled\n" 175 " 1 -- Error isolation enabled only for DIX Type 0\n" 176 " 2 -- Error isolation enabled for all Types\n"); 177 178 int ql2xiidmaenable = 1; 179 module_param(ql2xiidmaenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xiidmaenable, 181 "Enables iIDMA settings " 182 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 183 184 int ql2xmqsupport = 1; 185 module_param(ql2xmqsupport, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xmqsupport, 187 "Enable on demand multiple queue pairs support " 188 "Default is 1 for supported. " 189 "Set it to 0 to turn off mq qpair support."); 190 191 int ql2xfwloadbin; 192 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 193 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xfwloadbin, 195 "Option to specify location from which to load ISP firmware:.\n" 196 " 2 -- load firmware via the request_firmware() (hotplug).\n" 197 " interface.\n" 198 " 1 -- load firmware from flash.\n" 199 " 0 -- use default semantics.\n"); 200 201 int ql2xetsenable; 202 module_param(ql2xetsenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xetsenable, 204 "Enables firmware ETS burst." 205 "Default is 0 - skip ETS enablement."); 206 207 int ql2xdbwr = 1; 208 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 209 MODULE_PARM_DESC(ql2xdbwr, 210 "Option to specify scheme for request queue posting.\n" 211 " 0 -- Regular doorbell.\n" 212 " 1 -- CAMRAM doorbell (faster).\n"); 213 214 int ql2xgffidenable; 215 module_param(ql2xgffidenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xgffidenable, 217 "Enables GFF_ID checks of port type. " 218 "Default is 0 - Do not use GFF_ID information."); 219 220 int ql2xasynctmfenable = 1; 221 module_param(ql2xasynctmfenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xasynctmfenable, 223 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 224 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 225 226 int ql2xdontresethba; 227 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 228 MODULE_PARM_DESC(ql2xdontresethba, 229 "Option to specify reset behaviour.\n" 230 " 0 (Default) -- Reset on failure.\n" 231 " 1 -- Do not reset on failure.\n"); 232 233 uint64_t ql2xmaxlun = MAX_LUNS; 234 module_param(ql2xmaxlun, ullong, S_IRUGO); 235 MODULE_PARM_DESC(ql2xmaxlun, 236 "Defines the maximum LU number to register with the SCSI " 237 "midlayer. Default is 65535."); 238 239 int ql2xmdcapmask = 0x1F; 240 module_param(ql2xmdcapmask, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xmdcapmask, 242 "Set the Minidump driver capture mask level. " 243 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 244 245 int ql2xmdenable = 1; 246 module_param(ql2xmdenable, int, S_IRUGO); 247 MODULE_PARM_DESC(ql2xmdenable, 248 "Enable/disable MiniDump. " 249 "0 - MiniDump disabled. " 250 "1 (Default) - MiniDump enabled."); 251 252 int ql2xexlogins; 253 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 254 MODULE_PARM_DESC(ql2xexlogins, 255 "Number of extended Logins. " 256 "0 (Default)- Disabled."); 257 258 int ql2xexchoffld = 1024; 259 module_param(ql2xexchoffld, uint, 0644); 260 MODULE_PARM_DESC(ql2xexchoffld, 261 "Number of target exchanges."); 262 263 int ql2xiniexchg = 1024; 264 module_param(ql2xiniexchg, uint, 0644); 265 MODULE_PARM_DESC(ql2xiniexchg, 266 "Number of initiator exchanges."); 267 268 int ql2xfwholdabts; 269 module_param(ql2xfwholdabts, int, S_IRUGO); 270 MODULE_PARM_DESC(ql2xfwholdabts, 271 "Allow FW to hold status IOCB until ABTS rsp received. " 272 "0 (Default) Do not set fw option. " 273 "1 - Set fw option to hold ABTS."); 274 275 int ql2xmvasynctoatio = 1; 276 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 277 MODULE_PARM_DESC(ql2xmvasynctoatio, 278 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 279 "0 (Default). Do not move IOCBs" 280 "1 - Move IOCBs."); 281 282 int ql2xautodetectsfp = 1; 283 module_param(ql2xautodetectsfp, int, 0444); 284 MODULE_PARM_DESC(ql2xautodetectsfp, 285 "Detect SFP range and set appropriate distance.\n" 286 "1 (Default): Enable\n"); 287 288 int ql2xenablemsix = 1; 289 module_param(ql2xenablemsix, int, 0444); 290 MODULE_PARM_DESC(ql2xenablemsix, 291 "Set to enable MSI or MSI-X interrupt mechanism.\n" 292 " Default is 1, enable MSI-X interrupt mechanism.\n" 293 " 0 -- enable traditional pin-based mechanism.\n" 294 " 1 -- enable MSI-X interrupt mechanism.\n" 295 " 2 -- enable MSI interrupt mechanism.\n"); 296 297 int qla2xuseresexchforels; 298 module_param(qla2xuseresexchforels, int, 0444); 299 MODULE_PARM_DESC(qla2xuseresexchforels, 300 "Reserve 1/2 of emergency exchanges for ELS.\n" 301 " 0 (default): disabled"); 302 303 static int ql2xprotmask; 304 module_param(ql2xprotmask, int, 0644); 305 MODULE_PARM_DESC(ql2xprotmask, 306 "Override DIF/DIX protection capabilities mask\n" 307 "Default is 0 which sets protection mask based on " 308 "capabilities reported by HBA firmware.\n"); 309 310 static int ql2xprotguard; 311 module_param(ql2xprotguard, int, 0644); 312 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 313 " 0 -- Let HBA firmware decide\n" 314 " 1 -- Force T10 CRC\n" 315 " 2 -- Force IP checksum\n"); 316 317 int ql2xdifbundlinginternalbuffers; 318 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 319 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 320 "Force using internal buffers for DIF information\n" 321 "0 (Default). Based on check.\n" 322 "1 Force using internal buffers\n"); 323 324 int ql2xsmartsan; 325 module_param(ql2xsmartsan, int, 0444); 326 module_param_named(smartsan, ql2xsmartsan, int, 0444); 327 MODULE_PARM_DESC(ql2xsmartsan, 328 "Send SmartSAN Management Attributes for FDMI Registration." 329 " Default is 0 - No SmartSAN registration," 330 " 1 - Register SmartSAN Management Attributes."); 331 332 int ql2xrdpenable; 333 module_param(ql2xrdpenable, int, 0444); 334 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 335 MODULE_PARM_DESC(ql2xrdpenable, 336 "Enables RDP responses. " 337 "0 - no RDP responses (default). " 338 "1 - provide RDP responses."); 339 int ql2xabts_wait_nvme = 1; 340 module_param(ql2xabts_wait_nvme, int, 0444); 341 MODULE_PARM_DESC(ql2xabts_wait_nvme, 342 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 343 344 345 static u32 ql2xdelay_before_pci_error_handling = 5; 346 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 347 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 348 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 349 350 static void qla2x00_clear_drv_active(struct qla_hw_data *); 351 static void qla2x00_free_device(scsi_qla_host_t *); 352 static void qla2xxx_map_queues(struct Scsi_Host *shost); 353 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 354 355 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 356 module_param(ql2xnvme_queues, uint, S_IRUGO); 357 MODULE_PARM_DESC(ql2xnvme_queues, 358 "Number of NVMe Queues that can be configured.\n" 359 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 360 "1 - Minimum number of queues supported\n" 361 "8 - Default value"); 362 363 int ql2xfc2target = 1; 364 module_param(ql2xfc2target, int, 0444); 365 MODULE_PARM_DESC(qla2xfc2target, 366 "Enables FC2 Target support. " 367 "0 - FC2 Target support is disabled. " 368 "1 - FC2 Target support is enabled (default)."); 369 370 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 371 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 372 373 /* TODO Convert to inlines 374 * 375 * Timer routines 376 */ 377 378 __inline__ void 379 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 380 { 381 timer_setup(&vha->timer, qla2x00_timer, 0); 382 vha->timer.expires = jiffies + interval * HZ; 383 add_timer(&vha->timer); 384 vha->timer_active = 1; 385 } 386 387 static inline void 388 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 389 { 390 /* Currently used for 82XX only. */ 391 if (vha->device_flags & DFLG_DEV_FAILED) { 392 ql_dbg(ql_dbg_timer, vha, 0x600d, 393 "Device in a failed state, returning.\n"); 394 return; 395 } 396 397 mod_timer(&vha->timer, jiffies + interval * HZ); 398 } 399 400 static __inline__ void 401 qla2x00_stop_timer(scsi_qla_host_t *vha) 402 { 403 del_timer_sync(&vha->timer); 404 vha->timer_active = 0; 405 } 406 407 static int qla2x00_do_dpc(void *data); 408 409 static void qla2x00_rst_aen(scsi_qla_host_t *); 410 411 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 412 struct req_que **, struct rsp_que **); 413 static void qla2x00_free_fw_dump(struct qla_hw_data *); 414 static void qla2x00_mem_free(struct qla_hw_data *); 415 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 416 struct qla_qpair *qpair); 417 418 /* -------------------------------------------------------------------------- */ 419 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 420 struct rsp_que *rsp) 421 { 422 struct qla_hw_data *ha = vha->hw; 423 424 rsp->qpair = ha->base_qpair; 425 rsp->req = req; 426 ha->base_qpair->hw = ha; 427 ha->base_qpair->req = req; 428 ha->base_qpair->rsp = rsp; 429 ha->base_qpair->vha = vha; 430 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 431 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 432 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 433 ha->base_qpair->srb_mempool = ha->srb_mempool; 434 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 435 ha->base_qpair->enable_class_2 = ql2xenableclass2; 436 /* init qpair to this cpu. Will adjust at run time. */ 437 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 438 ha->base_qpair->pdev = ha->pdev; 439 440 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 441 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 442 } 443 444 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 445 struct rsp_que *rsp) 446 { 447 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 448 449 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 450 GFP_KERNEL); 451 if (!ha->req_q_map) { 452 ql_log(ql_log_fatal, vha, 0x003b, 453 "Unable to allocate memory for request queue ptrs.\n"); 454 goto fail_req_map; 455 } 456 457 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 458 GFP_KERNEL); 459 if (!ha->rsp_q_map) { 460 ql_log(ql_log_fatal, vha, 0x003c, 461 "Unable to allocate memory for response queue ptrs.\n"); 462 goto fail_rsp_map; 463 } 464 465 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 466 if (ha->base_qpair == NULL) { 467 ql_log(ql_log_warn, vha, 0x00e0, 468 "Failed to allocate base queue pair memory.\n"); 469 goto fail_base_qpair; 470 } 471 472 qla_init_base_qpair(vha, req, rsp); 473 474 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 475 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 476 GFP_KERNEL); 477 if (!ha->queue_pair_map) { 478 ql_log(ql_log_fatal, vha, 0x0180, 479 "Unable to allocate memory for queue pair ptrs.\n"); 480 goto fail_qpair_map; 481 } 482 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 483 kfree(ha->queue_pair_map); 484 ha->queue_pair_map = NULL; 485 goto fail_qpair_map; 486 } 487 } 488 489 /* 490 * Make sure we record at least the request and response queue zero in 491 * case we need to free them if part of the probe fails. 492 */ 493 ha->rsp_q_map[0] = rsp; 494 ha->req_q_map[0] = req; 495 set_bit(0, ha->rsp_qid_map); 496 set_bit(0, ha->req_qid_map); 497 return 0; 498 499 fail_qpair_map: 500 kfree(ha->base_qpair); 501 ha->base_qpair = NULL; 502 fail_base_qpair: 503 kfree(ha->rsp_q_map); 504 ha->rsp_q_map = NULL; 505 fail_rsp_map: 506 kfree(ha->req_q_map); 507 ha->req_q_map = NULL; 508 fail_req_map: 509 return -ENOMEM; 510 } 511 512 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 513 { 514 if (IS_QLAFX00(ha)) { 515 if (req && req->ring_fx00) 516 dma_free_coherent(&ha->pdev->dev, 517 (req->length_fx00 + 1) * sizeof(request_t), 518 req->ring_fx00, req->dma_fx00); 519 } else if (req && req->ring) 520 dma_free_coherent(&ha->pdev->dev, 521 (req->length + 1) * sizeof(request_t), 522 req->ring, req->dma); 523 524 if (req) 525 kfree(req->outstanding_cmds); 526 527 kfree(req); 528 } 529 530 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 531 { 532 if (IS_QLAFX00(ha)) { 533 if (rsp && rsp->ring_fx00) 534 dma_free_coherent(&ha->pdev->dev, 535 (rsp->length_fx00 + 1) * sizeof(request_t), 536 rsp->ring_fx00, rsp->dma_fx00); 537 } else if (rsp && rsp->ring) { 538 dma_free_coherent(&ha->pdev->dev, 539 (rsp->length + 1) * sizeof(response_t), 540 rsp->ring, rsp->dma); 541 } 542 kfree(rsp); 543 } 544 545 static void qla2x00_free_queues(struct qla_hw_data *ha) 546 { 547 struct req_que *req; 548 struct rsp_que *rsp; 549 int cnt; 550 unsigned long flags; 551 552 if (ha->queue_pair_map) { 553 kfree(ha->queue_pair_map); 554 ha->queue_pair_map = NULL; 555 } 556 if (ha->base_qpair) { 557 kfree(ha->base_qpair); 558 ha->base_qpair = NULL; 559 } 560 561 qla_mapq_free_qp_cpu_map(ha); 562 spin_lock_irqsave(&ha->hardware_lock, flags); 563 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 564 if (!test_bit(cnt, ha->req_qid_map)) 565 continue; 566 567 req = ha->req_q_map[cnt]; 568 clear_bit(cnt, ha->req_qid_map); 569 ha->req_q_map[cnt] = NULL; 570 571 spin_unlock_irqrestore(&ha->hardware_lock, flags); 572 qla2x00_free_req_que(ha, req); 573 spin_lock_irqsave(&ha->hardware_lock, flags); 574 } 575 spin_unlock_irqrestore(&ha->hardware_lock, flags); 576 577 kfree(ha->req_q_map); 578 ha->req_q_map = NULL; 579 580 581 spin_lock_irqsave(&ha->hardware_lock, flags); 582 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 583 if (!test_bit(cnt, ha->rsp_qid_map)) 584 continue; 585 586 rsp = ha->rsp_q_map[cnt]; 587 clear_bit(cnt, ha->rsp_qid_map); 588 ha->rsp_q_map[cnt] = NULL; 589 spin_unlock_irqrestore(&ha->hardware_lock, flags); 590 qla2x00_free_rsp_que(ha, rsp); 591 spin_lock_irqsave(&ha->hardware_lock, flags); 592 } 593 spin_unlock_irqrestore(&ha->hardware_lock, flags); 594 595 kfree(ha->rsp_q_map); 596 ha->rsp_q_map = NULL; 597 } 598 599 static char * 600 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 static const char *const pci_bus_modes[] = { 604 "33", "66", "100", "133", 605 }; 606 uint16_t pci_bus; 607 608 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 609 if (pci_bus) { 610 snprintf(str, str_len, "PCI-X (%s MHz)", 611 pci_bus_modes[pci_bus]); 612 } else { 613 pci_bus = (ha->pci_attr & BIT_8) >> 8; 614 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 615 } 616 617 return str; 618 } 619 620 static char * 621 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 622 { 623 static const char *const pci_bus_modes[] = { 624 "33", "66", "100", "133", 625 }; 626 struct qla_hw_data *ha = vha->hw; 627 uint32_t pci_bus; 628 629 if (pci_is_pcie(ha->pdev)) { 630 uint32_t lstat, lspeed, lwidth; 631 const char *speed_str; 632 633 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 634 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 635 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 636 637 switch (lspeed) { 638 case 1: 639 speed_str = "2.5GT/s"; 640 break; 641 case 2: 642 speed_str = "5.0GT/s"; 643 break; 644 case 3: 645 speed_str = "8.0GT/s"; 646 break; 647 case 4: 648 speed_str = "16.0GT/s"; 649 break; 650 default: 651 speed_str = "<unknown>"; 652 break; 653 } 654 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 655 656 return str; 657 } 658 659 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 660 if (pci_bus == 0 || pci_bus == 8) 661 snprintf(str, str_len, "PCI (%s MHz)", 662 pci_bus_modes[pci_bus >> 3]); 663 else 664 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 665 pci_bus & 4 ? 2 : 1, 666 pci_bus_modes[pci_bus & 3]); 667 668 return str; 669 } 670 671 static char * 672 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 673 { 674 char un_str[10]; 675 struct qla_hw_data *ha = vha->hw; 676 677 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 678 ha->fw_minor_version, ha->fw_subminor_version); 679 680 if (ha->fw_attributes & BIT_9) { 681 strcat(str, "FLX"); 682 return (str); 683 } 684 685 switch (ha->fw_attributes & 0xFF) { 686 case 0x7: 687 strcat(str, "EF"); 688 break; 689 case 0x17: 690 strcat(str, "TP"); 691 break; 692 case 0x37: 693 strcat(str, "IP"); 694 break; 695 case 0x77: 696 strcat(str, "VI"); 697 break; 698 default: 699 sprintf(un_str, "(%x)", ha->fw_attributes); 700 strcat(str, un_str); 701 break; 702 } 703 if (ha->fw_attributes & 0x100) 704 strcat(str, "X"); 705 706 return (str); 707 } 708 709 static char * 710 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 711 { 712 struct qla_hw_data *ha = vha->hw; 713 714 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 715 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 716 return str; 717 } 718 719 void qla2x00_sp_free_dma(srb_t *sp) 720 { 721 struct qla_hw_data *ha = sp->vha->hw; 722 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 723 724 if (sp->flags & SRB_DMA_VALID) { 725 scsi_dma_unmap(cmd); 726 sp->flags &= ~SRB_DMA_VALID; 727 } 728 729 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 730 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 731 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 732 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 736 /* List assured to be having elements */ 737 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 738 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 739 } 740 741 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 742 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 743 744 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 745 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 746 } 747 748 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 749 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 750 751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 752 ctx1->fcp_cmnd_dma); 753 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 754 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 755 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 756 } 757 758 if (sp->flags & SRB_GOT_BUF) 759 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 760 } 761 762 void qla2x00_sp_compl(srb_t *sp, int res) 763 { 764 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 765 struct completion *comp = sp->comp; 766 767 /* kref: INIT */ 768 kref_put(&sp->cmd_kref, qla2x00_sp_release); 769 cmd->result = res; 770 sp->type = 0; 771 scsi_done(cmd); 772 if (comp) 773 complete(comp); 774 } 775 776 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 777 { 778 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 779 struct qla_hw_data *ha = sp->fcport->vha->hw; 780 781 if (sp->flags & SRB_DMA_VALID) { 782 scsi_dma_unmap(cmd); 783 sp->flags &= ~SRB_DMA_VALID; 784 } 785 786 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 787 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 788 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 789 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 790 } 791 792 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 793 /* List assured to be having elements */ 794 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 795 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 796 } 797 798 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 799 struct crc_context *difctx = sp->u.scmd.crc_ctx; 800 struct dsd_dma *dif_dsd, *nxt_dsd; 801 802 list_for_each_entry_safe(dif_dsd, nxt_dsd, 803 &difctx->ldif_dma_hndl_list, list) { 804 list_del(&dif_dsd->list); 805 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 806 dif_dsd->dsd_list_dma); 807 kfree(dif_dsd); 808 difctx->no_dif_bundl--; 809 } 810 811 list_for_each_entry_safe(dif_dsd, nxt_dsd, 812 &difctx->ldif_dsd_list, list) { 813 list_del(&dif_dsd->list); 814 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 815 dif_dsd->dsd_list_dma); 816 kfree(dif_dsd); 817 difctx->no_ldif_dsd--; 818 } 819 820 if (difctx->no_ldif_dsd) { 821 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 822 "%s: difctx->no_ldif_dsd=%x\n", 823 __func__, difctx->no_ldif_dsd); 824 } 825 826 if (difctx->no_dif_bundl) { 827 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 828 "%s: difctx->no_dif_bundl=%x\n", 829 __func__, difctx->no_dif_bundl); 830 } 831 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 832 } 833 834 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 835 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 836 837 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 838 ctx1->fcp_cmnd_dma); 839 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 840 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 841 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 842 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 843 } 844 845 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 846 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 847 848 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 849 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 850 } 851 852 if (sp->flags & SRB_GOT_BUF) 853 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 854 } 855 856 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 857 { 858 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 859 struct completion *comp = sp->comp; 860 861 /* ref: INIT */ 862 kref_put(&sp->cmd_kref, qla2x00_sp_release); 863 cmd->result = res; 864 sp->type = 0; 865 scsi_done(cmd); 866 if (comp) 867 complete(comp); 868 } 869 870 static int 871 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 872 { 873 scsi_qla_host_t *vha = shost_priv(host); 874 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 875 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 876 struct qla_hw_data *ha = vha->hw; 877 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 878 srb_t *sp; 879 int rval; 880 881 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 882 WARN_ON_ONCE(!rport)) { 883 cmd->result = DID_NO_CONNECT << 16; 884 goto qc24_fail_command; 885 } 886 887 if (ha->mqenable) { 888 uint32_t tag; 889 uint16_t hwq; 890 struct qla_qpair *qpair = NULL; 891 892 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 893 hwq = blk_mq_unique_tag_to_hwq(tag); 894 qpair = ha->queue_pair_map[hwq]; 895 896 if (qpair) 897 return qla2xxx_mqueuecommand(host, cmd, qpair); 898 } 899 900 if (ha->flags.eeh_busy) { 901 if (ha->flags.pci_channel_io_perm_failure) { 902 ql_dbg(ql_dbg_aer, vha, 0x9010, 903 "PCI Channel IO permanent failure, exiting " 904 "cmd=%p.\n", cmd); 905 cmd->result = DID_NO_CONNECT << 16; 906 } else { 907 ql_dbg(ql_dbg_aer, vha, 0x9011, 908 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 909 cmd->result = DID_REQUEUE << 16; 910 } 911 goto qc24_fail_command; 912 } 913 914 rval = fc_remote_port_chkready(rport); 915 if (rval) { 916 cmd->result = rval; 917 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 918 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 919 cmd, rval); 920 goto qc24_fail_command; 921 } 922 923 if (!vha->flags.difdix_supported && 924 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 925 ql_dbg(ql_dbg_io, vha, 0x3004, 926 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 927 cmd); 928 cmd->result = DID_NO_CONNECT << 16; 929 goto qc24_fail_command; 930 } 931 932 if (!fcport || fcport->deleted) { 933 cmd->result = DID_IMM_RETRY << 16; 934 goto qc24_fail_command; 935 } 936 937 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 938 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 939 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 940 ql_dbg(ql_dbg_io, vha, 0x3005, 941 "Returning DNC, fcport_state=%d loop_state=%d.\n", 942 atomic_read(&fcport->state), 943 atomic_read(&base_vha->loop_state)); 944 cmd->result = DID_NO_CONNECT << 16; 945 goto qc24_fail_command; 946 } 947 goto qc24_target_busy; 948 } 949 950 /* 951 * Return target busy if we've received a non-zero retry_delay_timer 952 * in a FCP_RSP. 953 */ 954 if (fcport->retry_delay_timestamp == 0) { 955 /* retry delay not set */ 956 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 957 fcport->retry_delay_timestamp = 0; 958 else 959 goto qc24_target_busy; 960 961 sp = scsi_cmd_priv(cmd); 962 /* ref: INIT */ 963 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 964 965 sp->u.scmd.cmd = cmd; 966 sp->type = SRB_SCSI_CMD; 967 sp->free = qla2x00_sp_free_dma; 968 sp->done = qla2x00_sp_compl; 969 970 rval = ha->isp_ops->start_scsi(sp); 971 if (rval != QLA_SUCCESS) { 972 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 973 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 974 goto qc24_host_busy_free_sp; 975 } 976 977 return 0; 978 979 qc24_host_busy_free_sp: 980 /* ref: INIT */ 981 kref_put(&sp->cmd_kref, qla2x00_sp_release); 982 983 qc24_target_busy: 984 return SCSI_MLQUEUE_TARGET_BUSY; 985 986 qc24_fail_command: 987 scsi_done(cmd); 988 989 return 0; 990 } 991 992 /* For MQ supported I/O */ 993 int 994 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 995 struct qla_qpair *qpair) 996 { 997 scsi_qla_host_t *vha = shost_priv(host); 998 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 999 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1000 struct qla_hw_data *ha = vha->hw; 1001 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1002 srb_t *sp; 1003 int rval; 1004 1005 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1006 if (rval) { 1007 cmd->result = rval; 1008 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1009 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1010 cmd, rval); 1011 goto qc24_fail_command; 1012 } 1013 1014 if (!qpair->online) { 1015 ql_dbg(ql_dbg_io, vha, 0x3077, 1016 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1017 cmd->result = DID_NO_CONNECT << 16; 1018 goto qc24_fail_command; 1019 } 1020 1021 if (!fcport || fcport->deleted) { 1022 cmd->result = DID_IMM_RETRY << 16; 1023 goto qc24_fail_command; 1024 } 1025 1026 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1027 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1028 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1029 ql_dbg(ql_dbg_io, vha, 0x3077, 1030 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1031 atomic_read(&fcport->state), 1032 atomic_read(&base_vha->loop_state)); 1033 cmd->result = DID_NO_CONNECT << 16; 1034 goto qc24_fail_command; 1035 } 1036 goto qc24_target_busy; 1037 } 1038 1039 /* 1040 * Return target busy if we've received a non-zero retry_delay_timer 1041 * in a FCP_RSP. 1042 */ 1043 if (fcport->retry_delay_timestamp == 0) { 1044 /* retry delay not set */ 1045 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1046 fcport->retry_delay_timestamp = 0; 1047 else 1048 goto qc24_target_busy; 1049 1050 sp = scsi_cmd_priv(cmd); 1051 /* ref: INIT */ 1052 qla2xxx_init_sp(sp, vha, qpair, fcport); 1053 1054 sp->u.scmd.cmd = cmd; 1055 sp->type = SRB_SCSI_CMD; 1056 sp->free = qla2xxx_qpair_sp_free_dma; 1057 sp->done = qla2xxx_qpair_sp_compl; 1058 1059 rval = ha->isp_ops->start_scsi_mq(sp); 1060 if (rval != QLA_SUCCESS) { 1061 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1062 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1063 goto qc24_host_busy_free_sp; 1064 } 1065 1066 return 0; 1067 1068 qc24_host_busy_free_sp: 1069 /* ref: INIT */ 1070 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1071 1072 qc24_target_busy: 1073 return SCSI_MLQUEUE_TARGET_BUSY; 1074 1075 qc24_fail_command: 1076 scsi_done(cmd); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * qla2x00_wait_for_hba_online 1083 * Wait till the HBA is online after going through 1084 * <= MAX_RETRIES_OF_ISP_ABORT or 1085 * finally HBA is disabled ie marked offline 1086 * 1087 * Input: 1088 * ha - pointer to host adapter structure 1089 * 1090 * Note: 1091 * Does context switching-Release SPIN_LOCK 1092 * (if any) before calling this routine. 1093 * 1094 * Return: 1095 * Success (Adapter is online) : 0 1096 * Failed (Adapter is offline/disabled) : 1 1097 */ 1098 int 1099 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1100 { 1101 int return_status; 1102 unsigned long wait_online; 1103 struct qla_hw_data *ha = vha->hw; 1104 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1105 1106 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1107 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1108 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1109 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1110 ha->dpc_active) && time_before(jiffies, wait_online)) { 1111 1112 msleep(1000); 1113 } 1114 if (base_vha->flags.online) 1115 return_status = QLA_SUCCESS; 1116 else 1117 return_status = QLA_FUNCTION_FAILED; 1118 1119 return (return_status); 1120 } 1121 1122 static inline int test_fcport_count(scsi_qla_host_t *vha) 1123 { 1124 struct qla_hw_data *ha = vha->hw; 1125 unsigned long flags; 1126 int res; 1127 /* Return 0 = sleep, x=wake */ 1128 1129 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1130 ql_dbg(ql_dbg_init, vha, 0x00ec, 1131 "tgt %p, fcport_count=%d\n", 1132 vha, vha->fcport_count); 1133 res = (vha->fcport_count == 0); 1134 if (res) { 1135 struct fc_port *fcport; 1136 1137 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1138 if (fcport->deleted != QLA_SESS_DELETED) { 1139 /* session(s) may not be fully logged in 1140 * (ie fcport_count=0), but session 1141 * deletion thread(s) may be inflight. 1142 */ 1143 1144 res = 0; 1145 break; 1146 } 1147 } 1148 } 1149 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1150 1151 return res; 1152 } 1153 1154 /* 1155 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1156 * it has dependency on UNLOADING flag to stop device discovery 1157 */ 1158 void 1159 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1160 { 1161 u8 i; 1162 1163 qla2x00_mark_all_devices_lost(vha); 1164 1165 for (i = 0; i < 10; i++) { 1166 if (wait_event_timeout(vha->fcport_waitQ, 1167 test_fcport_count(vha), HZ) > 0) 1168 break; 1169 } 1170 1171 flush_workqueue(vha->hw->wq); 1172 } 1173 1174 /* 1175 * qla2x00_wait_for_hba_ready 1176 * Wait till the HBA is ready before doing driver unload 1177 * 1178 * Input: 1179 * ha - pointer to host adapter structure 1180 * 1181 * Note: 1182 * Does context switching-Release SPIN_LOCK 1183 * (if any) before calling this routine. 1184 * 1185 */ 1186 static void 1187 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1188 { 1189 struct qla_hw_data *ha = vha->hw; 1190 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1191 1192 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1193 ha->flags.mbox_busy) || 1194 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1195 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1196 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1197 break; 1198 msleep(1000); 1199 } 1200 } 1201 1202 int 1203 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1204 { 1205 int return_status; 1206 unsigned long wait_reset; 1207 struct qla_hw_data *ha = vha->hw; 1208 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1209 1210 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1211 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1212 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1213 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1214 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1215 1216 msleep(1000); 1217 1218 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1219 ha->flags.chip_reset_done) 1220 break; 1221 } 1222 if (ha->flags.chip_reset_done) 1223 return_status = QLA_SUCCESS; 1224 else 1225 return_status = QLA_FUNCTION_FAILED; 1226 1227 return return_status; 1228 } 1229 1230 /************************************************************************** 1231 * qla2xxx_eh_abort 1232 * 1233 * Description: 1234 * The abort function will abort the specified command. 1235 * 1236 * Input: 1237 * cmd = Linux SCSI command packet to be aborted. 1238 * 1239 * Returns: 1240 * Either SUCCESS or FAILED. 1241 * 1242 * Note: 1243 * Only return FAILED if command not returned by firmware. 1244 **************************************************************************/ 1245 static int 1246 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1247 { 1248 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1249 DECLARE_COMPLETION_ONSTACK(comp); 1250 srb_t *sp; 1251 int ret; 1252 unsigned int id; 1253 uint64_t lun; 1254 int rval; 1255 struct qla_hw_data *ha = vha->hw; 1256 uint32_t ratov_j; 1257 struct qla_qpair *qpair; 1258 unsigned long flags; 1259 int fast_fail_status = SUCCESS; 1260 1261 if (qla2x00_isp_reg_stat(ha)) { 1262 ql_log(ql_log_info, vha, 0x8042, 1263 "PCI/Register disconnect, exiting.\n"); 1264 qla_pci_set_eeh_busy(vha); 1265 return FAILED; 1266 } 1267 1268 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1269 ret = fc_block_scsi_eh(cmd); 1270 if (ret != 0) 1271 fast_fail_status = ret; 1272 1273 sp = scsi_cmd_priv(cmd); 1274 qpair = sp->qpair; 1275 1276 vha->cmd_timeout_cnt++; 1277 1278 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1279 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1280 1281 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1282 sp->comp = ∁ 1283 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1284 1285 1286 id = cmd->device->id; 1287 lun = cmd->device->lun; 1288 1289 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1290 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1291 vha->host_no, id, lun, sp, cmd, sp->handle); 1292 1293 /* 1294 * Abort will release the original Command/sp from FW. Let the 1295 * original command call scsi_done. In return, he will wakeup 1296 * this sleeping thread. 1297 */ 1298 rval = ha->isp_ops->abort_command(sp); 1299 1300 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1301 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1302 1303 /* Wait for the command completion. */ 1304 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1305 ratov_j = msecs_to_jiffies(ratov_j); 1306 switch (rval) { 1307 case QLA_SUCCESS: 1308 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1309 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1310 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1311 __func__, ha->r_a_tov/10); 1312 ret = FAILED; 1313 } else { 1314 ret = fast_fail_status; 1315 } 1316 break; 1317 default: 1318 ret = FAILED; 1319 break; 1320 } 1321 1322 sp->comp = NULL; 1323 1324 ql_log(ql_log_info, vha, 0x801c, 1325 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1326 vha->host_no, id, lun, ret); 1327 1328 return ret; 1329 } 1330 1331 #define ABORT_POLLING_PERIOD 1000 1332 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1333 1334 /* 1335 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1336 */ 1337 static int 1338 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1339 uint64_t l, enum nexus_wait_type type) 1340 { 1341 int cnt, match, status; 1342 unsigned long flags; 1343 scsi_qla_host_t *vha = qpair->vha; 1344 struct req_que *req = qpair->req; 1345 srb_t *sp; 1346 struct scsi_cmnd *cmd; 1347 unsigned long wait_iter = ABORT_WAIT_ITER; 1348 bool found; 1349 struct qla_hw_data *ha = vha->hw; 1350 1351 status = QLA_SUCCESS; 1352 1353 while (wait_iter--) { 1354 found = false; 1355 1356 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1357 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1358 sp = req->outstanding_cmds[cnt]; 1359 if (!sp) 1360 continue; 1361 if (sp->type != SRB_SCSI_CMD) 1362 continue; 1363 if (vha->vp_idx != sp->vha->vp_idx) 1364 continue; 1365 match = 0; 1366 cmd = GET_CMD_SP(sp); 1367 switch (type) { 1368 case WAIT_HOST: 1369 match = 1; 1370 break; 1371 case WAIT_TARGET: 1372 if (sp->fcport) 1373 match = sp->fcport->d_id.b24 == t; 1374 else 1375 match = 0; 1376 break; 1377 case WAIT_LUN: 1378 if (sp->fcport) 1379 match = (sp->fcport->d_id.b24 == t && 1380 cmd->device->lun == l); 1381 else 1382 match = 0; 1383 break; 1384 } 1385 if (!match) 1386 continue; 1387 1388 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1389 1390 if (unlikely(pci_channel_offline(ha->pdev)) || 1391 ha->flags.eeh_busy) { 1392 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1393 "Return:eh_wait.\n"); 1394 return status; 1395 } 1396 1397 /* 1398 * SRB_SCSI_CMD is still in the outstanding_cmds array. 1399 * it means scsi_done has not called. Wait for it to 1400 * clear from outstanding_cmds. 1401 */ 1402 msleep(ABORT_POLLING_PERIOD); 1403 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1404 found = true; 1405 } 1406 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1407 1408 if (!found) 1409 break; 1410 } 1411 1412 if (wait_iter == -1) 1413 status = QLA_FUNCTION_FAILED; 1414 1415 return status; 1416 } 1417 1418 int 1419 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1420 uint64_t l, enum nexus_wait_type type) 1421 { 1422 struct qla_qpair *qpair; 1423 struct qla_hw_data *ha = vha->hw; 1424 int i, status = QLA_SUCCESS; 1425 1426 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1427 type); 1428 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1429 qpair = ha->queue_pair_map[i]; 1430 if (!qpair) 1431 continue; 1432 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1433 type); 1434 } 1435 return status; 1436 } 1437 1438 static char *reset_errors[] = { 1439 "HBA not online", 1440 "HBA not ready", 1441 "Task management failed", 1442 "Waiting for command completions", 1443 }; 1444 1445 static int 1446 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1447 { 1448 struct scsi_device *sdev = cmd->device; 1449 scsi_qla_host_t *vha = shost_priv(sdev->host); 1450 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1451 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1452 struct qla_hw_data *ha = vha->hw; 1453 int err; 1454 1455 if (qla2x00_isp_reg_stat(ha)) { 1456 ql_log(ql_log_info, vha, 0x803e, 1457 "PCI/Register disconnect, exiting.\n"); 1458 qla_pci_set_eeh_busy(vha); 1459 return FAILED; 1460 } 1461 1462 if (!fcport) { 1463 return FAILED; 1464 } 1465 1466 err = fc_block_rport(rport); 1467 if (err != 0) 1468 return err; 1469 1470 if (fcport->deleted) 1471 return FAILED; 1472 1473 ql_log(ql_log_info, vha, 0x8009, 1474 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1475 sdev->id, sdev->lun, cmd); 1476 1477 err = 0; 1478 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1479 ql_log(ql_log_warn, vha, 0x800a, 1480 "Wait for hba online failed for cmd=%p.\n", cmd); 1481 goto eh_reset_failed; 1482 } 1483 err = 2; 1484 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1485 != QLA_SUCCESS) { 1486 ql_log(ql_log_warn, vha, 0x800c, 1487 "do_reset failed for cmd=%p.\n", cmd); 1488 goto eh_reset_failed; 1489 } 1490 err = 3; 1491 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 1492 cmd->device->lun, 1493 WAIT_LUN) != QLA_SUCCESS) { 1494 ql_log(ql_log_warn, vha, 0x800d, 1495 "wait for pending cmds failed for cmd=%p.\n", cmd); 1496 goto eh_reset_failed; 1497 } 1498 1499 ql_log(ql_log_info, vha, 0x800e, 1500 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1501 vha->host_no, sdev->id, sdev->lun, cmd); 1502 1503 return SUCCESS; 1504 1505 eh_reset_failed: 1506 ql_log(ql_log_info, vha, 0x800f, 1507 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1508 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1509 cmd); 1510 vha->reset_cmd_err_cnt++; 1511 return FAILED; 1512 } 1513 1514 static int 1515 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1516 { 1517 struct scsi_device *sdev = cmd->device; 1518 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1519 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1520 struct qla_hw_data *ha = vha->hw; 1521 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1522 int err; 1523 1524 if (qla2x00_isp_reg_stat(ha)) { 1525 ql_log(ql_log_info, vha, 0x803f, 1526 "PCI/Register disconnect, exiting.\n"); 1527 qla_pci_set_eeh_busy(vha); 1528 return FAILED; 1529 } 1530 1531 if (!fcport) { 1532 return FAILED; 1533 } 1534 1535 err = fc_block_rport(rport); 1536 if (err != 0) 1537 return err; 1538 1539 if (fcport->deleted) 1540 return FAILED; 1541 1542 ql_log(ql_log_info, vha, 0x8009, 1543 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1544 sdev->id, cmd); 1545 1546 err = 0; 1547 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1548 ql_log(ql_log_warn, vha, 0x800a, 1549 "Wait for hba online failed for cmd=%p.\n", cmd); 1550 goto eh_reset_failed; 1551 } 1552 err = 2; 1553 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1554 ql_log(ql_log_warn, vha, 0x800c, 1555 "target_reset failed for cmd=%p.\n", cmd); 1556 goto eh_reset_failed; 1557 } 1558 err = 3; 1559 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0, 1560 WAIT_TARGET) != QLA_SUCCESS) { 1561 ql_log(ql_log_warn, vha, 0x800d, 1562 "wait for pending cmds failed for cmd=%p.\n", cmd); 1563 goto eh_reset_failed; 1564 } 1565 1566 ql_log(ql_log_info, vha, 0x800e, 1567 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1568 vha->host_no, sdev->id, cmd); 1569 1570 return SUCCESS; 1571 1572 eh_reset_failed: 1573 ql_log(ql_log_info, vha, 0x800f, 1574 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1575 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1576 cmd); 1577 vha->reset_cmd_err_cnt++; 1578 return FAILED; 1579 } 1580 1581 /************************************************************************** 1582 * qla2xxx_eh_bus_reset 1583 * 1584 * Description: 1585 * The bus reset function will reset the bus and abort any executing 1586 * commands. 1587 * 1588 * Input: 1589 * cmd = Linux SCSI command packet of the command that cause the 1590 * bus reset. 1591 * 1592 * Returns: 1593 * SUCCESS/FAILURE (defined as macro in scsi.h). 1594 * 1595 **************************************************************************/ 1596 static int 1597 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1598 { 1599 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1600 int ret = FAILED; 1601 unsigned int id; 1602 uint64_t lun; 1603 struct qla_hw_data *ha = vha->hw; 1604 1605 if (qla2x00_isp_reg_stat(ha)) { 1606 ql_log(ql_log_info, vha, 0x8040, 1607 "PCI/Register disconnect, exiting.\n"); 1608 qla_pci_set_eeh_busy(vha); 1609 return FAILED; 1610 } 1611 1612 id = cmd->device->id; 1613 lun = cmd->device->lun; 1614 1615 if (qla2x00_chip_is_down(vha)) 1616 return ret; 1617 1618 ql_log(ql_log_info, vha, 0x8012, 1619 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1620 1621 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1622 ql_log(ql_log_fatal, vha, 0x8013, 1623 "Wait for hba online failed board disabled.\n"); 1624 goto eh_bus_reset_done; 1625 } 1626 1627 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1628 ret = SUCCESS; 1629 1630 if (ret == FAILED) 1631 goto eh_bus_reset_done; 1632 1633 /* Flush outstanding commands. */ 1634 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1635 QLA_SUCCESS) { 1636 ql_log(ql_log_warn, vha, 0x8014, 1637 "Wait for pending commands failed.\n"); 1638 ret = FAILED; 1639 } 1640 1641 eh_bus_reset_done: 1642 ql_log(ql_log_warn, vha, 0x802b, 1643 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1644 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1645 1646 return ret; 1647 } 1648 1649 /************************************************************************** 1650 * qla2xxx_eh_host_reset 1651 * 1652 * Description: 1653 * The reset function will reset the Adapter. 1654 * 1655 * Input: 1656 * cmd = Linux SCSI command packet of the command that cause the 1657 * adapter reset. 1658 * 1659 * Returns: 1660 * Either SUCCESS or FAILED. 1661 * 1662 * Note: 1663 **************************************************************************/ 1664 static int 1665 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1666 { 1667 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1668 struct qla_hw_data *ha = vha->hw; 1669 int ret = FAILED; 1670 unsigned int id; 1671 uint64_t lun; 1672 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1673 1674 if (qla2x00_isp_reg_stat(ha)) { 1675 ql_log(ql_log_info, vha, 0x8041, 1676 "PCI/Register disconnect, exiting.\n"); 1677 qla_pci_set_eeh_busy(vha); 1678 return SUCCESS; 1679 } 1680 1681 id = cmd->device->id; 1682 lun = cmd->device->lun; 1683 1684 ql_log(ql_log_info, vha, 0x8018, 1685 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1686 1687 /* 1688 * No point in issuing another reset if one is active. Also do not 1689 * attempt a reset if we are updating flash. 1690 */ 1691 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1692 goto eh_host_reset_lock; 1693 1694 if (vha != base_vha) { 1695 if (qla2x00_vp_abort_isp(vha)) 1696 goto eh_host_reset_lock; 1697 } else { 1698 if (IS_P3P_TYPE(vha->hw)) { 1699 if (!qla82xx_fcoe_ctx_reset(vha)) { 1700 /* Ctx reset success */ 1701 ret = SUCCESS; 1702 goto eh_host_reset_lock; 1703 } 1704 /* fall thru if ctx reset failed */ 1705 } 1706 if (ha->wq) 1707 flush_workqueue(ha->wq); 1708 1709 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1710 if (ha->isp_ops->abort_isp(base_vha)) { 1711 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1712 /* failed. schedule dpc to try */ 1713 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1714 1715 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1716 ql_log(ql_log_warn, vha, 0x802a, 1717 "wait for hba online failed.\n"); 1718 goto eh_host_reset_lock; 1719 } 1720 } 1721 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1722 } 1723 1724 /* Waiting for command to be returned to OS.*/ 1725 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1726 QLA_SUCCESS) 1727 ret = SUCCESS; 1728 1729 eh_host_reset_lock: 1730 ql_log(ql_log_info, vha, 0x8017, 1731 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1732 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1733 1734 return ret; 1735 } 1736 1737 /* 1738 * qla2x00_loop_reset 1739 * Issue loop reset. 1740 * 1741 * Input: 1742 * ha = adapter block pointer. 1743 * 1744 * Returns: 1745 * 0 = success 1746 */ 1747 int 1748 qla2x00_loop_reset(scsi_qla_host_t *vha) 1749 { 1750 int ret; 1751 struct qla_hw_data *ha = vha->hw; 1752 1753 if (IS_QLAFX00(ha)) 1754 return QLA_SUCCESS; 1755 1756 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1757 atomic_set(&vha->loop_state, LOOP_DOWN); 1758 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1759 qla2x00_mark_all_devices_lost(vha); 1760 ret = qla2x00_full_login_lip(vha); 1761 if (ret != QLA_SUCCESS) { 1762 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1763 "full_login_lip=%d.\n", ret); 1764 } 1765 } 1766 1767 if (ha->flags.enable_lip_reset) { 1768 ret = qla2x00_lip_reset(vha); 1769 if (ret != QLA_SUCCESS) 1770 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1771 "lip_reset failed (%d).\n", ret); 1772 } 1773 1774 /* Issue marker command only when we are going to start the I/O */ 1775 vha->marker_needed = 1; 1776 1777 return QLA_SUCCESS; 1778 } 1779 1780 /* 1781 * The caller must ensure that no completion interrupts will happen 1782 * while this function is in progress. 1783 */ 1784 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1785 unsigned long *flags) 1786 __releases(qp->qp_lock_ptr) 1787 __acquires(qp->qp_lock_ptr) 1788 { 1789 DECLARE_COMPLETION_ONSTACK(comp); 1790 scsi_qla_host_t *vha = qp->vha; 1791 struct qla_hw_data *ha = vha->hw; 1792 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1793 int rval; 1794 bool ret_cmd; 1795 uint32_t ratov_j; 1796 1797 lockdep_assert_held(qp->qp_lock_ptr); 1798 1799 if (qla2x00_chip_is_down(vha)) { 1800 sp->done(sp, res); 1801 return; 1802 } 1803 1804 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1805 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1806 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1807 !qla2x00_isp_reg_stat(ha))) { 1808 if (sp->comp) { 1809 sp->done(sp, res); 1810 return; 1811 } 1812 1813 sp->comp = ∁ 1814 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1815 1816 rval = ha->isp_ops->abort_command(sp); 1817 /* Wait for command completion. */ 1818 ret_cmd = false; 1819 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1820 ratov_j = msecs_to_jiffies(ratov_j); 1821 switch (rval) { 1822 case QLA_SUCCESS: 1823 if (wait_for_completion_timeout(&comp, ratov_j)) { 1824 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1825 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1826 __func__, ha->r_a_tov/10); 1827 ret_cmd = true; 1828 } 1829 /* else FW return SP to driver */ 1830 break; 1831 default: 1832 ret_cmd = true; 1833 break; 1834 } 1835 1836 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1837 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1838 sp->done(sp, res); 1839 } else { 1840 sp->done(sp, res); 1841 } 1842 } 1843 1844 /* 1845 * The caller must ensure that no completion interrupts will happen 1846 * while this function is in progress. 1847 */ 1848 static void 1849 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1850 { 1851 int cnt; 1852 unsigned long flags; 1853 srb_t *sp; 1854 scsi_qla_host_t *vha = qp->vha; 1855 struct qla_hw_data *ha = vha->hw; 1856 struct req_que *req; 1857 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1858 struct qla_tgt_cmd *cmd; 1859 1860 if (!ha->req_q_map) 1861 return; 1862 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1863 req = qp->req; 1864 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1865 sp = req->outstanding_cmds[cnt]; 1866 if (sp) { 1867 /* 1868 * perform lockless completion during driver unload 1869 */ 1870 if (qla2x00_chip_is_down(vha)) { 1871 req->outstanding_cmds[cnt] = NULL; 1872 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1873 sp->done(sp, res); 1874 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1875 continue; 1876 } 1877 1878 switch (sp->cmd_type) { 1879 case TYPE_SRB: 1880 qla2x00_abort_srb(qp, sp, res, &flags); 1881 break; 1882 case TYPE_TGT_CMD: 1883 if (!vha->hw->tgt.tgt_ops || !tgt || 1884 qla_ini_mode_enabled(vha)) { 1885 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1886 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1887 vha->dpc_flags); 1888 continue; 1889 } 1890 cmd = (struct qla_tgt_cmd *)sp; 1891 cmd->aborted = 1; 1892 break; 1893 case TYPE_TGT_TMCMD: 1894 /* Skip task management functions. */ 1895 break; 1896 default: 1897 break; 1898 } 1899 req->outstanding_cmds[cnt] = NULL; 1900 } 1901 } 1902 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1903 } 1904 1905 /* 1906 * The caller must ensure that no completion interrupts will happen 1907 * while this function is in progress. 1908 */ 1909 void 1910 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1911 { 1912 int que; 1913 struct qla_hw_data *ha = vha->hw; 1914 1915 /* Continue only if initialization complete. */ 1916 if (!ha->base_qpair) 1917 return; 1918 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1919 1920 if (!ha->queue_pair_map) 1921 return; 1922 for (que = 0; que < ha->max_qpairs; que++) { 1923 if (!ha->queue_pair_map[que]) 1924 continue; 1925 1926 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1927 } 1928 } 1929 1930 static int 1931 qla2xxx_slave_alloc(struct scsi_device *sdev) 1932 { 1933 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1934 1935 if (!rport || fc_remote_port_chkready(rport)) 1936 return -ENXIO; 1937 1938 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1939 1940 return 0; 1941 } 1942 1943 static int 1944 qla2xxx_slave_configure(struct scsi_device *sdev) 1945 { 1946 scsi_qla_host_t *vha = shost_priv(sdev->host); 1947 struct req_que *req = vha->req; 1948 1949 if (IS_T10_PI_CAPABLE(vha->hw)) 1950 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1951 1952 scsi_change_queue_depth(sdev, req->max_q_depth); 1953 return 0; 1954 } 1955 1956 static void 1957 qla2xxx_slave_destroy(struct scsi_device *sdev) 1958 { 1959 sdev->hostdata = NULL; 1960 } 1961 1962 /** 1963 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1964 * @ha: HA context 1965 * 1966 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1967 * supported addressing method. 1968 */ 1969 static void 1970 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1971 { 1972 /* Assume a 32bit DMA mask. */ 1973 ha->flags.enable_64bit_addressing = 0; 1974 1975 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1976 /* Any upper-dword bits set? */ 1977 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1978 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1979 /* Ok, a 64bit DMA mask is applicable. */ 1980 ha->flags.enable_64bit_addressing = 1; 1981 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1982 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1983 return; 1984 } 1985 } 1986 1987 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1988 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1989 } 1990 1991 static void 1992 qla2x00_enable_intrs(struct qla_hw_data *ha) 1993 { 1994 unsigned long flags = 0; 1995 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1996 1997 spin_lock_irqsave(&ha->hardware_lock, flags); 1998 ha->interrupts_on = 1; 1999 /* enable risc and host interrupts */ 2000 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2001 rd_reg_word(®->ictrl); 2002 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2003 2004 } 2005 2006 static void 2007 qla2x00_disable_intrs(struct qla_hw_data *ha) 2008 { 2009 unsigned long flags = 0; 2010 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2011 2012 spin_lock_irqsave(&ha->hardware_lock, flags); 2013 ha->interrupts_on = 0; 2014 /* disable risc and host interrupts */ 2015 wrt_reg_word(®->ictrl, 0); 2016 rd_reg_word(®->ictrl); 2017 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2018 } 2019 2020 static void 2021 qla24xx_enable_intrs(struct qla_hw_data *ha) 2022 { 2023 unsigned long flags = 0; 2024 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2025 2026 spin_lock_irqsave(&ha->hardware_lock, flags); 2027 ha->interrupts_on = 1; 2028 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2029 rd_reg_dword(®->ictrl); 2030 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2031 } 2032 2033 static void 2034 qla24xx_disable_intrs(struct qla_hw_data *ha) 2035 { 2036 unsigned long flags = 0; 2037 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2038 2039 if (IS_NOPOLLING_TYPE(ha)) 2040 return; 2041 spin_lock_irqsave(&ha->hardware_lock, flags); 2042 ha->interrupts_on = 0; 2043 wrt_reg_dword(®->ictrl, 0); 2044 rd_reg_dword(®->ictrl); 2045 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2046 } 2047 2048 static int 2049 qla2x00_iospace_config(struct qla_hw_data *ha) 2050 { 2051 resource_size_t pio; 2052 uint16_t msix; 2053 2054 if (pci_request_selected_regions(ha->pdev, ha->bars, 2055 QLA2XXX_DRIVER_NAME)) { 2056 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2057 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2058 pci_name(ha->pdev)); 2059 goto iospace_error_exit; 2060 } 2061 if (!(ha->bars & 1)) 2062 goto skip_pio; 2063 2064 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2065 pio = pci_resource_start(ha->pdev, 0); 2066 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2067 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2068 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2069 "Invalid pci I/O region size (%s).\n", 2070 pci_name(ha->pdev)); 2071 pio = 0; 2072 } 2073 } else { 2074 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2075 "Region #0 no a PIO resource (%s).\n", 2076 pci_name(ha->pdev)); 2077 pio = 0; 2078 } 2079 ha->pio_address = pio; 2080 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2081 "PIO address=%llu.\n", 2082 (unsigned long long)ha->pio_address); 2083 2084 skip_pio: 2085 /* Use MMIO operations for all accesses. */ 2086 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2087 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2088 "Region #1 not an MMIO resource (%s), aborting.\n", 2089 pci_name(ha->pdev)); 2090 goto iospace_error_exit; 2091 } 2092 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2093 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2094 "Invalid PCI mem region size (%s), aborting.\n", 2095 pci_name(ha->pdev)); 2096 goto iospace_error_exit; 2097 } 2098 2099 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2100 if (!ha->iobase) { 2101 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2102 "Cannot remap MMIO (%s), aborting.\n", 2103 pci_name(ha->pdev)); 2104 goto iospace_error_exit; 2105 } 2106 2107 /* Determine queue resources */ 2108 ha->max_req_queues = ha->max_rsp_queues = 1; 2109 ha->msix_count = QLA_BASE_VECTORS; 2110 2111 /* Check if FW supports MQ or not */ 2112 if (!(ha->fw_attributes & BIT_6)) 2113 goto mqiobase_exit; 2114 2115 if (!ql2xmqsupport || !ql2xnvmeenable || 2116 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2117 goto mqiobase_exit; 2118 2119 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2120 pci_resource_len(ha->pdev, 3)); 2121 if (ha->mqiobase) { 2122 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2123 "MQIO Base=%p.\n", ha->mqiobase); 2124 /* Read MSIX vector size of the board */ 2125 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2126 ha->msix_count = msix + 1; 2127 /* Max queues are bounded by available msix vectors */ 2128 /* MB interrupt uses 1 vector */ 2129 ha->max_req_queues = ha->msix_count - 1; 2130 ha->max_rsp_queues = ha->max_req_queues; 2131 /* Queue pairs is the max value minus the base queue pair */ 2132 ha->max_qpairs = ha->max_rsp_queues - 1; 2133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2134 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2135 2136 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2137 "MSI-X vector count: %d.\n", ha->msix_count); 2138 } else 2139 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2140 "BAR 3 not enabled.\n"); 2141 2142 mqiobase_exit: 2143 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2144 "MSIX Count: %d.\n", ha->msix_count); 2145 return (0); 2146 2147 iospace_error_exit: 2148 return (-ENOMEM); 2149 } 2150 2151 2152 static int 2153 qla83xx_iospace_config(struct qla_hw_data *ha) 2154 { 2155 uint16_t msix; 2156 2157 if (pci_request_selected_regions(ha->pdev, ha->bars, 2158 QLA2XXX_DRIVER_NAME)) { 2159 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2160 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2161 pci_name(ha->pdev)); 2162 2163 goto iospace_error_exit; 2164 } 2165 2166 /* Use MMIO operations for all accesses. */ 2167 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2168 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2169 "Invalid pci I/O region size (%s).\n", 2170 pci_name(ha->pdev)); 2171 goto iospace_error_exit; 2172 } 2173 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2174 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2175 "Invalid PCI mem region size (%s), aborting\n", 2176 pci_name(ha->pdev)); 2177 goto iospace_error_exit; 2178 } 2179 2180 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2181 if (!ha->iobase) { 2182 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2183 "Cannot remap MMIO (%s), aborting.\n", 2184 pci_name(ha->pdev)); 2185 goto iospace_error_exit; 2186 } 2187 2188 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2189 /* 83XX 26XX always use MQ type access for queues 2190 * - mbar 2, a.k.a region 4 */ 2191 ha->max_req_queues = ha->max_rsp_queues = 1; 2192 ha->msix_count = QLA_BASE_VECTORS; 2193 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2194 pci_resource_len(ha->pdev, 4)); 2195 2196 if (!ha->mqiobase) { 2197 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2198 "BAR2/region4 not enabled\n"); 2199 goto mqiobase_exit; 2200 } 2201 2202 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2203 pci_resource_len(ha->pdev, 2)); 2204 if (ha->msixbase) { 2205 /* Read MSIX vector size of the board */ 2206 pci_read_config_word(ha->pdev, 2207 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2208 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2209 /* 2210 * By default, driver uses at least two msix vectors 2211 * (default & rspq) 2212 */ 2213 if (ql2xmqsupport || ql2xnvmeenable) { 2214 /* MB interrupt uses 1 vector */ 2215 ha->max_req_queues = ha->msix_count - 1; 2216 2217 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2218 if (QLA_TGT_MODE_ENABLED()) 2219 ha->max_req_queues--; 2220 2221 ha->max_rsp_queues = ha->max_req_queues; 2222 2223 /* Queue pairs is the max value minus 2224 * the base queue pair */ 2225 ha->max_qpairs = ha->max_req_queues - 1; 2226 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2227 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2228 } 2229 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2230 "MSI-X vector count: %d.\n", ha->msix_count); 2231 } else 2232 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2233 "BAR 1 not enabled.\n"); 2234 2235 mqiobase_exit: 2236 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2237 "MSIX Count: %d.\n", ha->msix_count); 2238 return 0; 2239 2240 iospace_error_exit: 2241 return -ENOMEM; 2242 } 2243 2244 static struct isp_operations qla2100_isp_ops = { 2245 .pci_config = qla2100_pci_config, 2246 .reset_chip = qla2x00_reset_chip, 2247 .chip_diag = qla2x00_chip_diag, 2248 .config_rings = qla2x00_config_rings, 2249 .reset_adapter = qla2x00_reset_adapter, 2250 .nvram_config = qla2x00_nvram_config, 2251 .update_fw_options = qla2x00_update_fw_options, 2252 .load_risc = qla2x00_load_risc, 2253 .pci_info_str = qla2x00_pci_info_str, 2254 .fw_version_str = qla2x00_fw_version_str, 2255 .intr_handler = qla2100_intr_handler, 2256 .enable_intrs = qla2x00_enable_intrs, 2257 .disable_intrs = qla2x00_disable_intrs, 2258 .abort_command = qla2x00_abort_command, 2259 .target_reset = qla2x00_abort_target, 2260 .lun_reset = qla2x00_lun_reset, 2261 .fabric_login = qla2x00_login_fabric, 2262 .fabric_logout = qla2x00_fabric_logout, 2263 .calc_req_entries = qla2x00_calc_iocbs_32, 2264 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2265 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2266 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2267 .read_nvram = qla2x00_read_nvram_data, 2268 .write_nvram = qla2x00_write_nvram_data, 2269 .fw_dump = qla2100_fw_dump, 2270 .beacon_on = NULL, 2271 .beacon_off = NULL, 2272 .beacon_blink = NULL, 2273 .read_optrom = qla2x00_read_optrom_data, 2274 .write_optrom = qla2x00_write_optrom_data, 2275 .get_flash_version = qla2x00_get_flash_version, 2276 .start_scsi = qla2x00_start_scsi, 2277 .start_scsi_mq = NULL, 2278 .abort_isp = qla2x00_abort_isp, 2279 .iospace_config = qla2x00_iospace_config, 2280 .initialize_adapter = qla2x00_initialize_adapter, 2281 }; 2282 2283 static struct isp_operations qla2300_isp_ops = { 2284 .pci_config = qla2300_pci_config, 2285 .reset_chip = qla2x00_reset_chip, 2286 .chip_diag = qla2x00_chip_diag, 2287 .config_rings = qla2x00_config_rings, 2288 .reset_adapter = qla2x00_reset_adapter, 2289 .nvram_config = qla2x00_nvram_config, 2290 .update_fw_options = qla2x00_update_fw_options, 2291 .load_risc = qla2x00_load_risc, 2292 .pci_info_str = qla2x00_pci_info_str, 2293 .fw_version_str = qla2x00_fw_version_str, 2294 .intr_handler = qla2300_intr_handler, 2295 .enable_intrs = qla2x00_enable_intrs, 2296 .disable_intrs = qla2x00_disable_intrs, 2297 .abort_command = qla2x00_abort_command, 2298 .target_reset = qla2x00_abort_target, 2299 .lun_reset = qla2x00_lun_reset, 2300 .fabric_login = qla2x00_login_fabric, 2301 .fabric_logout = qla2x00_fabric_logout, 2302 .calc_req_entries = qla2x00_calc_iocbs_32, 2303 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2304 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2305 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2306 .read_nvram = qla2x00_read_nvram_data, 2307 .write_nvram = qla2x00_write_nvram_data, 2308 .fw_dump = qla2300_fw_dump, 2309 .beacon_on = qla2x00_beacon_on, 2310 .beacon_off = qla2x00_beacon_off, 2311 .beacon_blink = qla2x00_beacon_blink, 2312 .read_optrom = qla2x00_read_optrom_data, 2313 .write_optrom = qla2x00_write_optrom_data, 2314 .get_flash_version = qla2x00_get_flash_version, 2315 .start_scsi = qla2x00_start_scsi, 2316 .start_scsi_mq = NULL, 2317 .abort_isp = qla2x00_abort_isp, 2318 .iospace_config = qla2x00_iospace_config, 2319 .initialize_adapter = qla2x00_initialize_adapter, 2320 }; 2321 2322 static struct isp_operations qla24xx_isp_ops = { 2323 .pci_config = qla24xx_pci_config, 2324 .reset_chip = qla24xx_reset_chip, 2325 .chip_diag = qla24xx_chip_diag, 2326 .config_rings = qla24xx_config_rings, 2327 .reset_adapter = qla24xx_reset_adapter, 2328 .nvram_config = qla24xx_nvram_config, 2329 .update_fw_options = qla24xx_update_fw_options, 2330 .load_risc = qla24xx_load_risc, 2331 .pci_info_str = qla24xx_pci_info_str, 2332 .fw_version_str = qla24xx_fw_version_str, 2333 .intr_handler = qla24xx_intr_handler, 2334 .enable_intrs = qla24xx_enable_intrs, 2335 .disable_intrs = qla24xx_disable_intrs, 2336 .abort_command = qla24xx_abort_command, 2337 .target_reset = qla24xx_abort_target, 2338 .lun_reset = qla24xx_lun_reset, 2339 .fabric_login = qla24xx_login_fabric, 2340 .fabric_logout = qla24xx_fabric_logout, 2341 .calc_req_entries = NULL, 2342 .build_iocbs = NULL, 2343 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2344 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2345 .read_nvram = qla24xx_read_nvram_data, 2346 .write_nvram = qla24xx_write_nvram_data, 2347 .fw_dump = qla24xx_fw_dump, 2348 .beacon_on = qla24xx_beacon_on, 2349 .beacon_off = qla24xx_beacon_off, 2350 .beacon_blink = qla24xx_beacon_blink, 2351 .read_optrom = qla24xx_read_optrom_data, 2352 .write_optrom = qla24xx_write_optrom_data, 2353 .get_flash_version = qla24xx_get_flash_version, 2354 .start_scsi = qla24xx_start_scsi, 2355 .start_scsi_mq = NULL, 2356 .abort_isp = qla2x00_abort_isp, 2357 .iospace_config = qla2x00_iospace_config, 2358 .initialize_adapter = qla2x00_initialize_adapter, 2359 }; 2360 2361 static struct isp_operations qla25xx_isp_ops = { 2362 .pci_config = qla25xx_pci_config, 2363 .reset_chip = qla24xx_reset_chip, 2364 .chip_diag = qla24xx_chip_diag, 2365 .config_rings = qla24xx_config_rings, 2366 .reset_adapter = qla24xx_reset_adapter, 2367 .nvram_config = qla24xx_nvram_config, 2368 .update_fw_options = qla24xx_update_fw_options, 2369 .load_risc = qla24xx_load_risc, 2370 .pci_info_str = qla24xx_pci_info_str, 2371 .fw_version_str = qla24xx_fw_version_str, 2372 .intr_handler = qla24xx_intr_handler, 2373 .enable_intrs = qla24xx_enable_intrs, 2374 .disable_intrs = qla24xx_disable_intrs, 2375 .abort_command = qla24xx_abort_command, 2376 .target_reset = qla24xx_abort_target, 2377 .lun_reset = qla24xx_lun_reset, 2378 .fabric_login = qla24xx_login_fabric, 2379 .fabric_logout = qla24xx_fabric_logout, 2380 .calc_req_entries = NULL, 2381 .build_iocbs = NULL, 2382 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2383 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2384 .read_nvram = qla25xx_read_nvram_data, 2385 .write_nvram = qla25xx_write_nvram_data, 2386 .fw_dump = qla25xx_fw_dump, 2387 .beacon_on = qla24xx_beacon_on, 2388 .beacon_off = qla24xx_beacon_off, 2389 .beacon_blink = qla24xx_beacon_blink, 2390 .read_optrom = qla25xx_read_optrom_data, 2391 .write_optrom = qla24xx_write_optrom_data, 2392 .get_flash_version = qla24xx_get_flash_version, 2393 .start_scsi = qla24xx_dif_start_scsi, 2394 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2395 .abort_isp = qla2x00_abort_isp, 2396 .iospace_config = qla2x00_iospace_config, 2397 .initialize_adapter = qla2x00_initialize_adapter, 2398 }; 2399 2400 static struct isp_operations qla81xx_isp_ops = { 2401 .pci_config = qla25xx_pci_config, 2402 .reset_chip = qla24xx_reset_chip, 2403 .chip_diag = qla24xx_chip_diag, 2404 .config_rings = qla24xx_config_rings, 2405 .reset_adapter = qla24xx_reset_adapter, 2406 .nvram_config = qla81xx_nvram_config, 2407 .update_fw_options = qla24xx_update_fw_options, 2408 .load_risc = qla81xx_load_risc, 2409 .pci_info_str = qla24xx_pci_info_str, 2410 .fw_version_str = qla24xx_fw_version_str, 2411 .intr_handler = qla24xx_intr_handler, 2412 .enable_intrs = qla24xx_enable_intrs, 2413 .disable_intrs = qla24xx_disable_intrs, 2414 .abort_command = qla24xx_abort_command, 2415 .target_reset = qla24xx_abort_target, 2416 .lun_reset = qla24xx_lun_reset, 2417 .fabric_login = qla24xx_login_fabric, 2418 .fabric_logout = qla24xx_fabric_logout, 2419 .calc_req_entries = NULL, 2420 .build_iocbs = NULL, 2421 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2422 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2423 .read_nvram = NULL, 2424 .write_nvram = NULL, 2425 .fw_dump = qla81xx_fw_dump, 2426 .beacon_on = qla24xx_beacon_on, 2427 .beacon_off = qla24xx_beacon_off, 2428 .beacon_blink = qla83xx_beacon_blink, 2429 .read_optrom = qla25xx_read_optrom_data, 2430 .write_optrom = qla24xx_write_optrom_data, 2431 .get_flash_version = qla24xx_get_flash_version, 2432 .start_scsi = qla24xx_dif_start_scsi, 2433 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2434 .abort_isp = qla2x00_abort_isp, 2435 .iospace_config = qla2x00_iospace_config, 2436 .initialize_adapter = qla2x00_initialize_adapter, 2437 }; 2438 2439 static struct isp_operations qla82xx_isp_ops = { 2440 .pci_config = qla82xx_pci_config, 2441 .reset_chip = qla82xx_reset_chip, 2442 .chip_diag = qla24xx_chip_diag, 2443 .config_rings = qla82xx_config_rings, 2444 .reset_adapter = qla24xx_reset_adapter, 2445 .nvram_config = qla81xx_nvram_config, 2446 .update_fw_options = qla24xx_update_fw_options, 2447 .load_risc = qla82xx_load_risc, 2448 .pci_info_str = qla24xx_pci_info_str, 2449 .fw_version_str = qla24xx_fw_version_str, 2450 .intr_handler = qla82xx_intr_handler, 2451 .enable_intrs = qla82xx_enable_intrs, 2452 .disable_intrs = qla82xx_disable_intrs, 2453 .abort_command = qla24xx_abort_command, 2454 .target_reset = qla24xx_abort_target, 2455 .lun_reset = qla24xx_lun_reset, 2456 .fabric_login = qla24xx_login_fabric, 2457 .fabric_logout = qla24xx_fabric_logout, 2458 .calc_req_entries = NULL, 2459 .build_iocbs = NULL, 2460 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2461 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2462 .read_nvram = qla24xx_read_nvram_data, 2463 .write_nvram = qla24xx_write_nvram_data, 2464 .fw_dump = qla82xx_fw_dump, 2465 .beacon_on = qla82xx_beacon_on, 2466 .beacon_off = qla82xx_beacon_off, 2467 .beacon_blink = NULL, 2468 .read_optrom = qla82xx_read_optrom_data, 2469 .write_optrom = qla82xx_write_optrom_data, 2470 .get_flash_version = qla82xx_get_flash_version, 2471 .start_scsi = qla82xx_start_scsi, 2472 .start_scsi_mq = NULL, 2473 .abort_isp = qla82xx_abort_isp, 2474 .iospace_config = qla82xx_iospace_config, 2475 .initialize_adapter = qla2x00_initialize_adapter, 2476 }; 2477 2478 static struct isp_operations qla8044_isp_ops = { 2479 .pci_config = qla82xx_pci_config, 2480 .reset_chip = qla82xx_reset_chip, 2481 .chip_diag = qla24xx_chip_diag, 2482 .config_rings = qla82xx_config_rings, 2483 .reset_adapter = qla24xx_reset_adapter, 2484 .nvram_config = qla81xx_nvram_config, 2485 .update_fw_options = qla24xx_update_fw_options, 2486 .load_risc = qla82xx_load_risc, 2487 .pci_info_str = qla24xx_pci_info_str, 2488 .fw_version_str = qla24xx_fw_version_str, 2489 .intr_handler = qla8044_intr_handler, 2490 .enable_intrs = qla82xx_enable_intrs, 2491 .disable_intrs = qla82xx_disable_intrs, 2492 .abort_command = qla24xx_abort_command, 2493 .target_reset = qla24xx_abort_target, 2494 .lun_reset = qla24xx_lun_reset, 2495 .fabric_login = qla24xx_login_fabric, 2496 .fabric_logout = qla24xx_fabric_logout, 2497 .calc_req_entries = NULL, 2498 .build_iocbs = NULL, 2499 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2500 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2501 .read_nvram = NULL, 2502 .write_nvram = NULL, 2503 .fw_dump = qla8044_fw_dump, 2504 .beacon_on = qla82xx_beacon_on, 2505 .beacon_off = qla82xx_beacon_off, 2506 .beacon_blink = NULL, 2507 .read_optrom = qla8044_read_optrom_data, 2508 .write_optrom = qla8044_write_optrom_data, 2509 .get_flash_version = qla82xx_get_flash_version, 2510 .start_scsi = qla82xx_start_scsi, 2511 .start_scsi_mq = NULL, 2512 .abort_isp = qla8044_abort_isp, 2513 .iospace_config = qla82xx_iospace_config, 2514 .initialize_adapter = qla2x00_initialize_adapter, 2515 }; 2516 2517 static struct isp_operations qla83xx_isp_ops = { 2518 .pci_config = qla25xx_pci_config, 2519 .reset_chip = qla24xx_reset_chip, 2520 .chip_diag = qla24xx_chip_diag, 2521 .config_rings = qla24xx_config_rings, 2522 .reset_adapter = qla24xx_reset_adapter, 2523 .nvram_config = qla81xx_nvram_config, 2524 .update_fw_options = qla24xx_update_fw_options, 2525 .load_risc = qla81xx_load_risc, 2526 .pci_info_str = qla24xx_pci_info_str, 2527 .fw_version_str = qla24xx_fw_version_str, 2528 .intr_handler = qla24xx_intr_handler, 2529 .enable_intrs = qla24xx_enable_intrs, 2530 .disable_intrs = qla24xx_disable_intrs, 2531 .abort_command = qla24xx_abort_command, 2532 .target_reset = qla24xx_abort_target, 2533 .lun_reset = qla24xx_lun_reset, 2534 .fabric_login = qla24xx_login_fabric, 2535 .fabric_logout = qla24xx_fabric_logout, 2536 .calc_req_entries = NULL, 2537 .build_iocbs = NULL, 2538 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2539 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2540 .read_nvram = NULL, 2541 .write_nvram = NULL, 2542 .fw_dump = qla83xx_fw_dump, 2543 .beacon_on = qla24xx_beacon_on, 2544 .beacon_off = qla24xx_beacon_off, 2545 .beacon_blink = qla83xx_beacon_blink, 2546 .read_optrom = qla25xx_read_optrom_data, 2547 .write_optrom = qla24xx_write_optrom_data, 2548 .get_flash_version = qla24xx_get_flash_version, 2549 .start_scsi = qla24xx_dif_start_scsi, 2550 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2551 .abort_isp = qla2x00_abort_isp, 2552 .iospace_config = qla83xx_iospace_config, 2553 .initialize_adapter = qla2x00_initialize_adapter, 2554 }; 2555 2556 static struct isp_operations qlafx00_isp_ops = { 2557 .pci_config = qlafx00_pci_config, 2558 .reset_chip = qlafx00_soft_reset, 2559 .chip_diag = qlafx00_chip_diag, 2560 .config_rings = qlafx00_config_rings, 2561 .reset_adapter = qlafx00_soft_reset, 2562 .nvram_config = NULL, 2563 .update_fw_options = NULL, 2564 .load_risc = NULL, 2565 .pci_info_str = qlafx00_pci_info_str, 2566 .fw_version_str = qlafx00_fw_version_str, 2567 .intr_handler = qlafx00_intr_handler, 2568 .enable_intrs = qlafx00_enable_intrs, 2569 .disable_intrs = qlafx00_disable_intrs, 2570 .abort_command = qla24xx_async_abort_command, 2571 .target_reset = qlafx00_abort_target, 2572 .lun_reset = qlafx00_lun_reset, 2573 .fabric_login = NULL, 2574 .fabric_logout = NULL, 2575 .calc_req_entries = NULL, 2576 .build_iocbs = NULL, 2577 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2578 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2579 .read_nvram = qla24xx_read_nvram_data, 2580 .write_nvram = qla24xx_write_nvram_data, 2581 .fw_dump = NULL, 2582 .beacon_on = qla24xx_beacon_on, 2583 .beacon_off = qla24xx_beacon_off, 2584 .beacon_blink = NULL, 2585 .read_optrom = qla24xx_read_optrom_data, 2586 .write_optrom = qla24xx_write_optrom_data, 2587 .get_flash_version = qla24xx_get_flash_version, 2588 .start_scsi = qlafx00_start_scsi, 2589 .start_scsi_mq = NULL, 2590 .abort_isp = qlafx00_abort_isp, 2591 .iospace_config = qlafx00_iospace_config, 2592 .initialize_adapter = qlafx00_initialize_adapter, 2593 }; 2594 2595 static struct isp_operations qla27xx_isp_ops = { 2596 .pci_config = qla25xx_pci_config, 2597 .reset_chip = qla24xx_reset_chip, 2598 .chip_diag = qla24xx_chip_diag, 2599 .config_rings = qla24xx_config_rings, 2600 .reset_adapter = qla24xx_reset_adapter, 2601 .nvram_config = qla81xx_nvram_config, 2602 .update_fw_options = qla24xx_update_fw_options, 2603 .load_risc = qla81xx_load_risc, 2604 .pci_info_str = qla24xx_pci_info_str, 2605 .fw_version_str = qla24xx_fw_version_str, 2606 .intr_handler = qla24xx_intr_handler, 2607 .enable_intrs = qla24xx_enable_intrs, 2608 .disable_intrs = qla24xx_disable_intrs, 2609 .abort_command = qla24xx_abort_command, 2610 .target_reset = qla24xx_abort_target, 2611 .lun_reset = qla24xx_lun_reset, 2612 .fabric_login = qla24xx_login_fabric, 2613 .fabric_logout = qla24xx_fabric_logout, 2614 .calc_req_entries = NULL, 2615 .build_iocbs = NULL, 2616 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2617 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2618 .read_nvram = NULL, 2619 .write_nvram = NULL, 2620 .fw_dump = qla27xx_fwdump, 2621 .mpi_fw_dump = qla27xx_mpi_fwdump, 2622 .beacon_on = qla24xx_beacon_on, 2623 .beacon_off = qla24xx_beacon_off, 2624 .beacon_blink = qla83xx_beacon_blink, 2625 .read_optrom = qla25xx_read_optrom_data, 2626 .write_optrom = qla24xx_write_optrom_data, 2627 .get_flash_version = qla24xx_get_flash_version, 2628 .start_scsi = qla24xx_dif_start_scsi, 2629 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2630 .abort_isp = qla2x00_abort_isp, 2631 .iospace_config = qla83xx_iospace_config, 2632 .initialize_adapter = qla2x00_initialize_adapter, 2633 }; 2634 2635 static inline void 2636 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2637 { 2638 ha->device_type = DT_EXTENDED_IDS; 2639 switch (ha->pdev->device) { 2640 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2641 ha->isp_type |= DT_ISP2100; 2642 ha->device_type &= ~DT_EXTENDED_IDS; 2643 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2644 break; 2645 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2646 ha->isp_type |= DT_ISP2200; 2647 ha->device_type &= ~DT_EXTENDED_IDS; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2651 ha->isp_type |= DT_ISP2300; 2652 ha->device_type |= DT_ZIO_SUPPORTED; 2653 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2654 break; 2655 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2656 ha->isp_type |= DT_ISP2312; 2657 ha->device_type |= DT_ZIO_SUPPORTED; 2658 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2659 break; 2660 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2661 ha->isp_type |= DT_ISP2322; 2662 ha->device_type |= DT_ZIO_SUPPORTED; 2663 if (ha->pdev->subsystem_vendor == 0x1028 && 2664 ha->pdev->subsystem_device == 0x0170) 2665 ha->device_type |= DT_OEM_001; 2666 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2667 break; 2668 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2669 ha->isp_type |= DT_ISP6312; 2670 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2671 break; 2672 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2673 ha->isp_type |= DT_ISP6322; 2674 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2675 break; 2676 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2677 ha->isp_type |= DT_ISP2422; 2678 ha->device_type |= DT_ZIO_SUPPORTED; 2679 ha->device_type |= DT_FWI2; 2680 ha->device_type |= DT_IIDMA; 2681 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2682 break; 2683 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2684 ha->isp_type |= DT_ISP2432; 2685 ha->device_type |= DT_ZIO_SUPPORTED; 2686 ha->device_type |= DT_FWI2; 2687 ha->device_type |= DT_IIDMA; 2688 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2689 break; 2690 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2691 ha->isp_type |= DT_ISP8432; 2692 ha->device_type |= DT_ZIO_SUPPORTED; 2693 ha->device_type |= DT_FWI2; 2694 ha->device_type |= DT_IIDMA; 2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2696 break; 2697 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2698 ha->isp_type |= DT_ISP5422; 2699 ha->device_type |= DT_FWI2; 2700 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2701 break; 2702 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2703 ha->isp_type |= DT_ISP5432; 2704 ha->device_type |= DT_FWI2; 2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2706 break; 2707 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2708 ha->isp_type |= DT_ISP2532; 2709 ha->device_type |= DT_ZIO_SUPPORTED; 2710 ha->device_type |= DT_FWI2; 2711 ha->device_type |= DT_IIDMA; 2712 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2713 break; 2714 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2715 ha->isp_type |= DT_ISP8001; 2716 ha->device_type |= DT_ZIO_SUPPORTED; 2717 ha->device_type |= DT_FWI2; 2718 ha->device_type |= DT_IIDMA; 2719 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2720 break; 2721 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2722 ha->isp_type |= DT_ISP8021; 2723 ha->device_type |= DT_ZIO_SUPPORTED; 2724 ha->device_type |= DT_FWI2; 2725 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2726 /* Initialize 82XX ISP flags */ 2727 qla82xx_init_flags(ha); 2728 break; 2729 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2730 ha->isp_type |= DT_ISP8044; 2731 ha->device_type |= DT_ZIO_SUPPORTED; 2732 ha->device_type |= DT_FWI2; 2733 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2734 /* Initialize 82XX ISP flags */ 2735 qla82xx_init_flags(ha); 2736 break; 2737 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2738 ha->isp_type |= DT_ISP2031; 2739 ha->device_type |= DT_ZIO_SUPPORTED; 2740 ha->device_type |= DT_FWI2; 2741 ha->device_type |= DT_IIDMA; 2742 ha->device_type |= DT_T10_PI; 2743 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2744 break; 2745 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2746 ha->isp_type |= DT_ISP8031; 2747 ha->device_type |= DT_ZIO_SUPPORTED; 2748 ha->device_type |= DT_FWI2; 2749 ha->device_type |= DT_IIDMA; 2750 ha->device_type |= DT_T10_PI; 2751 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2752 break; 2753 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2754 ha->isp_type |= DT_ISPFX00; 2755 break; 2756 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2757 ha->isp_type |= DT_ISP2071; 2758 ha->device_type |= DT_ZIO_SUPPORTED; 2759 ha->device_type |= DT_FWI2; 2760 ha->device_type |= DT_IIDMA; 2761 ha->device_type |= DT_T10_PI; 2762 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2763 break; 2764 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2765 ha->isp_type |= DT_ISP2271; 2766 ha->device_type |= DT_ZIO_SUPPORTED; 2767 ha->device_type |= DT_FWI2; 2768 ha->device_type |= DT_IIDMA; 2769 ha->device_type |= DT_T10_PI; 2770 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2771 break; 2772 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2773 ha->isp_type |= DT_ISP2261; 2774 ha->device_type |= DT_ZIO_SUPPORTED; 2775 ha->device_type |= DT_FWI2; 2776 ha->device_type |= DT_IIDMA; 2777 ha->device_type |= DT_T10_PI; 2778 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2779 break; 2780 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2781 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2782 ha->isp_type |= DT_ISP2081; 2783 ha->device_type |= DT_ZIO_SUPPORTED; 2784 ha->device_type |= DT_FWI2; 2785 ha->device_type |= DT_IIDMA; 2786 ha->device_type |= DT_T10_PI; 2787 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2788 break; 2789 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2790 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2791 ha->isp_type |= DT_ISP2281; 2792 ha->device_type |= DT_ZIO_SUPPORTED; 2793 ha->device_type |= DT_FWI2; 2794 ha->device_type |= DT_IIDMA; 2795 ha->device_type |= DT_T10_PI; 2796 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2797 break; 2798 } 2799 2800 if (IS_QLA82XX(ha)) 2801 ha->port_no = ha->portnum & 1; 2802 else { 2803 /* Get adapter physical port no from interrupt pin register. */ 2804 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2805 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2806 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2807 ha->port_no--; 2808 else 2809 ha->port_no = !(ha->port_no & 1); 2810 } 2811 2812 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2813 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2814 ha->device_type, ha->port_no, ha->fw_srisc_address); 2815 } 2816 2817 static void 2818 qla2xxx_scan_start(struct Scsi_Host *shost) 2819 { 2820 scsi_qla_host_t *vha = shost_priv(shost); 2821 2822 if (vha->hw->flags.running_gold_fw) 2823 return; 2824 2825 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2826 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2827 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2828 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2829 } 2830 2831 static int 2832 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2833 { 2834 scsi_qla_host_t *vha = shost_priv(shost); 2835 2836 if (test_bit(UNLOADING, &vha->dpc_flags)) 2837 return 1; 2838 if (!vha->host) 2839 return 1; 2840 if (time > vha->hw->loop_reset_delay * HZ) 2841 return 1; 2842 2843 return atomic_read(&vha->loop_state) == LOOP_READY; 2844 } 2845 2846 static void qla_heartbeat_work_fn(struct work_struct *work) 2847 { 2848 struct qla_hw_data *ha = container_of(work, 2849 struct qla_hw_data, heartbeat_work); 2850 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2851 2852 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2853 qla_no_op_mb(base_vha); 2854 } 2855 2856 static void qla2x00_iocb_work_fn(struct work_struct *work) 2857 { 2858 struct scsi_qla_host *vha = container_of(work, 2859 struct scsi_qla_host, iocb_work); 2860 struct qla_hw_data *ha = vha->hw; 2861 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2862 int i = 2; 2863 unsigned long flags; 2864 2865 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2866 return; 2867 2868 while (!list_empty(&vha->work_list) && i > 0) { 2869 qla2x00_do_work(vha); 2870 i--; 2871 } 2872 2873 spin_lock_irqsave(&vha->work_lock, flags); 2874 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2875 spin_unlock_irqrestore(&vha->work_lock, flags); 2876 } 2877 2878 static void 2879 qla_trace_init(void) 2880 { 2881 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2882 if (!qla_trc_array) { 2883 ql_log(ql_log_fatal, NULL, 0x0001, 2884 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2885 return; 2886 } 2887 2888 QLA_TRACE_ENABLE(qla_trc_array); 2889 } 2890 2891 static void 2892 qla_trace_uninit(void) 2893 { 2894 if (!qla_trc_array) 2895 return; 2896 trace_array_put(qla_trc_array); 2897 } 2898 2899 /* 2900 * PCI driver interface 2901 */ 2902 static int 2903 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2904 { 2905 int ret = -ENODEV; 2906 struct Scsi_Host *host; 2907 scsi_qla_host_t *base_vha = NULL; 2908 struct qla_hw_data *ha; 2909 char pci_info[30]; 2910 char fw_str[30], wq_name[30]; 2911 struct scsi_host_template *sht; 2912 int bars, mem_only = 0; 2913 uint16_t req_length = 0, rsp_length = 0; 2914 struct req_que *req = NULL; 2915 struct rsp_que *rsp = NULL; 2916 int i; 2917 2918 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2919 sht = &qla2xxx_driver_template; 2920 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2921 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2939 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2940 mem_only = 1; 2941 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2942 "Mem only adapter.\n"); 2943 } 2944 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2945 "Bars=%d.\n", bars); 2946 2947 if (mem_only) { 2948 if (pci_enable_device_mem(pdev)) 2949 return ret; 2950 } else { 2951 if (pci_enable_device(pdev)) 2952 return ret; 2953 } 2954 2955 if (is_kdump_kernel()) { 2956 ql2xmqsupport = 0; 2957 ql2xallocfwdump = 0; 2958 } 2959 2960 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2961 if (!ha) { 2962 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2963 "Unable to allocate memory for ha.\n"); 2964 goto disable_device; 2965 } 2966 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2967 "Memory allocated for ha=%p.\n", ha); 2968 ha->pdev = pdev; 2969 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2970 spin_lock_init(&ha->tgt.q_full_lock); 2971 spin_lock_init(&ha->tgt.sess_lock); 2972 spin_lock_init(&ha->tgt.atio_lock); 2973 2974 spin_lock_init(&ha->sadb_lock); 2975 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2976 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2977 2978 spin_lock_init(&ha->sadb_fp_lock); 2979 2980 if (qla_edif_sadb_build_free_pool(ha)) { 2981 kfree(ha); 2982 goto disable_device; 2983 } 2984 2985 atomic_set(&ha->nvme_active_aen_cnt, 0); 2986 2987 /* Clear our data area */ 2988 ha->bars = bars; 2989 ha->mem_only = mem_only; 2990 spin_lock_init(&ha->hardware_lock); 2991 spin_lock_init(&ha->vport_slock); 2992 mutex_init(&ha->selflogin_lock); 2993 mutex_init(&ha->optrom_mutex); 2994 2995 /* Set ISP-type information. */ 2996 qla2x00_set_isp_flags(ha); 2997 2998 /* Set EEH reset type to fundamental if required by hba */ 2999 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 3000 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3001 pdev->needs_freset = 1; 3002 3003 ha->prev_topology = 0; 3004 ha->init_cb_size = sizeof(init_cb_t); 3005 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3006 ha->optrom_size = OPTROM_SIZE_2300; 3007 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3008 atomic_set(&ha->num_pend_mbx_stage1, 0); 3009 atomic_set(&ha->num_pend_mbx_stage2, 0); 3010 atomic_set(&ha->num_pend_mbx_stage3, 0); 3011 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3012 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3013 INIT_LIST_HEAD(&ha->tmf_pending); 3014 INIT_LIST_HEAD(&ha->tmf_active); 3015 3016 /* Assign ISP specific operations. */ 3017 if (IS_QLA2100(ha)) { 3018 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3019 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3020 req_length = REQUEST_ENTRY_CNT_2100; 3021 rsp_length = RESPONSE_ENTRY_CNT_2100; 3022 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3023 ha->gid_list_info_size = 4; 3024 ha->flash_conf_off = ~0; 3025 ha->flash_data_off = ~0; 3026 ha->nvram_conf_off = ~0; 3027 ha->nvram_data_off = ~0; 3028 ha->isp_ops = &qla2100_isp_ops; 3029 } else if (IS_QLA2200(ha)) { 3030 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3031 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3032 req_length = REQUEST_ENTRY_CNT_2200; 3033 rsp_length = RESPONSE_ENTRY_CNT_2100; 3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3035 ha->gid_list_info_size = 4; 3036 ha->flash_conf_off = ~0; 3037 ha->flash_data_off = ~0; 3038 ha->nvram_conf_off = ~0; 3039 ha->nvram_data_off = ~0; 3040 ha->isp_ops = &qla2100_isp_ops; 3041 } else if (IS_QLA23XX(ha)) { 3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3043 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3044 req_length = REQUEST_ENTRY_CNT_2200; 3045 rsp_length = RESPONSE_ENTRY_CNT_2300; 3046 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3047 ha->gid_list_info_size = 6; 3048 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3049 ha->optrom_size = OPTROM_SIZE_2322; 3050 ha->flash_conf_off = ~0; 3051 ha->flash_data_off = ~0; 3052 ha->nvram_conf_off = ~0; 3053 ha->nvram_data_off = ~0; 3054 ha->isp_ops = &qla2300_isp_ops; 3055 } else if (IS_QLA24XX_TYPE(ha)) { 3056 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3057 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3058 req_length = REQUEST_ENTRY_CNT_24XX; 3059 rsp_length = RESPONSE_ENTRY_CNT_2300; 3060 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3061 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3062 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3063 ha->gid_list_info_size = 8; 3064 ha->optrom_size = OPTROM_SIZE_24XX; 3065 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3066 ha->isp_ops = &qla24xx_isp_ops; 3067 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3068 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3069 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3070 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3071 } else if (IS_QLA25XX(ha)) { 3072 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3073 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3074 req_length = REQUEST_ENTRY_CNT_24XX; 3075 rsp_length = RESPONSE_ENTRY_CNT_2300; 3076 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3077 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3078 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3079 ha->gid_list_info_size = 8; 3080 ha->optrom_size = OPTROM_SIZE_25XX; 3081 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3082 ha->isp_ops = &qla25xx_isp_ops; 3083 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3084 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3085 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3086 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3087 } else if (IS_QLA81XX(ha)) { 3088 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3089 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3090 req_length = REQUEST_ENTRY_CNT_24XX; 3091 rsp_length = RESPONSE_ENTRY_CNT_2300; 3092 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3093 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3094 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3095 ha->gid_list_info_size = 8; 3096 ha->optrom_size = OPTROM_SIZE_81XX; 3097 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3098 ha->isp_ops = &qla81xx_isp_ops; 3099 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3100 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3101 ha->nvram_conf_off = ~0; 3102 ha->nvram_data_off = ~0; 3103 } else if (IS_QLA82XX(ha)) { 3104 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3105 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3106 req_length = REQUEST_ENTRY_CNT_82XX; 3107 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3108 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3109 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3110 ha->gid_list_info_size = 8; 3111 ha->optrom_size = OPTROM_SIZE_82XX; 3112 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3113 ha->isp_ops = &qla82xx_isp_ops; 3114 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3115 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3116 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3117 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3118 } else if (IS_QLA8044(ha)) { 3119 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3120 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3121 req_length = REQUEST_ENTRY_CNT_82XX; 3122 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3123 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3124 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3125 ha->gid_list_info_size = 8; 3126 ha->optrom_size = OPTROM_SIZE_83XX; 3127 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3128 ha->isp_ops = &qla8044_isp_ops; 3129 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3130 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3131 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3132 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3133 } else if (IS_QLA83XX(ha)) { 3134 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3135 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3136 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3137 req_length = REQUEST_ENTRY_CNT_83XX; 3138 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3139 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3140 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3141 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3142 ha->gid_list_info_size = 8; 3143 ha->optrom_size = OPTROM_SIZE_83XX; 3144 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3145 ha->isp_ops = &qla83xx_isp_ops; 3146 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3147 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3148 ha->nvram_conf_off = ~0; 3149 ha->nvram_data_off = ~0; 3150 } else if (IS_QLAFX00(ha)) { 3151 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3152 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3153 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3154 req_length = REQUEST_ENTRY_CNT_FX00; 3155 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3156 ha->isp_ops = &qlafx00_isp_ops; 3157 ha->port_down_retry_count = 30; /* default value */ 3158 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3159 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3160 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3161 ha->mr.fw_hbt_en = 1; 3162 ha->mr.host_info_resend = false; 3163 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3164 } else if (IS_QLA27XX(ha)) { 3165 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3166 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3167 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3168 req_length = REQUEST_ENTRY_CNT_83XX; 3169 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3170 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3171 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3172 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3173 ha->gid_list_info_size = 8; 3174 ha->optrom_size = OPTROM_SIZE_83XX; 3175 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3176 ha->isp_ops = &qla27xx_isp_ops; 3177 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3178 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3179 ha->nvram_conf_off = ~0; 3180 ha->nvram_data_off = ~0; 3181 } else if (IS_QLA28XX(ha)) { 3182 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3183 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3184 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3185 req_length = REQUEST_ENTRY_CNT_83XX; 3186 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3187 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3188 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3189 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3190 ha->gid_list_info_size = 8; 3191 ha->optrom_size = OPTROM_SIZE_28XX; 3192 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3193 ha->isp_ops = &qla27xx_isp_ops; 3194 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3195 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3196 ha->nvram_conf_off = ~0; 3197 ha->nvram_data_off = ~0; 3198 } 3199 3200 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3201 "mbx_count=%d, req_length=%d, " 3202 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3203 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3204 "max_fibre_devices=%d.\n", 3205 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3206 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3207 ha->nvram_npiv_size, ha->max_fibre_devices); 3208 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3209 "isp_ops=%p, flash_conf_off=%d, " 3210 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3211 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3212 ha->nvram_conf_off, ha->nvram_data_off); 3213 3214 /* Configure PCI I/O space */ 3215 ret = ha->isp_ops->iospace_config(ha); 3216 if (ret) 3217 goto iospace_config_failed; 3218 3219 ql_log_pci(ql_log_info, pdev, 0x001d, 3220 "Found an ISP%04X irq %d iobase 0x%p.\n", 3221 pdev->device, pdev->irq, ha->iobase); 3222 mutex_init(&ha->vport_lock); 3223 mutex_init(&ha->mq_lock); 3224 init_completion(&ha->mbx_cmd_comp); 3225 complete(&ha->mbx_cmd_comp); 3226 init_completion(&ha->mbx_intr_comp); 3227 init_completion(&ha->dcbx_comp); 3228 init_completion(&ha->lb_portup_comp); 3229 3230 set_bit(0, (unsigned long *) ha->vp_idx_map); 3231 3232 qla2x00_config_dma_addressing(ha); 3233 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3234 "64 Bit addressing is %s.\n", 3235 ha->flags.enable_64bit_addressing ? "enable" : 3236 "disable"); 3237 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3238 if (ret) { 3239 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3240 "Failed to allocate memory for adapter, aborting.\n"); 3241 3242 goto probe_hw_failed; 3243 } 3244 3245 req->max_q_depth = MAX_Q_DEPTH; 3246 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3247 req->max_q_depth = ql2xmaxqdepth; 3248 3249 3250 base_vha = qla2x00_create_host(sht, ha); 3251 if (!base_vha) { 3252 ret = -ENOMEM; 3253 goto probe_hw_failed; 3254 } 3255 3256 pci_set_drvdata(pdev, base_vha); 3257 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3258 3259 host = base_vha->host; 3260 base_vha->req = req; 3261 if (IS_QLA2XXX_MIDTYPE(ha)) 3262 base_vha->mgmt_svr_loop_id = 3263 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3264 else 3265 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3266 base_vha->vp_idx; 3267 3268 /* Setup fcport template structure. */ 3269 ha->mr.fcport.vha = base_vha; 3270 ha->mr.fcport.port_type = FCT_UNKNOWN; 3271 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3272 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3273 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3274 ha->mr.fcport.scan_state = 1; 3275 3276 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3277 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3278 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3279 3280 /* Set the SG table size based on ISP type */ 3281 if (!IS_FWI2_CAPABLE(ha)) { 3282 if (IS_QLA2100(ha)) 3283 host->sg_tablesize = 32; 3284 } else { 3285 if (!IS_QLA82XX(ha)) 3286 host->sg_tablesize = QLA_SG_ALL; 3287 } 3288 host->max_id = ha->max_fibre_devices; 3289 host->cmd_per_lun = 3; 3290 host->unique_id = host->host_no; 3291 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3292 host->max_cmd_len = 32; 3293 else 3294 host->max_cmd_len = MAX_CMDSZ; 3295 host->max_channel = MAX_BUSES - 1; 3296 /* Older HBAs support only 16-bit LUNs */ 3297 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3298 ql2xmaxlun > 0xffff) 3299 host->max_lun = 0xffff; 3300 else 3301 host->max_lun = ql2xmaxlun; 3302 host->transportt = qla2xxx_transport_template; 3303 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3304 3305 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3306 "max_id=%d this_id=%d " 3307 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3308 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3309 host->this_id, host->cmd_per_lun, host->unique_id, 3310 host->max_cmd_len, host->max_channel, host->max_lun, 3311 host->transportt, sht->vendor_id); 3312 3313 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3314 3315 /* Set up the irqs */ 3316 ret = qla2x00_request_irqs(ha, rsp); 3317 if (ret) 3318 goto probe_failed; 3319 3320 /* Alloc arrays of request and response ring ptrs */ 3321 ret = qla2x00_alloc_queues(ha, req, rsp); 3322 if (ret) { 3323 ql_log(ql_log_fatal, base_vha, 0x003d, 3324 "Failed to allocate memory for queue pointers..." 3325 "aborting.\n"); 3326 ret = -ENODEV; 3327 goto probe_failed; 3328 } 3329 3330 if (ha->mqenable) { 3331 /* number of hardware queues supported by blk/scsi-mq*/ 3332 host->nr_hw_queues = ha->max_qpairs; 3333 3334 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3335 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3336 } else { 3337 if (ql2xnvmeenable) { 3338 host->nr_hw_queues = ha->max_qpairs; 3339 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3340 "FC-NVMe support is enabled, HW queues=%d\n", 3341 host->nr_hw_queues); 3342 } else { 3343 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3344 "blk/scsi-mq disabled.\n"); 3345 } 3346 } 3347 3348 qlt_probe_one_stage1(base_vha, ha); 3349 3350 pci_save_state(pdev); 3351 3352 /* Assign back pointers */ 3353 rsp->req = req; 3354 req->rsp = rsp; 3355 3356 if (IS_QLAFX00(ha)) { 3357 ha->rsp_q_map[0] = rsp; 3358 ha->req_q_map[0] = req; 3359 set_bit(0, ha->req_qid_map); 3360 set_bit(0, ha->rsp_qid_map); 3361 } 3362 3363 /* FWI2-capable only. */ 3364 req->req_q_in = &ha->iobase->isp24.req_q_in; 3365 req->req_q_out = &ha->iobase->isp24.req_q_out; 3366 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3367 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3368 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3369 IS_QLA28XX(ha)) { 3370 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3371 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3372 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3373 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3374 } 3375 3376 if (IS_QLAFX00(ha)) { 3377 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3378 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3379 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3380 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3381 } 3382 3383 if (IS_P3P_TYPE(ha)) { 3384 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3385 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3386 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3387 } 3388 3389 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3390 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3391 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3392 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3393 "req->req_q_in=%p req->req_q_out=%p " 3394 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3395 req->req_q_in, req->req_q_out, 3396 rsp->rsp_q_in, rsp->rsp_q_out); 3397 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3398 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3399 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3400 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3401 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3402 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3403 3404 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3405 if (unlikely(!ha->wq)) { 3406 ret = -ENOMEM; 3407 goto probe_failed; 3408 } 3409 3410 if (ha->isp_ops->initialize_adapter(base_vha)) { 3411 ql_log(ql_log_fatal, base_vha, 0x00d6, 3412 "Failed to initialize adapter - Adapter flags %x.\n", 3413 base_vha->device_flags); 3414 3415 if (IS_QLA82XX(ha)) { 3416 qla82xx_idc_lock(ha); 3417 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3418 QLA8XXX_DEV_FAILED); 3419 qla82xx_idc_unlock(ha); 3420 ql_log(ql_log_fatal, base_vha, 0x00d7, 3421 "HW State: FAILED.\n"); 3422 } else if (IS_QLA8044(ha)) { 3423 qla8044_idc_lock(ha); 3424 qla8044_wr_direct(base_vha, 3425 QLA8044_CRB_DEV_STATE_INDEX, 3426 QLA8XXX_DEV_FAILED); 3427 qla8044_idc_unlock(ha); 3428 ql_log(ql_log_fatal, base_vha, 0x0150, 3429 "HW State: FAILED.\n"); 3430 } 3431 3432 ret = -ENODEV; 3433 goto probe_failed; 3434 } 3435 3436 if (IS_QLAFX00(ha)) 3437 host->can_queue = QLAFX00_MAX_CANQUEUE; 3438 else 3439 host->can_queue = req->num_outstanding_cmds - 10; 3440 3441 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3442 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3443 host->can_queue, base_vha->req, 3444 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3445 3446 /* Check if FW supports MQ or not for ISP25xx */ 3447 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3448 ha->mqenable = 0; 3449 3450 if (ha->mqenable) { 3451 bool startit = false; 3452 3453 if (QLA_TGT_MODE_ENABLED()) 3454 startit = false; 3455 3456 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3457 startit = true; 3458 3459 /* Create start of day qpairs for Block MQ */ 3460 for (i = 0; i < ha->max_qpairs; i++) 3461 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3462 } 3463 qla_init_iocb_limit(base_vha); 3464 3465 if (ha->flags.running_gold_fw) 3466 goto skip_dpc; 3467 3468 /* 3469 * Startup the kernel thread for this host adapter 3470 */ 3471 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3472 "%s_dpc", base_vha->host_str); 3473 if (IS_ERR(ha->dpc_thread)) { 3474 ql_log(ql_log_fatal, base_vha, 0x00ed, 3475 "Failed to start DPC thread.\n"); 3476 ret = PTR_ERR(ha->dpc_thread); 3477 ha->dpc_thread = NULL; 3478 goto probe_failed; 3479 } 3480 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3481 "DPC thread started successfully.\n"); 3482 3483 /* 3484 * If we're not coming up in initiator mode, we might sit for 3485 * a while without waking up the dpc thread, which leads to a 3486 * stuck process warning. So just kick the dpc once here and 3487 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3488 */ 3489 qla2xxx_wake_dpc(base_vha); 3490 3491 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3492 3493 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3494 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3495 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3496 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3497 3498 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3499 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3500 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3501 INIT_WORK(&ha->idc_state_handler, 3502 qla83xx_idc_state_handler_work); 3503 INIT_WORK(&ha->nic_core_unrecoverable, 3504 qla83xx_nic_core_unrecoverable_work); 3505 } 3506 3507 skip_dpc: 3508 list_add_tail(&base_vha->list, &ha->vp_list); 3509 base_vha->host->irq = ha->pdev->irq; 3510 3511 /* Initialized the timer */ 3512 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3513 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3514 "Started qla2x00_timer with " 3515 "interval=%d.\n", WATCH_INTERVAL); 3516 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3517 "Detected hba at address=%p.\n", 3518 ha); 3519 3520 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3521 if (ha->fw_attributes & BIT_4) { 3522 int prot = 0, guard; 3523 3524 base_vha->flags.difdix_supported = 1; 3525 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3526 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3527 if (ql2xenabledif == 1) 3528 prot = SHOST_DIX_TYPE0_PROTECTION; 3529 if (ql2xprotmask) 3530 scsi_host_set_prot(host, ql2xprotmask); 3531 else 3532 scsi_host_set_prot(host, 3533 prot | SHOST_DIF_TYPE1_PROTECTION 3534 | SHOST_DIF_TYPE2_PROTECTION 3535 | SHOST_DIF_TYPE3_PROTECTION 3536 | SHOST_DIX_TYPE1_PROTECTION 3537 | SHOST_DIX_TYPE2_PROTECTION 3538 | SHOST_DIX_TYPE3_PROTECTION); 3539 3540 guard = SHOST_DIX_GUARD_CRC; 3541 3542 if (IS_PI_IPGUARD_CAPABLE(ha) && 3543 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3544 guard |= SHOST_DIX_GUARD_IP; 3545 3546 if (ql2xprotguard) 3547 scsi_host_set_guard(host, ql2xprotguard); 3548 else 3549 scsi_host_set_guard(host, guard); 3550 } else 3551 base_vha->flags.difdix_supported = 0; 3552 } 3553 3554 ha->isp_ops->enable_intrs(ha); 3555 3556 if (IS_QLAFX00(ha)) { 3557 ret = qlafx00_fx_disc(base_vha, 3558 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3559 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3560 QLA_SG_ALL : 128; 3561 } 3562 3563 ret = scsi_add_host(host, &pdev->dev); 3564 if (ret) 3565 goto probe_failed; 3566 3567 base_vha->flags.init_done = 1; 3568 base_vha->flags.online = 1; 3569 ha->prev_minidump_failed = 0; 3570 3571 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3572 "Init done and hba is online.\n"); 3573 3574 if (qla_ini_mode_enabled(base_vha) || 3575 qla_dual_mode_enabled(base_vha)) 3576 scsi_scan_host(host); 3577 else 3578 ql_log(ql_log_info, base_vha, 0x0122, 3579 "skipping scsi_scan_host() for non-initiator port\n"); 3580 3581 qla2x00_alloc_sysfs_attr(base_vha); 3582 3583 if (IS_QLAFX00(ha)) { 3584 ret = qlafx00_fx_disc(base_vha, 3585 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3586 3587 /* Register system information */ 3588 ret = qlafx00_fx_disc(base_vha, 3589 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3590 } 3591 3592 qla2x00_init_host_attr(base_vha); 3593 3594 qla2x00_dfs_setup(base_vha); 3595 3596 ql_log(ql_log_info, base_vha, 0x00fb, 3597 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3598 ql_log(ql_log_info, base_vha, 0x00fc, 3599 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3600 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3601 sizeof(pci_info)), 3602 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3603 base_vha->host_no, 3604 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3605 3606 qlt_add_target(ha, base_vha); 3607 3608 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3609 3610 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3611 return -ENODEV; 3612 3613 return 0; 3614 3615 probe_failed: 3616 qla_enode_stop(base_vha); 3617 qla_edb_stop(base_vha); 3618 vfree(base_vha->scan.l); 3619 if (base_vha->gnl.l) { 3620 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3621 base_vha->gnl.l, base_vha->gnl.ldma); 3622 base_vha->gnl.l = NULL; 3623 } 3624 3625 if (base_vha->timer_active) 3626 qla2x00_stop_timer(base_vha); 3627 base_vha->flags.online = 0; 3628 if (ha->dpc_thread) { 3629 struct task_struct *t = ha->dpc_thread; 3630 3631 ha->dpc_thread = NULL; 3632 kthread_stop(t); 3633 } 3634 3635 qla2x00_free_device(base_vha); 3636 scsi_host_put(base_vha->host); 3637 /* 3638 * Need to NULL out local req/rsp after 3639 * qla2x00_free_device => qla2x00_free_queues frees 3640 * what these are pointing to. Or else we'll 3641 * fall over below in qla2x00_free_req/rsp_que. 3642 */ 3643 req = NULL; 3644 rsp = NULL; 3645 3646 probe_hw_failed: 3647 qla2x00_mem_free(ha); 3648 qla2x00_free_req_que(ha, req); 3649 qla2x00_free_rsp_que(ha, rsp); 3650 qla2x00_clear_drv_active(ha); 3651 3652 iospace_config_failed: 3653 if (IS_P3P_TYPE(ha)) { 3654 if (!ha->nx_pcibase) 3655 iounmap((device_reg_t *)ha->nx_pcibase); 3656 if (!ql2xdbwr) 3657 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3658 } else { 3659 if (ha->iobase) 3660 iounmap(ha->iobase); 3661 if (ha->cregbase) 3662 iounmap(ha->cregbase); 3663 } 3664 pci_release_selected_regions(ha->pdev, ha->bars); 3665 kfree(ha); 3666 3667 disable_device: 3668 pci_disable_device(pdev); 3669 return ret; 3670 } 3671 3672 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3673 { 3674 scsi_qla_host_t *vp; 3675 unsigned long flags; 3676 struct qla_hw_data *ha; 3677 3678 if (!base_vha) 3679 return; 3680 3681 ha = base_vha->hw; 3682 3683 spin_lock_irqsave(&ha->vport_slock, flags); 3684 list_for_each_entry(vp, &ha->vp_list, list) 3685 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3686 3687 /* 3688 * Indicate device removal to prevent future board_disable 3689 * and wait until any pending board_disable has completed. 3690 */ 3691 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3692 spin_unlock_irqrestore(&ha->vport_slock, flags); 3693 } 3694 3695 static void 3696 qla2x00_shutdown(struct pci_dev *pdev) 3697 { 3698 scsi_qla_host_t *vha; 3699 struct qla_hw_data *ha; 3700 3701 vha = pci_get_drvdata(pdev); 3702 ha = vha->hw; 3703 3704 ql_log(ql_log_info, vha, 0xfffa, 3705 "Adapter shutdown\n"); 3706 3707 /* 3708 * Prevent future board_disable and wait 3709 * until any pending board_disable has completed. 3710 */ 3711 __qla_set_remove_flag(vha); 3712 cancel_work_sync(&ha->board_disable); 3713 3714 if (!atomic_read(&pdev->enable_cnt)) 3715 return; 3716 3717 /* Notify ISPFX00 firmware */ 3718 if (IS_QLAFX00(ha)) 3719 qlafx00_driver_shutdown(vha, 20); 3720 3721 /* Turn-off FCE trace */ 3722 if (ha->flags.fce_enabled) { 3723 qla2x00_disable_fce_trace(vha, NULL, NULL); 3724 ha->flags.fce_enabled = 0; 3725 } 3726 3727 /* Turn-off EFT trace */ 3728 if (ha->eft) 3729 qla2x00_disable_eft_trace(vha); 3730 3731 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3732 IS_QLA28XX(ha)) { 3733 if (ha->flags.fw_started) 3734 qla2x00_abort_isp_cleanup(vha); 3735 } else { 3736 /* Stop currently executing firmware. */ 3737 qla2x00_try_to_stop_firmware(vha); 3738 } 3739 3740 /* Disable timer */ 3741 if (vha->timer_active) 3742 qla2x00_stop_timer(vha); 3743 3744 /* Turn adapter off line */ 3745 vha->flags.online = 0; 3746 3747 /* turn-off interrupts on the card */ 3748 if (ha->interrupts_on) { 3749 vha->flags.init_done = 0; 3750 ha->isp_ops->disable_intrs(ha); 3751 } 3752 3753 qla2x00_free_irqs(vha); 3754 3755 qla2x00_free_fw_dump(ha); 3756 3757 pci_disable_device(pdev); 3758 ql_log(ql_log_info, vha, 0xfffe, 3759 "Adapter shutdown successfully.\n"); 3760 } 3761 3762 /* Deletes all the virtual ports for a given ha */ 3763 static void 3764 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3765 { 3766 scsi_qla_host_t *vha; 3767 unsigned long flags; 3768 3769 mutex_lock(&ha->vport_lock); 3770 while (ha->cur_vport_count) { 3771 spin_lock_irqsave(&ha->vport_slock, flags); 3772 3773 BUG_ON(base_vha->list.next == &ha->vp_list); 3774 /* This assumes first entry in ha->vp_list is always base vha */ 3775 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3776 scsi_host_get(vha->host); 3777 3778 spin_unlock_irqrestore(&ha->vport_slock, flags); 3779 mutex_unlock(&ha->vport_lock); 3780 3781 qla_nvme_delete(vha); 3782 3783 fc_vport_terminate(vha->fc_vport); 3784 scsi_host_put(vha->host); 3785 3786 mutex_lock(&ha->vport_lock); 3787 } 3788 mutex_unlock(&ha->vport_lock); 3789 } 3790 3791 /* Stops all deferred work threads */ 3792 static void 3793 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3794 { 3795 /* Cancel all work and destroy DPC workqueues */ 3796 if (ha->dpc_lp_wq) { 3797 cancel_work_sync(&ha->idc_aen); 3798 destroy_workqueue(ha->dpc_lp_wq); 3799 ha->dpc_lp_wq = NULL; 3800 } 3801 3802 if (ha->dpc_hp_wq) { 3803 cancel_work_sync(&ha->nic_core_reset); 3804 cancel_work_sync(&ha->idc_state_handler); 3805 cancel_work_sync(&ha->nic_core_unrecoverable); 3806 destroy_workqueue(ha->dpc_hp_wq); 3807 ha->dpc_hp_wq = NULL; 3808 } 3809 3810 /* Kill the kernel thread for this host */ 3811 if (ha->dpc_thread) { 3812 struct task_struct *t = ha->dpc_thread; 3813 3814 /* 3815 * qla2xxx_wake_dpc checks for ->dpc_thread 3816 * so we need to zero it out. 3817 */ 3818 ha->dpc_thread = NULL; 3819 kthread_stop(t); 3820 } 3821 } 3822 3823 static void 3824 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3825 { 3826 if (IS_QLA82XX(ha)) { 3827 3828 iounmap((device_reg_t *)ha->nx_pcibase); 3829 if (!ql2xdbwr) 3830 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3831 } else { 3832 if (ha->iobase) 3833 iounmap(ha->iobase); 3834 3835 if (ha->cregbase) 3836 iounmap(ha->cregbase); 3837 3838 if (ha->mqiobase) 3839 iounmap(ha->mqiobase); 3840 3841 if (ha->msixbase) 3842 iounmap(ha->msixbase); 3843 } 3844 } 3845 3846 static void 3847 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3848 { 3849 if (IS_QLA8044(ha)) { 3850 qla8044_idc_lock(ha); 3851 qla8044_clear_drv_active(ha); 3852 qla8044_idc_unlock(ha); 3853 } else if (IS_QLA82XX(ha)) { 3854 qla82xx_idc_lock(ha); 3855 qla82xx_clear_drv_active(ha); 3856 qla82xx_idc_unlock(ha); 3857 } 3858 } 3859 3860 static void 3861 qla2x00_remove_one(struct pci_dev *pdev) 3862 { 3863 scsi_qla_host_t *base_vha; 3864 struct qla_hw_data *ha; 3865 3866 base_vha = pci_get_drvdata(pdev); 3867 ha = base_vha->hw; 3868 ql_log(ql_log_info, base_vha, 0xb079, 3869 "Removing driver\n"); 3870 __qla_set_remove_flag(base_vha); 3871 cancel_work_sync(&ha->board_disable); 3872 3873 /* 3874 * If the PCI device is disabled then there was a PCI-disconnect and 3875 * qla2x00_disable_board_on_pci_error has taken care of most of the 3876 * resources. 3877 */ 3878 if (!atomic_read(&pdev->enable_cnt)) { 3879 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3880 base_vha->gnl.l, base_vha->gnl.ldma); 3881 base_vha->gnl.l = NULL; 3882 scsi_host_put(base_vha->host); 3883 kfree(ha); 3884 pci_set_drvdata(pdev, NULL); 3885 return; 3886 } 3887 qla2x00_wait_for_hba_ready(base_vha); 3888 3889 /* 3890 * if UNLOADING flag is already set, then continue unload, 3891 * where it was set first. 3892 */ 3893 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3894 return; 3895 3896 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3897 IS_QLA28XX(ha)) { 3898 if (ha->flags.fw_started) 3899 qla2x00_abort_isp_cleanup(base_vha); 3900 } else if (!IS_QLAFX00(ha)) { 3901 if (IS_QLA8031(ha)) { 3902 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3903 "Clearing fcoe driver presence.\n"); 3904 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3905 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3906 "Error while clearing DRV-Presence.\n"); 3907 } 3908 3909 qla2x00_try_to_stop_firmware(base_vha); 3910 } 3911 3912 qla2x00_wait_for_sess_deletion(base_vha); 3913 3914 qla_nvme_delete(base_vha); 3915 3916 dma_free_coherent(&ha->pdev->dev, 3917 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3918 3919 base_vha->gnl.l = NULL; 3920 qla_enode_stop(base_vha); 3921 qla_edb_stop(base_vha); 3922 3923 vfree(base_vha->scan.l); 3924 3925 if (IS_QLAFX00(ha)) 3926 qlafx00_driver_shutdown(base_vha, 20); 3927 3928 qla2x00_delete_all_vps(ha, base_vha); 3929 3930 qla2x00_dfs_remove(base_vha); 3931 3932 qla84xx_put_chip(base_vha); 3933 3934 /* Disable timer */ 3935 if (base_vha->timer_active) 3936 qla2x00_stop_timer(base_vha); 3937 3938 base_vha->flags.online = 0; 3939 3940 /* free DMA memory */ 3941 if (ha->exlogin_buf) 3942 qla2x00_free_exlogin_buffer(ha); 3943 3944 /* free DMA memory */ 3945 if (ha->exchoffld_buf) 3946 qla2x00_free_exchoffld_buffer(ha); 3947 3948 qla2x00_destroy_deferred_work(ha); 3949 3950 qlt_remove_target(ha, base_vha); 3951 3952 qla2x00_free_sysfs_attr(base_vha, true); 3953 3954 fc_remove_host(base_vha->host); 3955 3956 scsi_remove_host(base_vha->host); 3957 3958 qla2x00_free_device(base_vha); 3959 3960 qla2x00_clear_drv_active(ha); 3961 3962 scsi_host_put(base_vha->host); 3963 3964 qla2x00_unmap_iobases(ha); 3965 3966 pci_release_selected_regions(ha->pdev, ha->bars); 3967 kfree(ha); 3968 3969 pci_disable_device(pdev); 3970 } 3971 3972 static inline void 3973 qla24xx_free_purex_list(struct purex_list *list) 3974 { 3975 struct purex_item *item, *next; 3976 ulong flags; 3977 3978 spin_lock_irqsave(&list->lock, flags); 3979 list_for_each_entry_safe(item, next, &list->head, list) { 3980 list_del(&item->list); 3981 if (item == &item->vha->default_item) 3982 continue; 3983 kfree(item); 3984 } 3985 spin_unlock_irqrestore(&list->lock, flags); 3986 } 3987 3988 static void 3989 qla2x00_free_device(scsi_qla_host_t *vha) 3990 { 3991 struct qla_hw_data *ha = vha->hw; 3992 3993 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3994 3995 /* Disable timer */ 3996 if (vha->timer_active) 3997 qla2x00_stop_timer(vha); 3998 3999 qla25xx_delete_queues(vha); 4000 vha->flags.online = 0; 4001 4002 /* turn-off interrupts on the card */ 4003 if (ha->interrupts_on) { 4004 vha->flags.init_done = 0; 4005 ha->isp_ops->disable_intrs(ha); 4006 } 4007 4008 qla2x00_free_fcports(vha); 4009 4010 qla2x00_free_irqs(vha); 4011 4012 /* Flush the work queue and remove it */ 4013 if (ha->wq) { 4014 destroy_workqueue(ha->wq); 4015 ha->wq = NULL; 4016 } 4017 4018 4019 qla24xx_free_purex_list(&vha->purex_list); 4020 4021 qla2x00_mem_free(ha); 4022 4023 qla82xx_md_free(vha); 4024 4025 qla_edif_sadb_release_free_pool(ha); 4026 qla_edif_sadb_release(ha); 4027 4028 qla2x00_free_queues(ha); 4029 } 4030 4031 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4032 { 4033 fc_port_t *fcport, *tfcport; 4034 4035 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4036 qla2x00_free_fcport(fcport); 4037 } 4038 4039 static inline void 4040 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4041 { 4042 int now; 4043 4044 if (!fcport->rport) 4045 return; 4046 4047 if (fcport->rport) { 4048 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4049 "%s %8phN. rport %p roles %x\n", 4050 __func__, fcport->port_name, fcport->rport, 4051 fcport->rport->roles); 4052 fc_remote_port_delete(fcport->rport); 4053 } 4054 qlt_do_generation_tick(vha, &now); 4055 } 4056 4057 /* 4058 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4059 * 4060 * Input: ha = adapter block pointer. fcport = port structure pointer. 4061 * 4062 * Return: None. 4063 * 4064 * Context: 4065 */ 4066 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4067 int do_login) 4068 { 4069 if (IS_QLAFX00(vha->hw)) { 4070 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4071 qla2x00_schedule_rport_del(vha, fcport); 4072 return; 4073 } 4074 4075 if (atomic_read(&fcport->state) == FCS_ONLINE && 4076 vha->vp_idx == fcport->vha->vp_idx) { 4077 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4078 qla2x00_schedule_rport_del(vha, fcport); 4079 } 4080 4081 /* 4082 * We may need to retry the login, so don't change the state of the 4083 * port but do the retries. 4084 */ 4085 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4086 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4087 4088 if (!do_login) 4089 return; 4090 4091 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4092 } 4093 4094 void 4095 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4096 { 4097 fc_port_t *fcport; 4098 4099 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4100 "Mark all dev lost\n"); 4101 4102 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4103 if (ql2xfc2target && 4104 fcport->loop_id != FC_NO_LOOP_ID && 4105 (fcport->flags & FCF_FCP2_DEVICE) && 4106 fcport->port_type == FCT_TARGET && 4107 !qla2x00_reset_active(vha)) { 4108 ql_dbg(ql_dbg_disc, vha, 0x211a, 4109 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4110 fcport->flags, fcport->port_type, 4111 fcport->d_id.b24, fcport->port_name); 4112 continue; 4113 } 4114 fcport->scan_state = 0; 4115 qlt_schedule_sess_for_deletion(fcport); 4116 } 4117 } 4118 4119 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4120 { 4121 int i; 4122 4123 if (IS_FWI2_CAPABLE(ha)) 4124 return; 4125 4126 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4127 set_bit(i, ha->loop_id_map); 4128 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4129 set_bit(BROADCAST, ha->loop_id_map); 4130 } 4131 4132 /* 4133 * qla2x00_mem_alloc 4134 * Allocates adapter memory. 4135 * 4136 * Returns: 4137 * 0 = success. 4138 * !0 = failure. 4139 */ 4140 static int 4141 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4142 struct req_que **req, struct rsp_que **rsp) 4143 { 4144 char name[16]; 4145 int rc; 4146 4147 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4148 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4149 if (!ha->vp_map) 4150 goto fail; 4151 } 4152 4153 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4154 &ha->init_cb_dma, GFP_KERNEL); 4155 if (!ha->init_cb) 4156 goto fail_free_vp_map; 4157 4158 rc = btree_init32(&ha->host_map); 4159 if (rc) 4160 goto fail_free_init_cb; 4161 4162 if (qlt_mem_alloc(ha) < 0) 4163 goto fail_free_btree; 4164 4165 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4166 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4167 if (!ha->gid_list) 4168 goto fail_free_tgt_mem; 4169 4170 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4171 if (!ha->srb_mempool) 4172 goto fail_free_gid_list; 4173 4174 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4175 /* Allocate cache for CT6 Ctx. */ 4176 if (!ctx_cachep) { 4177 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4178 sizeof(struct ct6_dsd), 0, 4179 SLAB_HWCACHE_ALIGN, NULL); 4180 if (!ctx_cachep) 4181 goto fail_free_srb_mempool; 4182 } 4183 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4184 ctx_cachep); 4185 if (!ha->ctx_mempool) 4186 goto fail_free_srb_mempool; 4187 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4188 "ctx_cachep=%p ctx_mempool=%p.\n", 4189 ctx_cachep, ha->ctx_mempool); 4190 } 4191 4192 /* Get memory for cached NVRAM */ 4193 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4194 if (!ha->nvram) 4195 goto fail_free_ctx_mempool; 4196 4197 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4198 ha->pdev->device); 4199 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4200 DMA_POOL_SIZE, 8, 0); 4201 if (!ha->s_dma_pool) 4202 goto fail_free_nvram; 4203 4204 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4205 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4206 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4207 4208 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4209 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4210 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4211 if (!ha->dl_dma_pool) { 4212 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4213 "Failed to allocate memory for dl_dma_pool.\n"); 4214 goto fail_s_dma_pool; 4215 } 4216 4217 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4218 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4219 if (!ha->fcp_cmnd_dma_pool) { 4220 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4221 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4222 goto fail_dl_dma_pool; 4223 } 4224 4225 if (ql2xenabledif) { 4226 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4227 struct dsd_dma *dsd, *nxt; 4228 uint i; 4229 /* Creata a DMA pool of buffers for DIF bundling */ 4230 ha->dif_bundl_pool = dma_pool_create(name, 4231 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4232 if (!ha->dif_bundl_pool) { 4233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4234 "%s: failed create dif_bundl_pool\n", 4235 __func__); 4236 goto fail_dif_bundl_dma_pool; 4237 } 4238 4239 INIT_LIST_HEAD(&ha->pool.good.head); 4240 INIT_LIST_HEAD(&ha->pool.unusable.head); 4241 ha->pool.good.count = 0; 4242 ha->pool.unusable.count = 0; 4243 for (i = 0; i < 128; i++) { 4244 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4245 if (!dsd) { 4246 ql_dbg_pci(ql_dbg_init, ha->pdev, 4247 0xe0ee, "%s: failed alloc dsd\n", 4248 __func__); 4249 return -ENOMEM; 4250 } 4251 ha->dif_bundle_kallocs++; 4252 4253 dsd->dsd_addr = dma_pool_alloc( 4254 ha->dif_bundl_pool, GFP_ATOMIC, 4255 &dsd->dsd_list_dma); 4256 if (!dsd->dsd_addr) { 4257 ql_dbg_pci(ql_dbg_init, ha->pdev, 4258 0xe0ee, 4259 "%s: failed alloc ->dsd_addr\n", 4260 __func__); 4261 kfree(dsd); 4262 ha->dif_bundle_kallocs--; 4263 continue; 4264 } 4265 ha->dif_bundle_dma_allocs++; 4266 4267 /* 4268 * if DMA buffer crosses 4G boundary, 4269 * put it on bad list 4270 */ 4271 if (MSD(dsd->dsd_list_dma) ^ 4272 MSD(dsd->dsd_list_dma + bufsize)) { 4273 list_add_tail(&dsd->list, 4274 &ha->pool.unusable.head); 4275 ha->pool.unusable.count++; 4276 } else { 4277 list_add_tail(&dsd->list, 4278 &ha->pool.good.head); 4279 ha->pool.good.count++; 4280 } 4281 } 4282 4283 /* return the good ones back to the pool */ 4284 list_for_each_entry_safe(dsd, nxt, 4285 &ha->pool.good.head, list) { 4286 list_del(&dsd->list); 4287 dma_pool_free(ha->dif_bundl_pool, 4288 dsd->dsd_addr, dsd->dsd_list_dma); 4289 ha->dif_bundle_dma_allocs--; 4290 kfree(dsd); 4291 ha->dif_bundle_kallocs--; 4292 } 4293 4294 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4295 "%s: dif dma pool (good=%u unusable=%u)\n", 4296 __func__, ha->pool.good.count, 4297 ha->pool.unusable.count); 4298 } 4299 4300 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4301 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4302 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4303 ha->dif_bundl_pool); 4304 } 4305 4306 /* Allocate memory for SNS commands */ 4307 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4308 /* Get consistent memory allocated for SNS commands */ 4309 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4310 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4311 if (!ha->sns_cmd) 4312 goto fail_dma_pool; 4313 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4314 "sns_cmd: %p.\n", ha->sns_cmd); 4315 } else { 4316 /* Get consistent memory allocated for MS IOCB */ 4317 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4318 &ha->ms_iocb_dma); 4319 if (!ha->ms_iocb) 4320 goto fail_dma_pool; 4321 /* Get consistent memory allocated for CT SNS commands */ 4322 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4323 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4324 if (!ha->ct_sns) 4325 goto fail_free_ms_iocb; 4326 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4327 "ms_iocb=%p ct_sns=%p.\n", 4328 ha->ms_iocb, ha->ct_sns); 4329 } 4330 4331 /* Allocate memory for request ring */ 4332 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4333 if (!*req) { 4334 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4335 "Failed to allocate memory for req.\n"); 4336 goto fail_req; 4337 } 4338 (*req)->length = req_len; 4339 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4340 ((*req)->length + 1) * sizeof(request_t), 4341 &(*req)->dma, GFP_KERNEL); 4342 if (!(*req)->ring) { 4343 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4344 "Failed to allocate memory for req_ring.\n"); 4345 goto fail_req_ring; 4346 } 4347 /* Allocate memory for response ring */ 4348 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4349 if (!*rsp) { 4350 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4351 "Failed to allocate memory for rsp.\n"); 4352 goto fail_rsp; 4353 } 4354 (*rsp)->hw = ha; 4355 (*rsp)->length = rsp_len; 4356 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4357 ((*rsp)->length + 1) * sizeof(response_t), 4358 &(*rsp)->dma, GFP_KERNEL); 4359 if (!(*rsp)->ring) { 4360 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4361 "Failed to allocate memory for rsp_ring.\n"); 4362 goto fail_rsp_ring; 4363 } 4364 (*req)->rsp = *rsp; 4365 (*rsp)->req = *req; 4366 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4367 "req=%p req->length=%d req->ring=%p rsp=%p " 4368 "rsp->length=%d rsp->ring=%p.\n", 4369 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4370 (*rsp)->ring); 4371 /* Allocate memory for NVRAM data for vports */ 4372 if (ha->nvram_npiv_size) { 4373 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4374 sizeof(struct qla_npiv_entry), 4375 GFP_KERNEL); 4376 if (!ha->npiv_info) { 4377 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4378 "Failed to allocate memory for npiv_info.\n"); 4379 goto fail_npiv_info; 4380 } 4381 } else 4382 ha->npiv_info = NULL; 4383 4384 /* Get consistent memory allocated for EX-INIT-CB. */ 4385 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4386 IS_QLA28XX(ha)) { 4387 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4388 &ha->ex_init_cb_dma); 4389 if (!ha->ex_init_cb) 4390 goto fail_ex_init_cb; 4391 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4392 "ex_init_cb=%p.\n", ha->ex_init_cb); 4393 } 4394 4395 /* Get consistent memory allocated for Special Features-CB. */ 4396 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4397 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4398 &ha->sf_init_cb_dma); 4399 if (!ha->sf_init_cb) 4400 goto fail_sf_init_cb; 4401 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4402 "sf_init_cb=%p.\n", ha->sf_init_cb); 4403 } 4404 4405 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4406 4407 /* Get consistent memory allocated for Async Port-Database. */ 4408 if (!IS_FWI2_CAPABLE(ha)) { 4409 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4410 &ha->async_pd_dma); 4411 if (!ha->async_pd) 4412 goto fail_async_pd; 4413 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4414 "async_pd=%p.\n", ha->async_pd); 4415 } 4416 4417 INIT_LIST_HEAD(&ha->vp_list); 4418 4419 /* Allocate memory for our loop_id bitmap */ 4420 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4421 sizeof(long), 4422 GFP_KERNEL); 4423 if (!ha->loop_id_map) 4424 goto fail_loop_id_map; 4425 else { 4426 qla2x00_set_reserved_loop_ids(ha); 4427 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4428 "loop_id_map=%p.\n", ha->loop_id_map); 4429 } 4430 4431 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4432 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4433 if (!ha->sfp_data) { 4434 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4435 "Unable to allocate memory for SFP read-data.\n"); 4436 goto fail_sfp_data; 4437 } 4438 4439 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4440 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4441 GFP_KERNEL); 4442 if (!ha->flt) { 4443 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4444 "Unable to allocate memory for FLT.\n"); 4445 goto fail_flt_buffer; 4446 } 4447 4448 /* allocate the purex dma pool */ 4449 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4450 ELS_MAX_PAYLOAD, 8, 0); 4451 4452 if (!ha->purex_dma_pool) { 4453 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4454 "Unable to allocate purex_dma_pool.\n"); 4455 goto fail_flt; 4456 } 4457 4458 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4459 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4460 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4461 4462 if (!ha->elsrej.c) { 4463 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4464 "Alloc failed for els reject cmd.\n"); 4465 goto fail_elsrej; 4466 } 4467 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4468 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4469 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4470 return 0; 4471 4472 fail_elsrej: 4473 dma_pool_destroy(ha->purex_dma_pool); 4474 fail_flt: 4475 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4476 ha->flt, ha->flt_dma); 4477 4478 fail_flt_buffer: 4479 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4480 ha->sfp_data, ha->sfp_data_dma); 4481 fail_sfp_data: 4482 kfree(ha->loop_id_map); 4483 fail_loop_id_map: 4484 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4485 fail_async_pd: 4486 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4487 fail_sf_init_cb: 4488 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4489 fail_ex_init_cb: 4490 kfree(ha->npiv_info); 4491 fail_npiv_info: 4492 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4493 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4494 (*rsp)->ring = NULL; 4495 (*rsp)->dma = 0; 4496 fail_rsp_ring: 4497 kfree(*rsp); 4498 *rsp = NULL; 4499 fail_rsp: 4500 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4501 sizeof(request_t), (*req)->ring, (*req)->dma); 4502 (*req)->ring = NULL; 4503 (*req)->dma = 0; 4504 fail_req_ring: 4505 kfree(*req); 4506 *req = NULL; 4507 fail_req: 4508 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4509 ha->ct_sns, ha->ct_sns_dma); 4510 ha->ct_sns = NULL; 4511 ha->ct_sns_dma = 0; 4512 fail_free_ms_iocb: 4513 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4514 ha->ms_iocb = NULL; 4515 ha->ms_iocb_dma = 0; 4516 4517 if (ha->sns_cmd) 4518 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4519 ha->sns_cmd, ha->sns_cmd_dma); 4520 fail_dma_pool: 4521 if (ql2xenabledif) { 4522 struct dsd_dma *dsd, *nxt; 4523 4524 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4525 list) { 4526 list_del(&dsd->list); 4527 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4528 dsd->dsd_list_dma); 4529 ha->dif_bundle_dma_allocs--; 4530 kfree(dsd); 4531 ha->dif_bundle_kallocs--; 4532 ha->pool.unusable.count--; 4533 } 4534 dma_pool_destroy(ha->dif_bundl_pool); 4535 ha->dif_bundl_pool = NULL; 4536 } 4537 4538 fail_dif_bundl_dma_pool: 4539 if (IS_QLA82XX(ha) || ql2xenabledif) { 4540 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4541 ha->fcp_cmnd_dma_pool = NULL; 4542 } 4543 fail_dl_dma_pool: 4544 if (IS_QLA82XX(ha) || ql2xenabledif) { 4545 dma_pool_destroy(ha->dl_dma_pool); 4546 ha->dl_dma_pool = NULL; 4547 } 4548 fail_s_dma_pool: 4549 dma_pool_destroy(ha->s_dma_pool); 4550 ha->s_dma_pool = NULL; 4551 fail_free_nvram: 4552 kfree(ha->nvram); 4553 ha->nvram = NULL; 4554 fail_free_ctx_mempool: 4555 mempool_destroy(ha->ctx_mempool); 4556 ha->ctx_mempool = NULL; 4557 fail_free_srb_mempool: 4558 mempool_destroy(ha->srb_mempool); 4559 ha->srb_mempool = NULL; 4560 fail_free_gid_list: 4561 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4562 ha->gid_list, 4563 ha->gid_list_dma); 4564 ha->gid_list = NULL; 4565 ha->gid_list_dma = 0; 4566 fail_free_tgt_mem: 4567 qlt_mem_free(ha); 4568 fail_free_btree: 4569 btree_destroy32(&ha->host_map); 4570 fail_free_init_cb: 4571 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4572 ha->init_cb_dma); 4573 ha->init_cb = NULL; 4574 ha->init_cb_dma = 0; 4575 fail_free_vp_map: 4576 kfree(ha->vp_map); 4577 fail: 4578 ql_log(ql_log_fatal, NULL, 0x0030, 4579 "Memory allocation failure.\n"); 4580 return -ENOMEM; 4581 } 4582 4583 int 4584 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4585 { 4586 int rval; 4587 uint16_t size, max_cnt; 4588 uint32_t temp; 4589 struct qla_hw_data *ha = vha->hw; 4590 4591 /* Return if we don't need to alloacate any extended logins */ 4592 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4593 return QLA_SUCCESS; 4594 4595 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4596 return QLA_SUCCESS; 4597 4598 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4599 max_cnt = 0; 4600 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4601 if (rval != QLA_SUCCESS) { 4602 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4603 "Failed to get exlogin status.\n"); 4604 return rval; 4605 } 4606 4607 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4608 temp *= size; 4609 4610 if (temp != ha->exlogin_size) { 4611 qla2x00_free_exlogin_buffer(ha); 4612 ha->exlogin_size = temp; 4613 4614 ql_log(ql_log_info, vha, 0xd024, 4615 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4616 max_cnt, size, temp); 4617 4618 ql_log(ql_log_info, vha, 0xd025, 4619 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4620 4621 /* Get consistent memory for extended logins */ 4622 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4623 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4624 if (!ha->exlogin_buf) { 4625 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4626 "Failed to allocate memory for exlogin_buf_dma.\n"); 4627 return -ENOMEM; 4628 } 4629 } 4630 4631 /* Now configure the dma buffer */ 4632 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4633 if (rval) { 4634 ql_log(ql_log_fatal, vha, 0xd033, 4635 "Setup extended login buffer ****FAILED****.\n"); 4636 qla2x00_free_exlogin_buffer(ha); 4637 } 4638 4639 return rval; 4640 } 4641 4642 /* 4643 * qla2x00_free_exlogin_buffer 4644 * 4645 * Input: 4646 * ha = adapter block pointer 4647 */ 4648 void 4649 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4650 { 4651 if (ha->exlogin_buf) { 4652 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4653 ha->exlogin_buf, ha->exlogin_buf_dma); 4654 ha->exlogin_buf = NULL; 4655 ha->exlogin_size = 0; 4656 } 4657 } 4658 4659 static void 4660 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4661 { 4662 u32 temp; 4663 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4664 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4665 4666 if (max_cnt > vha->hw->max_exchg) 4667 max_cnt = vha->hw->max_exchg; 4668 4669 if (qla_ini_mode_enabled(vha)) { 4670 if (vha->ql2xiniexchg > max_cnt) 4671 vha->ql2xiniexchg = max_cnt; 4672 4673 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4674 *ret_cnt = vha->ql2xiniexchg; 4675 4676 } else if (qla_tgt_mode_enabled(vha)) { 4677 if (vha->ql2xexchoffld > max_cnt) { 4678 vha->ql2xexchoffld = max_cnt; 4679 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4680 } 4681 4682 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4683 *ret_cnt = vha->ql2xexchoffld; 4684 } else if (qla_dual_mode_enabled(vha)) { 4685 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4686 if (temp > max_cnt) { 4687 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4688 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4689 temp = max_cnt; 4690 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4691 } 4692 4693 if (temp > FW_DEF_EXCHANGES_CNT) 4694 *ret_cnt = temp; 4695 } 4696 } 4697 4698 int 4699 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4700 { 4701 int rval; 4702 u16 size, max_cnt; 4703 u32 actual_cnt, totsz; 4704 struct qla_hw_data *ha = vha->hw; 4705 4706 if (!ha->flags.exchoffld_enabled) 4707 return QLA_SUCCESS; 4708 4709 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4710 return QLA_SUCCESS; 4711 4712 max_cnt = 0; 4713 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4714 if (rval != QLA_SUCCESS) { 4715 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4716 "Failed to get exlogin status.\n"); 4717 return rval; 4718 } 4719 4720 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4721 ql_log(ql_log_info, vha, 0xd014, 4722 "Actual exchange offload count: %d.\n", actual_cnt); 4723 4724 totsz = actual_cnt * size; 4725 4726 if (totsz != ha->exchoffld_size) { 4727 qla2x00_free_exchoffld_buffer(ha); 4728 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4729 ha->exchoffld_size = 0; 4730 ha->flags.exchoffld_enabled = 0; 4731 return QLA_SUCCESS; 4732 } 4733 4734 ha->exchoffld_size = totsz; 4735 4736 ql_log(ql_log_info, vha, 0xd016, 4737 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4738 max_cnt, actual_cnt, size, totsz); 4739 4740 ql_log(ql_log_info, vha, 0xd017, 4741 "Exchange Buffers requested size = 0x%x\n", 4742 ha->exchoffld_size); 4743 4744 /* Get consistent memory for extended logins */ 4745 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4746 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4747 if (!ha->exchoffld_buf) { 4748 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4749 "Failed to allocate memory for Exchange Offload.\n"); 4750 4751 if (ha->max_exchg > 4752 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4753 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4754 } else if (ha->max_exchg > 4755 (FW_DEF_EXCHANGES_CNT + 512)) { 4756 ha->max_exchg -= 512; 4757 } else { 4758 ha->flags.exchoffld_enabled = 0; 4759 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4760 "Disabling Exchange offload due to lack of memory\n"); 4761 } 4762 ha->exchoffld_size = 0; 4763 4764 return -ENOMEM; 4765 } 4766 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4767 /* pathological case */ 4768 qla2x00_free_exchoffld_buffer(ha); 4769 ha->exchoffld_size = 0; 4770 ha->flags.exchoffld_enabled = 0; 4771 ql_log(ql_log_info, vha, 0xd016, 4772 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4773 ha->exchoffld_size, actual_cnt, size, totsz); 4774 return 0; 4775 } 4776 4777 /* Now configure the dma buffer */ 4778 rval = qla_set_exchoffld_mem_cfg(vha); 4779 if (rval) { 4780 ql_log(ql_log_fatal, vha, 0xd02e, 4781 "Setup exchange offload buffer ****FAILED****.\n"); 4782 qla2x00_free_exchoffld_buffer(ha); 4783 } else { 4784 /* re-adjust number of target exchange */ 4785 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4786 4787 if (qla_ini_mode_enabled(vha)) 4788 icb->exchange_count = 0; 4789 else 4790 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4791 } 4792 4793 return rval; 4794 } 4795 4796 /* 4797 * qla2x00_free_exchoffld_buffer 4798 * 4799 * Input: 4800 * ha = adapter block pointer 4801 */ 4802 void 4803 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4804 { 4805 if (ha->exchoffld_buf) { 4806 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4807 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4808 ha->exchoffld_buf = NULL; 4809 ha->exchoffld_size = 0; 4810 } 4811 } 4812 4813 /* 4814 * qla2x00_free_fw_dump 4815 * Frees fw dump stuff. 4816 * 4817 * Input: 4818 * ha = adapter block pointer 4819 */ 4820 static void 4821 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4822 { 4823 struct fwdt *fwdt = ha->fwdt; 4824 uint j; 4825 4826 if (ha->fce) 4827 dma_free_coherent(&ha->pdev->dev, 4828 FCE_SIZE, ha->fce, ha->fce_dma); 4829 4830 if (ha->eft) 4831 dma_free_coherent(&ha->pdev->dev, 4832 EFT_SIZE, ha->eft, ha->eft_dma); 4833 4834 vfree(ha->fw_dump); 4835 4836 ha->fce = NULL; 4837 ha->fce_dma = 0; 4838 ha->flags.fce_enabled = 0; 4839 ha->eft = NULL; 4840 ha->eft_dma = 0; 4841 ha->fw_dumped = false; 4842 ha->fw_dump_cap_flags = 0; 4843 ha->fw_dump_reading = 0; 4844 ha->fw_dump = NULL; 4845 ha->fw_dump_len = 0; 4846 4847 for (j = 0; j < 2; j++, fwdt++) { 4848 vfree(fwdt->template); 4849 fwdt->template = NULL; 4850 fwdt->length = 0; 4851 } 4852 } 4853 4854 /* 4855 * qla2x00_mem_free 4856 * Frees all adapter allocated memory. 4857 * 4858 * Input: 4859 * ha = adapter block pointer. 4860 */ 4861 static void 4862 qla2x00_mem_free(struct qla_hw_data *ha) 4863 { 4864 qla2x00_free_fw_dump(ha); 4865 4866 if (ha->mctp_dump) 4867 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4868 ha->mctp_dump_dma); 4869 ha->mctp_dump = NULL; 4870 4871 mempool_destroy(ha->srb_mempool); 4872 ha->srb_mempool = NULL; 4873 4874 if (ha->dcbx_tlv) 4875 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4876 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4877 ha->dcbx_tlv = NULL; 4878 4879 if (ha->xgmac_data) 4880 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4881 ha->xgmac_data, ha->xgmac_data_dma); 4882 ha->xgmac_data = NULL; 4883 4884 if (ha->sns_cmd) 4885 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4886 ha->sns_cmd, ha->sns_cmd_dma); 4887 ha->sns_cmd = NULL; 4888 ha->sns_cmd_dma = 0; 4889 4890 if (ha->ct_sns) 4891 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4892 ha->ct_sns, ha->ct_sns_dma); 4893 ha->ct_sns = NULL; 4894 ha->ct_sns_dma = 0; 4895 4896 if (ha->sfp_data) 4897 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4898 ha->sfp_data_dma); 4899 ha->sfp_data = NULL; 4900 4901 if (ha->flt) 4902 dma_free_coherent(&ha->pdev->dev, 4903 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4904 ha->flt, ha->flt_dma); 4905 ha->flt = NULL; 4906 ha->flt_dma = 0; 4907 4908 if (ha->ms_iocb) 4909 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4910 ha->ms_iocb = NULL; 4911 ha->ms_iocb_dma = 0; 4912 4913 if (ha->sf_init_cb) 4914 dma_pool_free(ha->s_dma_pool, 4915 ha->sf_init_cb, ha->sf_init_cb_dma); 4916 4917 if (ha->ex_init_cb) 4918 dma_pool_free(ha->s_dma_pool, 4919 ha->ex_init_cb, ha->ex_init_cb_dma); 4920 ha->ex_init_cb = NULL; 4921 ha->ex_init_cb_dma = 0; 4922 4923 if (ha->async_pd) 4924 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4925 ha->async_pd = NULL; 4926 ha->async_pd_dma = 0; 4927 4928 dma_pool_destroy(ha->s_dma_pool); 4929 ha->s_dma_pool = NULL; 4930 4931 if (ha->gid_list) 4932 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4933 ha->gid_list, ha->gid_list_dma); 4934 ha->gid_list = NULL; 4935 ha->gid_list_dma = 0; 4936 4937 if (IS_QLA82XX(ha)) { 4938 if (!list_empty(&ha->gbl_dsd_list)) { 4939 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4940 4941 /* clean up allocated prev pool */ 4942 list_for_each_entry_safe(dsd_ptr, 4943 tdsd_ptr, &ha->gbl_dsd_list, list) { 4944 dma_pool_free(ha->dl_dma_pool, 4945 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4946 list_del(&dsd_ptr->list); 4947 kfree(dsd_ptr); 4948 } 4949 } 4950 } 4951 4952 dma_pool_destroy(ha->dl_dma_pool); 4953 ha->dl_dma_pool = NULL; 4954 4955 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4956 ha->fcp_cmnd_dma_pool = NULL; 4957 4958 mempool_destroy(ha->ctx_mempool); 4959 ha->ctx_mempool = NULL; 4960 4961 if (ql2xenabledif && ha->dif_bundl_pool) { 4962 struct dsd_dma *dsd, *nxt; 4963 4964 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4965 list) { 4966 list_del(&dsd->list); 4967 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4968 dsd->dsd_list_dma); 4969 ha->dif_bundle_dma_allocs--; 4970 kfree(dsd); 4971 ha->dif_bundle_kallocs--; 4972 ha->pool.unusable.count--; 4973 } 4974 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4975 list_del(&dsd->list); 4976 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4977 dsd->dsd_list_dma); 4978 ha->dif_bundle_dma_allocs--; 4979 kfree(dsd); 4980 ha->dif_bundle_kallocs--; 4981 } 4982 } 4983 4984 dma_pool_destroy(ha->dif_bundl_pool); 4985 ha->dif_bundl_pool = NULL; 4986 4987 qlt_mem_free(ha); 4988 qla_remove_hostmap(ha); 4989 4990 if (ha->init_cb) 4991 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4992 ha->init_cb, ha->init_cb_dma); 4993 4994 dma_pool_destroy(ha->purex_dma_pool); 4995 ha->purex_dma_pool = NULL; 4996 4997 if (ha->elsrej.c) { 4998 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4999 ha->elsrej.c, ha->elsrej.cdma); 5000 ha->elsrej.c = NULL; 5001 } 5002 5003 ha->init_cb = NULL; 5004 ha->init_cb_dma = 0; 5005 5006 vfree(ha->optrom_buffer); 5007 ha->optrom_buffer = NULL; 5008 kfree(ha->nvram); 5009 ha->nvram = NULL; 5010 kfree(ha->npiv_info); 5011 ha->npiv_info = NULL; 5012 kfree(ha->swl); 5013 ha->swl = NULL; 5014 kfree(ha->loop_id_map); 5015 ha->sf_init_cb = NULL; 5016 ha->sf_init_cb_dma = 0; 5017 ha->loop_id_map = NULL; 5018 5019 kfree(ha->vp_map); 5020 ha->vp_map = NULL; 5021 } 5022 5023 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht, 5024 struct qla_hw_data *ha) 5025 { 5026 struct Scsi_Host *host; 5027 struct scsi_qla_host *vha = NULL; 5028 5029 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5030 if (!host) { 5031 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5032 "Failed to allocate host from the scsi layer, aborting.\n"); 5033 return NULL; 5034 } 5035 5036 /* Clear our data area */ 5037 vha = shost_priv(host); 5038 memset(vha, 0, sizeof(scsi_qla_host_t)); 5039 5040 vha->host = host; 5041 vha->host_no = host->host_no; 5042 vha->hw = ha; 5043 5044 vha->qlini_mode = ql2x_ini_mode; 5045 vha->ql2xexchoffld = ql2xexchoffld; 5046 vha->ql2xiniexchg = ql2xiniexchg; 5047 5048 INIT_LIST_HEAD(&vha->vp_fcports); 5049 INIT_LIST_HEAD(&vha->work_list); 5050 INIT_LIST_HEAD(&vha->list); 5051 INIT_LIST_HEAD(&vha->qla_cmd_list); 5052 INIT_LIST_HEAD(&vha->logo_list); 5053 INIT_LIST_HEAD(&vha->plogi_ack_list); 5054 INIT_LIST_HEAD(&vha->qp_list); 5055 INIT_LIST_HEAD(&vha->gnl.fcports); 5056 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5057 5058 INIT_LIST_HEAD(&vha->purex_list.head); 5059 spin_lock_init(&vha->purex_list.lock); 5060 5061 spin_lock_init(&vha->work_lock); 5062 spin_lock_init(&vha->cmd_list_lock); 5063 init_waitqueue_head(&vha->fcport_waitQ); 5064 init_waitqueue_head(&vha->vref_waitq); 5065 qla_enode_init(vha); 5066 qla_edb_init(vha); 5067 5068 5069 vha->gnl.size = sizeof(struct get_name_list_extended) * 5070 (ha->max_loop_id + 1); 5071 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5072 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5073 if (!vha->gnl.l) { 5074 ql_log(ql_log_fatal, vha, 0xd04a, 5075 "Alloc failed for name list.\n"); 5076 scsi_host_put(vha->host); 5077 return NULL; 5078 } 5079 5080 /* todo: what about ext login? */ 5081 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5082 vha->scan.l = vmalloc(vha->scan.size); 5083 if (!vha->scan.l) { 5084 ql_log(ql_log_fatal, vha, 0xd04a, 5085 "Alloc failed for scan database.\n"); 5086 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5087 vha->gnl.l, vha->gnl.ldma); 5088 vha->gnl.l = NULL; 5089 scsi_host_put(vha->host); 5090 return NULL; 5091 } 5092 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5093 5094 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", 5095 QLA2XXX_DRIVER_NAME, vha->host_no); 5096 ql_dbg(ql_dbg_init, vha, 0x0041, 5097 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5098 vha->host, vha->hw, vha, 5099 dev_name(&(ha->pdev->dev))); 5100 5101 return vha; 5102 } 5103 5104 struct qla_work_evt * 5105 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5106 { 5107 struct qla_work_evt *e; 5108 5109 if (test_bit(UNLOADING, &vha->dpc_flags)) 5110 return NULL; 5111 5112 if (qla_vha_mark_busy(vha)) 5113 return NULL; 5114 5115 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5116 if (!e) { 5117 QLA_VHA_MARK_NOT_BUSY(vha); 5118 return NULL; 5119 } 5120 5121 INIT_LIST_HEAD(&e->list); 5122 e->type = type; 5123 e->flags = QLA_EVT_FLAG_FREE; 5124 return e; 5125 } 5126 5127 int 5128 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5129 { 5130 unsigned long flags; 5131 bool q = false; 5132 5133 spin_lock_irqsave(&vha->work_lock, flags); 5134 list_add_tail(&e->list, &vha->work_list); 5135 5136 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5137 q = true; 5138 5139 spin_unlock_irqrestore(&vha->work_lock, flags); 5140 5141 if (q) 5142 queue_work(vha->hw->wq, &vha->iocb_work); 5143 5144 return QLA_SUCCESS; 5145 } 5146 5147 int 5148 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5149 u32 data) 5150 { 5151 struct qla_work_evt *e; 5152 5153 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5154 if (!e) 5155 return QLA_FUNCTION_FAILED; 5156 5157 e->u.aen.code = code; 5158 e->u.aen.data = data; 5159 return qla2x00_post_work(vha, e); 5160 } 5161 5162 int 5163 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5164 { 5165 struct qla_work_evt *e; 5166 5167 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5168 if (!e) 5169 return QLA_FUNCTION_FAILED; 5170 5171 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5172 return qla2x00_post_work(vha, e); 5173 } 5174 5175 #define qla2x00_post_async_work(name, type) \ 5176 int qla2x00_post_async_##name##_work( \ 5177 struct scsi_qla_host *vha, \ 5178 fc_port_t *fcport, uint16_t *data) \ 5179 { \ 5180 struct qla_work_evt *e; \ 5181 \ 5182 e = qla2x00_alloc_work(vha, type); \ 5183 if (!e) \ 5184 return QLA_FUNCTION_FAILED; \ 5185 \ 5186 e->u.logio.fcport = fcport; \ 5187 if (data) { \ 5188 e->u.logio.data[0] = data[0]; \ 5189 e->u.logio.data[1] = data[1]; \ 5190 } \ 5191 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5192 return qla2x00_post_work(vha, e); \ 5193 } 5194 5195 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5196 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5197 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5198 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5199 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5200 5201 int 5202 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5203 { 5204 struct qla_work_evt *e; 5205 5206 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5207 if (!e) 5208 return QLA_FUNCTION_FAILED; 5209 5210 e->u.uevent.code = code; 5211 return qla2x00_post_work(vha, e); 5212 } 5213 5214 static void 5215 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5216 { 5217 char event_string[40]; 5218 char *envp[] = { event_string, NULL }; 5219 5220 switch (code) { 5221 case QLA_UEVENT_CODE_FW_DUMP: 5222 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5223 vha->host_no); 5224 break; 5225 default: 5226 /* do nothing */ 5227 break; 5228 } 5229 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5230 } 5231 5232 int 5233 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5234 uint32_t *data, int cnt) 5235 { 5236 struct qla_work_evt *e; 5237 5238 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5239 if (!e) 5240 return QLA_FUNCTION_FAILED; 5241 5242 e->u.aenfx.evtcode = evtcode; 5243 e->u.aenfx.count = cnt; 5244 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5245 return qla2x00_post_work(vha, e); 5246 } 5247 5248 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5249 { 5250 unsigned long flags; 5251 5252 if (IS_SW_RESV_ADDR(fcport->d_id)) 5253 return; 5254 5255 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5256 if (fcport->disc_state == DSC_UPD_FCPORT) { 5257 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5258 return; 5259 } 5260 fcport->jiffies_at_registration = jiffies; 5261 fcport->sec_since_registration = 0; 5262 fcport->next_disc_state = DSC_DELETED; 5263 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5264 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5265 5266 queue_work(system_unbound_wq, &fcport->reg_work); 5267 } 5268 5269 static 5270 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5271 { 5272 unsigned long flags; 5273 fc_port_t *fcport = NULL, *tfcp; 5274 struct qlt_plogi_ack_t *pla = 5275 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5276 uint8_t free_fcport = 0; 5277 5278 ql_dbg(ql_dbg_disc, vha, 0xffff, 5279 "%s %d %8phC enter\n", 5280 __func__, __LINE__, e->u.new_sess.port_name); 5281 5282 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5283 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5284 if (fcport) { 5285 fcport->d_id = e->u.new_sess.id; 5286 if (pla) { 5287 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5288 memcpy(fcport->node_name, 5289 pla->iocb.u.isp24.u.plogi.node_name, 5290 WWN_SIZE); 5291 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5292 /* we took an extra ref_count to prevent PLOGI ACK when 5293 * fcport/sess has not been created. 5294 */ 5295 pla->ref_count--; 5296 } 5297 } else { 5298 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5299 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5300 if (fcport) { 5301 fcport->d_id = e->u.new_sess.id; 5302 fcport->flags |= FCF_FABRIC_DEVICE; 5303 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5304 fcport->tgt_short_link_down_cnt = 0; 5305 5306 memcpy(fcport->port_name, e->u.new_sess.port_name, 5307 WWN_SIZE); 5308 5309 fcport->fc4_type = e->u.new_sess.fc4_type; 5310 if (NVME_PRIORITY(vha->hw, fcport)) 5311 fcport->do_prli_nvme = 1; 5312 else 5313 fcport->do_prli_nvme = 0; 5314 5315 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5316 fcport->dm_login_expire = jiffies + 5317 QLA_N2N_WAIT_TIME * HZ; 5318 fcport->fc4_type = FS_FC4TYPE_FCP; 5319 fcport->n2n_flag = 1; 5320 if (vha->flags.nvme_enabled) 5321 fcport->fc4_type |= FS_FC4TYPE_NVME; 5322 } 5323 5324 } else { 5325 ql_dbg(ql_dbg_disc, vha, 0xffff, 5326 "%s %8phC mem alloc fail.\n", 5327 __func__, e->u.new_sess.port_name); 5328 5329 if (pla) { 5330 list_del(&pla->list); 5331 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5332 } 5333 return; 5334 } 5335 5336 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5337 /* search again to make sure no one else got ahead */ 5338 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5339 e->u.new_sess.port_name, 1); 5340 if (tfcp) { 5341 /* should rarily happen */ 5342 ql_dbg(ql_dbg_disc, vha, 0xffff, 5343 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5344 __func__, tfcp->port_name, tfcp->disc_state, 5345 tfcp->fw_login_state); 5346 5347 free_fcport = 1; 5348 } else { 5349 list_add_tail(&fcport->list, &vha->vp_fcports); 5350 5351 } 5352 if (pla) { 5353 qlt_plogi_ack_link(vha, pla, fcport, 5354 QLT_PLOGI_LINK_SAME_WWN); 5355 pla->ref_count--; 5356 } 5357 } 5358 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5359 5360 if (fcport) { 5361 fcport->id_changed = 1; 5362 fcport->scan_state = QLA_FCPORT_FOUND; 5363 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5364 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5365 5366 if (pla) { 5367 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5368 u16 wd3_lo; 5369 5370 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5371 fcport->local = 0; 5372 fcport->loop_id = 5373 le16_to_cpu( 5374 pla->iocb.u.isp24.nport_handle); 5375 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5376 wd3_lo = 5377 le16_to_cpu( 5378 pla->iocb.u.isp24.u.prli.wd3_lo); 5379 5380 if (wd3_lo & BIT_7) 5381 fcport->conf_compl_supported = 1; 5382 5383 if ((wd3_lo & BIT_4) == 0) 5384 fcport->port_type = FCT_INITIATOR; 5385 else 5386 fcport->port_type = FCT_TARGET; 5387 } 5388 qlt_plogi_ack_unref(vha, pla); 5389 } else { 5390 fc_port_t *dfcp = NULL; 5391 5392 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5393 tfcp = qla2x00_find_fcport_by_nportid(vha, 5394 &e->u.new_sess.id, 1); 5395 if (tfcp && (tfcp != fcport)) { 5396 /* 5397 * We have a conflict fcport with same NportID. 5398 */ 5399 ql_dbg(ql_dbg_disc, vha, 0xffff, 5400 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5401 __func__, tfcp->port_name, tfcp->disc_state, 5402 tfcp->fw_login_state); 5403 5404 switch (tfcp->disc_state) { 5405 case DSC_DELETED: 5406 break; 5407 case DSC_DELETE_PEND: 5408 fcport->login_pause = 1; 5409 tfcp->conflict = fcport; 5410 break; 5411 default: 5412 fcport->login_pause = 1; 5413 tfcp->conflict = fcport; 5414 dfcp = tfcp; 5415 break; 5416 } 5417 } 5418 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5419 if (dfcp) 5420 qlt_schedule_sess_for_deletion(tfcp); 5421 5422 if (N2N_TOPO(vha->hw)) { 5423 fcport->flags &= ~FCF_FABRIC_DEVICE; 5424 fcport->keep_nport_handle = 1; 5425 if (vha->flags.nvme_enabled) { 5426 fcport->fc4_type = 5427 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5428 fcport->n2n_flag = 1; 5429 } 5430 fcport->fw_login_state = 0; 5431 5432 schedule_delayed_work(&vha->scan.scan_work, 5); 5433 } else { 5434 qla24xx_fcport_handle_login(vha, fcport); 5435 } 5436 } 5437 } 5438 5439 if (free_fcport) { 5440 qla2x00_free_fcport(fcport); 5441 if (pla) { 5442 list_del(&pla->list); 5443 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5444 } 5445 } 5446 } 5447 5448 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5449 { 5450 struct srb *sp = e->u.iosb.sp; 5451 int rval; 5452 5453 rval = qla2x00_start_sp(sp); 5454 if (rval != QLA_SUCCESS) { 5455 ql_dbg(ql_dbg_disc, vha, 0x2043, 5456 "%s: %s: Re-issue IOCB failed (%d).\n", 5457 __func__, sp->name, rval); 5458 qla24xx_sp_unmap(vha, sp); 5459 } 5460 } 5461 5462 void 5463 qla2x00_do_work(struct scsi_qla_host *vha) 5464 { 5465 struct qla_work_evt *e, *tmp; 5466 unsigned long flags; 5467 LIST_HEAD(work); 5468 int rc; 5469 5470 spin_lock_irqsave(&vha->work_lock, flags); 5471 list_splice_init(&vha->work_list, &work); 5472 spin_unlock_irqrestore(&vha->work_lock, flags); 5473 5474 list_for_each_entry_safe(e, tmp, &work, list) { 5475 rc = QLA_SUCCESS; 5476 switch (e->type) { 5477 case QLA_EVT_AEN: 5478 fc_host_post_event(vha->host, fc_get_event_number(), 5479 e->u.aen.code, e->u.aen.data); 5480 break; 5481 case QLA_EVT_IDC_ACK: 5482 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5483 break; 5484 case QLA_EVT_ASYNC_LOGIN: 5485 qla2x00_async_login(vha, e->u.logio.fcport, 5486 e->u.logio.data); 5487 break; 5488 case QLA_EVT_ASYNC_LOGOUT: 5489 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5490 break; 5491 case QLA_EVT_ASYNC_ADISC: 5492 qla2x00_async_adisc(vha, e->u.logio.fcport, 5493 e->u.logio.data); 5494 break; 5495 case QLA_EVT_UEVENT: 5496 qla2x00_uevent_emit(vha, e->u.uevent.code); 5497 break; 5498 case QLA_EVT_AENFX: 5499 qlafx00_process_aen(vha, e); 5500 break; 5501 case QLA_EVT_UNMAP: 5502 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5503 break; 5504 case QLA_EVT_RELOGIN: 5505 qla2x00_relogin(vha); 5506 break; 5507 case QLA_EVT_NEW_SESS: 5508 qla24xx_create_new_sess(vha, e); 5509 break; 5510 case QLA_EVT_GPDB: 5511 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5512 e->u.fcport.opt); 5513 break; 5514 case QLA_EVT_PRLI: 5515 qla24xx_async_prli(vha, e->u.fcport.fcport); 5516 break; 5517 case QLA_EVT_GPSC: 5518 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5519 break; 5520 case QLA_EVT_GNL: 5521 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5522 break; 5523 case QLA_EVT_NACK: 5524 qla24xx_do_nack_work(vha, e); 5525 break; 5526 case QLA_EVT_ASYNC_PRLO: 5527 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5528 break; 5529 case QLA_EVT_ASYNC_PRLO_DONE: 5530 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5531 e->u.logio.data); 5532 break; 5533 case QLA_EVT_GPNFT: 5534 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5535 e->u.gpnft.sp); 5536 break; 5537 case QLA_EVT_GPNFT_DONE: 5538 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5539 break; 5540 case QLA_EVT_GNNFT_DONE: 5541 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5542 break; 5543 case QLA_EVT_GFPNID: 5544 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5545 break; 5546 case QLA_EVT_SP_RETRY: 5547 qla_sp_retry(vha, e); 5548 break; 5549 case QLA_EVT_IIDMA: 5550 qla_do_iidma_work(vha, e->u.fcport.fcport); 5551 break; 5552 case QLA_EVT_ELS_PLOGI: 5553 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5554 e->u.fcport.fcport, false); 5555 break; 5556 case QLA_EVT_SA_REPLACE: 5557 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5558 break; 5559 } 5560 5561 if (rc == EAGAIN) { 5562 /* put 'work' at head of 'vha->work_list' */ 5563 spin_lock_irqsave(&vha->work_lock, flags); 5564 list_splice(&work, &vha->work_list); 5565 spin_unlock_irqrestore(&vha->work_lock, flags); 5566 break; 5567 } 5568 list_del_init(&e->list); 5569 if (e->flags & QLA_EVT_FLAG_FREE) 5570 kfree(e); 5571 5572 /* For each work completed decrement vha ref count */ 5573 QLA_VHA_MARK_NOT_BUSY(vha); 5574 } 5575 } 5576 5577 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5578 { 5579 struct qla_work_evt *e; 5580 5581 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5582 5583 if (!e) { 5584 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5585 return QLA_FUNCTION_FAILED; 5586 } 5587 5588 return qla2x00_post_work(vha, e); 5589 } 5590 5591 /* Relogins all the fcports of a vport 5592 * Context: dpc thread 5593 */ 5594 void qla2x00_relogin(struct scsi_qla_host *vha) 5595 { 5596 fc_port_t *fcport; 5597 int status, relogin_needed = 0; 5598 struct event_arg ea; 5599 5600 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5601 /* 5602 * If the port is not ONLINE then try to login 5603 * to it if we haven't run out of retries. 5604 */ 5605 if (atomic_read(&fcport->state) != FCS_ONLINE && 5606 fcport->login_retry) { 5607 if (fcport->scan_state != QLA_FCPORT_FOUND || 5608 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5609 fcport->disc_state == DSC_LOGIN_COMPLETE) 5610 continue; 5611 5612 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5613 fcport->disc_state == DSC_DELETE_PEND) { 5614 relogin_needed = 1; 5615 } else { 5616 if (vha->hw->current_topology != ISP_CFG_NL) { 5617 memset(&ea, 0, sizeof(ea)); 5618 ea.fcport = fcport; 5619 qla24xx_handle_relogin_event(vha, &ea); 5620 } else if (vha->hw->current_topology == 5621 ISP_CFG_NL && 5622 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5623 (void)qla24xx_fcport_handle_login(vha, 5624 fcport); 5625 } else if (vha->hw->current_topology == 5626 ISP_CFG_NL) { 5627 fcport->login_retry--; 5628 status = 5629 qla2x00_local_device_login(vha, 5630 fcport); 5631 if (status == QLA_SUCCESS) { 5632 fcport->old_loop_id = 5633 fcport->loop_id; 5634 ql_dbg(ql_dbg_disc, vha, 0x2003, 5635 "Port login OK: logged in ID 0x%x.\n", 5636 fcport->loop_id); 5637 qla2x00_update_fcport 5638 (vha, fcport); 5639 } else if (status == 1) { 5640 set_bit(RELOGIN_NEEDED, 5641 &vha->dpc_flags); 5642 /* retry the login again */ 5643 ql_dbg(ql_dbg_disc, vha, 0x2007, 5644 "Retrying %d login again loop_id 0x%x.\n", 5645 fcport->login_retry, 5646 fcport->loop_id); 5647 } else { 5648 fcport->login_retry = 0; 5649 } 5650 5651 if (fcport->login_retry == 0 && 5652 status != QLA_SUCCESS) 5653 qla2x00_clear_loop_id(fcport); 5654 } 5655 } 5656 } 5657 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5658 break; 5659 } 5660 5661 if (relogin_needed) 5662 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5663 5664 ql_dbg(ql_dbg_disc, vha, 0x400e, 5665 "Relogin end.\n"); 5666 } 5667 5668 /* Schedule work on any of the dpc-workqueues */ 5669 void 5670 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5671 { 5672 struct qla_hw_data *ha = base_vha->hw; 5673 5674 switch (work_code) { 5675 case MBA_IDC_AEN: /* 0x8200 */ 5676 if (ha->dpc_lp_wq) 5677 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5678 break; 5679 5680 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5681 if (!ha->flags.nic_core_reset_hdlr_active) { 5682 if (ha->dpc_hp_wq) 5683 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5684 } else 5685 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5686 "NIC Core reset is already active. Skip " 5687 "scheduling it again.\n"); 5688 break; 5689 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5690 if (ha->dpc_hp_wq) 5691 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5692 break; 5693 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5694 if (ha->dpc_hp_wq) 5695 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5696 break; 5697 default: 5698 ql_log(ql_log_warn, base_vha, 0xb05f, 5699 "Unknown work-code=0x%x.\n", work_code); 5700 } 5701 5702 return; 5703 } 5704 5705 /* Work: Perform NIC Core Unrecoverable state handling */ 5706 void 5707 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5708 { 5709 struct qla_hw_data *ha = 5710 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5711 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5712 uint32_t dev_state = 0; 5713 5714 qla83xx_idc_lock(base_vha, 0); 5715 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5716 qla83xx_reset_ownership(base_vha); 5717 if (ha->flags.nic_core_reset_owner) { 5718 ha->flags.nic_core_reset_owner = 0; 5719 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5720 QLA8XXX_DEV_FAILED); 5721 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5722 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5723 } 5724 qla83xx_idc_unlock(base_vha, 0); 5725 } 5726 5727 /* Work: Execute IDC state handler */ 5728 void 5729 qla83xx_idc_state_handler_work(struct work_struct *work) 5730 { 5731 struct qla_hw_data *ha = 5732 container_of(work, struct qla_hw_data, idc_state_handler); 5733 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5734 uint32_t dev_state = 0; 5735 5736 qla83xx_idc_lock(base_vha, 0); 5737 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5738 if (dev_state == QLA8XXX_DEV_FAILED || 5739 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5740 qla83xx_idc_state_handler(base_vha); 5741 qla83xx_idc_unlock(base_vha, 0); 5742 } 5743 5744 static int 5745 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5746 { 5747 int rval = QLA_SUCCESS; 5748 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5749 uint32_t heart_beat_counter1, heart_beat_counter2; 5750 5751 do { 5752 if (time_after(jiffies, heart_beat_wait)) { 5753 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5754 "Nic Core f/w is not alive.\n"); 5755 rval = QLA_FUNCTION_FAILED; 5756 break; 5757 } 5758 5759 qla83xx_idc_lock(base_vha, 0); 5760 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5761 &heart_beat_counter1); 5762 qla83xx_idc_unlock(base_vha, 0); 5763 msleep(100); 5764 qla83xx_idc_lock(base_vha, 0); 5765 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5766 &heart_beat_counter2); 5767 qla83xx_idc_unlock(base_vha, 0); 5768 } while (heart_beat_counter1 == heart_beat_counter2); 5769 5770 return rval; 5771 } 5772 5773 /* Work: Perform NIC Core Reset handling */ 5774 void 5775 qla83xx_nic_core_reset_work(struct work_struct *work) 5776 { 5777 struct qla_hw_data *ha = 5778 container_of(work, struct qla_hw_data, nic_core_reset); 5779 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5780 uint32_t dev_state = 0; 5781 5782 if (IS_QLA2031(ha)) { 5783 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5784 ql_log(ql_log_warn, base_vha, 0xb081, 5785 "Failed to dump mctp\n"); 5786 return; 5787 } 5788 5789 if (!ha->flags.nic_core_reset_hdlr_active) { 5790 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5791 qla83xx_idc_lock(base_vha, 0); 5792 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5793 &dev_state); 5794 qla83xx_idc_unlock(base_vha, 0); 5795 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5796 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5797 "Nic Core f/w is alive.\n"); 5798 return; 5799 } 5800 } 5801 5802 ha->flags.nic_core_reset_hdlr_active = 1; 5803 if (qla83xx_nic_core_reset(base_vha)) { 5804 /* NIC Core reset failed. */ 5805 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5806 "NIC Core reset failed.\n"); 5807 } 5808 ha->flags.nic_core_reset_hdlr_active = 0; 5809 } 5810 } 5811 5812 /* Work: Handle 8200 IDC aens */ 5813 void 5814 qla83xx_service_idc_aen(struct work_struct *work) 5815 { 5816 struct qla_hw_data *ha = 5817 container_of(work, struct qla_hw_data, idc_aen); 5818 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5819 uint32_t dev_state, idc_control; 5820 5821 qla83xx_idc_lock(base_vha, 0); 5822 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5823 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5824 qla83xx_idc_unlock(base_vha, 0); 5825 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5826 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5827 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5828 "Application requested NIC Core Reset.\n"); 5829 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5830 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5831 QLA_SUCCESS) { 5832 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5833 "Other protocol driver requested NIC Core Reset.\n"); 5834 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5835 } 5836 } else if (dev_state == QLA8XXX_DEV_FAILED || 5837 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5838 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5839 } 5840 } 5841 5842 /* 5843 * Control the frequency of IDC lock retries 5844 */ 5845 #define QLA83XX_WAIT_LOGIC_MS 100 5846 5847 static int 5848 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5849 { 5850 int rval; 5851 uint32_t data; 5852 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5853 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5854 struct qla_hw_data *ha = base_vha->hw; 5855 5856 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5857 "Trying force recovery of the IDC lock.\n"); 5858 5859 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5860 if (rval) 5861 return rval; 5862 5863 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5864 return QLA_SUCCESS; 5865 } else { 5866 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5867 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5868 data); 5869 if (rval) 5870 return rval; 5871 5872 msleep(200); 5873 5874 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5875 &data); 5876 if (rval) 5877 return rval; 5878 5879 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5880 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5881 ~(idc_lck_rcvry_stage_mask)); 5882 rval = qla83xx_wr_reg(base_vha, 5883 QLA83XX_IDC_LOCK_RECOVERY, data); 5884 if (rval) 5885 return rval; 5886 5887 /* Forcefully perform IDC UnLock */ 5888 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5889 &data); 5890 if (rval) 5891 return rval; 5892 /* Clear lock-id by setting 0xff */ 5893 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5894 0xff); 5895 if (rval) 5896 return rval; 5897 /* Clear lock-recovery by setting 0x0 */ 5898 rval = qla83xx_wr_reg(base_vha, 5899 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5900 if (rval) 5901 return rval; 5902 } else 5903 return QLA_SUCCESS; 5904 } 5905 5906 return rval; 5907 } 5908 5909 static int 5910 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5911 { 5912 int rval = QLA_SUCCESS; 5913 uint32_t o_drv_lockid, n_drv_lockid; 5914 unsigned long lock_recovery_timeout; 5915 5916 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5917 retry_lockid: 5918 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5919 if (rval) 5920 goto exit; 5921 5922 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5923 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5924 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5925 return QLA_SUCCESS; 5926 else 5927 return QLA_FUNCTION_FAILED; 5928 } 5929 5930 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5931 if (rval) 5932 goto exit; 5933 5934 if (o_drv_lockid == n_drv_lockid) { 5935 msleep(QLA83XX_WAIT_LOGIC_MS); 5936 goto retry_lockid; 5937 } else 5938 return QLA_SUCCESS; 5939 5940 exit: 5941 return rval; 5942 } 5943 5944 /* 5945 * Context: task, can sleep 5946 */ 5947 void 5948 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5949 { 5950 uint32_t data; 5951 uint32_t lock_owner; 5952 struct qla_hw_data *ha = base_vha->hw; 5953 5954 might_sleep(); 5955 5956 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5957 retry_lock: 5958 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5959 == QLA_SUCCESS) { 5960 if (data) { 5961 /* Setting lock-id to our function-number */ 5962 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5963 ha->portnum); 5964 } else { 5965 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5966 &lock_owner); 5967 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5968 "Failed to acquire IDC lock, acquired by %d, " 5969 "retrying...\n", lock_owner); 5970 5971 /* Retry/Perform IDC-Lock recovery */ 5972 if (qla83xx_idc_lock_recovery(base_vha) 5973 == QLA_SUCCESS) { 5974 msleep(QLA83XX_WAIT_LOGIC_MS); 5975 goto retry_lock; 5976 } else 5977 ql_log(ql_log_warn, base_vha, 0xb075, 5978 "IDC Lock recovery FAILED.\n"); 5979 } 5980 5981 } 5982 5983 return; 5984 } 5985 5986 static bool 5987 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5988 struct purex_entry_24xx *purex) 5989 { 5990 char fwstr[16]; 5991 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5992 struct port_database_24xx *pdb; 5993 5994 /* Domain Controller is always logged-out. */ 5995 /* if RDP request is not from Domain Controller: */ 5996 if (sid != 0xfffc01) 5997 return false; 5998 5999 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 6000 6001 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 6002 if (!pdb) { 6003 ql_dbg(ql_dbg_init, vha, 0x0181, 6004 "%s: Failed allocate pdb\n", __func__); 6005 } else if (qla24xx_get_port_database(vha, 6006 le16_to_cpu(purex->nport_handle), pdb)) { 6007 ql_dbg(ql_dbg_init, vha, 0x0181, 6008 "%s: Failed get pdb sid=%x\n", __func__, sid); 6009 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6010 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6011 ql_dbg(ql_dbg_init, vha, 0x0181, 6012 "%s: Port not logged in sid=%#x\n", __func__, sid); 6013 } else { 6014 /* RDP request is from logged in port */ 6015 kfree(pdb); 6016 return false; 6017 } 6018 kfree(pdb); 6019 6020 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6021 fwstr[strcspn(fwstr, " ")] = 0; 6022 /* if FW version allows RDP response length upto 2048 bytes: */ 6023 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6024 return false; 6025 6026 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6027 6028 /* RDP response length is to be reduced to maximum 256 bytes */ 6029 return true; 6030 } 6031 6032 /* 6033 * Function Name: qla24xx_process_purex_iocb 6034 * 6035 * Description: 6036 * Prepare a RDP response and send to Fabric switch 6037 * 6038 * PARAMETERS: 6039 * vha: SCSI qla host 6040 * purex: RDP request received by HBA 6041 */ 6042 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6043 struct purex_item *item) 6044 { 6045 struct qla_hw_data *ha = vha->hw; 6046 struct purex_entry_24xx *purex = 6047 (struct purex_entry_24xx *)&item->iocb; 6048 dma_addr_t rsp_els_dma; 6049 dma_addr_t rsp_payload_dma; 6050 dma_addr_t stat_dma; 6051 dma_addr_t sfp_dma; 6052 struct els_entry_24xx *rsp_els = NULL; 6053 struct rdp_rsp_payload *rsp_payload = NULL; 6054 struct link_statistics *stat = NULL; 6055 uint8_t *sfp = NULL; 6056 uint16_t sfp_flags = 0; 6057 uint rsp_payload_length = sizeof(*rsp_payload); 6058 int rval; 6059 6060 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6061 "%s: Enter\n", __func__); 6062 6063 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6064 "-------- ELS REQ -------\n"); 6065 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6066 purex, sizeof(*purex)); 6067 6068 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6069 rsp_payload_length = 6070 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6071 ql_dbg(ql_dbg_init, vha, 0x0181, 6072 "Reducing RSP payload length to %u bytes...\n", 6073 rsp_payload_length); 6074 } 6075 6076 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6077 &rsp_els_dma, GFP_KERNEL); 6078 if (!rsp_els) { 6079 ql_log(ql_log_warn, vha, 0x0183, 6080 "Failed allocate dma buffer ELS RSP.\n"); 6081 goto dealloc; 6082 } 6083 6084 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6085 &rsp_payload_dma, GFP_KERNEL); 6086 if (!rsp_payload) { 6087 ql_log(ql_log_warn, vha, 0x0184, 6088 "Failed allocate dma buffer ELS RSP payload.\n"); 6089 goto dealloc; 6090 } 6091 6092 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6093 &sfp_dma, GFP_KERNEL); 6094 6095 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6096 &stat_dma, GFP_KERNEL); 6097 6098 /* Prepare Response IOCB */ 6099 rsp_els->entry_type = ELS_IOCB_TYPE; 6100 rsp_els->entry_count = 1; 6101 rsp_els->sys_define = 0; 6102 rsp_els->entry_status = 0; 6103 rsp_els->handle = 0; 6104 rsp_els->nport_handle = purex->nport_handle; 6105 rsp_els->tx_dsd_count = cpu_to_le16(1); 6106 rsp_els->vp_index = purex->vp_idx; 6107 rsp_els->sof_type = EST_SOFI3; 6108 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6109 rsp_els->rx_dsd_count = 0; 6110 rsp_els->opcode = purex->els_frame_payload[0]; 6111 6112 rsp_els->d_id[0] = purex->s_id[0]; 6113 rsp_els->d_id[1] = purex->s_id[1]; 6114 rsp_els->d_id[2] = purex->s_id[2]; 6115 6116 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6117 rsp_els->rx_byte_count = 0; 6118 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6119 6120 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6121 rsp_els->tx_len = rsp_els->tx_byte_count; 6122 6123 rsp_els->rx_address = 0; 6124 rsp_els->rx_len = 0; 6125 6126 /* Prepare Response Payload */ 6127 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6128 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6129 sizeof(rsp_payload->hdr)); 6130 6131 /* Link service Request Info Descriptor */ 6132 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6133 rsp_payload->ls_req_info_desc.desc_len = 6134 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6135 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6136 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6137 6138 /* Link service Request Info Descriptor 2 */ 6139 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6140 rsp_payload->ls_req_info_desc2.desc_len = 6141 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6142 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6143 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6144 6145 6146 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6147 rsp_payload->sfp_diag_desc.desc_len = 6148 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6149 6150 if (sfp) { 6151 /* SFP Flags */ 6152 memset(sfp, 0, SFP_RTDI_LEN); 6153 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6154 if (!rval) { 6155 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6156 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6157 sfp_flags |= BIT_0; /* short wave */ 6158 else if (sfp[0] & BIT_1) 6159 sfp_flags |= BIT_1; /* long wave 1310nm */ 6160 else if (sfp[1] & BIT_4) 6161 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6162 } 6163 6164 /* SFP Type */ 6165 memset(sfp, 0, SFP_RTDI_LEN); 6166 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6167 if (!rval) { 6168 sfp_flags |= BIT_4; /* optical */ 6169 if (sfp[0] == 0x3) 6170 sfp_flags |= BIT_6; /* sfp+ */ 6171 } 6172 6173 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6174 6175 /* SFP Diagnostics */ 6176 memset(sfp, 0, SFP_RTDI_LEN); 6177 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6178 if (!rval) { 6179 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6180 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6181 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6182 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6183 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6184 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6185 } 6186 } 6187 6188 /* Port Speed Descriptor */ 6189 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6190 rsp_payload->port_speed_desc.desc_len = 6191 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6192 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6193 qla25xx_fdmi_port_speed_capability(ha)); 6194 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6195 qla25xx_fdmi_port_speed_currently(ha)); 6196 6197 /* Link Error Status Descriptor */ 6198 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6199 rsp_payload->ls_err_desc.desc_len = 6200 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6201 6202 if (stat) { 6203 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6204 if (!rval) { 6205 rsp_payload->ls_err_desc.link_fail_cnt = 6206 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6207 rsp_payload->ls_err_desc.loss_sync_cnt = 6208 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6209 rsp_payload->ls_err_desc.loss_sig_cnt = 6210 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6211 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6212 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6213 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6214 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6215 rsp_payload->ls_err_desc.inval_crc_cnt = 6216 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6217 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6218 } 6219 } 6220 6221 /* Portname Descriptor */ 6222 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6223 rsp_payload->port_name_diag_desc.desc_len = 6224 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6225 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6226 vha->node_name, 6227 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6228 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6229 vha->port_name, 6230 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6231 6232 /* F-Port Portname Descriptor */ 6233 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6234 rsp_payload->port_name_direct_desc.desc_len = 6235 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6236 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6237 vha->fabric_node_name, 6238 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6239 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6240 vha->fabric_port_name, 6241 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6242 6243 /* Bufer Credit Descriptor */ 6244 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6245 rsp_payload->buffer_credit_desc.desc_len = 6246 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6247 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6248 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6249 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6250 6251 if (ha->flags.plogi_template_valid) { 6252 uint32_t tmp = 6253 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6254 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6255 } 6256 6257 if (rsp_payload_length < sizeof(*rsp_payload)) 6258 goto send; 6259 6260 /* Optical Element Descriptor, Temperature */ 6261 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6262 rsp_payload->optical_elmt_desc[0].desc_len = 6263 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6264 /* Optical Element Descriptor, Voltage */ 6265 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6266 rsp_payload->optical_elmt_desc[1].desc_len = 6267 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6268 /* Optical Element Descriptor, Tx Bias Current */ 6269 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6270 rsp_payload->optical_elmt_desc[2].desc_len = 6271 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6272 /* Optical Element Descriptor, Tx Power */ 6273 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6274 rsp_payload->optical_elmt_desc[3].desc_len = 6275 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6276 /* Optical Element Descriptor, Rx Power */ 6277 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6278 rsp_payload->optical_elmt_desc[4].desc_len = 6279 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6280 6281 if (sfp) { 6282 memset(sfp, 0, SFP_RTDI_LEN); 6283 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6284 if (!rval) { 6285 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6286 6287 /* Optical Element Descriptor, Temperature */ 6288 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6289 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6290 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6291 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6292 rsp_payload->optical_elmt_desc[0].element_flags = 6293 cpu_to_be32(1 << 28); 6294 6295 /* Optical Element Descriptor, Voltage */ 6296 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6297 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6298 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6299 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6300 rsp_payload->optical_elmt_desc[1].element_flags = 6301 cpu_to_be32(2 << 28); 6302 6303 /* Optical Element Descriptor, Tx Bias Current */ 6304 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6305 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6306 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6307 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6308 rsp_payload->optical_elmt_desc[2].element_flags = 6309 cpu_to_be32(3 << 28); 6310 6311 /* Optical Element Descriptor, Tx Power */ 6312 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6313 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6314 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6315 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6316 rsp_payload->optical_elmt_desc[3].element_flags = 6317 cpu_to_be32(4 << 28); 6318 6319 /* Optical Element Descriptor, Rx Power */ 6320 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6321 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6322 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6323 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6324 rsp_payload->optical_elmt_desc[4].element_flags = 6325 cpu_to_be32(5 << 28); 6326 } 6327 6328 memset(sfp, 0, SFP_RTDI_LEN); 6329 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6330 if (!rval) { 6331 /* Temperature high/low alarm/warning */ 6332 rsp_payload->optical_elmt_desc[0].element_flags |= 6333 cpu_to_be32( 6334 (sfp[0] >> 7 & 1) << 3 | 6335 (sfp[0] >> 6 & 1) << 2 | 6336 (sfp[4] >> 7 & 1) << 1 | 6337 (sfp[4] >> 6 & 1) << 0); 6338 6339 /* Voltage high/low alarm/warning */ 6340 rsp_payload->optical_elmt_desc[1].element_flags |= 6341 cpu_to_be32( 6342 (sfp[0] >> 5 & 1) << 3 | 6343 (sfp[0] >> 4 & 1) << 2 | 6344 (sfp[4] >> 5 & 1) << 1 | 6345 (sfp[4] >> 4 & 1) << 0); 6346 6347 /* Tx Bias Current high/low alarm/warning */ 6348 rsp_payload->optical_elmt_desc[2].element_flags |= 6349 cpu_to_be32( 6350 (sfp[0] >> 3 & 1) << 3 | 6351 (sfp[0] >> 2 & 1) << 2 | 6352 (sfp[4] >> 3 & 1) << 1 | 6353 (sfp[4] >> 2 & 1) << 0); 6354 6355 /* Tx Power high/low alarm/warning */ 6356 rsp_payload->optical_elmt_desc[3].element_flags |= 6357 cpu_to_be32( 6358 (sfp[0] >> 1 & 1) << 3 | 6359 (sfp[0] >> 0 & 1) << 2 | 6360 (sfp[4] >> 1 & 1) << 1 | 6361 (sfp[4] >> 0 & 1) << 0); 6362 6363 /* Rx Power high/low alarm/warning */ 6364 rsp_payload->optical_elmt_desc[4].element_flags |= 6365 cpu_to_be32( 6366 (sfp[1] >> 7 & 1) << 3 | 6367 (sfp[1] >> 6 & 1) << 2 | 6368 (sfp[5] >> 7 & 1) << 1 | 6369 (sfp[5] >> 6 & 1) << 0); 6370 } 6371 } 6372 6373 /* Optical Product Data Descriptor */ 6374 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6375 rsp_payload->optical_prod_desc.desc_len = 6376 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6377 6378 if (sfp) { 6379 memset(sfp, 0, SFP_RTDI_LEN); 6380 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6381 if (!rval) { 6382 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6383 sfp + 0, 6384 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6385 memcpy(rsp_payload->optical_prod_desc.part_number, 6386 sfp + 20, 6387 sizeof(rsp_payload->optical_prod_desc.part_number)); 6388 memcpy(rsp_payload->optical_prod_desc.revision, 6389 sfp + 36, 6390 sizeof(rsp_payload->optical_prod_desc.revision)); 6391 memcpy(rsp_payload->optical_prod_desc.serial_number, 6392 sfp + 48, 6393 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6394 } 6395 6396 memset(sfp, 0, SFP_RTDI_LEN); 6397 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6398 if (!rval) { 6399 memcpy(rsp_payload->optical_prod_desc.date, 6400 sfp + 0, 6401 sizeof(rsp_payload->optical_prod_desc.date)); 6402 } 6403 } 6404 6405 send: 6406 ql_dbg(ql_dbg_init, vha, 0x0183, 6407 "Sending ELS Response to RDP Request...\n"); 6408 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6409 "-------- ELS RSP -------\n"); 6410 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6411 rsp_els, sizeof(*rsp_els)); 6412 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6413 "-------- ELS RSP PAYLOAD -------\n"); 6414 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6415 rsp_payload, rsp_payload_length); 6416 6417 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6418 6419 if (rval) { 6420 ql_log(ql_log_warn, vha, 0x0188, 6421 "%s: iocb failed to execute -> %x\n", __func__, rval); 6422 } else if (rsp_els->comp_status) { 6423 ql_log(ql_log_warn, vha, 0x0189, 6424 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6425 __func__, rsp_els->comp_status, 6426 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6427 } else { 6428 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6429 } 6430 6431 dealloc: 6432 if (stat) 6433 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6434 stat, stat_dma); 6435 if (sfp) 6436 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6437 sfp, sfp_dma); 6438 if (rsp_payload) 6439 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6440 rsp_payload, rsp_payload_dma); 6441 if (rsp_els) 6442 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6443 rsp_els, rsp_els_dma); 6444 } 6445 6446 void 6447 qla24xx_free_purex_item(struct purex_item *item) 6448 { 6449 if (item == &item->vha->default_item) 6450 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6451 else 6452 kfree(item); 6453 } 6454 6455 void qla24xx_process_purex_list(struct purex_list *list) 6456 { 6457 struct list_head head = LIST_HEAD_INIT(head); 6458 struct purex_item *item, *next; 6459 ulong flags; 6460 6461 spin_lock_irqsave(&list->lock, flags); 6462 list_splice_init(&list->head, &head); 6463 spin_unlock_irqrestore(&list->lock, flags); 6464 6465 list_for_each_entry_safe(item, next, &head, list) { 6466 list_del(&item->list); 6467 item->process_item(item->vha, item); 6468 qla24xx_free_purex_item(item); 6469 } 6470 } 6471 6472 /* 6473 * Context: task, can sleep 6474 */ 6475 void 6476 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6477 { 6478 #if 0 6479 uint16_t options = (requester_id << 15) | BIT_7; 6480 #endif 6481 uint16_t retry; 6482 uint32_t data; 6483 struct qla_hw_data *ha = base_vha->hw; 6484 6485 might_sleep(); 6486 6487 /* IDC-unlock implementation using driver-unlock/lock-id 6488 * remote registers 6489 */ 6490 retry = 0; 6491 retry_unlock: 6492 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6493 == QLA_SUCCESS) { 6494 if (data == ha->portnum) { 6495 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6496 /* Clearing lock-id by setting 0xff */ 6497 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6498 } else if (retry < 10) { 6499 /* SV: XXX: IDC unlock retrying needed here? */ 6500 6501 /* Retry for IDC-unlock */ 6502 msleep(QLA83XX_WAIT_LOGIC_MS); 6503 retry++; 6504 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6505 "Failed to release IDC lock, retrying=%d\n", retry); 6506 goto retry_unlock; 6507 } 6508 } else if (retry < 10) { 6509 /* Retry for IDC-unlock */ 6510 msleep(QLA83XX_WAIT_LOGIC_MS); 6511 retry++; 6512 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6513 "Failed to read drv-lockid, retrying=%d\n", retry); 6514 goto retry_unlock; 6515 } 6516 6517 return; 6518 6519 #if 0 6520 /* XXX: IDC-unlock implementation using access-control mbx */ 6521 retry = 0; 6522 retry_unlock2: 6523 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6524 if (retry < 10) { 6525 /* Retry for IDC-unlock */ 6526 msleep(QLA83XX_WAIT_LOGIC_MS); 6527 retry++; 6528 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6529 "Failed to release IDC lock, retrying=%d\n", retry); 6530 goto retry_unlock2; 6531 } 6532 } 6533 6534 return; 6535 #endif 6536 } 6537 6538 int 6539 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6540 { 6541 int rval = QLA_SUCCESS; 6542 struct qla_hw_data *ha = vha->hw; 6543 uint32_t drv_presence; 6544 6545 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6546 if (rval == QLA_SUCCESS) { 6547 drv_presence |= (1 << ha->portnum); 6548 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6549 drv_presence); 6550 } 6551 6552 return rval; 6553 } 6554 6555 int 6556 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6557 { 6558 int rval = QLA_SUCCESS; 6559 6560 qla83xx_idc_lock(vha, 0); 6561 rval = __qla83xx_set_drv_presence(vha); 6562 qla83xx_idc_unlock(vha, 0); 6563 6564 return rval; 6565 } 6566 6567 int 6568 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6569 { 6570 int rval = QLA_SUCCESS; 6571 struct qla_hw_data *ha = vha->hw; 6572 uint32_t drv_presence; 6573 6574 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6575 if (rval == QLA_SUCCESS) { 6576 drv_presence &= ~(1 << ha->portnum); 6577 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6578 drv_presence); 6579 } 6580 6581 return rval; 6582 } 6583 6584 int 6585 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6586 { 6587 int rval = QLA_SUCCESS; 6588 6589 qla83xx_idc_lock(vha, 0); 6590 rval = __qla83xx_clear_drv_presence(vha); 6591 qla83xx_idc_unlock(vha, 0); 6592 6593 return rval; 6594 } 6595 6596 static void 6597 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6598 { 6599 struct qla_hw_data *ha = vha->hw; 6600 uint32_t drv_ack, drv_presence; 6601 unsigned long ack_timeout; 6602 6603 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6604 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6605 while (1) { 6606 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6607 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6608 if ((drv_ack & drv_presence) == drv_presence) 6609 break; 6610 6611 if (time_after_eq(jiffies, ack_timeout)) { 6612 ql_log(ql_log_warn, vha, 0xb067, 6613 "RESET ACK TIMEOUT! drv_presence=0x%x " 6614 "drv_ack=0x%x\n", drv_presence, drv_ack); 6615 /* 6616 * The function(s) which did not ack in time are forced 6617 * to withdraw any further participation in the IDC 6618 * reset. 6619 */ 6620 if (drv_ack != drv_presence) 6621 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6622 drv_ack); 6623 break; 6624 } 6625 6626 qla83xx_idc_unlock(vha, 0); 6627 msleep(1000); 6628 qla83xx_idc_lock(vha, 0); 6629 } 6630 6631 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6632 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6633 } 6634 6635 static int 6636 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6637 { 6638 int rval = QLA_SUCCESS; 6639 uint32_t idc_control; 6640 6641 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6642 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6643 6644 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6645 __qla83xx_get_idc_control(vha, &idc_control); 6646 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6647 __qla83xx_set_idc_control(vha, 0); 6648 6649 qla83xx_idc_unlock(vha, 0); 6650 rval = qla83xx_restart_nic_firmware(vha); 6651 qla83xx_idc_lock(vha, 0); 6652 6653 if (rval != QLA_SUCCESS) { 6654 ql_log(ql_log_fatal, vha, 0xb06a, 6655 "Failed to restart NIC f/w.\n"); 6656 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6657 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6658 } else { 6659 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6660 "Success in restarting nic f/w.\n"); 6661 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6662 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6663 } 6664 6665 return rval; 6666 } 6667 6668 /* Assumes idc_lock always held on entry */ 6669 int 6670 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6671 { 6672 struct qla_hw_data *ha = base_vha->hw; 6673 int rval = QLA_SUCCESS; 6674 unsigned long dev_init_timeout; 6675 uint32_t dev_state; 6676 6677 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6678 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6679 6680 while (1) { 6681 6682 if (time_after_eq(jiffies, dev_init_timeout)) { 6683 ql_log(ql_log_warn, base_vha, 0xb06e, 6684 "Initialization TIMEOUT!\n"); 6685 /* Init timeout. Disable further NIC Core 6686 * communication. 6687 */ 6688 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6689 QLA8XXX_DEV_FAILED); 6690 ql_log(ql_log_info, base_vha, 0xb06f, 6691 "HW State: FAILED.\n"); 6692 } 6693 6694 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6695 switch (dev_state) { 6696 case QLA8XXX_DEV_READY: 6697 if (ha->flags.nic_core_reset_owner) 6698 qla83xx_idc_audit(base_vha, 6699 IDC_AUDIT_COMPLETION); 6700 ha->flags.nic_core_reset_owner = 0; 6701 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6702 "Reset_owner reset by 0x%x.\n", 6703 ha->portnum); 6704 goto exit; 6705 case QLA8XXX_DEV_COLD: 6706 if (ha->flags.nic_core_reset_owner) 6707 rval = qla83xx_device_bootstrap(base_vha); 6708 else { 6709 /* Wait for AEN to change device-state */ 6710 qla83xx_idc_unlock(base_vha, 0); 6711 msleep(1000); 6712 qla83xx_idc_lock(base_vha, 0); 6713 } 6714 break; 6715 case QLA8XXX_DEV_INITIALIZING: 6716 /* Wait for AEN to change device-state */ 6717 qla83xx_idc_unlock(base_vha, 0); 6718 msleep(1000); 6719 qla83xx_idc_lock(base_vha, 0); 6720 break; 6721 case QLA8XXX_DEV_NEED_RESET: 6722 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6723 qla83xx_need_reset_handler(base_vha); 6724 else { 6725 /* Wait for AEN to change device-state */ 6726 qla83xx_idc_unlock(base_vha, 0); 6727 msleep(1000); 6728 qla83xx_idc_lock(base_vha, 0); 6729 } 6730 /* reset timeout value after need reset handler */ 6731 dev_init_timeout = jiffies + 6732 (ha->fcoe_dev_init_timeout * HZ); 6733 break; 6734 case QLA8XXX_DEV_NEED_QUIESCENT: 6735 /* XXX: DEBUG for now */ 6736 qla83xx_idc_unlock(base_vha, 0); 6737 msleep(1000); 6738 qla83xx_idc_lock(base_vha, 0); 6739 break; 6740 case QLA8XXX_DEV_QUIESCENT: 6741 /* XXX: DEBUG for now */ 6742 if (ha->flags.quiesce_owner) 6743 goto exit; 6744 6745 qla83xx_idc_unlock(base_vha, 0); 6746 msleep(1000); 6747 qla83xx_idc_lock(base_vha, 0); 6748 dev_init_timeout = jiffies + 6749 (ha->fcoe_dev_init_timeout * HZ); 6750 break; 6751 case QLA8XXX_DEV_FAILED: 6752 if (ha->flags.nic_core_reset_owner) 6753 qla83xx_idc_audit(base_vha, 6754 IDC_AUDIT_COMPLETION); 6755 ha->flags.nic_core_reset_owner = 0; 6756 __qla83xx_clear_drv_presence(base_vha); 6757 qla83xx_idc_unlock(base_vha, 0); 6758 qla8xxx_dev_failed_handler(base_vha); 6759 rval = QLA_FUNCTION_FAILED; 6760 qla83xx_idc_lock(base_vha, 0); 6761 goto exit; 6762 case QLA8XXX_BAD_VALUE: 6763 qla83xx_idc_unlock(base_vha, 0); 6764 msleep(1000); 6765 qla83xx_idc_lock(base_vha, 0); 6766 break; 6767 default: 6768 ql_log(ql_log_warn, base_vha, 0xb071, 6769 "Unknown Device State: %x.\n", dev_state); 6770 qla83xx_idc_unlock(base_vha, 0); 6771 qla8xxx_dev_failed_handler(base_vha); 6772 rval = QLA_FUNCTION_FAILED; 6773 qla83xx_idc_lock(base_vha, 0); 6774 goto exit; 6775 } 6776 } 6777 6778 exit: 6779 return rval; 6780 } 6781 6782 void 6783 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6784 { 6785 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6786 board_disable); 6787 struct pci_dev *pdev = ha->pdev; 6788 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6789 6790 ql_log(ql_log_warn, base_vha, 0x015b, 6791 "Disabling adapter.\n"); 6792 6793 if (!atomic_read(&pdev->enable_cnt)) { 6794 ql_log(ql_log_info, base_vha, 0xfffc, 6795 "PCI device disabled, no action req for PCI error=%lx\n", 6796 base_vha->pci_flags); 6797 return; 6798 } 6799 6800 /* 6801 * if UNLOADING flag is already set, then continue unload, 6802 * where it was set first. 6803 */ 6804 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6805 return; 6806 6807 qla2x00_wait_for_sess_deletion(base_vha); 6808 6809 qla2x00_delete_all_vps(ha, base_vha); 6810 6811 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6812 6813 qla2x00_dfs_remove(base_vha); 6814 6815 qla84xx_put_chip(base_vha); 6816 6817 if (base_vha->timer_active) 6818 qla2x00_stop_timer(base_vha); 6819 6820 base_vha->flags.online = 0; 6821 6822 qla2x00_destroy_deferred_work(ha); 6823 6824 /* 6825 * Do not try to stop beacon blink as it will issue a mailbox 6826 * command. 6827 */ 6828 qla2x00_free_sysfs_attr(base_vha, false); 6829 6830 fc_remove_host(base_vha->host); 6831 6832 scsi_remove_host(base_vha->host); 6833 6834 base_vha->flags.init_done = 0; 6835 qla25xx_delete_queues(base_vha); 6836 qla2x00_free_fcports(base_vha); 6837 qla2x00_free_irqs(base_vha); 6838 qla2x00_mem_free(ha); 6839 qla82xx_md_free(base_vha); 6840 qla2x00_free_queues(ha); 6841 6842 qla2x00_unmap_iobases(ha); 6843 6844 pci_release_selected_regions(ha->pdev, ha->bars); 6845 pci_disable_device(pdev); 6846 6847 /* 6848 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6849 */ 6850 } 6851 6852 /************************************************************************** 6853 * qla2x00_do_dpc 6854 * This kernel thread is a task that is schedule by the interrupt handler 6855 * to perform the background processing for interrupts. 6856 * 6857 * Notes: 6858 * This task always run in the context of a kernel thread. It 6859 * is kick-off by the driver's detect code and starts up 6860 * up one per adapter. It immediately goes to sleep and waits for 6861 * some fibre event. When either the interrupt handler or 6862 * the timer routine detects a event it will one of the task 6863 * bits then wake us up. 6864 **************************************************************************/ 6865 static int 6866 qla2x00_do_dpc(void *data) 6867 { 6868 scsi_qla_host_t *base_vha; 6869 struct qla_hw_data *ha; 6870 uint32_t online; 6871 struct qla_qpair *qpair; 6872 6873 ha = (struct qla_hw_data *)data; 6874 base_vha = pci_get_drvdata(ha->pdev); 6875 6876 set_user_nice(current, MIN_NICE); 6877 6878 set_current_state(TASK_INTERRUPTIBLE); 6879 while (!kthread_should_stop()) { 6880 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6881 "DPC handler sleeping.\n"); 6882 6883 schedule(); 6884 6885 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6886 qla_pci_set_eeh_busy(base_vha); 6887 6888 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6889 goto end_loop; 6890 6891 if (ha->flags.eeh_busy) { 6892 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6893 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6894 goto end_loop; 6895 } 6896 6897 ha->dpc_active = 1; 6898 6899 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6900 "DPC handler waking up, dpc_flags=0x%lx.\n", 6901 base_vha->dpc_flags); 6902 6903 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6904 break; 6905 6906 if (IS_P3P_TYPE(ha)) { 6907 if (IS_QLA8044(ha)) { 6908 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6909 &base_vha->dpc_flags)) { 6910 qla8044_idc_lock(ha); 6911 qla8044_wr_direct(base_vha, 6912 QLA8044_CRB_DEV_STATE_INDEX, 6913 QLA8XXX_DEV_FAILED); 6914 qla8044_idc_unlock(ha); 6915 ql_log(ql_log_info, base_vha, 0x4004, 6916 "HW State: FAILED.\n"); 6917 qla8044_device_state_handler(base_vha); 6918 continue; 6919 } 6920 6921 } else { 6922 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6923 &base_vha->dpc_flags)) { 6924 qla82xx_idc_lock(ha); 6925 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6926 QLA8XXX_DEV_FAILED); 6927 qla82xx_idc_unlock(ha); 6928 ql_log(ql_log_info, base_vha, 0x0151, 6929 "HW State: FAILED.\n"); 6930 qla82xx_device_state_handler(base_vha); 6931 continue; 6932 } 6933 } 6934 6935 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6936 &base_vha->dpc_flags)) { 6937 6938 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6939 "FCoE context reset scheduled.\n"); 6940 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6941 &base_vha->dpc_flags))) { 6942 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6943 /* FCoE-ctx reset failed. 6944 * Escalate to chip-reset 6945 */ 6946 set_bit(ISP_ABORT_NEEDED, 6947 &base_vha->dpc_flags); 6948 } 6949 clear_bit(ABORT_ISP_ACTIVE, 6950 &base_vha->dpc_flags); 6951 } 6952 6953 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6954 "FCoE context reset end.\n"); 6955 } 6956 } else if (IS_QLAFX00(ha)) { 6957 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6958 &base_vha->dpc_flags)) { 6959 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6960 "Firmware Reset Recovery\n"); 6961 if (qlafx00_reset_initialize(base_vha)) { 6962 /* Failed. Abort isp later. */ 6963 if (!test_bit(UNLOADING, 6964 &base_vha->dpc_flags)) { 6965 set_bit(ISP_UNRECOVERABLE, 6966 &base_vha->dpc_flags); 6967 ql_dbg(ql_dbg_dpc, base_vha, 6968 0x4021, 6969 "Reset Recovery Failed\n"); 6970 } 6971 } 6972 } 6973 6974 if (test_and_clear_bit(FX00_TARGET_SCAN, 6975 &base_vha->dpc_flags)) { 6976 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6977 "ISPFx00 Target Scan scheduled\n"); 6978 if (qlafx00_rescan_isp(base_vha)) { 6979 if (!test_bit(UNLOADING, 6980 &base_vha->dpc_flags)) 6981 set_bit(ISP_UNRECOVERABLE, 6982 &base_vha->dpc_flags); 6983 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6984 "ISPFx00 Target Scan Failed\n"); 6985 } 6986 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6987 "ISPFx00 Target Scan End\n"); 6988 } 6989 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6990 &base_vha->dpc_flags)) { 6991 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6992 "ISPFx00 Host Info resend scheduled\n"); 6993 qlafx00_fx_disc(base_vha, 6994 &base_vha->hw->mr.fcport, 6995 FXDISC_REG_HOST_INFO); 6996 } 6997 } 6998 6999 if (test_and_clear_bit(DETECT_SFP_CHANGE, 7000 &base_vha->dpc_flags)) { 7001 /* Semantic: 7002 * - NO-OP -- await next ISP-ABORT. Preferred method 7003 * to minimize disruptions that will occur 7004 * when a forced chip-reset occurs. 7005 * - Force -- ISP-ABORT scheduled. 7006 */ 7007 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7008 } 7009 7010 if (test_and_clear_bit 7011 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7012 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7013 bool do_reset = true; 7014 7015 switch (base_vha->qlini_mode) { 7016 case QLA2XXX_INI_MODE_ENABLED: 7017 break; 7018 case QLA2XXX_INI_MODE_DISABLED: 7019 if (!qla_tgt_mode_enabled(base_vha) && 7020 !ha->flags.fw_started) 7021 do_reset = false; 7022 break; 7023 case QLA2XXX_INI_MODE_DUAL: 7024 if (!qla_dual_mode_enabled(base_vha) && 7025 !ha->flags.fw_started) 7026 do_reset = false; 7027 break; 7028 default: 7029 break; 7030 } 7031 7032 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7033 &base_vha->dpc_flags))) { 7034 base_vha->flags.online = 1; 7035 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7036 "ISP abort scheduled.\n"); 7037 if (ha->isp_ops->abort_isp(base_vha)) { 7038 /* failed. retry later */ 7039 set_bit(ISP_ABORT_NEEDED, 7040 &base_vha->dpc_flags); 7041 } 7042 clear_bit(ABORT_ISP_ACTIVE, 7043 &base_vha->dpc_flags); 7044 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7045 "ISP abort end.\n"); 7046 } 7047 } 7048 7049 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7050 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7051 qla24xx_process_purex_list 7052 (&base_vha->purex_list); 7053 clear_bit(PROCESS_PUREX_IOCB, 7054 &base_vha->dpc_flags); 7055 } 7056 } 7057 7058 if (IS_QLAFX00(ha)) 7059 goto loop_resync_check; 7060 7061 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7062 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7063 "Quiescence mode scheduled.\n"); 7064 if (IS_P3P_TYPE(ha)) { 7065 if (IS_QLA82XX(ha)) 7066 qla82xx_device_state_handler(base_vha); 7067 if (IS_QLA8044(ha)) 7068 qla8044_device_state_handler(base_vha); 7069 clear_bit(ISP_QUIESCE_NEEDED, 7070 &base_vha->dpc_flags); 7071 if (!ha->flags.quiesce_owner) { 7072 qla2x00_perform_loop_resync(base_vha); 7073 if (IS_QLA82XX(ha)) { 7074 qla82xx_idc_lock(ha); 7075 qla82xx_clear_qsnt_ready( 7076 base_vha); 7077 qla82xx_idc_unlock(ha); 7078 } else if (IS_QLA8044(ha)) { 7079 qla8044_idc_lock(ha); 7080 qla8044_clear_qsnt_ready( 7081 base_vha); 7082 qla8044_idc_unlock(ha); 7083 } 7084 } 7085 } else { 7086 clear_bit(ISP_QUIESCE_NEEDED, 7087 &base_vha->dpc_flags); 7088 qla2x00_quiesce_io(base_vha); 7089 } 7090 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7091 "Quiescence mode end.\n"); 7092 } 7093 7094 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7095 &base_vha->dpc_flags) && 7096 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7097 7098 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7099 "Reset marker scheduled.\n"); 7100 qla2x00_rst_aen(base_vha); 7101 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7102 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7103 "Reset marker end.\n"); 7104 } 7105 7106 /* Retry each device up to login retry count */ 7107 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7108 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7109 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7110 7111 if (!base_vha->relogin_jif || 7112 time_after_eq(jiffies, base_vha->relogin_jif)) { 7113 base_vha->relogin_jif = jiffies + HZ; 7114 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7115 7116 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7117 "Relogin scheduled.\n"); 7118 qla24xx_post_relogin_work(base_vha); 7119 } 7120 } 7121 loop_resync_check: 7122 if (!qla2x00_reset_active(base_vha) && 7123 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7124 &base_vha->dpc_flags)) { 7125 /* 7126 * Allow abort_isp to complete before moving on to scanning. 7127 */ 7128 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7129 "Loop resync scheduled.\n"); 7130 7131 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7132 &base_vha->dpc_flags))) { 7133 7134 qla2x00_loop_resync(base_vha); 7135 7136 clear_bit(LOOP_RESYNC_ACTIVE, 7137 &base_vha->dpc_flags); 7138 } 7139 7140 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7141 "Loop resync end.\n"); 7142 } 7143 7144 if (IS_QLAFX00(ha)) 7145 goto intr_on_check; 7146 7147 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7148 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7149 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7150 qla2xxx_flash_npiv_conf(base_vha); 7151 } 7152 7153 intr_on_check: 7154 if (!ha->interrupts_on) 7155 ha->isp_ops->enable_intrs(ha); 7156 7157 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7158 &base_vha->dpc_flags)) { 7159 if (ha->beacon_blink_led == 1) 7160 ha->isp_ops->beacon_blink(base_vha); 7161 } 7162 7163 /* qpair online check */ 7164 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7165 &base_vha->dpc_flags)) { 7166 if (ha->flags.eeh_busy || 7167 ha->flags.pci_channel_io_perm_failure) 7168 online = 0; 7169 else 7170 online = 1; 7171 7172 mutex_lock(&ha->mq_lock); 7173 list_for_each_entry(qpair, &base_vha->qp_list, 7174 qp_list_elem) 7175 qpair->online = online; 7176 mutex_unlock(&ha->mq_lock); 7177 } 7178 7179 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7180 &base_vha->dpc_flags)) { 7181 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7182 7183 if (threshold > ha->orig_fw_xcb_count) 7184 threshold = ha->orig_fw_xcb_count; 7185 7186 ql_log(ql_log_info, base_vha, 0xffffff, 7187 "SET ZIO Activity exchange threshold to %d.\n", 7188 threshold); 7189 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7190 ql_log(ql_log_info, base_vha, 0xffffff, 7191 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7192 threshold); 7193 } 7194 } 7195 7196 if (!IS_QLAFX00(ha)) 7197 qla2x00_do_dpc_all_vps(base_vha); 7198 7199 if (test_and_clear_bit(N2N_LINK_RESET, 7200 &base_vha->dpc_flags)) { 7201 qla2x00_lip_reset(base_vha); 7202 } 7203 7204 ha->dpc_active = 0; 7205 end_loop: 7206 set_current_state(TASK_INTERRUPTIBLE); 7207 } /* End of while(1) */ 7208 __set_current_state(TASK_RUNNING); 7209 7210 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7211 "DPC handler exiting.\n"); 7212 7213 /* 7214 * Make sure that nobody tries to wake us up again. 7215 */ 7216 ha->dpc_active = 0; 7217 7218 /* Cleanup any residual CTX SRBs. */ 7219 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7220 7221 return 0; 7222 } 7223 7224 void 7225 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7226 { 7227 struct qla_hw_data *ha = vha->hw; 7228 struct task_struct *t = ha->dpc_thread; 7229 7230 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7231 wake_up_process(t); 7232 } 7233 7234 /* 7235 * qla2x00_rst_aen 7236 * Processes asynchronous reset. 7237 * 7238 * Input: 7239 * ha = adapter block pointer. 7240 */ 7241 static void 7242 qla2x00_rst_aen(scsi_qla_host_t *vha) 7243 { 7244 if (vha->flags.online && !vha->flags.reset_active && 7245 !atomic_read(&vha->loop_down_timer) && 7246 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7247 do { 7248 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7249 7250 /* 7251 * Issue marker command only when we are going to start 7252 * the I/O. 7253 */ 7254 vha->marker_needed = 1; 7255 } while (!atomic_read(&vha->loop_down_timer) && 7256 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7257 } 7258 } 7259 7260 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7261 { 7262 struct qla_hw_data *ha = vha->hw; 7263 u32 cmpl_cnt; 7264 u16 i; 7265 bool do_heartbeat = false; 7266 7267 /* 7268 * Allow do_heartbeat only if we don’t have any active interrupts, 7269 * but there are still IOs outstanding with firmware. 7270 */ 7271 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7272 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7273 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7274 do_heartbeat = true; 7275 goto skip; 7276 } 7277 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7278 7279 for (i = 0; i < ha->max_qpairs; i++) { 7280 if (ha->queue_pair_map[i]) { 7281 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7282 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7283 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7284 do_heartbeat = true; 7285 break; 7286 } 7287 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7288 } 7289 } 7290 7291 skip: 7292 return do_heartbeat; 7293 } 7294 7295 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7296 { 7297 struct qla_hw_data *ha = vha->hw; 7298 7299 if (vha->vp_idx) 7300 return; 7301 7302 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7303 return; 7304 7305 /* 7306 * dpc thread cannot run if heartbeat is running at the same time. 7307 * We also do not want to starve heartbeat task. Therefore, do 7308 * heartbeat task at least once every 5 seconds. 7309 */ 7310 if (dpc_started && 7311 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7312 return; 7313 7314 if (qla_do_heartbeat(vha)) { 7315 ha->last_heartbeat_run_jiffies = jiffies; 7316 queue_work(ha->wq, &ha->heartbeat_work); 7317 } 7318 } 7319 7320 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7321 { 7322 struct qla_hw_data *ha = vha->hw; 7323 7324 if (!ha->flags.eeh_busy) 7325 return; 7326 if (ha->pci_error_state) 7327 /* system is trying to recover */ 7328 return; 7329 7330 /* 7331 * Current system is not handling PCIE error. At this point, this is 7332 * best effort to wind down the adapter. 7333 */ 7334 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7335 !ha->flags.eeh_flush) { 7336 ql_log(ql_log_info, vha, 0x9009, 7337 "PCI Error detected, attempting to reset hardware.\n"); 7338 7339 ha->isp_ops->reset_chip(vha); 7340 ha->isp_ops->disable_intrs(ha); 7341 7342 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7343 ha->eeh_jif = jiffies; 7344 7345 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7346 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7347 pci_clear_master(ha->pdev); 7348 7349 /* flush all command */ 7350 qla2x00_abort_isp_cleanup(vha); 7351 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7352 7353 ql_log(ql_log_info, vha, 0x900a, 7354 "PCI Error handling complete, all IOs aborted.\n"); 7355 } 7356 } 7357 7358 /************************************************************************** 7359 * qla2x00_timer 7360 * 7361 * Description: 7362 * One second timer 7363 * 7364 * Context: Interrupt 7365 ***************************************************************************/ 7366 void 7367 qla2x00_timer(struct timer_list *t) 7368 { 7369 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7370 unsigned long cpu_flags = 0; 7371 int start_dpc = 0; 7372 int index; 7373 srb_t *sp; 7374 uint16_t w; 7375 struct qla_hw_data *ha = vha->hw; 7376 struct req_que *req; 7377 unsigned long flags; 7378 fc_port_t *fcport = NULL; 7379 7380 if (ha->flags.eeh_busy) { 7381 qla_wind_down_chip(vha); 7382 7383 ql_dbg(ql_dbg_timer, vha, 0x6000, 7384 "EEH = %d, restarting timer.\n", 7385 ha->flags.eeh_busy); 7386 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7387 return; 7388 } 7389 7390 /* 7391 * Hardware read to raise pending EEH errors during mailbox waits. If 7392 * the read returns -1 then disable the board. 7393 */ 7394 if (!pci_channel_offline(ha->pdev)) { 7395 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7396 qla2x00_check_reg16_for_disconnect(vha, w); 7397 } 7398 7399 /* Make sure qla82xx_watchdog is run only for physical port */ 7400 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7401 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7402 start_dpc++; 7403 if (IS_QLA82XX(ha)) 7404 qla82xx_watchdog(vha); 7405 else if (IS_QLA8044(ha)) 7406 qla8044_watchdog(vha); 7407 } 7408 7409 if (!vha->vp_idx && IS_QLAFX00(ha)) 7410 qlafx00_timer_routine(vha); 7411 7412 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7413 vha->link_down_time++; 7414 7415 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7416 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7417 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7418 fcport->tgt_link_down_time++; 7419 } 7420 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7421 7422 /* Loop down handler. */ 7423 if (atomic_read(&vha->loop_down_timer) > 0 && 7424 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7425 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7426 && vha->flags.online) { 7427 7428 if (atomic_read(&vha->loop_down_timer) == 7429 vha->loop_down_abort_time) { 7430 7431 ql_log(ql_log_info, vha, 0x6008, 7432 "Loop down - aborting the queues before time expires.\n"); 7433 7434 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7435 atomic_set(&vha->loop_state, LOOP_DEAD); 7436 7437 /* 7438 * Schedule an ISP abort to return any FCP2-device 7439 * commands. 7440 */ 7441 /* NPIV - scan physical port only */ 7442 if (!vha->vp_idx) { 7443 spin_lock_irqsave(&ha->hardware_lock, 7444 cpu_flags); 7445 req = ha->req_q_map[0]; 7446 for (index = 1; 7447 index < req->num_outstanding_cmds; 7448 index++) { 7449 fc_port_t *sfcp; 7450 7451 sp = req->outstanding_cmds[index]; 7452 if (!sp) 7453 continue; 7454 if (sp->cmd_type != TYPE_SRB) 7455 continue; 7456 if (sp->type != SRB_SCSI_CMD) 7457 continue; 7458 sfcp = sp->fcport; 7459 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7460 continue; 7461 7462 if (IS_QLA82XX(ha)) 7463 set_bit(FCOE_CTX_RESET_NEEDED, 7464 &vha->dpc_flags); 7465 else 7466 set_bit(ISP_ABORT_NEEDED, 7467 &vha->dpc_flags); 7468 break; 7469 } 7470 spin_unlock_irqrestore(&ha->hardware_lock, 7471 cpu_flags); 7472 } 7473 start_dpc++; 7474 } 7475 7476 /* if the loop has been down for 4 minutes, reinit adapter */ 7477 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7478 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7479 ql_log(ql_log_warn, vha, 0x6009, 7480 "Loop down - aborting ISP.\n"); 7481 7482 if (IS_QLA82XX(ha)) 7483 set_bit(FCOE_CTX_RESET_NEEDED, 7484 &vha->dpc_flags); 7485 else 7486 set_bit(ISP_ABORT_NEEDED, 7487 &vha->dpc_flags); 7488 } 7489 } 7490 ql_dbg(ql_dbg_timer, vha, 0x600a, 7491 "Loop down - seconds remaining %d.\n", 7492 atomic_read(&vha->loop_down_timer)); 7493 } 7494 /* Check if beacon LED needs to be blinked for physical host only */ 7495 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7496 /* There is no beacon_blink function for ISP82xx */ 7497 if (!IS_P3P_TYPE(ha)) { 7498 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7499 start_dpc++; 7500 } 7501 } 7502 7503 /* check if edif running */ 7504 if (vha->hw->flags.edif_enabled) 7505 qla_edif_timer(vha); 7506 7507 /* Process any deferred work. */ 7508 if (!list_empty(&vha->work_list)) { 7509 unsigned long flags; 7510 bool q = false; 7511 7512 spin_lock_irqsave(&vha->work_lock, flags); 7513 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7514 q = true; 7515 spin_unlock_irqrestore(&vha->work_lock, flags); 7516 if (q) 7517 queue_work(vha->hw->wq, &vha->iocb_work); 7518 } 7519 7520 /* 7521 * FC-NVME 7522 * see if the active AEN count has changed from what was last reported. 7523 */ 7524 index = atomic_read(&ha->nvme_active_aen_cnt); 7525 if (!vha->vp_idx && 7526 (index != ha->nvme_last_rptd_aen) && 7527 ha->zio_mode == QLA_ZIO_MODE_6 && 7528 !ha->flags.host_shutting_down) { 7529 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7530 ql_log(ql_log_info, vha, 0x3002, 7531 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7532 ha->nvme_last_rptd_aen); 7533 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7534 start_dpc++; 7535 } 7536 7537 if (!vha->vp_idx && 7538 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7539 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7540 ql_log(ql_log_info, vha, 0x3002, 7541 "Sched: Set ZIO exchange threshold to %d.\n", 7542 ha->last_zio_threshold); 7543 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7544 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7545 start_dpc++; 7546 } 7547 qla_adjust_buf(vha); 7548 7549 /* borrowing w to signify dpc will run */ 7550 w = 0; 7551 /* Schedule the DPC routine if needed */ 7552 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7553 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7554 start_dpc || 7555 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7556 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7557 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7558 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7559 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7560 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7561 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7562 ql_dbg(ql_dbg_timer, vha, 0x600b, 7563 "isp_abort_needed=%d loop_resync_needed=%d " 7564 "start_dpc=%d reset_marker_needed=%d", 7565 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7566 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7567 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7568 ql_dbg(ql_dbg_timer, vha, 0x600c, 7569 "beacon_blink_needed=%d isp_unrecoverable=%d " 7570 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7571 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7572 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7573 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7574 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7575 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7576 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7577 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7578 qla2xxx_wake_dpc(vha); 7579 w = 1; 7580 } 7581 7582 qla_heart_beat(vha, w); 7583 7584 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7585 } 7586 7587 /* Firmware interface routines. */ 7588 7589 #define FW_ISP21XX 0 7590 #define FW_ISP22XX 1 7591 #define FW_ISP2300 2 7592 #define FW_ISP2322 3 7593 #define FW_ISP24XX 4 7594 #define FW_ISP25XX 5 7595 #define FW_ISP81XX 6 7596 #define FW_ISP82XX 7 7597 #define FW_ISP2031 8 7598 #define FW_ISP8031 9 7599 #define FW_ISP27XX 10 7600 #define FW_ISP28XX 11 7601 7602 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7603 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7604 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7605 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7606 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7607 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7608 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7609 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7610 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7611 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7612 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7613 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7614 7615 7616 static DEFINE_MUTEX(qla_fw_lock); 7617 7618 static struct fw_blob qla_fw_blobs[] = { 7619 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7620 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7621 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7622 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7623 { .name = FW_FILE_ISP24XX, }, 7624 { .name = FW_FILE_ISP25XX, }, 7625 { .name = FW_FILE_ISP81XX, }, 7626 { .name = FW_FILE_ISP82XX, }, 7627 { .name = FW_FILE_ISP2031, }, 7628 { .name = FW_FILE_ISP8031, }, 7629 { .name = FW_FILE_ISP27XX, }, 7630 { .name = FW_FILE_ISP28XX, }, 7631 { .name = NULL, }, 7632 }; 7633 7634 struct fw_blob * 7635 qla2x00_request_firmware(scsi_qla_host_t *vha) 7636 { 7637 struct qla_hw_data *ha = vha->hw; 7638 struct fw_blob *blob; 7639 7640 if (IS_QLA2100(ha)) { 7641 blob = &qla_fw_blobs[FW_ISP21XX]; 7642 } else if (IS_QLA2200(ha)) { 7643 blob = &qla_fw_blobs[FW_ISP22XX]; 7644 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7645 blob = &qla_fw_blobs[FW_ISP2300]; 7646 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7647 blob = &qla_fw_blobs[FW_ISP2322]; 7648 } else if (IS_QLA24XX_TYPE(ha)) { 7649 blob = &qla_fw_blobs[FW_ISP24XX]; 7650 } else if (IS_QLA25XX(ha)) { 7651 blob = &qla_fw_blobs[FW_ISP25XX]; 7652 } else if (IS_QLA81XX(ha)) { 7653 blob = &qla_fw_blobs[FW_ISP81XX]; 7654 } else if (IS_QLA82XX(ha)) { 7655 blob = &qla_fw_blobs[FW_ISP82XX]; 7656 } else if (IS_QLA2031(ha)) { 7657 blob = &qla_fw_blobs[FW_ISP2031]; 7658 } else if (IS_QLA8031(ha)) { 7659 blob = &qla_fw_blobs[FW_ISP8031]; 7660 } else if (IS_QLA27XX(ha)) { 7661 blob = &qla_fw_blobs[FW_ISP27XX]; 7662 } else if (IS_QLA28XX(ha)) { 7663 blob = &qla_fw_blobs[FW_ISP28XX]; 7664 } else { 7665 return NULL; 7666 } 7667 7668 if (!blob->name) 7669 return NULL; 7670 7671 mutex_lock(&qla_fw_lock); 7672 if (blob->fw) 7673 goto out; 7674 7675 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7676 ql_log(ql_log_warn, vha, 0x0063, 7677 "Failed to load firmware image (%s).\n", blob->name); 7678 blob->fw = NULL; 7679 blob = NULL; 7680 } 7681 7682 out: 7683 mutex_unlock(&qla_fw_lock); 7684 return blob; 7685 } 7686 7687 static void 7688 qla2x00_release_firmware(void) 7689 { 7690 struct fw_blob *blob; 7691 7692 mutex_lock(&qla_fw_lock); 7693 for (blob = qla_fw_blobs; blob->name; blob++) 7694 release_firmware(blob->fw); 7695 mutex_unlock(&qla_fw_lock); 7696 } 7697 7698 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7699 { 7700 struct qla_hw_data *ha = vha->hw; 7701 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7702 struct qla_qpair *qpair = NULL; 7703 struct scsi_qla_host *vp, *tvp; 7704 fc_port_t *fcport; 7705 int i; 7706 unsigned long flags; 7707 7708 ql_dbg(ql_dbg_aer, vha, 0x9000, 7709 "%s\n", __func__); 7710 ha->chip_reset++; 7711 7712 ha->base_qpair->chip_reset = ha->chip_reset; 7713 for (i = 0; i < ha->max_qpairs; i++) { 7714 if (ha->queue_pair_map[i]) 7715 ha->queue_pair_map[i]->chip_reset = 7716 ha->base_qpair->chip_reset; 7717 } 7718 7719 /* 7720 * purge mailbox might take a while. Slot Reset/chip reset 7721 * will take care of the purge 7722 */ 7723 7724 mutex_lock(&ha->mq_lock); 7725 ha->base_qpair->online = 0; 7726 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7727 qpair->online = 0; 7728 wmb(); 7729 mutex_unlock(&ha->mq_lock); 7730 7731 qla2x00_mark_all_devices_lost(vha); 7732 7733 spin_lock_irqsave(&ha->vport_slock, flags); 7734 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7735 atomic_inc(&vp->vref_count); 7736 spin_unlock_irqrestore(&ha->vport_slock, flags); 7737 qla2x00_mark_all_devices_lost(vp); 7738 spin_lock_irqsave(&ha->vport_slock, flags); 7739 atomic_dec(&vp->vref_count); 7740 } 7741 spin_unlock_irqrestore(&ha->vport_slock, flags); 7742 7743 /* Clear all async request states across all VPs. */ 7744 list_for_each_entry(fcport, &vha->vp_fcports, list) 7745 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7746 7747 spin_lock_irqsave(&ha->vport_slock, flags); 7748 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7749 atomic_inc(&vp->vref_count); 7750 spin_unlock_irqrestore(&ha->vport_slock, flags); 7751 list_for_each_entry(fcport, &vp->vp_fcports, list) 7752 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7753 spin_lock_irqsave(&ha->vport_slock, flags); 7754 atomic_dec(&vp->vref_count); 7755 } 7756 spin_unlock_irqrestore(&ha->vport_slock, flags); 7757 } 7758 7759 7760 static pci_ers_result_t 7761 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7762 { 7763 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7764 struct qla_hw_data *ha = vha->hw; 7765 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7766 7767 ql_log(ql_log_warn, vha, 0x9000, 7768 "PCI error detected, state %x.\n", state); 7769 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7770 7771 if (!atomic_read(&pdev->enable_cnt)) { 7772 ql_log(ql_log_info, vha, 0xffff, 7773 "PCI device is disabled,state %x\n", state); 7774 ret = PCI_ERS_RESULT_NEED_RESET; 7775 goto out; 7776 } 7777 7778 switch (state) { 7779 case pci_channel_io_normal: 7780 qla_pci_set_eeh_busy(vha); 7781 if (ql2xmqsupport || ql2xnvmeenable) { 7782 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7783 qla2xxx_wake_dpc(vha); 7784 } 7785 ret = PCI_ERS_RESULT_CAN_RECOVER; 7786 break; 7787 case pci_channel_io_frozen: 7788 qla_pci_set_eeh_busy(vha); 7789 ret = PCI_ERS_RESULT_NEED_RESET; 7790 break; 7791 case pci_channel_io_perm_failure: 7792 ha->flags.pci_channel_io_perm_failure = 1; 7793 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7794 if (ql2xmqsupport || ql2xnvmeenable) { 7795 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7796 qla2xxx_wake_dpc(vha); 7797 } 7798 ret = PCI_ERS_RESULT_DISCONNECT; 7799 } 7800 out: 7801 ql_dbg(ql_dbg_aer, vha, 0x600d, 7802 "PCI error detected returning [%x].\n", ret); 7803 return ret; 7804 } 7805 7806 static pci_ers_result_t 7807 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7808 { 7809 int risc_paused = 0; 7810 uint32_t stat; 7811 unsigned long flags; 7812 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7813 struct qla_hw_data *ha = base_vha->hw; 7814 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7815 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7816 7817 ql_log(ql_log_warn, base_vha, 0x9000, 7818 "mmio enabled\n"); 7819 7820 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7821 7822 if (IS_QLA82XX(ha)) 7823 return PCI_ERS_RESULT_RECOVERED; 7824 7825 if (qla2x00_isp_reg_stat(ha)) { 7826 ql_log(ql_log_info, base_vha, 0x803f, 7827 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7828 goto out; 7829 } 7830 7831 spin_lock_irqsave(&ha->hardware_lock, flags); 7832 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7833 stat = rd_reg_word(®->hccr); 7834 if (stat & HCCR_RISC_PAUSE) 7835 risc_paused = 1; 7836 } else if (IS_QLA23XX(ha)) { 7837 stat = rd_reg_dword(®->u.isp2300.host_status); 7838 if (stat & HSR_RISC_PAUSED) 7839 risc_paused = 1; 7840 } else if (IS_FWI2_CAPABLE(ha)) { 7841 stat = rd_reg_dword(®24->host_status); 7842 if (stat & HSRX_RISC_PAUSED) 7843 risc_paused = 1; 7844 } 7845 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7846 7847 if (risc_paused) { 7848 ql_log(ql_log_info, base_vha, 0x9003, 7849 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7850 qla2xxx_dump_fw(base_vha); 7851 } 7852 out: 7853 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7854 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7855 "mmio enabled returning.\n"); 7856 return PCI_ERS_RESULT_NEED_RESET; 7857 } 7858 7859 static pci_ers_result_t 7860 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7861 { 7862 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7863 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7864 struct qla_hw_data *ha = base_vha->hw; 7865 int rc; 7866 struct qla_qpair *qpair = NULL; 7867 7868 ql_log(ql_log_warn, base_vha, 0x9004, 7869 "Slot Reset.\n"); 7870 7871 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7872 /* Workaround: qla2xxx driver which access hardware earlier 7873 * needs error state to be pci_channel_io_online. 7874 * Otherwise mailbox command timesout. 7875 */ 7876 pdev->error_state = pci_channel_io_normal; 7877 7878 pci_restore_state(pdev); 7879 7880 /* pci_restore_state() clears the saved_state flag of the device 7881 * save restored state which resets saved_state flag 7882 */ 7883 pci_save_state(pdev); 7884 7885 if (ha->mem_only) 7886 rc = pci_enable_device_mem(pdev); 7887 else 7888 rc = pci_enable_device(pdev); 7889 7890 if (rc) { 7891 ql_log(ql_log_warn, base_vha, 0x9005, 7892 "Can't re-enable PCI device after reset.\n"); 7893 goto exit_slot_reset; 7894 } 7895 7896 7897 if (ha->isp_ops->pci_config(base_vha)) 7898 goto exit_slot_reset; 7899 7900 mutex_lock(&ha->mq_lock); 7901 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7902 qpair->online = 1; 7903 mutex_unlock(&ha->mq_lock); 7904 7905 ha->flags.eeh_busy = 0; 7906 base_vha->flags.online = 1; 7907 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7908 ha->isp_ops->abort_isp(base_vha); 7909 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7910 7911 if (qla2x00_isp_reg_stat(ha)) { 7912 ha->flags.eeh_busy = 1; 7913 qla_pci_error_cleanup(base_vha); 7914 ql_log(ql_log_warn, base_vha, 0x9005, 7915 "Device unable to recover from PCI error.\n"); 7916 } else { 7917 ret = PCI_ERS_RESULT_RECOVERED; 7918 } 7919 7920 exit_slot_reset: 7921 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7922 "Slot Reset returning %x.\n", ret); 7923 7924 return ret; 7925 } 7926 7927 static void 7928 qla2xxx_pci_resume(struct pci_dev *pdev) 7929 { 7930 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7931 struct qla_hw_data *ha = base_vha->hw; 7932 int ret; 7933 7934 ql_log(ql_log_warn, base_vha, 0x900f, 7935 "Pci Resume.\n"); 7936 7937 7938 ret = qla2x00_wait_for_hba_online(base_vha); 7939 if (ret != QLA_SUCCESS) { 7940 ql_log(ql_log_fatal, base_vha, 0x9002, 7941 "The device failed to resume I/O from slot/link_reset.\n"); 7942 } 7943 ha->pci_error_state = QLA_PCI_RESUME; 7944 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7945 "Pci Resume returning.\n"); 7946 } 7947 7948 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7949 { 7950 struct qla_hw_data *ha = vha->hw; 7951 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7952 bool do_cleanup = false; 7953 unsigned long flags; 7954 7955 if (ha->flags.eeh_busy) 7956 return; 7957 7958 spin_lock_irqsave(&base_vha->work_lock, flags); 7959 if (!ha->flags.eeh_busy) { 7960 ha->eeh_jif = jiffies; 7961 ha->flags.eeh_flush = 0; 7962 7963 ha->flags.eeh_busy = 1; 7964 do_cleanup = true; 7965 } 7966 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7967 7968 if (do_cleanup) 7969 qla_pci_error_cleanup(base_vha); 7970 } 7971 7972 /* 7973 * this routine will schedule a task to pause IO from interrupt context 7974 * if caller sees a PCIE error event (register read = 0xf's) 7975 */ 7976 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7977 { 7978 struct qla_hw_data *ha = vha->hw; 7979 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7980 7981 if (ha->flags.eeh_busy) 7982 return; 7983 7984 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7985 qla2xxx_wake_dpc(base_vha); 7986 } 7987 7988 static void 7989 qla_pci_reset_prepare(struct pci_dev *pdev) 7990 { 7991 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7992 struct qla_hw_data *ha = base_vha->hw; 7993 struct qla_qpair *qpair; 7994 7995 ql_log(ql_log_warn, base_vha, 0xffff, 7996 "%s.\n", __func__); 7997 7998 /* 7999 * PCI FLR/function reset is about to reset the 8000 * slot. Stop the chip to stop all DMA access. 8001 * It is assumed that pci_reset_done will be called 8002 * after FLR to resume Chip operation. 8003 */ 8004 ha->flags.eeh_busy = 1; 8005 mutex_lock(&ha->mq_lock); 8006 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8007 qpair->online = 0; 8008 mutex_unlock(&ha->mq_lock); 8009 8010 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8011 qla2x00_abort_isp_cleanup(base_vha); 8012 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8013 } 8014 8015 static void 8016 qla_pci_reset_done(struct pci_dev *pdev) 8017 { 8018 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8019 struct qla_hw_data *ha = base_vha->hw; 8020 struct qla_qpair *qpair; 8021 8022 ql_log(ql_log_warn, base_vha, 0xffff, 8023 "%s.\n", __func__); 8024 8025 /* 8026 * FLR just completed by PCI layer. Resume adapter 8027 */ 8028 ha->flags.eeh_busy = 0; 8029 mutex_lock(&ha->mq_lock); 8030 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8031 qpair->online = 1; 8032 mutex_unlock(&ha->mq_lock); 8033 8034 base_vha->flags.online = 1; 8035 ha->isp_ops->abort_isp(base_vha); 8036 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8037 } 8038 8039 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8040 { 8041 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8042 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8043 8044 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8045 blk_mq_map_queues(qmap); 8046 else 8047 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8048 } 8049 8050 struct scsi_host_template qla2xxx_driver_template = { 8051 .module = THIS_MODULE, 8052 .name = QLA2XXX_DRIVER_NAME, 8053 .queuecommand = qla2xxx_queuecommand, 8054 8055 .eh_timed_out = fc_eh_timed_out, 8056 .eh_abort_handler = qla2xxx_eh_abort, 8057 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8058 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8059 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8060 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8061 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8062 8063 .slave_configure = qla2xxx_slave_configure, 8064 8065 .slave_alloc = qla2xxx_slave_alloc, 8066 .slave_destroy = qla2xxx_slave_destroy, 8067 .scan_finished = qla2xxx_scan_finished, 8068 .scan_start = qla2xxx_scan_start, 8069 .change_queue_depth = scsi_change_queue_depth, 8070 .map_queues = qla2xxx_map_queues, 8071 .this_id = -1, 8072 .cmd_per_lun = 3, 8073 .sg_tablesize = SG_ALL, 8074 8075 .max_sectors = 0xFFFF, 8076 .shost_groups = qla2x00_host_groups, 8077 8078 .supported_mode = MODE_INITIATOR, 8079 .track_queue_depth = 1, 8080 .cmd_size = sizeof(srb_t), 8081 }; 8082 8083 static const struct pci_error_handlers qla2xxx_err_handler = { 8084 .error_detected = qla2xxx_pci_error_detected, 8085 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8086 .slot_reset = qla2xxx_pci_slot_reset, 8087 .resume = qla2xxx_pci_resume, 8088 .reset_prepare = qla_pci_reset_prepare, 8089 .reset_done = qla_pci_reset_done, 8090 }; 8091 8092 static struct pci_device_id qla2xxx_pci_tbl[] = { 8093 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8094 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8095 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8096 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8097 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8098 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8099 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8100 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8101 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8102 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8103 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8104 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8105 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8106 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8107 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8112 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8113 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8114 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8115 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8116 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8117 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8118 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8119 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8120 { 0 }, 8121 }; 8122 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8123 8124 static struct pci_driver qla2xxx_pci_driver = { 8125 .name = QLA2XXX_DRIVER_NAME, 8126 .driver = { 8127 .owner = THIS_MODULE, 8128 }, 8129 .id_table = qla2xxx_pci_tbl, 8130 .probe = qla2x00_probe_one, 8131 .remove = qla2x00_remove_one, 8132 .shutdown = qla2x00_shutdown, 8133 .err_handler = &qla2xxx_err_handler, 8134 }; 8135 8136 static const struct file_operations apidev_fops = { 8137 .owner = THIS_MODULE, 8138 .llseek = noop_llseek, 8139 }; 8140 8141 /** 8142 * qla2x00_module_init - Module initialization. 8143 **/ 8144 static int __init 8145 qla2x00_module_init(void) 8146 { 8147 int ret = 0; 8148 8149 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8150 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8151 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8152 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8153 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8154 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8155 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8156 BUILD_BUG_ON(sizeof(request_t) != 64); 8157 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8158 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8159 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8160 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8161 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8162 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8163 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8164 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8165 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8166 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8167 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8168 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8169 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8170 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8171 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8172 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8173 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8174 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8175 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8176 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8177 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8178 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8179 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8180 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8181 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8182 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8183 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8184 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8185 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8186 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8187 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8188 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8189 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8190 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8191 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8192 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8193 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8194 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8195 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8196 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8197 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8198 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8199 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8200 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8201 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8202 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8203 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8204 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8205 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8206 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8207 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8208 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8209 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8210 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8211 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8212 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8213 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8214 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8215 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8216 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8217 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8218 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8219 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8220 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8221 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8222 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8223 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8224 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8225 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8226 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8227 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8228 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8229 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8230 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8231 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8232 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8233 8234 qla_trace_init(); 8235 8236 /* Allocate cache for SRBs. */ 8237 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8238 SLAB_HWCACHE_ALIGN, NULL); 8239 if (srb_cachep == NULL) { 8240 ql_log(ql_log_fatal, NULL, 0x0001, 8241 "Unable to allocate SRB cache...Failing load!.\n"); 8242 return -ENOMEM; 8243 } 8244 8245 /* Initialize target kmem_cache and mem_pools */ 8246 ret = qlt_init(); 8247 if (ret < 0) { 8248 goto destroy_cache; 8249 } else if (ret > 0) { 8250 /* 8251 * If initiator mode is explictly disabled by qlt_init(), 8252 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8253 * performing scsi_scan_target() during LOOP UP event. 8254 */ 8255 qla2xxx_transport_functions.disable_target_scan = 1; 8256 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8257 } 8258 8259 /* Derive version string. */ 8260 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8261 if (ql2xextended_error_logging) 8262 strcat(qla2x00_version_str, "-debug"); 8263 if (ql2xextended_error_logging == 1) 8264 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8265 8266 qla2xxx_transport_template = 8267 fc_attach_transport(&qla2xxx_transport_functions); 8268 if (!qla2xxx_transport_template) { 8269 ql_log(ql_log_fatal, NULL, 0x0002, 8270 "fc_attach_transport failed...Failing load!.\n"); 8271 ret = -ENODEV; 8272 goto qlt_exit; 8273 } 8274 8275 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8276 if (apidev_major < 0) { 8277 ql_log(ql_log_fatal, NULL, 0x0003, 8278 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8279 } 8280 8281 qla2xxx_transport_vport_template = 8282 fc_attach_transport(&qla2xxx_transport_vport_functions); 8283 if (!qla2xxx_transport_vport_template) { 8284 ql_log(ql_log_fatal, NULL, 0x0004, 8285 "fc_attach_transport vport failed...Failing load!.\n"); 8286 ret = -ENODEV; 8287 goto unreg_chrdev; 8288 } 8289 ql_log(ql_log_info, NULL, 0x0005, 8290 "QLogic Fibre Channel HBA Driver: %s.\n", 8291 qla2x00_version_str); 8292 ret = pci_register_driver(&qla2xxx_pci_driver); 8293 if (ret) { 8294 ql_log(ql_log_fatal, NULL, 0x0006, 8295 "pci_register_driver failed...ret=%d Failing load!.\n", 8296 ret); 8297 goto release_vport_transport; 8298 } 8299 return ret; 8300 8301 release_vport_transport: 8302 fc_release_transport(qla2xxx_transport_vport_template); 8303 8304 unreg_chrdev: 8305 if (apidev_major >= 0) 8306 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8307 fc_release_transport(qla2xxx_transport_template); 8308 8309 qlt_exit: 8310 qlt_exit(); 8311 8312 destroy_cache: 8313 kmem_cache_destroy(srb_cachep); 8314 8315 qla_trace_uninit(); 8316 return ret; 8317 } 8318 8319 /** 8320 * qla2x00_module_exit - Module cleanup. 8321 **/ 8322 static void __exit 8323 qla2x00_module_exit(void) 8324 { 8325 pci_unregister_driver(&qla2xxx_pci_driver); 8326 qla2x00_release_firmware(); 8327 kmem_cache_destroy(ctx_cachep); 8328 fc_release_transport(qla2xxx_transport_vport_template); 8329 if (apidev_major >= 0) 8330 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8331 fc_release_transport(qla2xxx_transport_template); 8332 qlt_exit(); 8333 kmem_cache_destroy(srb_cachep); 8334 qla_trace_uninit(); 8335 } 8336 8337 module_init(qla2x00_module_init); 8338 module_exit(qla2x00_module_exit); 8339 8340 MODULE_AUTHOR("QLogic Corporation"); 8341 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8342 MODULE_LICENSE("GPL"); 8343 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8344 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8345 MODULE_FIRMWARE(FW_FILE_ISP2300); 8346 MODULE_FIRMWARE(FW_FILE_ISP2322); 8347 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8348 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8349