1 /****************************************************************************** 2 * QLOGIC LINUX SOFTWARE 3 * 4 * QLogic ISP2x00 device driver for Linux 2.6.x 5 * Copyright (C) 2003-2004 QLogic Corporation 6 * (www.qlogic.com) 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 ******************************************************************************/ 19 20 /* 21 * Driver debug definitions. 22 */ 23 /* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ 24 /* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ 25 /* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ 26 /* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ 27 /* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ 28 /* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ 29 /* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ 30 /* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */ 31 /* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */ 32 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */ 33 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */ 34 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */ 35 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */ 36 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */ 37 /* 38 * Local Macro Definitions. 39 */ 40 #if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \ 41 defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \ 42 defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \ 43 defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) || \ 44 defined(QL_DEBUG_LEVEL_9) || defined(QL_DEBUG_LEVEL_10) || \ 45 defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \ 46 defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14) 47 #define QL_DEBUG_ROUTINES 48 #endif 49 50 /* 51 * Macros use for debugging the driver. 52 */ 53 #undef ENTER_TRACE 54 #if defined(ENTER_TRACE) 55 #define ENTER(x) do { printk("qla2100 : Entering %s()\n", x); } while (0) 56 #define LEAVE(x) do { printk("qla2100 : Leaving %s()\n", x); } while (0) 57 #define ENTER_INTR(x) do { printk("qla2100 : Entering %s()\n", x); } while (0) 58 #define LEAVE_INTR(x) do { printk("qla2100 : Leaving %s()\n", x); } while (0) 59 #else 60 #define ENTER(x) do {} while (0) 61 #define LEAVE(x) do {} while (0) 62 #define ENTER_INTR(x) do {} while (0) 63 #define LEAVE_INTR(x) do {} while (0) 64 #endif 65 66 #if DEBUG_QLA2100 67 #define DEBUG(x) do {x;} while (0); 68 #else 69 #define DEBUG(x) do {} while (0); 70 #endif 71 72 #if defined(QL_DEBUG_LEVEL_1) 73 #define DEBUG1(x) do {x;} while (0); 74 #else 75 #define DEBUG1(x) do {} while (0); 76 #endif 77 78 #if defined(QL_DEBUG_LEVEL_2) 79 #define DEBUG2(x) do {x;} while (0); 80 #define DEBUG2_3(x) do {x;} while (0); 81 #define DEBUG2_3_11(x) do {x;} while (0); 82 #define DEBUG2_9_10(x) do {x;} while (0); 83 #define DEBUG2_11(x) do {x;} while (0); 84 #else 85 #define DEBUG2(x) do {} while (0); 86 #endif 87 88 #if defined(QL_DEBUG_LEVEL_3) 89 #define DEBUG3(x) do {x;} while (0); 90 #define DEBUG2_3(x) do {x;} while (0); 91 #define DEBUG2_3_11(x) do {x;} while (0); 92 #define DEBUG3_11(x) do {x;} while (0); 93 #else 94 #define DEBUG3(x) do {} while (0); 95 #if !defined(QL_DEBUG_LEVEL_2) 96 #define DEBUG2_3(x) do {} while (0); 97 #endif 98 #endif 99 100 #if defined(QL_DEBUG_LEVEL_4) 101 #define DEBUG4(x) do {x;} while (0); 102 #else 103 #define DEBUG4(x) do {} while (0); 104 #endif 105 106 #if defined(QL_DEBUG_LEVEL_5) 107 #define DEBUG5(x) do {x;} while (0); 108 #else 109 #define DEBUG5(x) do {} while (0); 110 #endif 111 112 #if defined(QL_DEBUG_LEVEL_7) 113 #define DEBUG7(x) do {x;} while (0); 114 #else 115 #define DEBUG7(x) do {} while (0); 116 #endif 117 118 #if defined(QL_DEBUG_LEVEL_9) 119 #define DEBUG9(x) do {x;} while (0); 120 #define DEBUG9_10(x) do {x;} while (0); 121 #define DEBUG2_9_10(x) do {x;} while (0); 122 #else 123 #define DEBUG9(x) do {} while (0); 124 #endif 125 126 #if defined(QL_DEBUG_LEVEL_10) 127 #define DEBUG10(x) do {x;} while (0); 128 #define DEBUG2_9_10(x) do {x;} while (0); 129 #define DEBUG9_10(x) do {x;} while (0); 130 #else 131 #define DEBUG10(x) do {} while (0); 132 #if !defined(DEBUG2_9_10) 133 #define DEBUG2_9_10(x) do {} while (0); 134 #endif 135 #if !defined(DEBUG9_10) 136 #define DEBUG9_10(x) do {} while (0); 137 #endif 138 #endif 139 140 #if defined(QL_DEBUG_LEVEL_11) 141 #define DEBUG11(x) do{x;} while(0); 142 #if !defined(DEBUG2_11) 143 #define DEBUG2_11(x) do{x;} while(0); 144 #endif 145 #if !defined(DEBUG2_3_11) 146 #define DEBUG2_3_11(x) do{x;} while(0); 147 #endif 148 #if !defined(DEBUG3_11) 149 #define DEBUG3_11(x) do{x;} while(0); 150 #endif 151 #else 152 #define DEBUG11(x) do{} while(0); 153 #if !defined(QL_DEBUG_LEVEL_2) 154 #define DEBUG2_11(x) do{} while(0); 155 #if !defined(QL_DEBUG_LEVEL_3) 156 #define DEBUG2_3_11(x) do{} while(0); 157 #endif 158 #endif 159 #if !defined(QL_DEBUG_LEVEL_3) 160 #define DEBUG3_11(x) do{} while(0); 161 #endif 162 #endif 163 164 #if defined(QL_DEBUG_LEVEL_12) 165 #define DEBUG12(x) do {x;} while (0); 166 #else 167 #define DEBUG12(x) do {} while (0); 168 #endif 169 170 #if defined(QL_DEBUG_LEVEL_13) 171 #define DEBUG13(x) do {x;} while (0) 172 #else 173 #define DEBUG13(x) do {} while (0) 174 #endif 175 176 #if defined(QL_DEBUG_LEVEL_14) 177 #define DEBUG14(x) do {x;} while (0) 178 #else 179 #define DEBUG14(x) do {} while (0) 180 #endif 181 182 /* 183 * Firmware Dump structure definition 184 */ 185 #define FW_DUMP_SIZE_128K 0xBC000 186 #define FW_DUMP_SIZE_512K 0x2FC000 187 #define FW_DUMP_SIZE_1M 0x5FC000 188 189 struct qla2300_fw_dump { 190 uint16_t hccr; 191 uint16_t pbiu_reg[8]; 192 uint16_t risc_host_reg[8]; 193 uint16_t mailbox_reg[32]; 194 uint16_t resp_dma_reg[32]; 195 uint16_t dma_reg[48]; 196 uint16_t risc_hdw_reg[16]; 197 uint16_t risc_gp0_reg[16]; 198 uint16_t risc_gp1_reg[16]; 199 uint16_t risc_gp2_reg[16]; 200 uint16_t risc_gp3_reg[16]; 201 uint16_t risc_gp4_reg[16]; 202 uint16_t risc_gp5_reg[16]; 203 uint16_t risc_gp6_reg[16]; 204 uint16_t risc_gp7_reg[16]; 205 uint16_t frame_buf_hdw_reg[64]; 206 uint16_t fpm_b0_reg[64]; 207 uint16_t fpm_b1_reg[64]; 208 uint16_t risc_ram[0xf800]; 209 uint16_t stack_ram[0x1000]; 210 uint16_t data_ram[1]; 211 }; 212 213 struct qla2100_fw_dump { 214 uint16_t hccr; 215 uint16_t pbiu_reg[8]; 216 uint16_t mailbox_reg[32]; 217 uint16_t dma_reg[48]; 218 uint16_t risc_hdw_reg[16]; 219 uint16_t risc_gp0_reg[16]; 220 uint16_t risc_gp1_reg[16]; 221 uint16_t risc_gp2_reg[16]; 222 uint16_t risc_gp3_reg[16]; 223 uint16_t risc_gp4_reg[16]; 224 uint16_t risc_gp5_reg[16]; 225 uint16_t risc_gp6_reg[16]; 226 uint16_t risc_gp7_reg[16]; 227 uint16_t frame_buf_hdw_reg[16]; 228 uint16_t fpm_b0_reg[64]; 229 uint16_t fpm_b1_reg[64]; 230 uint16_t risc_ram[0xf000]; 231 }; 232 233 234