1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2005 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 11 static inline void 12 qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump) 13 { 14 fw_dump->fw_major_version = htonl(ha->fw_major_version); 15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 17 fw_dump->fw_attributes = htonl(ha->fw_attributes); 18 19 fw_dump->vendor = htonl(ha->pdev->vendor); 20 fw_dump->device = htonl(ha->pdev->device); 21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 23 } 24 25 static inline void * 26 qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr) 27 { 28 /* Request queue. */ 29 memcpy(ptr, ha->request_ring, ha->request_q_length * 30 sizeof(request_t)); 31 32 /* Response queue. */ 33 ptr += ha->request_q_length * sizeof(request_t); 34 memcpy(ptr, ha->response_ring, ha->response_q_length * 35 sizeof(response_t)); 36 37 return ptr + (ha->response_q_length * sizeof(response_t)); 38 } 39 40 static int 41 qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, 42 uint32_t cram_size, uint32_t *ext_mem, void **nxt) 43 { 44 int rval; 45 uint32_t cnt, stat, timer, risc_address, ext_mem_cnt; 46 uint16_t mb[4]; 47 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 48 49 rval = QLA_SUCCESS; 50 risc_address = ext_mem_cnt = 0; 51 memset(mb, 0, sizeof(mb)); 52 53 /* Code RAM. */ 54 risc_address = 0x20000; 55 WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); 56 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 57 58 for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS; 59 cnt++, risc_address++) { 60 WRT_REG_WORD(®->mailbox1, LSW(risc_address)); 61 WRT_REG_WORD(®->mailbox8, MSW(risc_address)); 62 RD_REG_WORD(®->mailbox8); 63 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 64 65 for (timer = 6000000; timer; timer--) { 66 /* Check for pending interrupts. */ 67 stat = RD_REG_DWORD(®->host_status); 68 if (stat & HSRX_RISC_INT) { 69 stat &= 0xff; 70 71 if (stat == 0x1 || stat == 0x2 || 72 stat == 0x10 || stat == 0x11) { 73 set_bit(MBX_INTERRUPT, 74 &ha->mbx_cmd_flags); 75 76 mb[0] = RD_REG_WORD(®->mailbox0); 77 mb[2] = RD_REG_WORD(®->mailbox2); 78 mb[3] = RD_REG_WORD(®->mailbox3); 79 80 WRT_REG_DWORD(®->hccr, 81 HCCRX_CLR_RISC_INT); 82 RD_REG_DWORD(®->hccr); 83 break; 84 } 85 86 /* Clear this intr; it wasn't a mailbox intr */ 87 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 88 RD_REG_DWORD(®->hccr); 89 } 90 udelay(5); 91 } 92 93 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 94 rval = mb[0] & MBS_MASK; 95 code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); 96 } else { 97 rval = QLA_FUNCTION_FAILED; 98 } 99 } 100 101 if (rval == QLA_SUCCESS) { 102 /* External Memory. */ 103 risc_address = 0x100000; 104 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; 105 WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); 106 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 107 } 108 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; 109 cnt++, risc_address++) { 110 WRT_REG_WORD(®->mailbox1, LSW(risc_address)); 111 WRT_REG_WORD(®->mailbox8, MSW(risc_address)); 112 RD_REG_WORD(®->mailbox8); 113 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 114 115 for (timer = 6000000; timer; timer--) { 116 /* Check for pending interrupts. */ 117 stat = RD_REG_DWORD(®->host_status); 118 if (stat & HSRX_RISC_INT) { 119 stat &= 0xff; 120 121 if (stat == 0x1 || stat == 0x2 || 122 stat == 0x10 || stat == 0x11) { 123 set_bit(MBX_INTERRUPT, 124 &ha->mbx_cmd_flags); 125 126 mb[0] = RD_REG_WORD(®->mailbox0); 127 mb[2] = RD_REG_WORD(®->mailbox2); 128 mb[3] = RD_REG_WORD(®->mailbox3); 129 130 WRT_REG_DWORD(®->hccr, 131 HCCRX_CLR_RISC_INT); 132 RD_REG_DWORD(®->hccr); 133 break; 134 } 135 136 /* Clear this intr; it wasn't a mailbox intr */ 137 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 138 RD_REG_DWORD(®->hccr); 139 } 140 udelay(5); 141 } 142 143 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 144 rval = mb[0] & MBS_MASK; 145 ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 146 } else { 147 rval = QLA_FUNCTION_FAILED; 148 } 149 } 150 151 *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL; 152 return rval; 153 } 154 155 static uint32_t * 156 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 157 uint32_t count, uint32_t *buf) 158 { 159 uint32_t __iomem *dmp_reg; 160 161 WRT_REG_DWORD(®->iobase_addr, iobase); 162 dmp_reg = ®->iobase_window; 163 while (count--) 164 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); 165 166 return buf; 167 } 168 169 static inline int 170 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) 171 { 172 int rval = QLA_SUCCESS; 173 uint32_t cnt; 174 175 if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) 176 return rval; 177 178 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); 179 for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && 180 rval == QLA_SUCCESS; cnt--) { 181 if (cnt) 182 udelay(100); 183 else 184 rval = QLA_FUNCTION_TIMEOUT; 185 } 186 187 return rval; 188 } 189 190 static int 191 qla24xx_soft_reset(scsi_qla_host_t *ha) 192 { 193 int rval = QLA_SUCCESS; 194 uint32_t cnt; 195 uint16_t mb0, wd; 196 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 197 198 /* Reset RISC. */ 199 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 200 for (cnt = 0; cnt < 30000; cnt++) { 201 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 202 break; 203 204 udelay(10); 205 } 206 207 WRT_REG_DWORD(®->ctrl_status, 208 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 209 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 210 211 udelay(100); 212 /* Wait for firmware to complete NVRAM accesses. */ 213 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 214 for (cnt = 10000 ; cnt && mb0; cnt--) { 215 udelay(5); 216 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 217 barrier(); 218 } 219 220 /* Wait for soft-reset to complete. */ 221 for (cnt = 0; cnt < 30000; cnt++) { 222 if ((RD_REG_DWORD(®->ctrl_status) & 223 CSRX_ISP_SOFT_RESET) == 0) 224 break; 225 226 udelay(10); 227 } 228 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 229 RD_REG_DWORD(®->hccr); /* PCI Posting. */ 230 231 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && 232 rval == QLA_SUCCESS; cnt--) { 233 if (cnt) 234 udelay(100); 235 else 236 rval = QLA_FUNCTION_TIMEOUT; 237 } 238 239 return rval; 240 } 241 242 static inline void 243 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 244 uint16_t *buf) 245 { 246 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 247 248 while (count--) 249 *buf++ = htons(RD_REG_WORD(dmp_reg++)); 250 } 251 252 /** 253 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 254 * @ha: HA context 255 * @hardware_locked: Called with the hardware_lock 256 */ 257 void 258 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 259 { 260 int rval; 261 uint32_t cnt, timer; 262 uint32_t risc_address; 263 uint16_t mb0, mb2; 264 265 uint32_t stat; 266 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 267 uint16_t __iomem *dmp_reg; 268 unsigned long flags; 269 struct qla2300_fw_dump *fw; 270 uint32_t data_ram_cnt; 271 272 risc_address = data_ram_cnt = 0; 273 mb0 = mb2 = 0; 274 flags = 0; 275 276 if (!hardware_locked) 277 spin_lock_irqsave(&ha->hardware_lock, flags); 278 279 if (!ha->fw_dump) { 280 qla_printk(KERN_WARNING, ha, 281 "No buffer available for dump!!!\n"); 282 goto qla2300_fw_dump_failed; 283 } 284 285 if (ha->fw_dumped) { 286 qla_printk(KERN_WARNING, ha, 287 "Firmware has been previously dumped (%p) -- ignoring " 288 "request...\n", ha->fw_dump); 289 goto qla2300_fw_dump_failed; 290 } 291 fw = &ha->fw_dump->isp.isp23; 292 qla2xxx_prep_dump(ha, ha->fw_dump); 293 294 rval = QLA_SUCCESS; 295 fw->hccr = htons(RD_REG_WORD(®->hccr)); 296 297 /* Pause RISC. */ 298 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 299 if (IS_QLA2300(ha)) { 300 for (cnt = 30000; 301 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 302 rval == QLA_SUCCESS; cnt--) { 303 if (cnt) 304 udelay(100); 305 else 306 rval = QLA_FUNCTION_TIMEOUT; 307 } 308 } else { 309 RD_REG_WORD(®->hccr); /* PCI Posting. */ 310 udelay(10); 311 } 312 313 if (rval == QLA_SUCCESS) { 314 dmp_reg = ®->flash_address; 315 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 316 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 317 318 dmp_reg = ®->u.isp2300.req_q_in; 319 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 320 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 321 322 dmp_reg = ®->u.isp2300.mailbox0; 323 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 324 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 325 326 WRT_REG_WORD(®->ctrl_status, 0x40); 327 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 328 329 WRT_REG_WORD(®->ctrl_status, 0x50); 330 qla2xxx_read_window(reg, 48, fw->dma_reg); 331 332 WRT_REG_WORD(®->ctrl_status, 0x00); 333 dmp_reg = ®->risc_hw; 334 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 335 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 336 337 WRT_REG_WORD(®->pcr, 0x2000); 338 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 339 340 WRT_REG_WORD(®->pcr, 0x2200); 341 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 342 343 WRT_REG_WORD(®->pcr, 0x2400); 344 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 345 346 WRT_REG_WORD(®->pcr, 0x2600); 347 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 348 349 WRT_REG_WORD(®->pcr, 0x2800); 350 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 351 352 WRT_REG_WORD(®->pcr, 0x2A00); 353 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 354 355 WRT_REG_WORD(®->pcr, 0x2C00); 356 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 357 358 WRT_REG_WORD(®->pcr, 0x2E00); 359 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 360 361 WRT_REG_WORD(®->ctrl_status, 0x10); 362 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 363 364 WRT_REG_WORD(®->ctrl_status, 0x20); 365 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 366 367 WRT_REG_WORD(®->ctrl_status, 0x30); 368 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 369 370 /* Reset RISC. */ 371 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 372 for (cnt = 0; cnt < 30000; cnt++) { 373 if ((RD_REG_WORD(®->ctrl_status) & 374 CSR_ISP_SOFT_RESET) == 0) 375 break; 376 377 udelay(10); 378 } 379 } 380 381 if (!IS_QLA2300(ha)) { 382 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 383 rval == QLA_SUCCESS; cnt--) { 384 if (cnt) 385 udelay(100); 386 else 387 rval = QLA_FUNCTION_TIMEOUT; 388 } 389 } 390 391 if (rval == QLA_SUCCESS) { 392 /* Get RISC SRAM. */ 393 risc_address = 0x800; 394 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 395 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 396 } 397 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 398 cnt++, risc_address++) { 399 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address); 400 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 401 402 for (timer = 6000000; timer; timer--) { 403 /* Check for pending interrupts. */ 404 stat = RD_REG_DWORD(®->u.isp2300.host_status); 405 if (stat & HSR_RISC_INT) { 406 stat &= 0xff; 407 408 if (stat == 0x1 || stat == 0x2) { 409 set_bit(MBX_INTERRUPT, 410 &ha->mbx_cmd_flags); 411 412 mb0 = RD_MAILBOX_REG(ha, reg, 0); 413 mb2 = RD_MAILBOX_REG(ha, reg, 2); 414 415 /* Release mailbox registers. */ 416 WRT_REG_WORD(®->semaphore, 0); 417 WRT_REG_WORD(®->hccr, 418 HCCR_CLR_RISC_INT); 419 RD_REG_WORD(®->hccr); 420 break; 421 } else if (stat == 0x10 || stat == 0x11) { 422 set_bit(MBX_INTERRUPT, 423 &ha->mbx_cmd_flags); 424 425 mb0 = RD_MAILBOX_REG(ha, reg, 0); 426 mb2 = RD_MAILBOX_REG(ha, reg, 2); 427 428 WRT_REG_WORD(®->hccr, 429 HCCR_CLR_RISC_INT); 430 RD_REG_WORD(®->hccr); 431 break; 432 } 433 434 /* clear this intr; it wasn't a mailbox intr */ 435 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 436 RD_REG_WORD(®->hccr); 437 } 438 udelay(5); 439 } 440 441 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 442 rval = mb0 & MBS_MASK; 443 fw->risc_ram[cnt] = htons(mb2); 444 } else { 445 rval = QLA_FUNCTION_FAILED; 446 } 447 } 448 449 if (rval == QLA_SUCCESS) { 450 /* Get stack SRAM. */ 451 risc_address = 0x10000; 452 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED); 453 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 454 } 455 for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS; 456 cnt++, risc_address++) { 457 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address)); 458 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address)); 459 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 460 461 for (timer = 6000000; timer; timer--) { 462 /* Check for pending interrupts. */ 463 stat = RD_REG_DWORD(®->u.isp2300.host_status); 464 if (stat & HSR_RISC_INT) { 465 stat &= 0xff; 466 467 if (stat == 0x1 || stat == 0x2) { 468 set_bit(MBX_INTERRUPT, 469 &ha->mbx_cmd_flags); 470 471 mb0 = RD_MAILBOX_REG(ha, reg, 0); 472 mb2 = RD_MAILBOX_REG(ha, reg, 2); 473 474 /* Release mailbox registers. */ 475 WRT_REG_WORD(®->semaphore, 0); 476 WRT_REG_WORD(®->hccr, 477 HCCR_CLR_RISC_INT); 478 RD_REG_WORD(®->hccr); 479 break; 480 } else if (stat == 0x10 || stat == 0x11) { 481 set_bit(MBX_INTERRUPT, 482 &ha->mbx_cmd_flags); 483 484 mb0 = RD_MAILBOX_REG(ha, reg, 0); 485 mb2 = RD_MAILBOX_REG(ha, reg, 2); 486 487 WRT_REG_WORD(®->hccr, 488 HCCR_CLR_RISC_INT); 489 RD_REG_WORD(®->hccr); 490 break; 491 } 492 493 /* clear this intr; it wasn't a mailbox intr */ 494 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 495 RD_REG_WORD(®->hccr); 496 } 497 udelay(5); 498 } 499 500 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 501 rval = mb0 & MBS_MASK; 502 fw->stack_ram[cnt] = htons(mb2); 503 } else { 504 rval = QLA_FUNCTION_FAILED; 505 } 506 } 507 508 if (rval == QLA_SUCCESS) { 509 /* Get data SRAM. */ 510 risc_address = 0x11000; 511 data_ram_cnt = ha->fw_memory_size - risc_address + 1; 512 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED); 513 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 514 } 515 for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS; 516 cnt++, risc_address++) { 517 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address)); 518 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address)); 519 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 520 521 for (timer = 6000000; timer; timer--) { 522 /* Check for pending interrupts. */ 523 stat = RD_REG_DWORD(®->u.isp2300.host_status); 524 if (stat & HSR_RISC_INT) { 525 stat &= 0xff; 526 527 if (stat == 0x1 || stat == 0x2) { 528 set_bit(MBX_INTERRUPT, 529 &ha->mbx_cmd_flags); 530 531 mb0 = RD_MAILBOX_REG(ha, reg, 0); 532 mb2 = RD_MAILBOX_REG(ha, reg, 2); 533 534 /* Release mailbox registers. */ 535 WRT_REG_WORD(®->semaphore, 0); 536 WRT_REG_WORD(®->hccr, 537 HCCR_CLR_RISC_INT); 538 RD_REG_WORD(®->hccr); 539 break; 540 } else if (stat == 0x10 || stat == 0x11) { 541 set_bit(MBX_INTERRUPT, 542 &ha->mbx_cmd_flags); 543 544 mb0 = RD_MAILBOX_REG(ha, reg, 0); 545 mb2 = RD_MAILBOX_REG(ha, reg, 2); 546 547 WRT_REG_WORD(®->hccr, 548 HCCR_CLR_RISC_INT); 549 RD_REG_WORD(®->hccr); 550 break; 551 } 552 553 /* clear this intr; it wasn't a mailbox intr */ 554 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 555 RD_REG_WORD(®->hccr); 556 } 557 udelay(5); 558 } 559 560 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 561 rval = mb0 & MBS_MASK; 562 fw->data_ram[cnt] = htons(mb2); 563 } else { 564 rval = QLA_FUNCTION_FAILED; 565 } 566 } 567 568 if (rval == QLA_SUCCESS) 569 qla2xxx_copy_queues(ha, &fw->data_ram[cnt]); 570 571 if (rval != QLA_SUCCESS) { 572 qla_printk(KERN_WARNING, ha, 573 "Failed to dump firmware (%x)!!!\n", rval); 574 ha->fw_dumped = 0; 575 576 } else { 577 qla_printk(KERN_INFO, ha, 578 "Firmware dump saved to temp buffer (%ld/%p).\n", 579 ha->host_no, ha->fw_dump); 580 ha->fw_dumped = 1; 581 } 582 583 qla2300_fw_dump_failed: 584 if (!hardware_locked) 585 spin_unlock_irqrestore(&ha->hardware_lock, flags); 586 } 587 588 /** 589 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 590 * @ha: HA context 591 * @hardware_locked: Called with the hardware_lock 592 */ 593 void 594 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 595 { 596 int rval; 597 uint32_t cnt, timer; 598 uint16_t risc_address; 599 uint16_t mb0, mb2; 600 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 601 uint16_t __iomem *dmp_reg; 602 unsigned long flags; 603 struct qla2100_fw_dump *fw; 604 605 risc_address = 0; 606 mb0 = mb2 = 0; 607 flags = 0; 608 609 if (!hardware_locked) 610 spin_lock_irqsave(&ha->hardware_lock, flags); 611 612 if (!ha->fw_dump) { 613 qla_printk(KERN_WARNING, ha, 614 "No buffer available for dump!!!\n"); 615 goto qla2100_fw_dump_failed; 616 } 617 618 if (ha->fw_dumped) { 619 qla_printk(KERN_WARNING, ha, 620 "Firmware has been previously dumped (%p) -- ignoring " 621 "request...\n", ha->fw_dump); 622 goto qla2100_fw_dump_failed; 623 } 624 fw = &ha->fw_dump->isp.isp21; 625 qla2xxx_prep_dump(ha, ha->fw_dump); 626 627 rval = QLA_SUCCESS; 628 fw->hccr = htons(RD_REG_WORD(®->hccr)); 629 630 /* Pause RISC. */ 631 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 632 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 633 rval == QLA_SUCCESS; cnt--) { 634 if (cnt) 635 udelay(100); 636 else 637 rval = QLA_FUNCTION_TIMEOUT; 638 } 639 if (rval == QLA_SUCCESS) { 640 dmp_reg = ®->flash_address; 641 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 642 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 643 644 dmp_reg = ®->u.isp2100.mailbox0; 645 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 646 if (cnt == 8) 647 dmp_reg = ®->u_end.isp2200.mailbox8; 648 649 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 650 } 651 652 dmp_reg = ®->u.isp2100.unused_2[0]; 653 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 654 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 655 656 WRT_REG_WORD(®->ctrl_status, 0x00); 657 dmp_reg = ®->risc_hw; 658 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 659 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 660 661 WRT_REG_WORD(®->pcr, 0x2000); 662 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 663 664 WRT_REG_WORD(®->pcr, 0x2100); 665 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 666 667 WRT_REG_WORD(®->pcr, 0x2200); 668 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 669 670 WRT_REG_WORD(®->pcr, 0x2300); 671 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 672 673 WRT_REG_WORD(®->pcr, 0x2400); 674 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 675 676 WRT_REG_WORD(®->pcr, 0x2500); 677 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 678 679 WRT_REG_WORD(®->pcr, 0x2600); 680 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 681 682 WRT_REG_WORD(®->pcr, 0x2700); 683 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 684 685 WRT_REG_WORD(®->ctrl_status, 0x10); 686 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 687 688 WRT_REG_WORD(®->ctrl_status, 0x20); 689 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 690 691 WRT_REG_WORD(®->ctrl_status, 0x30); 692 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 693 694 /* Reset the ISP. */ 695 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 696 } 697 698 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 699 rval == QLA_SUCCESS; cnt--) { 700 if (cnt) 701 udelay(100); 702 else 703 rval = QLA_FUNCTION_TIMEOUT; 704 } 705 706 /* Pause RISC. */ 707 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 708 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 709 710 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 711 for (cnt = 30000; 712 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 713 rval == QLA_SUCCESS; cnt--) { 714 if (cnt) 715 udelay(100); 716 else 717 rval = QLA_FUNCTION_TIMEOUT; 718 } 719 if (rval == QLA_SUCCESS) { 720 /* Set memory configuration and timing. */ 721 if (IS_QLA2100(ha)) 722 WRT_REG_WORD(®->mctr, 0xf1); 723 else 724 WRT_REG_WORD(®->mctr, 0xf2); 725 RD_REG_WORD(®->mctr); /* PCI Posting. */ 726 727 /* Release RISC. */ 728 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 729 } 730 } 731 732 if (rval == QLA_SUCCESS) { 733 /* Get RISC SRAM. */ 734 risc_address = 0x1000; 735 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 736 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 737 } 738 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 739 cnt++, risc_address++) { 740 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 741 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 742 743 for (timer = 6000000; timer != 0; timer--) { 744 /* Check for pending interrupts. */ 745 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { 746 if (RD_REG_WORD(®->semaphore) & BIT_0) { 747 set_bit(MBX_INTERRUPT, 748 &ha->mbx_cmd_flags); 749 750 mb0 = RD_MAILBOX_REG(ha, reg, 0); 751 mb2 = RD_MAILBOX_REG(ha, reg, 2); 752 753 WRT_REG_WORD(®->semaphore, 0); 754 WRT_REG_WORD(®->hccr, 755 HCCR_CLR_RISC_INT); 756 RD_REG_WORD(®->hccr); 757 break; 758 } 759 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 760 RD_REG_WORD(®->hccr); 761 } 762 udelay(5); 763 } 764 765 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 766 rval = mb0 & MBS_MASK; 767 fw->risc_ram[cnt] = htons(mb2); 768 } else { 769 rval = QLA_FUNCTION_FAILED; 770 } 771 } 772 773 if (rval == QLA_SUCCESS) 774 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 775 776 if (rval != QLA_SUCCESS) { 777 qla_printk(KERN_WARNING, ha, 778 "Failed to dump firmware (%x)!!!\n", rval); 779 ha->fw_dumped = 0; 780 781 } else { 782 qla_printk(KERN_INFO, ha, 783 "Firmware dump saved to temp buffer (%ld/%p).\n", 784 ha->host_no, ha->fw_dump); 785 ha->fw_dumped = 1; 786 } 787 788 qla2100_fw_dump_failed: 789 if (!hardware_locked) 790 spin_unlock_irqrestore(&ha->hardware_lock, flags); 791 } 792 793 void 794 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 795 { 796 int rval; 797 uint32_t cnt; 798 uint32_t risc_address; 799 800 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 801 uint32_t __iomem *dmp_reg; 802 uint32_t *iter_reg; 803 uint16_t __iomem *mbx_reg; 804 unsigned long flags; 805 struct qla24xx_fw_dump *fw; 806 uint32_t ext_mem_cnt; 807 void *nxt; 808 809 risc_address = ext_mem_cnt = 0; 810 flags = 0; 811 812 if (!hardware_locked) 813 spin_lock_irqsave(&ha->hardware_lock, flags); 814 815 if (!ha->fw_dump) { 816 qla_printk(KERN_WARNING, ha, 817 "No buffer available for dump!!!\n"); 818 goto qla24xx_fw_dump_failed; 819 } 820 821 if (ha->fw_dumped) { 822 qla_printk(KERN_WARNING, ha, 823 "Firmware has been previously dumped (%p) -- ignoring " 824 "request...\n", ha->fw_dump); 825 goto qla24xx_fw_dump_failed; 826 } 827 fw = &ha->fw_dump->isp.isp24; 828 qla2xxx_prep_dump(ha, ha->fw_dump); 829 830 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 831 832 /* Pause RISC. */ 833 rval = qla24xx_pause_risc(reg); 834 if (rval != QLA_SUCCESS) 835 goto qla24xx_fw_dump_failed_0; 836 837 /* Host interface registers. */ 838 dmp_reg = ®->flash_addr; 839 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 840 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 841 842 /* Disable interrupts. */ 843 WRT_REG_DWORD(®->ictrl, 0); 844 RD_REG_DWORD(®->ictrl); 845 846 /* Shadow registers. */ 847 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 848 RD_REG_DWORD(®->iobase_addr); 849 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 850 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 851 852 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 853 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 854 855 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 856 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 857 858 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 859 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 860 861 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 862 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 863 864 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 865 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 866 867 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 868 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 869 870 /* Mailbox registers. */ 871 mbx_reg = ®->mailbox0; 872 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 873 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 874 875 /* Transfer sequence registers. */ 876 iter_reg = fw->xseq_gp_reg; 877 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 878 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 879 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 880 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 881 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 882 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 883 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 884 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 885 886 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 887 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 888 889 /* Receive sequence registers. */ 890 iter_reg = fw->rseq_gp_reg; 891 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 892 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 893 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 894 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 895 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 896 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 897 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 898 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 899 900 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 901 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 902 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 903 904 /* Command DMA registers. */ 905 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 906 907 /* Queues. */ 908 iter_reg = fw->req0_dma_reg; 909 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 910 dmp_reg = ®->iobase_q; 911 for (cnt = 0; cnt < 7; cnt++) 912 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 913 914 iter_reg = fw->resp0_dma_reg; 915 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 916 dmp_reg = ®->iobase_q; 917 for (cnt = 0; cnt < 7; cnt++) 918 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 919 920 iter_reg = fw->req1_dma_reg; 921 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 922 dmp_reg = ®->iobase_q; 923 for (cnt = 0; cnt < 7; cnt++) 924 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 925 926 /* Transmit DMA registers. */ 927 iter_reg = fw->xmt0_dma_reg; 928 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 929 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 930 931 iter_reg = fw->xmt1_dma_reg; 932 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 933 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 934 935 iter_reg = fw->xmt2_dma_reg; 936 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 937 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 938 939 iter_reg = fw->xmt3_dma_reg; 940 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 941 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 942 943 iter_reg = fw->xmt4_dma_reg; 944 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 945 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 946 947 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 948 949 /* Receive DMA registers. */ 950 iter_reg = fw->rcvt0_data_dma_reg; 951 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 952 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 953 954 iter_reg = fw->rcvt1_data_dma_reg; 955 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 956 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 957 958 /* RISC registers. */ 959 iter_reg = fw->risc_gp_reg; 960 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 961 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 962 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 963 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 964 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 965 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 966 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 967 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 968 969 /* Local memory controller registers. */ 970 iter_reg = fw->lmc_reg; 971 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 972 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 973 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 974 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 975 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 976 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 977 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 978 979 /* Fibre Protocol Module registers. */ 980 iter_reg = fw->fpm_hdw_reg; 981 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 982 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 983 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 984 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 985 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 986 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 987 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 988 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 989 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 990 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 991 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 992 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 993 994 /* Frame Buffer registers. */ 995 iter_reg = fw->fb_hdw_reg; 996 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 997 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 998 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 999 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1000 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1001 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1002 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1003 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1004 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1005 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1006 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1007 1008 rval = qla24xx_soft_reset(ha); 1009 if (rval != QLA_SUCCESS) 1010 goto qla24xx_fw_dump_failed_0; 1011 1012 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1013 fw->ext_mem, &nxt); 1014 if (rval != QLA_SUCCESS) 1015 goto qla24xx_fw_dump_failed_0; 1016 1017 nxt = qla2xxx_copy_queues(ha, nxt); 1018 if (ha->eft) 1019 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); 1020 1021 qla24xx_fw_dump_failed_0: 1022 if (rval != QLA_SUCCESS) { 1023 qla_printk(KERN_WARNING, ha, 1024 "Failed to dump firmware (%x)!!!\n", rval); 1025 ha->fw_dumped = 0; 1026 1027 } else { 1028 qla_printk(KERN_INFO, ha, 1029 "Firmware dump saved to temp buffer (%ld/%p).\n", 1030 ha->host_no, ha->fw_dump); 1031 ha->fw_dumped = 1; 1032 } 1033 1034 qla24xx_fw_dump_failed: 1035 if (!hardware_locked) 1036 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1037 } 1038 1039 void 1040 qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 1041 { 1042 int rval; 1043 uint32_t cnt; 1044 uint32_t risc_address; 1045 1046 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1047 uint32_t __iomem *dmp_reg; 1048 uint32_t *iter_reg; 1049 uint16_t __iomem *mbx_reg; 1050 unsigned long flags; 1051 struct qla25xx_fw_dump *fw; 1052 uint32_t ext_mem_cnt; 1053 void *nxt; 1054 1055 risc_address = ext_mem_cnt = 0; 1056 flags = 0; 1057 1058 if (!hardware_locked) 1059 spin_lock_irqsave(&ha->hardware_lock, flags); 1060 1061 if (!ha->fw_dump) { 1062 qla_printk(KERN_WARNING, ha, 1063 "No buffer available for dump!!!\n"); 1064 goto qla25xx_fw_dump_failed; 1065 } 1066 1067 if (ha->fw_dumped) { 1068 qla_printk(KERN_WARNING, ha, 1069 "Firmware has been previously dumped (%p) -- ignoring " 1070 "request...\n", ha->fw_dump); 1071 goto qla25xx_fw_dump_failed; 1072 } 1073 fw = &ha->fw_dump->isp.isp25; 1074 qla2xxx_prep_dump(ha, ha->fw_dump); 1075 ha->fw_dump->version = __constant_htonl(2); 1076 1077 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1078 1079 /* Pause RISC. */ 1080 rval = qla24xx_pause_risc(reg); 1081 if (rval != QLA_SUCCESS) 1082 goto qla25xx_fw_dump_failed_0; 1083 1084 /* Host/Risc registers. */ 1085 iter_reg = fw->host_risc_reg; 1086 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1087 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1088 1089 /* PCIe registers. */ 1090 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1091 RD_REG_DWORD(®->iobase_addr); 1092 WRT_REG_DWORD(®->iobase_window, 0x01); 1093 dmp_reg = ®->iobase_c4; 1094 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1095 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1096 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1097 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1098 WRT_REG_DWORD(®->iobase_window, 0x00); 1099 RD_REG_DWORD(®->iobase_window); 1100 1101 /* Host interface registers. */ 1102 dmp_reg = ®->flash_addr; 1103 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1104 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1105 1106 /* Disable interrupts. */ 1107 WRT_REG_DWORD(®->ictrl, 0); 1108 RD_REG_DWORD(®->ictrl); 1109 1110 /* Shadow registers. */ 1111 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1112 RD_REG_DWORD(®->iobase_addr); 1113 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1114 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1115 1116 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1117 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1118 1119 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1120 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1121 1122 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1123 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1124 1125 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1126 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1127 1128 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1129 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1130 1131 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1132 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1133 1134 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1135 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1136 1137 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1138 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1139 1140 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1141 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1142 1143 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1144 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1145 1146 /* RISC I/O register. */ 1147 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1148 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1149 1150 /* Mailbox registers. */ 1151 mbx_reg = ®->mailbox0; 1152 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1153 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1154 1155 /* Transfer sequence registers. */ 1156 iter_reg = fw->xseq_gp_reg; 1157 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1158 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1159 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1160 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1161 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1162 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1163 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1164 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1165 1166 iter_reg = fw->xseq_0_reg; 1167 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1168 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1169 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1170 1171 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1172 1173 /* Receive sequence registers. */ 1174 iter_reg = fw->rseq_gp_reg; 1175 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1176 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1177 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1178 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1179 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1180 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1181 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1182 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1183 1184 iter_reg = fw->rseq_0_reg; 1185 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1186 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1187 1188 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1189 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1190 1191 /* Auxiliary sequence registers. */ 1192 iter_reg = fw->aseq_gp_reg; 1193 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1194 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1195 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1196 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1197 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1198 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1199 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1200 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1201 1202 iter_reg = fw->aseq_0_reg; 1203 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1204 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1205 1206 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1207 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1208 1209 /* Command DMA registers. */ 1210 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1211 1212 /* Queues. */ 1213 iter_reg = fw->req0_dma_reg; 1214 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1215 dmp_reg = ®->iobase_q; 1216 for (cnt = 0; cnt < 7; cnt++) 1217 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1218 1219 iter_reg = fw->resp0_dma_reg; 1220 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1221 dmp_reg = ®->iobase_q; 1222 for (cnt = 0; cnt < 7; cnt++) 1223 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1224 1225 iter_reg = fw->req1_dma_reg; 1226 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1227 dmp_reg = ®->iobase_q; 1228 for (cnt = 0; cnt < 7; cnt++) 1229 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1230 1231 /* Transmit DMA registers. */ 1232 iter_reg = fw->xmt0_dma_reg; 1233 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1234 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1235 1236 iter_reg = fw->xmt1_dma_reg; 1237 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1238 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1239 1240 iter_reg = fw->xmt2_dma_reg; 1241 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1242 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1243 1244 iter_reg = fw->xmt3_dma_reg; 1245 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1246 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1247 1248 iter_reg = fw->xmt4_dma_reg; 1249 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1250 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1251 1252 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1253 1254 /* Receive DMA registers. */ 1255 iter_reg = fw->rcvt0_data_dma_reg; 1256 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1257 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1258 1259 iter_reg = fw->rcvt1_data_dma_reg; 1260 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1261 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1262 1263 /* RISC registers. */ 1264 iter_reg = fw->risc_gp_reg; 1265 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1266 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1267 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1268 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1269 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1270 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1271 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1272 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1273 1274 /* Local memory controller registers. */ 1275 iter_reg = fw->lmc_reg; 1276 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1277 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1278 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1279 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1280 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1281 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1282 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1283 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1284 1285 /* Fibre Protocol Module registers. */ 1286 iter_reg = fw->fpm_hdw_reg; 1287 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1288 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1289 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1290 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1291 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1292 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1293 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1294 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1295 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1296 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1297 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1298 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1299 1300 /* Frame Buffer registers. */ 1301 iter_reg = fw->fb_hdw_reg; 1302 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1303 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1304 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1305 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1306 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1307 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1308 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1309 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1310 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1311 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1312 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1313 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1314 1315 rval = qla24xx_soft_reset(ha); 1316 if (rval != QLA_SUCCESS) 1317 goto qla25xx_fw_dump_failed_0; 1318 1319 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1320 fw->ext_mem, &nxt); 1321 if (rval != QLA_SUCCESS) 1322 goto qla25xx_fw_dump_failed_0; 1323 1324 nxt = qla2xxx_copy_queues(ha, nxt); 1325 if (ha->eft) 1326 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); 1327 1328 qla25xx_fw_dump_failed_0: 1329 if (rval != QLA_SUCCESS) { 1330 qla_printk(KERN_WARNING, ha, 1331 "Failed to dump firmware (%x)!!!\n", rval); 1332 ha->fw_dumped = 0; 1333 1334 } else { 1335 qla_printk(KERN_INFO, ha, 1336 "Firmware dump saved to temp buffer (%ld/%p).\n", 1337 ha->host_no, ha->fw_dump); 1338 ha->fw_dumped = 1; 1339 } 1340 1341 qla25xx_fw_dump_failed: 1342 if (!hardware_locked) 1343 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1344 } 1345 1346 /****************************************************************************/ 1347 /* Driver Debug Functions. */ 1348 /****************************************************************************/ 1349 1350 void 1351 qla2x00_dump_regs(scsi_qla_host_t *ha) 1352 { 1353 int i; 1354 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1355 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 1356 uint16_t __iomem *mbx_reg; 1357 1358 mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0: 1359 MAILBOX_REG(ha, reg, 0); 1360 1361 printk("Mailbox registers:\n"); 1362 for (i = 0; i < 6; i++) 1363 printk("scsi(%ld): mbox %d 0x%04x \n", ha->host_no, i, 1364 RD_REG_WORD(mbx_reg++)); 1365 } 1366 1367 1368 void 1369 qla2x00_dump_buffer(uint8_t * b, uint32_t size) 1370 { 1371 uint32_t cnt; 1372 uint8_t c; 1373 1374 printk(" 0 1 2 3 4 5 6 7 8 9 " 1375 "Ah Bh Ch Dh Eh Fh\n"); 1376 printk("----------------------------------------" 1377 "----------------------\n"); 1378 1379 for (cnt = 0; cnt < size;) { 1380 c = *b++; 1381 printk("%02x",(uint32_t) c); 1382 cnt++; 1383 if (!(cnt % 16)) 1384 printk("\n"); 1385 else 1386 printk(" "); 1387 } 1388 if (cnt % 16) 1389 printk("\n"); 1390 } 1391 1392 /************************************************************************** 1393 * qla2x00_print_scsi_cmd 1394 * Dumps out info about the scsi cmd and srb. 1395 * Input 1396 * cmd : struct scsi_cmnd 1397 **************************************************************************/ 1398 void 1399 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) 1400 { 1401 int i; 1402 struct scsi_qla_host *ha; 1403 srb_t *sp; 1404 1405 ha = shost_priv(cmd->device->host); 1406 1407 sp = (srb_t *) cmd->SCp.ptr; 1408 printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble); 1409 printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n", 1410 cmd->device->channel, cmd->device->id, cmd->device->lun, 1411 cmd->cmd_len); 1412 printk(" CDB: "); 1413 for (i = 0; i < cmd->cmd_len; i++) { 1414 printk("0x%02x ", cmd->cmnd[i]); 1415 } 1416 printk("\n seg_cnt=%d, allowed=%d, retries=%d\n", 1417 scsi_sg_count(cmd), cmd->allowed, cmd->retries); 1418 printk(" request buffer=0x%p, request buffer len=0x%x\n", 1419 scsi_sglist(cmd), scsi_bufflen(cmd)); 1420 printk(" tag=%d, transfersize=0x%x\n", 1421 cmd->tag, cmd->transfersize); 1422 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp); 1423 printk(" data direction=%d\n", cmd->sc_data_direction); 1424 1425 if (!sp) 1426 return; 1427 1428 printk(" sp flags=0x%x\n", sp->flags); 1429 } 1430 1431 void 1432 qla2x00_dump_pkt(void *pkt) 1433 { 1434 uint32_t i; 1435 uint8_t *data = (uint8_t *) pkt; 1436 1437 for (i = 0; i < 64; i++) { 1438 if (!(i % 4)) 1439 printk("\n%02x: ", i); 1440 1441 printk("%02x ", data[i]); 1442 } 1443 printk("\n"); 1444 } 1445 1446 #if defined(QL_DEBUG_ROUTINES) 1447 /* 1448 * qla2x00_formatted_dump_buffer 1449 * Prints string plus buffer. 1450 * 1451 * Input: 1452 * string = Null terminated string (no newline at end). 1453 * buffer = buffer address. 1454 * wd_size = word size 8, 16, 32 or 64 bits 1455 * count = number of words. 1456 */ 1457 void 1458 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer, 1459 uint8_t wd_size, uint32_t count) 1460 { 1461 uint32_t cnt; 1462 uint16_t *buf16; 1463 uint32_t *buf32; 1464 1465 if (strcmp(string, "") != 0) 1466 printk("%s\n",string); 1467 1468 switch (wd_size) { 1469 case 8: 1470 printk(" 0 1 2 3 4 5 6 7 " 1471 "8 9 Ah Bh Ch Dh Eh Fh\n"); 1472 printk("-----------------------------------------" 1473 "-------------------------------------\n"); 1474 1475 for (cnt = 1; cnt <= count; cnt++, buffer++) { 1476 printk("%02x",*buffer); 1477 if (cnt % 16 == 0) 1478 printk("\n"); 1479 else 1480 printk(" "); 1481 } 1482 if (cnt % 16 != 0) 1483 printk("\n"); 1484 break; 1485 case 16: 1486 printk(" 0 2 4 6 8 Ah " 1487 " Ch Eh\n"); 1488 printk("-----------------------------------------" 1489 "-------------\n"); 1490 1491 buf16 = (uint16_t *) buffer; 1492 for (cnt = 1; cnt <= count; cnt++, buf16++) { 1493 printk("%4x",*buf16); 1494 1495 if (cnt % 8 == 0) 1496 printk("\n"); 1497 else if (*buf16 < 10) 1498 printk(" "); 1499 else 1500 printk(" "); 1501 } 1502 if (cnt % 8 != 0) 1503 printk("\n"); 1504 break; 1505 case 32: 1506 printk(" 0 4 8 Ch\n"); 1507 printk("------------------------------------------\n"); 1508 1509 buf32 = (uint32_t *) buffer; 1510 for (cnt = 1; cnt <= count; cnt++, buf32++) { 1511 printk("%8x", *buf32); 1512 1513 if (cnt % 4 == 0) 1514 printk("\n"); 1515 else if (*buf32 < 10) 1516 printk(" "); 1517 else 1518 printk(" "); 1519 } 1520 if (cnt % 4 != 0) 1521 printk("\n"); 1522 break; 1523 default: 1524 break; 1525 } 1526 } 1527 #endif 1528