1 /* 2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware) 3 * bus adaptor found on Power Macintosh computers. 4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA) 5 * controller. 6 * 7 * Paul Mackerras, August 1996. 8 * Copyright (C) 1996 Paul Mackerras. 9 * 10 * Apr. 21 2002 - BenH Rework bus reset code for new error handler 11 * Add delay after initial bus reset 12 * Add module parameters 13 * 14 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting 15 * issues 16 * To do: 17 * - handle aborts correctly 18 * - retry arbitration if lost (unless higher levels do this for us) 19 * - power down the chip when no device is detected 20 */ 21 #include <linux/module.h> 22 #include <linux/kernel.h> 23 #include <linux/delay.h> 24 #include <linux/types.h> 25 #include <linux/string.h> 26 #include <linux/slab.h> 27 #include <linux/blkdev.h> 28 #include <linux/proc_fs.h> 29 #include <linux/stat.h> 30 #include <linux/interrupt.h> 31 #include <linux/reboot.h> 32 #include <linux/spinlock.h> 33 #include <asm/dbdma.h> 34 #include <asm/io.h> 35 #include <asm/pgtable.h> 36 #include <asm/prom.h> 37 #include <asm/system.h> 38 #include <asm/irq.h> 39 #include <asm/hydra.h> 40 #include <asm/processor.h> 41 #include <asm/machdep.h> 42 #include <asm/pmac_feature.h> 43 #include <asm/pci-bridge.h> 44 #include <asm/macio.h> 45 46 #include <scsi/scsi.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <scsi/scsi_device.h> 49 #include <scsi/scsi_host.h> 50 51 #include "mesh.h" 52 53 #if 1 54 #undef KERN_DEBUG 55 #define KERN_DEBUG KERN_WARNING 56 #endif 57 58 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)"); 59 MODULE_DESCRIPTION("PowerMac MESH SCSI driver"); 60 MODULE_LICENSE("GPL"); 61 62 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE; 63 static int sync_targets = 0xff; 64 static int resel_targets = 0xff; 65 static int debug_targets = 0; /* print debug for these targets */ 66 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS; 67 68 module_param(sync_rate, int, 0); 69 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)"); 70 module_param(sync_targets, int, 0); 71 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous"); 72 module_param(resel_targets, int, 0); 73 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect"); 74 module_param(debug_targets, int, 0644); 75 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets"); 76 module_param(init_reset_delay, int, 0); 77 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)"); 78 79 static int mesh_sync_period = 100; 80 static int mesh_sync_offset = 0; 81 static unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */ 82 83 #define ALLOW_SYNC(tgt) ((sync_targets >> (tgt)) & 1) 84 #define ALLOW_RESEL(tgt) ((resel_targets >> (tgt)) & 1) 85 #define ALLOW_DEBUG(tgt) ((debug_targets >> (tgt)) & 1) 86 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id)) 87 88 #undef MESH_DBG 89 #define N_DBG_LOG 50 90 #define N_DBG_SLOG 20 91 #define NUM_DBG_EVENTS 13 92 #undef DBG_USE_TB /* bombs on 601 */ 93 94 struct dbglog { 95 char *fmt; 96 u32 tb; 97 u8 phase; 98 u8 bs0; 99 u8 bs1; 100 u8 tgt; 101 int d; 102 }; 103 104 enum mesh_phase { 105 idle, 106 arbitrating, 107 selecting, 108 commanding, 109 dataing, 110 statusing, 111 busfreeing, 112 disconnecting, 113 reselecting, 114 sleeping 115 }; 116 117 enum msg_phase { 118 msg_none, 119 msg_out, 120 msg_out_xxx, 121 msg_out_last, 122 msg_in, 123 msg_in_bad, 124 }; 125 126 enum sdtr_phase { 127 do_sdtr, 128 sdtr_sent, 129 sdtr_done 130 }; 131 132 struct mesh_target { 133 enum sdtr_phase sdtr_state; 134 int sync_params; 135 int data_goes_out; /* guess as to data direction */ 136 struct scsi_cmnd *current_req; 137 u32 saved_ptr; 138 #ifdef MESH_DBG 139 int log_ix; 140 int n_log; 141 struct dbglog log[N_DBG_LOG]; 142 #endif 143 }; 144 145 struct mesh_state { 146 volatile struct mesh_regs __iomem *mesh; 147 int meshintr; 148 volatile struct dbdma_regs __iomem *dma; 149 int dmaintr; 150 struct Scsi_Host *host; 151 struct mesh_state *next; 152 struct scsi_cmnd *request_q; 153 struct scsi_cmnd *request_qtail; 154 enum mesh_phase phase; /* what we're currently trying to do */ 155 enum msg_phase msgphase; 156 int conn_tgt; /* target we're connected to */ 157 struct scsi_cmnd *current_req; /* req we're currently working on */ 158 int data_ptr; 159 int dma_started; 160 int dma_count; 161 int stat; 162 int aborting; 163 int expect_reply; 164 int n_msgin; 165 u8 msgin[16]; 166 int n_msgout; 167 int last_n_msgout; 168 u8 msgout[16]; 169 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */ 170 dma_addr_t dma_cmd_bus; 171 void *dma_cmd_space; 172 int dma_cmd_size; 173 int clk_freq; 174 struct mesh_target tgts[8]; 175 struct macio_dev *mdev; 176 struct pci_dev* pdev; 177 #ifdef MESH_DBG 178 int log_ix; 179 int n_log; 180 struct dbglog log[N_DBG_SLOG]; 181 #endif 182 }; 183 184 /* 185 * Driver is too messy, we need a few prototypes... 186 */ 187 static void mesh_done(struct mesh_state *ms, int start_next); 188 static void mesh_interrupt(struct mesh_state *ms); 189 static void cmd_complete(struct mesh_state *ms); 190 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd); 191 static void halt_dma(struct mesh_state *ms); 192 static void phase_mismatch(struct mesh_state *ms); 193 194 195 /* 196 * Some debugging & logging routines 197 */ 198 199 #ifdef MESH_DBG 200 201 static inline u32 readtb(void) 202 { 203 u32 tb; 204 205 #ifdef DBG_USE_TB 206 /* Beware: if you enable this, it will crash on 601s. */ 207 asm ("mftb %0" : "=r" (tb) : ); 208 #else 209 tb = 0; 210 #endif 211 return tb; 212 } 213 214 static void dlog(struct mesh_state *ms, char *fmt, int a) 215 { 216 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 217 struct dbglog *tlp, *slp; 218 219 tlp = &tp->log[tp->log_ix]; 220 slp = &ms->log[ms->log_ix]; 221 tlp->fmt = fmt; 222 tlp->tb = readtb(); 223 tlp->phase = (ms->msgphase << 4) + ms->phase; 224 tlp->bs0 = ms->mesh->bus_status0; 225 tlp->bs1 = ms->mesh->bus_status1; 226 tlp->tgt = ms->conn_tgt; 227 tlp->d = a; 228 *slp = *tlp; 229 if (++tp->log_ix >= N_DBG_LOG) 230 tp->log_ix = 0; 231 if (tp->n_log < N_DBG_LOG) 232 ++tp->n_log; 233 if (++ms->log_ix >= N_DBG_SLOG) 234 ms->log_ix = 0; 235 if (ms->n_log < N_DBG_SLOG) 236 ++ms->n_log; 237 } 238 239 static void dumplog(struct mesh_state *ms, int t) 240 { 241 struct mesh_target *tp = &ms->tgts[t]; 242 struct dbglog *lp; 243 int i; 244 245 if (tp->n_log == 0) 246 return; 247 i = tp->log_ix - tp->n_log; 248 if (i < 0) 249 i += N_DBG_LOG; 250 tp->n_log = 0; 251 do { 252 lp = &tp->log[i]; 253 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ", 254 t, lp->bs1, lp->bs0, lp->phase); 255 #ifdef DBG_USE_TB 256 printk("tb=%10u ", lp->tb); 257 #endif 258 printk(lp->fmt, lp->d); 259 printk("\n"); 260 if (++i >= N_DBG_LOG) 261 i = 0; 262 } while (i != tp->log_ix); 263 } 264 265 static void dumpslog(struct mesh_state *ms) 266 { 267 struct dbglog *lp; 268 int i; 269 270 if (ms->n_log == 0) 271 return; 272 i = ms->log_ix - ms->n_log; 273 if (i < 0) 274 i += N_DBG_SLOG; 275 ms->n_log = 0; 276 do { 277 lp = &ms->log[i]; 278 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ", 279 lp->bs1, lp->bs0, lp->phase, lp->tgt); 280 #ifdef DBG_USE_TB 281 printk("tb=%10u ", lp->tb); 282 #endif 283 printk(lp->fmt, lp->d); 284 printk("\n"); 285 if (++i >= N_DBG_SLOG) 286 i = 0; 287 } while (i != ms->log_ix); 288 } 289 290 #else 291 292 static inline void dlog(struct mesh_state *ms, char *fmt, int a) 293 {} 294 static inline void dumplog(struct mesh_state *ms, int tgt) 295 {} 296 static inline void dumpslog(struct mesh_state *ms) 297 {} 298 299 #endif /* MESH_DBG */ 300 301 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d)) 302 303 static void 304 mesh_dump_regs(struct mesh_state *ms) 305 { 306 volatile struct mesh_regs __iomem *mr = ms->mesh; 307 volatile struct dbdma_regs __iomem *md = ms->dma; 308 int t; 309 struct mesh_target *tp; 310 311 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n", 312 ms, mr, md); 313 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x " 314 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n", 315 (mr->count_hi << 8) + mr->count_lo, mr->sequence, 316 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, 317 mr->exception, mr->error, mr->intr_mask, mr->interrupt, 318 mr->sync_params); 319 while(in_8(&mr->fifo_count)) 320 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); 321 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n", 322 in_le32(&md->status), in_le32(&md->cmdptr)); 323 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n", 324 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); 325 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n", 326 ms->dma_started, ms->dma_count, ms->n_msgout); 327 for (t = 0; t < 8; ++t) { 328 tp = &ms->tgts[t]; 329 if (tp->current_req == NULL) 330 continue; 331 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n", 332 t, tp->current_req, tp->data_goes_out, tp->saved_ptr); 333 } 334 } 335 336 337 /* 338 * Flush write buffers on the bus path to the mesh 339 */ 340 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr) 341 { 342 (void)in_8(&mr->mesh_id); 343 } 344 345 346 /* 347 * Complete a SCSI command 348 */ 349 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd) 350 { 351 (*cmd->scsi_done)(cmd); 352 } 353 354 355 /* Called with meshinterrupt disabled, initialize the chipset 356 * and eventually do the initial bus reset. The lock must not be 357 * held since we can schedule. 358 */ 359 static void mesh_init(struct mesh_state *ms) 360 { 361 volatile struct mesh_regs __iomem *mr = ms->mesh; 362 volatile struct dbdma_regs __iomem *md = ms->dma; 363 364 mesh_flush_io(mr); 365 udelay(100); 366 367 /* Reset controller */ 368 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ 369 out_8(&mr->exception, 0xff); /* clear all exception bits */ 370 out_8(&mr->error, 0xff); /* clear all error bits */ 371 out_8(&mr->sequence, SEQ_RESETMESH); 372 mesh_flush_io(mr); 373 udelay(10); 374 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 375 out_8(&mr->source_id, ms->host->this_id); 376 out_8(&mr->sel_timeout, 25); /* 250ms */ 377 out_8(&mr->sync_params, ASYNC_PARAMS); 378 379 if (init_reset_delay) { 380 printk(KERN_INFO "mesh: performing initial bus reset...\n"); 381 382 /* Reset bus */ 383 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ 384 mesh_flush_io(mr); 385 udelay(30); /* leave it on for >= 25us */ 386 out_8(&mr->bus_status1, 0); /* negate RST */ 387 mesh_flush_io(mr); 388 389 /* Wait for bus to come back */ 390 msleep(init_reset_delay); 391 } 392 393 /* Reconfigure controller */ 394 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ 395 out_8(&mr->sequence, SEQ_FLUSHFIFO); 396 mesh_flush_io(mr); 397 udelay(1); 398 out_8(&mr->sync_params, ASYNC_PARAMS); 399 out_8(&mr->sequence, SEQ_ENBRESEL); 400 401 ms->phase = idle; 402 ms->msgphase = msg_none; 403 } 404 405 406 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd) 407 { 408 volatile struct mesh_regs __iomem *mr = ms->mesh; 409 int t, id; 410 411 id = cmd->device->id; 412 ms->current_req = cmd; 413 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE; 414 ms->tgts[id].current_req = cmd; 415 416 #if 1 417 if (DEBUG_TARGET(cmd)) { 418 int i; 419 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=", 420 cmd, cmd->serial_number, id); 421 for (i = 0; i < cmd->cmd_len; ++i) 422 printk(" %x", cmd->cmnd[i]); 423 printk(" use_sg=%d buffer=%p bufflen=%u\n", 424 cmd->use_sg, cmd->request_buffer, cmd->request_bufflen); 425 } 426 #endif 427 if (ms->dma_started) 428 panic("mesh: double DMA start !\n"); 429 430 ms->phase = arbitrating; 431 ms->msgphase = msg_none; 432 ms->data_ptr = 0; 433 ms->dma_started = 0; 434 ms->n_msgout = 0; 435 ms->last_n_msgout = 0; 436 ms->expect_reply = 0; 437 ms->conn_tgt = id; 438 ms->tgts[id].saved_ptr = 0; 439 ms->stat = DID_OK; 440 ms->aborting = 0; 441 #ifdef MESH_DBG 442 ms->tgts[id].n_log = 0; 443 dlog(ms, "start cmd=%x", (int) cmd); 444 #endif 445 446 /* Off we go */ 447 dlog(ms, "about to arb, intr/exc/err/fc=%.8x", 448 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 449 out_8(&mr->interrupt, INT_CMDDONE); 450 out_8(&mr->sequence, SEQ_ENBRESEL); 451 mesh_flush_io(mr); 452 udelay(1); 453 454 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { 455 /* 456 * Some other device has the bus or is arbitrating for it - 457 * probably a target which is about to reselect us. 458 */ 459 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x", 460 MKWORD(mr->interrupt, mr->exception, 461 mr->error, mr->fifo_count)); 462 for (t = 100; t > 0; --t) { 463 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) 464 break; 465 if (in_8(&mr->interrupt) != 0) { 466 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x", 467 MKWORD(mr->interrupt, mr->exception, 468 mr->error, mr->fifo_count)); 469 mesh_interrupt(ms); 470 if (ms->phase != arbitrating) 471 return; 472 } 473 udelay(1); 474 } 475 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { 476 /* XXX should try again in a little while */ 477 ms->stat = DID_BUS_BUSY; 478 ms->phase = idle; 479 mesh_done(ms, 0); 480 return; 481 } 482 } 483 484 /* 485 * Apparently the mesh has a bug where it will assert both its 486 * own bit and the target's bit on the bus during arbitration. 487 */ 488 out_8(&mr->dest_id, mr->source_id); 489 490 /* 491 * There appears to be a race with reselection sometimes, 492 * where a target reselects us just as we issue the 493 * arbitrate command. It seems that then the arbitrate 494 * command just hangs waiting for the bus to be free 495 * without giving us a reselection exception. 496 * The only way I have found to get it to respond correctly 497 * is this: disable reselection before issuing the arbitrate 498 * command, then after issuing it, if it looks like a target 499 * is trying to reselect us, reset the mesh and then enable 500 * reselection. 501 */ 502 out_8(&mr->sequence, SEQ_DISRESEL); 503 if (in_8(&mr->interrupt) != 0) { 504 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x", 505 MKWORD(mr->interrupt, mr->exception, 506 mr->error, mr->fifo_count)); 507 mesh_interrupt(ms); 508 if (ms->phase != arbitrating) 509 return; 510 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x", 511 MKWORD(mr->interrupt, mr->exception, 512 mr->error, mr->fifo_count)); 513 } 514 515 out_8(&mr->sequence, SEQ_ARBITRATE); 516 517 for (t = 230; t > 0; --t) { 518 if (in_8(&mr->interrupt) != 0) 519 break; 520 udelay(1); 521 } 522 dlog(ms, "after arb, intr/exc/err/fc=%.8x", 523 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 524 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) 525 && (in_8(&mr->bus_status0) & BS0_IO)) { 526 /* looks like a reselection - try resetting the mesh */ 527 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x", 528 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 529 out_8(&mr->sequence, SEQ_RESETMESH); 530 mesh_flush_io(mr); 531 udelay(10); 532 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 533 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 534 out_8(&mr->sequence, SEQ_ENBRESEL); 535 mesh_flush_io(mr); 536 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) 537 udelay(1); 538 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x", 539 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 540 #ifndef MESH_MULTIPLE_HOSTS 541 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) 542 && (in_8(&mr->bus_status0) & BS0_IO)) { 543 printk(KERN_ERR "mesh: controller not responding" 544 " to reselection!\n"); 545 /* 546 * If this is a target reselecting us, and the 547 * mesh isn't responding, the higher levels of 548 * the scsi code will eventually time out and 549 * reset the bus. 550 */ 551 } 552 #endif 553 } 554 } 555 556 /* 557 * Start the next command for a MESH. 558 * Should be called with interrupts disabled. 559 */ 560 static void mesh_start(struct mesh_state *ms) 561 { 562 struct scsi_cmnd *cmd, *prev, *next; 563 564 if (ms->phase != idle || ms->current_req != NULL) { 565 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)", 566 ms->phase, ms); 567 return; 568 } 569 570 while (ms->phase == idle) { 571 prev = NULL; 572 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) { 573 if (cmd == NULL) 574 return; 575 if (ms->tgts[cmd->device->id].current_req == NULL) 576 break; 577 prev = cmd; 578 } 579 next = (struct scsi_cmnd *) cmd->host_scribble; 580 if (prev == NULL) 581 ms->request_q = next; 582 else 583 prev->host_scribble = (void *) next; 584 if (next == NULL) 585 ms->request_qtail = prev; 586 587 mesh_start_cmd(ms, cmd); 588 } 589 } 590 591 static void mesh_done(struct mesh_state *ms, int start_next) 592 { 593 struct scsi_cmnd *cmd; 594 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 595 596 cmd = ms->current_req; 597 ms->current_req = NULL; 598 tp->current_req = NULL; 599 if (cmd) { 600 cmd->result = (ms->stat << 16) + cmd->SCp.Status; 601 if (ms->stat == DID_OK) 602 cmd->result += (cmd->SCp.Message << 8); 603 if (DEBUG_TARGET(cmd)) { 604 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n", 605 cmd->result, ms->data_ptr, cmd->request_bufflen); 606 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3) 607 && cmd->request_buffer != 0) { 608 unsigned char *b = cmd->request_buffer; 609 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n", 610 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); 611 } 612 } 613 cmd->SCp.this_residual -= ms->data_ptr; 614 mesh_completed(ms, cmd); 615 } 616 if (start_next) { 617 out_8(&ms->mesh->sequence, SEQ_ENBRESEL); 618 mesh_flush_io(ms->mesh); 619 udelay(1); 620 ms->phase = idle; 621 mesh_start(ms); 622 } 623 } 624 625 static inline void add_sdtr_msg(struct mesh_state *ms) 626 { 627 int i = ms->n_msgout; 628 629 ms->msgout[i] = EXTENDED_MESSAGE; 630 ms->msgout[i+1] = 3; 631 ms->msgout[i+2] = EXTENDED_SDTR; 632 ms->msgout[i+3] = mesh_sync_period/4; 633 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0); 634 ms->n_msgout = i + 5; 635 } 636 637 static void set_sdtr(struct mesh_state *ms, int period, int offset) 638 { 639 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 640 volatile struct mesh_regs __iomem *mr = ms->mesh; 641 int v, tr; 642 643 tp->sdtr_state = sdtr_done; 644 if (offset == 0) { 645 /* asynchronous */ 646 if (SYNC_OFF(tp->sync_params)) 647 printk(KERN_INFO "mesh: target %d now asynchronous\n", 648 ms->conn_tgt); 649 tp->sync_params = ASYNC_PARAMS; 650 out_8(&mr->sync_params, ASYNC_PARAMS); 651 return; 652 } 653 /* 654 * We need to compute ceil(clk_freq * period / 500e6) - 2 655 * without incurring overflow. 656 */ 657 v = (ms->clk_freq / 5000) * period; 658 if (v <= 250000) { 659 /* special case: sync_period == 5 * clk_period */ 660 v = 0; 661 /* units of tr are 100kB/s */ 662 tr = (ms->clk_freq + 250000) / 500000; 663 } else { 664 /* sync_period == (v + 2) * 2 * clk_period */ 665 v = (v + 99999) / 100000 - 2; 666 if (v > 15) 667 v = 15; /* oops */ 668 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000; 669 } 670 if (offset > 15) 671 offset = 15; /* can't happen */ 672 tp->sync_params = SYNC_PARAMS(offset, v); 673 out_8(&mr->sync_params, tp->sync_params); 674 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n", 675 ms->conn_tgt, tr/10, tr%10); 676 } 677 678 static void start_phase(struct mesh_state *ms) 679 { 680 int i, seq, nb; 681 volatile struct mesh_regs __iomem *mr = ms->mesh; 682 volatile struct dbdma_regs __iomem *md = ms->dma; 683 struct scsi_cmnd *cmd = ms->current_req; 684 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 685 686 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x", 687 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); 688 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 689 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); 690 switch (ms->msgphase) { 691 case msg_none: 692 break; 693 694 case msg_in: 695 out_8(&mr->count_hi, 0); 696 out_8(&mr->count_lo, 1); 697 out_8(&mr->sequence, SEQ_MSGIN + seq); 698 ms->n_msgin = 0; 699 return; 700 701 case msg_out: 702 /* 703 * To make sure ATN drops before we assert ACK for 704 * the last byte of the message, we have to do the 705 * last byte specially. 706 */ 707 if (ms->n_msgout <= 0) { 708 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n", 709 ms->n_msgout); 710 mesh_dump_regs(ms); 711 ms->msgphase = msg_none; 712 break; 713 } 714 if (ALLOW_DEBUG(ms->conn_tgt)) { 715 printk(KERN_DEBUG "mesh: sending %d msg bytes:", 716 ms->n_msgout); 717 for (i = 0; i < ms->n_msgout; ++i) 718 printk(" %x", ms->msgout[i]); 719 printk("\n"); 720 } 721 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0], 722 ms->msgout[1], ms->msgout[2])); 723 out_8(&mr->count_hi, 0); 724 out_8(&mr->sequence, SEQ_FLUSHFIFO); 725 mesh_flush_io(mr); 726 udelay(1); 727 /* 728 * If ATN is not already asserted, we assert it, then 729 * issue a SEQ_MSGOUT to get the mesh to drop ACK. 730 */ 731 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { 732 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); 733 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ 734 mesh_flush_io(mr); 735 udelay(1); 736 out_8(&mr->count_lo, 1); 737 out_8(&mr->sequence, SEQ_MSGOUT + seq); 738 out_8(&mr->bus_status0, 0); /* release explicit ATN */ 739 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); 740 } 741 if (ms->n_msgout == 1) { 742 /* 743 * We can't issue the SEQ_MSGOUT without ATN 744 * until the target has asserted REQ. The logic 745 * in cmd_complete handles both situations: 746 * REQ already asserted or not. 747 */ 748 cmd_complete(ms); 749 } else { 750 out_8(&mr->count_lo, ms->n_msgout - 1); 751 out_8(&mr->sequence, SEQ_MSGOUT + seq); 752 for (i = 0; i < ms->n_msgout - 1; ++i) 753 out_8(&mr->fifo, ms->msgout[i]); 754 } 755 return; 756 757 default: 758 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n", 759 ms->msgphase); 760 } 761 762 switch (ms->phase) { 763 case selecting: 764 out_8(&mr->dest_id, ms->conn_tgt); 765 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); 766 break; 767 case commanding: 768 out_8(&mr->sync_params, tp->sync_params); 769 out_8(&mr->count_hi, 0); 770 if (cmd) { 771 out_8(&mr->count_lo, cmd->cmd_len); 772 out_8(&mr->sequence, SEQ_COMMAND + seq); 773 for (i = 0; i < cmd->cmd_len; ++i) 774 out_8(&mr->fifo, cmd->cmnd[i]); 775 } else { 776 out_8(&mr->count_lo, 6); 777 out_8(&mr->sequence, SEQ_COMMAND + seq); 778 for (i = 0; i < 6; ++i) 779 out_8(&mr->fifo, 0); 780 } 781 break; 782 case dataing: 783 /* transfer data, if any */ 784 if (!ms->dma_started) { 785 set_dma_cmds(ms, cmd); 786 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds)); 787 out_le32(&md->control, (RUN << 16) | RUN); 788 ms->dma_started = 1; 789 } 790 nb = ms->dma_count; 791 if (nb > 0xfff0) 792 nb = 0xfff0; 793 ms->dma_count -= nb; 794 ms->data_ptr += nb; 795 out_8(&mr->count_lo, nb); 796 out_8(&mr->count_hi, nb >> 8); 797 out_8(&mr->sequence, (tp->data_goes_out? 798 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq); 799 break; 800 case statusing: 801 out_8(&mr->count_hi, 0); 802 out_8(&mr->count_lo, 1); 803 out_8(&mr->sequence, SEQ_STATUS + seq); 804 break; 805 case busfreeing: 806 case disconnecting: 807 out_8(&mr->sequence, SEQ_ENBRESEL); 808 mesh_flush_io(mr); 809 udelay(1); 810 dlog(ms, "enbresel intr/exc/err/fc=%.8x", 811 MKWORD(mr->interrupt, mr->exception, mr->error, 812 mr->fifo_count)); 813 out_8(&mr->sequence, SEQ_BUSFREE); 814 break; 815 default: 816 printk(KERN_ERR "mesh: start_phase called with phase=%d\n", 817 ms->phase); 818 dumpslog(ms); 819 } 820 821 } 822 823 static inline void get_msgin(struct mesh_state *ms) 824 { 825 volatile struct mesh_regs __iomem *mr = ms->mesh; 826 int i, n; 827 828 n = mr->fifo_count; 829 if (n != 0) { 830 i = ms->n_msgin; 831 ms->n_msgin = i + n; 832 for (; n > 0; --n) 833 ms->msgin[i++] = in_8(&mr->fifo); 834 } 835 } 836 837 static inline int msgin_length(struct mesh_state *ms) 838 { 839 int b, n; 840 841 n = 1; 842 if (ms->n_msgin > 0) { 843 b = ms->msgin[0]; 844 if (b == 1) { 845 /* extended message */ 846 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2; 847 } else if (0x20 <= b && b <= 0x2f) { 848 /* 2-byte message */ 849 n = 2; 850 } 851 } 852 return n; 853 } 854 855 static void reselected(struct mesh_state *ms) 856 { 857 volatile struct mesh_regs __iomem *mr = ms->mesh; 858 struct scsi_cmnd *cmd; 859 struct mesh_target *tp; 860 int b, t, prev; 861 862 switch (ms->phase) { 863 case idle: 864 break; 865 case arbitrating: 866 if ((cmd = ms->current_req) != NULL) { 867 /* put the command back on the queue */ 868 cmd->host_scribble = (void *) ms->request_q; 869 if (ms->request_q == NULL) 870 ms->request_qtail = cmd; 871 ms->request_q = cmd; 872 tp = &ms->tgts[cmd->device->id]; 873 tp->current_req = NULL; 874 } 875 break; 876 case busfreeing: 877 ms->phase = reselecting; 878 mesh_done(ms, 0); 879 break; 880 case disconnecting: 881 break; 882 default: 883 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n", 884 ms->msgphase, ms->phase, ms->conn_tgt); 885 dumplog(ms, ms->conn_tgt); 886 dumpslog(ms); 887 } 888 889 if (ms->dma_started) { 890 printk(KERN_ERR "mesh: reselected with DMA started !\n"); 891 halt_dma(ms); 892 } 893 ms->current_req = NULL; 894 ms->phase = dataing; 895 ms->msgphase = msg_in; 896 ms->n_msgout = 0; 897 ms->last_n_msgout = 0; 898 prev = ms->conn_tgt; 899 900 /* 901 * We seem to get abortive reselections sometimes. 902 */ 903 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { 904 static int mesh_aborted_resels; 905 mesh_aborted_resels++; 906 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 907 mesh_flush_io(mr); 908 udelay(1); 909 out_8(&mr->sequence, SEQ_ENBRESEL); 910 mesh_flush_io(mr); 911 udelay(5); 912 dlog(ms, "extra resel err/exc/fc = %.6x", 913 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); 914 } 915 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 916 mesh_flush_io(mr); 917 udelay(1); 918 out_8(&mr->sequence, SEQ_ENBRESEL); 919 mesh_flush_io(mr); 920 udelay(1); 921 out_8(&mr->sync_params, ASYNC_PARAMS); 922 923 /* 924 * Find out who reselected us. 925 */ 926 if (in_8(&mr->fifo_count) == 0) { 927 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n"); 928 ms->conn_tgt = ms->host->this_id; 929 goto bogus; 930 } 931 /* get the last byte in the fifo */ 932 do { 933 b = in_8(&mr->fifo); 934 dlog(ms, "reseldata %x", b); 935 } while (in_8(&mr->fifo_count)); 936 for (t = 0; t < 8; ++t) 937 if ((b & (1 << t)) != 0 && t != ms->host->this_id) 938 break; 939 if (b != (1 << t) + (1 << ms->host->this_id)) { 940 printk(KERN_ERR "mesh: bad reselection data %x\n", b); 941 ms->conn_tgt = ms->host->this_id; 942 goto bogus; 943 } 944 945 946 /* 947 * Set up to continue with that target's transfer. 948 */ 949 ms->conn_tgt = t; 950 tp = &ms->tgts[t]; 951 out_8(&mr->sync_params, tp->sync_params); 952 if (ALLOW_DEBUG(t)) { 953 printk(KERN_DEBUG "mesh: reselected by target %d\n", t); 954 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n", 955 tp->saved_ptr, tp->data_goes_out, tp->current_req); 956 } 957 ms->current_req = tp->current_req; 958 if (tp->current_req == NULL) { 959 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t); 960 goto bogus; 961 } 962 ms->data_ptr = tp->saved_ptr; 963 dlog(ms, "resel prev tgt=%d", prev); 964 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); 965 start_phase(ms); 966 return; 967 968 bogus: 969 dumplog(ms, ms->conn_tgt); 970 dumpslog(ms); 971 ms->data_ptr = 0; 972 ms->aborting = 1; 973 start_phase(ms); 974 } 975 976 static void do_abort(struct mesh_state *ms) 977 { 978 ms->msgout[0] = ABORT; 979 ms->n_msgout = 1; 980 ms->aborting = 1; 981 ms->stat = DID_ABORT; 982 dlog(ms, "abort", 0); 983 } 984 985 static void handle_reset(struct mesh_state *ms) 986 { 987 int tgt; 988 struct mesh_target *tp; 989 struct scsi_cmnd *cmd; 990 volatile struct mesh_regs __iomem *mr = ms->mesh; 991 992 for (tgt = 0; tgt < 8; ++tgt) { 993 tp = &ms->tgts[tgt]; 994 if ((cmd = tp->current_req) != NULL) { 995 cmd->result = DID_RESET << 16; 996 tp->current_req = NULL; 997 mesh_completed(ms, cmd); 998 } 999 ms->tgts[tgt].sdtr_state = do_sdtr; 1000 ms->tgts[tgt].sync_params = ASYNC_PARAMS; 1001 } 1002 ms->current_req = NULL; 1003 while ((cmd = ms->request_q) != NULL) { 1004 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble; 1005 cmd->result = DID_RESET << 16; 1006 mesh_completed(ms, cmd); 1007 } 1008 ms->phase = idle; 1009 ms->msgphase = msg_none; 1010 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1011 out_8(&mr->sequence, SEQ_FLUSHFIFO); 1012 mesh_flush_io(mr); 1013 udelay(1); 1014 out_8(&mr->sync_params, ASYNC_PARAMS); 1015 out_8(&mr->sequence, SEQ_ENBRESEL); 1016 } 1017 1018 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id) 1019 { 1020 unsigned long flags; 1021 struct mesh_state *ms = dev_id; 1022 struct Scsi_Host *dev = ms->host; 1023 1024 spin_lock_irqsave(dev->host_lock, flags); 1025 mesh_interrupt(ms); 1026 spin_unlock_irqrestore(dev->host_lock, flags); 1027 return IRQ_HANDLED; 1028 } 1029 1030 static void handle_error(struct mesh_state *ms) 1031 { 1032 int err, exc, count; 1033 volatile struct mesh_regs __iomem *mr = ms->mesh; 1034 1035 err = in_8(&mr->error); 1036 exc = in_8(&mr->exception); 1037 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1038 dlog(ms, "error err/exc/fc/cl=%.8x", 1039 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); 1040 if (err & ERR_SCSIRESET) { 1041 /* SCSI bus was reset */ 1042 printk(KERN_INFO "mesh: SCSI bus reset detected: " 1043 "waiting for end..."); 1044 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) 1045 udelay(1); 1046 printk("done\n"); 1047 handle_reset(ms); 1048 /* request_q is empty, no point in mesh_start() */ 1049 return; 1050 } 1051 if (err & ERR_UNEXPDISC) { 1052 /* Unexpected disconnect */ 1053 if (exc & EXC_RESELECTED) { 1054 reselected(ms); 1055 return; 1056 } 1057 if (!ms->aborting) { 1058 printk(KERN_WARNING "mesh: target %d aborted\n", 1059 ms->conn_tgt); 1060 dumplog(ms, ms->conn_tgt); 1061 dumpslog(ms); 1062 } 1063 out_8(&mr->interrupt, INT_CMDDONE); 1064 ms->stat = DID_ABORT; 1065 mesh_done(ms, 1); 1066 return; 1067 } 1068 if (err & ERR_PARITY) { 1069 if (ms->msgphase == msg_in) { 1070 printk(KERN_ERR "mesh: msg parity error, target %d\n", 1071 ms->conn_tgt); 1072 ms->msgout[0] = MSG_PARITY_ERROR; 1073 ms->n_msgout = 1; 1074 ms->msgphase = msg_in_bad; 1075 cmd_complete(ms); 1076 return; 1077 } 1078 if (ms->stat == DID_OK) { 1079 printk(KERN_ERR "mesh: parity error, target %d\n", 1080 ms->conn_tgt); 1081 ms->stat = DID_PARITY; 1082 } 1083 count = (mr->count_hi << 8) + mr->count_lo; 1084 if (count == 0) { 1085 cmd_complete(ms); 1086 } else { 1087 /* reissue the data transfer command */ 1088 out_8(&mr->sequence, mr->sequence); 1089 } 1090 return; 1091 } 1092 if (err & ERR_SEQERR) { 1093 if (exc & EXC_RESELECTED) { 1094 /* This can happen if we issue a command to 1095 get the bus just after the target reselects us. */ 1096 static int mesh_resel_seqerr; 1097 mesh_resel_seqerr++; 1098 reselected(ms); 1099 return; 1100 } 1101 if (exc == EXC_PHASEMM) { 1102 static int mesh_phasemm_seqerr; 1103 mesh_phasemm_seqerr++; 1104 phase_mismatch(ms); 1105 return; 1106 } 1107 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n", 1108 err, exc); 1109 } else { 1110 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc); 1111 } 1112 mesh_dump_regs(ms); 1113 dumplog(ms, ms->conn_tgt); 1114 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { 1115 /* try to do what the target wants */ 1116 do_abort(ms); 1117 phase_mismatch(ms); 1118 return; 1119 } 1120 ms->stat = DID_ERROR; 1121 mesh_done(ms, 1); 1122 } 1123 1124 static void handle_exception(struct mesh_state *ms) 1125 { 1126 int exc; 1127 volatile struct mesh_regs __iomem *mr = ms->mesh; 1128 1129 exc = in_8(&mr->exception); 1130 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); 1131 if (exc & EXC_RESELECTED) { 1132 static int mesh_resel_exc; 1133 mesh_resel_exc++; 1134 reselected(ms); 1135 } else if (exc == EXC_ARBLOST) { 1136 printk(KERN_DEBUG "mesh: lost arbitration\n"); 1137 ms->stat = DID_BUS_BUSY; 1138 mesh_done(ms, 1); 1139 } else if (exc == EXC_SELTO) { 1140 /* selection timed out */ 1141 ms->stat = DID_BAD_TARGET; 1142 mesh_done(ms, 1); 1143 } else if (exc == EXC_PHASEMM) { 1144 /* target wants to do something different: 1145 find out what it wants and do it. */ 1146 phase_mismatch(ms); 1147 } else { 1148 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc); 1149 mesh_dump_regs(ms); 1150 dumplog(ms, ms->conn_tgt); 1151 do_abort(ms); 1152 phase_mismatch(ms); 1153 } 1154 } 1155 1156 static void handle_msgin(struct mesh_state *ms) 1157 { 1158 int i, code; 1159 struct scsi_cmnd *cmd = ms->current_req; 1160 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 1161 1162 if (ms->n_msgin == 0) 1163 return; 1164 code = ms->msgin[0]; 1165 if (ALLOW_DEBUG(ms->conn_tgt)) { 1166 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin); 1167 for (i = 0; i < ms->n_msgin; ++i) 1168 printk(" %x", ms->msgin[i]); 1169 printk("\n"); 1170 } 1171 dlog(ms, "msgin msg=%.8x", 1172 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2])); 1173 1174 ms->expect_reply = 0; 1175 ms->n_msgout = 0; 1176 if (ms->n_msgin < msgin_length(ms)) 1177 goto reject; 1178 if (cmd) 1179 cmd->SCp.Message = code; 1180 switch (code) { 1181 case COMMAND_COMPLETE: 1182 break; 1183 case EXTENDED_MESSAGE: 1184 switch (ms->msgin[2]) { 1185 case EXTENDED_MODIFY_DATA_POINTER: 1186 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6] 1187 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8); 1188 break; 1189 case EXTENDED_SDTR: 1190 if (tp->sdtr_state != sdtr_sent) { 1191 /* reply with an SDTR */ 1192 add_sdtr_msg(ms); 1193 /* limit period to at least his value, 1194 offset to no more than his */ 1195 if (ms->msgout[3] < ms->msgin[3]) 1196 ms->msgout[3] = ms->msgin[3]; 1197 if (ms->msgout[4] > ms->msgin[4]) 1198 ms->msgout[4] = ms->msgin[4]; 1199 set_sdtr(ms, ms->msgout[3], ms->msgout[4]); 1200 ms->msgphase = msg_out; 1201 } else { 1202 set_sdtr(ms, ms->msgin[3], ms->msgin[4]); 1203 } 1204 break; 1205 default: 1206 goto reject; 1207 } 1208 break; 1209 case SAVE_POINTERS: 1210 tp->saved_ptr = ms->data_ptr; 1211 break; 1212 case RESTORE_POINTERS: 1213 ms->data_ptr = tp->saved_ptr; 1214 break; 1215 case DISCONNECT: 1216 ms->phase = disconnecting; 1217 break; 1218 case ABORT: 1219 break; 1220 case MESSAGE_REJECT: 1221 if (tp->sdtr_state == sdtr_sent) 1222 set_sdtr(ms, 0, 0); 1223 break; 1224 case NOP: 1225 break; 1226 default: 1227 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) { 1228 if (cmd == NULL) { 1229 do_abort(ms); 1230 ms->msgphase = msg_out; 1231 } else if (code != cmd->device->lun + IDENTIFY_BASE) { 1232 printk(KERN_WARNING "mesh: lun mismatch " 1233 "(%d != %d) on reselection from " 1234 "target %d\n", code - IDENTIFY_BASE, 1235 cmd->device->lun, ms->conn_tgt); 1236 } 1237 break; 1238 } 1239 goto reject; 1240 } 1241 return; 1242 1243 reject: 1244 printk(KERN_WARNING "mesh: rejecting message from target %d:", 1245 ms->conn_tgt); 1246 for (i = 0; i < ms->n_msgin; ++i) 1247 printk(" %x", ms->msgin[i]); 1248 printk("\n"); 1249 ms->msgout[0] = MESSAGE_REJECT; 1250 ms->n_msgout = 1; 1251 ms->msgphase = msg_out; 1252 } 1253 1254 /* 1255 * Set up DMA commands for transferring data. 1256 */ 1257 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd) 1258 { 1259 int i, dma_cmd, total, off, dtot; 1260 struct scatterlist *scl; 1261 struct dbdma_cmd *dcmds; 1262 1263 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out? 1264 OUTPUT_MORE: INPUT_MORE; 1265 dcmds = ms->dma_cmds; 1266 dtot = 0; 1267 if (cmd) { 1268 cmd->SCp.this_residual = cmd->request_bufflen; 1269 if (cmd->use_sg > 0) { 1270 int nseg; 1271 total = 0; 1272 scl = (struct scatterlist *) cmd->request_buffer; 1273 off = ms->data_ptr; 1274 nseg = pci_map_sg(ms->pdev, scl, cmd->use_sg, 1275 cmd->sc_data_direction); 1276 for (i = 0; i <nseg; ++i, ++scl) { 1277 u32 dma_addr = sg_dma_address(scl); 1278 u32 dma_len = sg_dma_len(scl); 1279 1280 total += scl->length; 1281 if (off >= dma_len) { 1282 off -= dma_len; 1283 continue; 1284 } 1285 if (dma_len > 0xffff) 1286 panic("mesh: scatterlist element >= 64k"); 1287 st_le16(&dcmds->req_count, dma_len - off); 1288 st_le16(&dcmds->command, dma_cmd); 1289 st_le32(&dcmds->phy_addr, dma_addr + off); 1290 dcmds->xfer_status = 0; 1291 ++dcmds; 1292 dtot += dma_len - off; 1293 off = 0; 1294 } 1295 } else if (ms->data_ptr < cmd->request_bufflen) { 1296 dtot = cmd->request_bufflen - ms->data_ptr; 1297 if (dtot > 0xffff) 1298 panic("mesh: transfer size >= 64k"); 1299 st_le16(&dcmds->req_count, dtot); 1300 /* XXX Use pci DMA API here ... */ 1301 st_le32(&dcmds->phy_addr, 1302 virt_to_phys(cmd->request_buffer) + ms->data_ptr); 1303 dcmds->xfer_status = 0; 1304 ++dcmds; 1305 } 1306 } 1307 if (dtot == 0) { 1308 /* Either the target has overrun our buffer, 1309 or the caller didn't provide a buffer. */ 1310 static char mesh_extra_buf[64]; 1311 1312 dtot = sizeof(mesh_extra_buf); 1313 st_le16(&dcmds->req_count, dtot); 1314 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf)); 1315 dcmds->xfer_status = 0; 1316 ++dcmds; 1317 } 1318 dma_cmd += OUTPUT_LAST - OUTPUT_MORE; 1319 st_le16(&dcmds[-1].command, dma_cmd); 1320 memset(dcmds, 0, sizeof(*dcmds)); 1321 st_le16(&dcmds->command, DBDMA_STOP); 1322 ms->dma_count = dtot; 1323 } 1324 1325 static void halt_dma(struct mesh_state *ms) 1326 { 1327 volatile struct dbdma_regs __iomem *md = ms->dma; 1328 volatile struct mesh_regs __iomem *mr = ms->mesh; 1329 struct scsi_cmnd *cmd = ms->current_req; 1330 int t, nb; 1331 1332 if (!ms->tgts[ms->conn_tgt].data_goes_out) { 1333 /* wait a little while until the fifo drains */ 1334 t = 50; 1335 while (t > 0 && in_8(&mr->fifo_count) != 0 1336 && (in_le32(&md->status) & ACTIVE) != 0) { 1337 --t; 1338 udelay(1); 1339 } 1340 } 1341 out_le32(&md->control, RUN << 16); /* turn off RUN bit */ 1342 nb = (mr->count_hi << 8) + mr->count_lo; 1343 dlog(ms, "halt_dma fc/count=%.6x", 1344 MKWORD(0, mr->fifo_count, 0, nb)); 1345 if (ms->tgts[ms->conn_tgt].data_goes_out) 1346 nb += mr->fifo_count; 1347 /* nb is the number of bytes not yet transferred 1348 to/from the target. */ 1349 ms->data_ptr -= nb; 1350 dlog(ms, "data_ptr %x", ms->data_ptr); 1351 if (ms->data_ptr < 0) { 1352 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n", 1353 ms->data_ptr, nb, ms); 1354 ms->data_ptr = 0; 1355 #ifdef MESH_DBG 1356 dumplog(ms, ms->conn_tgt); 1357 dumpslog(ms); 1358 #endif /* MESH_DBG */ 1359 } else if (cmd && cmd->request_bufflen != 0 && 1360 ms->data_ptr > cmd->request_bufflen) { 1361 printk(KERN_DEBUG "mesh: target %d overrun, " 1362 "data_ptr=%x total=%x goes_out=%d\n", 1363 ms->conn_tgt, ms->data_ptr, cmd->request_bufflen, 1364 ms->tgts[ms->conn_tgt].data_goes_out); 1365 } 1366 if (cmd->use_sg != 0) { 1367 struct scatterlist *sg; 1368 sg = (struct scatterlist *)cmd->request_buffer; 1369 pci_unmap_sg(ms->pdev, sg, cmd->use_sg, cmd->sc_data_direction); 1370 } 1371 ms->dma_started = 0; 1372 } 1373 1374 static void phase_mismatch(struct mesh_state *ms) 1375 { 1376 volatile struct mesh_regs __iomem *mr = ms->mesh; 1377 int phase; 1378 1379 dlog(ms, "phasemm ch/cl/seq/fc=%.8x", 1380 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); 1381 phase = in_8(&mr->bus_status0) & BS0_PHASE; 1382 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) { 1383 /* output the last byte of the message, without ATN */ 1384 out_8(&mr->count_lo, 1); 1385 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); 1386 mesh_flush_io(mr); 1387 udelay(1); 1388 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); 1389 ms->msgphase = msg_out_last; 1390 return; 1391 } 1392 1393 if (ms->msgphase == msg_in) { 1394 get_msgin(ms); 1395 if (ms->n_msgin) 1396 handle_msgin(ms); 1397 } 1398 1399 if (ms->dma_started) 1400 halt_dma(ms); 1401 if (mr->fifo_count) { 1402 out_8(&mr->sequence, SEQ_FLUSHFIFO); 1403 mesh_flush_io(mr); 1404 udelay(1); 1405 } 1406 1407 ms->msgphase = msg_none; 1408 switch (phase) { 1409 case BP_DATAIN: 1410 ms->tgts[ms->conn_tgt].data_goes_out = 0; 1411 ms->phase = dataing; 1412 break; 1413 case BP_DATAOUT: 1414 ms->tgts[ms->conn_tgt].data_goes_out = 1; 1415 ms->phase = dataing; 1416 break; 1417 case BP_COMMAND: 1418 ms->phase = commanding; 1419 break; 1420 case BP_STATUS: 1421 ms->phase = statusing; 1422 break; 1423 case BP_MSGIN: 1424 ms->msgphase = msg_in; 1425 ms->n_msgin = 0; 1426 break; 1427 case BP_MSGOUT: 1428 ms->msgphase = msg_out; 1429 if (ms->n_msgout == 0) { 1430 if (ms->aborting) { 1431 do_abort(ms); 1432 } else { 1433 if (ms->last_n_msgout == 0) { 1434 printk(KERN_DEBUG 1435 "mesh: no msg to repeat\n"); 1436 ms->msgout[0] = NOP; 1437 ms->last_n_msgout = 1; 1438 } 1439 ms->n_msgout = ms->last_n_msgout; 1440 } 1441 } 1442 break; 1443 default: 1444 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase); 1445 ms->stat = DID_ERROR; 1446 mesh_done(ms, 1); 1447 return; 1448 } 1449 1450 start_phase(ms); 1451 } 1452 1453 static void cmd_complete(struct mesh_state *ms) 1454 { 1455 volatile struct mesh_regs __iomem *mr = ms->mesh; 1456 struct scsi_cmnd *cmd = ms->current_req; 1457 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 1458 int seq, n, t; 1459 1460 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); 1461 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); 1462 switch (ms->msgphase) { 1463 case msg_out_xxx: 1464 /* huh? we expected a phase mismatch */ 1465 ms->n_msgin = 0; 1466 ms->msgphase = msg_in; 1467 /* fall through */ 1468 1469 case msg_in: 1470 /* should have some message bytes in fifo */ 1471 get_msgin(ms); 1472 n = msgin_length(ms); 1473 if (ms->n_msgin < n) { 1474 out_8(&mr->count_lo, n - ms->n_msgin); 1475 out_8(&mr->sequence, SEQ_MSGIN + seq); 1476 } else { 1477 ms->msgphase = msg_none; 1478 handle_msgin(ms); 1479 start_phase(ms); 1480 } 1481 break; 1482 1483 case msg_in_bad: 1484 out_8(&mr->sequence, SEQ_FLUSHFIFO); 1485 mesh_flush_io(mr); 1486 udelay(1); 1487 out_8(&mr->count_lo, 1); 1488 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); 1489 break; 1490 1491 case msg_out: 1492 /* 1493 * To get the right timing on ATN wrt ACK, we have 1494 * to get the MESH to drop ACK, wait until REQ gets 1495 * asserted, then drop ATN. To do this we first 1496 * issue a SEQ_MSGOUT with ATN and wait for REQ, 1497 * then change the command to a SEQ_MSGOUT w/o ATN. 1498 * If we don't see REQ in a reasonable time, we 1499 * change the command to SEQ_MSGIN with ATN, 1500 * wait for the phase mismatch interrupt, then 1501 * issue the SEQ_MSGOUT without ATN. 1502 */ 1503 out_8(&mr->count_lo, 1); 1504 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); 1505 t = 30; /* wait up to 30us */ 1506 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) 1507 udelay(1); 1508 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x", 1509 MKWORD(mr->error, mr->exception, 1510 mr->fifo_count, mr->count_lo)); 1511 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { 1512 /* whoops, target didn't do what we expected */ 1513 ms->last_n_msgout = ms->n_msgout; 1514 ms->n_msgout = 0; 1515 if (in_8(&mr->interrupt) & INT_ERROR) { 1516 printk(KERN_ERR "mesh: error %x in msg_out\n", 1517 in_8(&mr->error)); 1518 handle_error(ms); 1519 return; 1520 } 1521 if (in_8(&mr->exception) != EXC_PHASEMM) 1522 printk(KERN_ERR "mesh: exc %x in msg_out\n", 1523 in_8(&mr->exception)); 1524 else 1525 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n", 1526 in_8(&mr->bus_status0)); 1527 handle_exception(ms); 1528 return; 1529 } 1530 if (in_8(&mr->bus_status0) & BS0_REQ) { 1531 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); 1532 mesh_flush_io(mr); 1533 udelay(1); 1534 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); 1535 ms->msgphase = msg_out_last; 1536 } else { 1537 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); 1538 ms->msgphase = msg_out_xxx; 1539 } 1540 break; 1541 1542 case msg_out_last: 1543 ms->last_n_msgout = ms->n_msgout; 1544 ms->n_msgout = 0; 1545 ms->msgphase = ms->expect_reply? msg_in: msg_none; 1546 start_phase(ms); 1547 break; 1548 1549 case msg_none: 1550 switch (ms->phase) { 1551 case idle: 1552 printk(KERN_ERR "mesh: interrupt in idle phase?\n"); 1553 dumpslog(ms); 1554 return; 1555 case selecting: 1556 dlog(ms, "Selecting phase at command completion",0); 1557 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt), 1558 (cmd? cmd->device->lun: 0)); 1559 ms->n_msgout = 1; 1560 ms->expect_reply = 0; 1561 if (ms->aborting) { 1562 ms->msgout[0] = ABORT; 1563 ms->n_msgout++; 1564 } else if (tp->sdtr_state == do_sdtr) { 1565 /* add SDTR message */ 1566 add_sdtr_msg(ms); 1567 ms->expect_reply = 1; 1568 tp->sdtr_state = sdtr_sent; 1569 } 1570 ms->msgphase = msg_out; 1571 /* 1572 * We need to wait for REQ before dropping ATN. 1573 * We wait for at most 30us, then fall back to 1574 * a scheme where we issue a SEQ_COMMAND with ATN, 1575 * which will give us a phase mismatch interrupt 1576 * when REQ does come, and then we send the message. 1577 */ 1578 t = 230; /* wait up to 230us */ 1579 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { 1580 if (--t < 0) { 1581 dlog(ms, "impatient for req", ms->n_msgout); 1582 ms->msgphase = msg_none; 1583 break; 1584 } 1585 udelay(1); 1586 } 1587 break; 1588 case dataing: 1589 if (ms->dma_count != 0) { 1590 start_phase(ms); 1591 return; 1592 } 1593 /* 1594 * We can get a phase mismatch here if the target 1595 * changes to the status phase, even though we have 1596 * had a command complete interrupt. Then, if we 1597 * issue the SEQ_STATUS command, we'll get a sequence 1598 * error interrupt. Which isn't so bad except that 1599 * occasionally the mesh actually executes the 1600 * SEQ_STATUS *as well as* giving us the sequence 1601 * error and phase mismatch exception. 1602 */ 1603 out_8(&mr->sequence, 0); 1604 out_8(&mr->interrupt, 1605 INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1606 halt_dma(ms); 1607 break; 1608 case statusing: 1609 if (cmd) { 1610 cmd->SCp.Status = mr->fifo; 1611 if (DEBUG_TARGET(cmd)) 1612 printk(KERN_DEBUG "mesh: status is %x\n", 1613 cmd->SCp.Status); 1614 } 1615 ms->msgphase = msg_in; 1616 break; 1617 case busfreeing: 1618 mesh_done(ms, 1); 1619 return; 1620 case disconnecting: 1621 ms->current_req = NULL; 1622 ms->phase = idle; 1623 mesh_start(ms); 1624 return; 1625 default: 1626 break; 1627 } 1628 ++ms->phase; 1629 start_phase(ms); 1630 break; 1631 } 1632 } 1633 1634 1635 /* 1636 * Called by midlayer with host locked to queue a new 1637 * request 1638 */ 1639 static int mesh_queue(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *)) 1640 { 1641 struct mesh_state *ms; 1642 1643 cmd->scsi_done = done; 1644 cmd->host_scribble = NULL; 1645 1646 ms = (struct mesh_state *) cmd->device->host->hostdata; 1647 1648 if (ms->request_q == NULL) 1649 ms->request_q = cmd; 1650 else 1651 ms->request_qtail->host_scribble = (void *) cmd; 1652 ms->request_qtail = cmd; 1653 1654 if (ms->phase == idle) 1655 mesh_start(ms); 1656 1657 return 0; 1658 } 1659 1660 /* 1661 * Called to handle interrupts, either call by the interrupt 1662 * handler (do_mesh_interrupt) or by other functions in 1663 * exceptional circumstances 1664 */ 1665 static void mesh_interrupt(struct mesh_state *ms) 1666 { 1667 volatile struct mesh_regs __iomem *mr = ms->mesh; 1668 int intr; 1669 1670 #if 0 1671 if (ALLOW_DEBUG(ms->conn_tgt)) 1672 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x " 1673 "phase=%d msgphase=%d\n", mr->bus_status0, 1674 mr->interrupt, mr->exception, mr->error, 1675 ms->phase, ms->msgphase); 1676 #endif 1677 while ((intr = in_8(&mr->interrupt)) != 0) { 1678 dlog(ms, "interrupt intr/err/exc/seq=%.8x", 1679 MKWORD(intr, mr->error, mr->exception, mr->sequence)); 1680 if (intr & INT_ERROR) { 1681 handle_error(ms); 1682 } else if (intr & INT_EXCEPTION) { 1683 handle_exception(ms); 1684 } else if (intr & INT_CMDDONE) { 1685 out_8(&mr->interrupt, INT_CMDDONE); 1686 cmd_complete(ms); 1687 } 1688 } 1689 } 1690 1691 /* Todo: here we can at least try to remove the command from the 1692 * queue if it isn't connected yet, and for pending command, assert 1693 * ATN until the bus gets freed. 1694 */ 1695 static int mesh_abort(struct scsi_cmnd *cmd) 1696 { 1697 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; 1698 1699 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd); 1700 mesh_dump_regs(ms); 1701 dumplog(ms, cmd->device->id); 1702 dumpslog(ms); 1703 return FAILED; 1704 } 1705 1706 /* 1707 * Called by the midlayer with the lock held to reset the 1708 * SCSI host and bus. 1709 * The midlayer will wait for devices to come back, we don't need 1710 * to do that ourselves 1711 */ 1712 static int mesh_host_reset(struct scsi_cmnd *cmd) 1713 { 1714 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; 1715 volatile struct mesh_regs __iomem *mr = ms->mesh; 1716 volatile struct dbdma_regs __iomem *md = ms->dma; 1717 unsigned long flags; 1718 1719 printk(KERN_DEBUG "mesh_host_reset\n"); 1720 1721 spin_lock_irqsave(ms->host->host_lock, flags); 1722 1723 /* Reset the controller & dbdma channel */ 1724 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ 1725 out_8(&mr->exception, 0xff); /* clear all exception bits */ 1726 out_8(&mr->error, 0xff); /* clear all error bits */ 1727 out_8(&mr->sequence, SEQ_RESETMESH); 1728 mesh_flush_io(mr); 1729 udelay(1); 1730 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1731 out_8(&mr->source_id, ms->host->this_id); 1732 out_8(&mr->sel_timeout, 25); /* 250ms */ 1733 out_8(&mr->sync_params, ASYNC_PARAMS); 1734 1735 /* Reset the bus */ 1736 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ 1737 mesh_flush_io(mr); 1738 udelay(30); /* leave it on for >= 25us */ 1739 out_8(&mr->bus_status1, 0); /* negate RST */ 1740 1741 /* Complete pending commands */ 1742 handle_reset(ms); 1743 1744 spin_unlock_irqrestore(ms->host->host_lock, flags); 1745 return SUCCESS; 1746 } 1747 1748 static void set_mesh_power(struct mesh_state *ms, int state) 1749 { 1750 if (!machine_is(powermac)) 1751 return; 1752 if (state) { 1753 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1); 1754 msleep(200); 1755 } else { 1756 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0); 1757 msleep(10); 1758 } 1759 } 1760 1761 1762 #ifdef CONFIG_PM 1763 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg) 1764 { 1765 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1766 unsigned long flags; 1767 1768 switch (mesg.event) { 1769 case PM_EVENT_SUSPEND: 1770 case PM_EVENT_FREEZE: 1771 break; 1772 default: 1773 return 0; 1774 } 1775 if (mesg.event == mdev->ofdev.dev.power.power_state.event) 1776 return 0; 1777 1778 scsi_block_requests(ms->host); 1779 spin_lock_irqsave(ms->host->host_lock, flags); 1780 while(ms->phase != idle) { 1781 spin_unlock_irqrestore(ms->host->host_lock, flags); 1782 msleep(10); 1783 spin_lock_irqsave(ms->host->host_lock, flags); 1784 } 1785 ms->phase = sleeping; 1786 spin_unlock_irqrestore(ms->host->host_lock, flags); 1787 disable_irq(ms->meshintr); 1788 set_mesh_power(ms, 0); 1789 1790 mdev->ofdev.dev.power.power_state = mesg; 1791 1792 return 0; 1793 } 1794 1795 static int mesh_resume(struct macio_dev *mdev) 1796 { 1797 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1798 unsigned long flags; 1799 1800 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON) 1801 return 0; 1802 1803 set_mesh_power(ms, 1); 1804 mesh_init(ms); 1805 spin_lock_irqsave(ms->host->host_lock, flags); 1806 mesh_start(ms); 1807 spin_unlock_irqrestore(ms->host->host_lock, flags); 1808 enable_irq(ms->meshintr); 1809 scsi_unblock_requests(ms->host); 1810 1811 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON; 1812 1813 return 0; 1814 } 1815 1816 #endif /* CONFIG_PM */ 1817 1818 /* 1819 * If we leave drives set for synchronous transfers (especially 1820 * CDROMs), and reboot to MacOS, it gets confused, poor thing. 1821 * So, on reboot we reset the SCSI bus. 1822 */ 1823 static int mesh_shutdown(struct macio_dev *mdev) 1824 { 1825 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1826 volatile struct mesh_regs __iomem *mr; 1827 unsigned long flags; 1828 1829 printk(KERN_INFO "resetting MESH scsi bus(es)\n"); 1830 spin_lock_irqsave(ms->host->host_lock, flags); 1831 mr = ms->mesh; 1832 out_8(&mr->intr_mask, 0); 1833 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1834 out_8(&mr->bus_status1, BS1_RST); 1835 mesh_flush_io(mr); 1836 udelay(30); 1837 out_8(&mr->bus_status1, 0); 1838 spin_unlock_irqrestore(ms->host->host_lock, flags); 1839 1840 return 0; 1841 } 1842 1843 static struct scsi_host_template mesh_template = { 1844 .proc_name = "mesh", 1845 .name = "MESH", 1846 .queuecommand = mesh_queue, 1847 .eh_abort_handler = mesh_abort, 1848 .eh_host_reset_handler = mesh_host_reset, 1849 .can_queue = 20, 1850 .this_id = 7, 1851 .sg_tablesize = SG_ALL, 1852 .cmd_per_lun = 2, 1853 .use_clustering = DISABLE_CLUSTERING, 1854 }; 1855 1856 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match) 1857 { 1858 struct device_node *mesh = macio_get_of_node(mdev); 1859 struct pci_dev* pdev = macio_get_pci_dev(mdev); 1860 int tgt, minper; 1861 const int *cfp; 1862 struct mesh_state *ms; 1863 struct Scsi_Host *mesh_host; 1864 void *dma_cmd_space; 1865 dma_addr_t dma_cmd_bus; 1866 1867 switch (mdev->bus->chip->type) { 1868 case macio_heathrow: 1869 case macio_gatwick: 1870 case macio_paddington: 1871 use_active_neg = 0; 1872 break; 1873 default: 1874 use_active_neg = SEQ_ACTIVE_NEG; 1875 } 1876 1877 if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) { 1878 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs" 1879 " (got %d,%d)\n", macio_resource_count(mdev), 1880 macio_irq_count(mdev)); 1881 return -ENODEV; 1882 } 1883 1884 if (macio_request_resources(mdev, "mesh") != 0) { 1885 printk(KERN_ERR "mesh: unable to request memory resources"); 1886 return -EBUSY; 1887 } 1888 mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state)); 1889 if (mesh_host == NULL) { 1890 printk(KERN_ERR "mesh: couldn't register host"); 1891 goto out_release; 1892 } 1893 1894 /* Old junk for root discovery, that will die ultimately */ 1895 #if !defined(MODULE) 1896 note_scsi_host(mesh, mesh_host); 1897 #endif 1898 1899 mesh_host->base = macio_resource_start(mdev, 0); 1900 mesh_host->irq = macio_irq(mdev, 0); 1901 ms = (struct mesh_state *) mesh_host->hostdata; 1902 macio_set_drvdata(mdev, ms); 1903 ms->host = mesh_host; 1904 ms->mdev = mdev; 1905 ms->pdev = pdev; 1906 1907 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000); 1908 if (ms->mesh == NULL) { 1909 printk(KERN_ERR "mesh: can't map registers\n"); 1910 goto out_free; 1911 } 1912 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000); 1913 if (ms->dma == NULL) { 1914 printk(KERN_ERR "mesh: can't map registers\n"); 1915 iounmap(ms->mesh); 1916 goto out_free; 1917 } 1918 1919 ms->meshintr = macio_irq(mdev, 0); 1920 ms->dmaintr = macio_irq(mdev, 1); 1921 1922 /* Space for dma command list: +1 for stop command, 1923 * +1 to allow for aligning. 1924 */ 1925 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd); 1926 1927 /* We use the PCI APIs for now until the generic one gets fixed 1928 * enough or until we get some macio-specific versions 1929 */ 1930 dma_cmd_space = pci_alloc_consistent(macio_get_pci_dev(mdev), 1931 ms->dma_cmd_size, 1932 &dma_cmd_bus); 1933 if (dma_cmd_space == NULL) { 1934 printk(KERN_ERR "mesh: can't allocate DMA table\n"); 1935 goto out_unmap; 1936 } 1937 memset(dma_cmd_space, 0, ms->dma_cmd_size); 1938 1939 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space); 1940 ms->dma_cmd_space = dma_cmd_space; 1941 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds) 1942 - (unsigned long)dma_cmd_space; 1943 ms->current_req = NULL; 1944 for (tgt = 0; tgt < 8; ++tgt) { 1945 ms->tgts[tgt].sdtr_state = do_sdtr; 1946 ms->tgts[tgt].sync_params = ASYNC_PARAMS; 1947 ms->tgts[tgt].current_req = NULL; 1948 } 1949 1950 if ((cfp = of_get_property(mesh, "clock-frequency", NULL))) 1951 ms->clk_freq = *cfp; 1952 else { 1953 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n"); 1954 ms->clk_freq = 50000000; 1955 } 1956 1957 /* The maximum sync rate is clock / 5; increase 1958 * mesh_sync_period if necessary. 1959 */ 1960 minper = 1000000000 / (ms->clk_freq / 5); /* ns */ 1961 if (mesh_sync_period < minper) 1962 mesh_sync_period = minper; 1963 1964 /* Power up the chip */ 1965 set_mesh_power(ms, 1); 1966 1967 /* Set it up */ 1968 mesh_init(ms); 1969 1970 /* Request interrupt */ 1971 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) { 1972 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr); 1973 goto out_shutdown; 1974 } 1975 1976 /* Add scsi host & scan */ 1977 if (scsi_add_host(mesh_host, &mdev->ofdev.dev)) 1978 goto out_release_irq; 1979 scsi_scan_host(mesh_host); 1980 1981 return 0; 1982 1983 out_release_irq: 1984 free_irq(ms->meshintr, ms); 1985 out_shutdown: 1986 /* shutdown & reset bus in case of error or macos can be confused 1987 * at reboot if the bus was set to synchronous mode already 1988 */ 1989 mesh_shutdown(mdev); 1990 set_mesh_power(ms, 0); 1991 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size, 1992 ms->dma_cmd_space, ms->dma_cmd_bus); 1993 out_unmap: 1994 iounmap(ms->dma); 1995 iounmap(ms->mesh); 1996 out_free: 1997 scsi_host_put(mesh_host); 1998 out_release: 1999 macio_release_resources(mdev); 2000 2001 return -ENODEV; 2002 } 2003 2004 static int mesh_remove(struct macio_dev *mdev) 2005 { 2006 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 2007 struct Scsi_Host *mesh_host = ms->host; 2008 2009 scsi_remove_host(mesh_host); 2010 2011 free_irq(ms->meshintr, ms); 2012 2013 /* Reset scsi bus */ 2014 mesh_shutdown(mdev); 2015 2016 /* Shut down chip & termination */ 2017 set_mesh_power(ms, 0); 2018 2019 /* Unmap registers & dma controller */ 2020 iounmap(ms->mesh); 2021 iounmap(ms->dma); 2022 2023 /* Free DMA commands memory */ 2024 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size, 2025 ms->dma_cmd_space, ms->dma_cmd_bus); 2026 2027 /* Release memory resources */ 2028 macio_release_resources(mdev); 2029 2030 scsi_host_put(mesh_host); 2031 2032 return 0; 2033 } 2034 2035 2036 static struct of_device_id mesh_match[] = 2037 { 2038 { 2039 .name = "mesh", 2040 }, 2041 { 2042 .type = "scsi", 2043 .compatible = "chrp,mesh0" 2044 }, 2045 {}, 2046 }; 2047 MODULE_DEVICE_TABLE (of, mesh_match); 2048 2049 static struct macio_driver mesh_driver = 2050 { 2051 .name = "mesh", 2052 .match_table = mesh_match, 2053 .probe = mesh_probe, 2054 .remove = mesh_remove, 2055 .shutdown = mesh_shutdown, 2056 #ifdef CONFIG_PM 2057 .suspend = mesh_suspend, 2058 .resume = mesh_resume, 2059 #endif 2060 }; 2061 2062 2063 static int __init init_mesh(void) 2064 { 2065 2066 /* Calculate sync rate from module parameters */ 2067 if (sync_rate > 10) 2068 sync_rate = 10; 2069 if (sync_rate > 0) { 2070 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate); 2071 mesh_sync_period = 1000 / sync_rate; /* ns */ 2072 mesh_sync_offset = 15; 2073 } else 2074 printk(KERN_INFO "mesh: configured for asynchronous\n"); 2075 2076 return macio_register_driver(&mesh_driver); 2077 } 2078 2079 static void __exit exit_mesh(void) 2080 { 2081 return macio_unregister_driver(&mesh_driver); 2082 } 2083 2084 module_init(init_mesh); 2085 module_exit(exit_mesh); 2086