1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS) 24 #define CONFIG_SCSI_LPFC_DEBUG_FS 25 #endif 26 27 #define LPFC_ACTIVE_MBOX_WAIT_CNT 100 28 #define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000 29 #define LPFC_XRI_EXCH_BUSY_WAIT_T1 10 30 #define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000 31 #define LPFC_RPI_LOW_WATER_MARK 10 32 33 #define LPFC_UNREG_FCF 1 34 #define LPFC_SKIP_UNREG_FCF 0 35 36 /* Amount of time in seconds for waiting FCF rediscovery to complete */ 37 #define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */ 38 39 /* Number of SGL entries can be posted in a 4KB nonembedded mbox command */ 40 #define LPFC_NEMBED_MBOX_SGL_CNT 254 41 42 /* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */ 43 #define LPFC_HBA_HDWQ_MIN 0 44 #define LPFC_HBA_HDWQ_MAX 128 45 #define LPFC_HBA_HDWQ_DEF 0 46 47 /* Common buffer size to accomidate SCSI and NVME IO buffers */ 48 #define LPFC_COMMON_IO_BUF_SZ 768 49 50 /* 51 * Provide the default FCF Record attributes used by the driver 52 * when nonFIP mode is configured and there is no other default 53 * FCF Record attributes. 54 */ 55 #define LPFC_FCOE_FCF_DEF_INDEX 0 56 #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF 57 #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF 58 59 #define LPFC_FCOE_NULL_VID 0xFFF 60 #define LPFC_FCOE_IGNORE_VID 0xFFFF 61 62 /* First 3 bytes of default FCF MAC is specified by FC_MAP */ 63 #define LPFC_FCOE_FCF_MAC3 0xFF 64 #define LPFC_FCOE_FCF_MAC4 0xFF 65 #define LPFC_FCOE_FCF_MAC5 0xFE 66 #define LPFC_FCOE_FCF_MAP0 0x0E 67 #define LPFC_FCOE_FCF_MAP1 0xFC 68 #define LPFC_FCOE_FCF_MAP2 0x00 69 #define LPFC_FCOE_MAX_RCV_SIZE 0x800 70 #define LPFC_FCOE_FKA_ADV_PER 0 71 #define LPFC_FCOE_FIP_PRIORITY 0x80 72 73 #define sli4_sid_from_fc_hdr(fc_hdr) \ 74 ((fc_hdr)->fh_s_id[0] << 16 | \ 75 (fc_hdr)->fh_s_id[1] << 8 | \ 76 (fc_hdr)->fh_s_id[2]) 77 78 #define sli4_did_from_fc_hdr(fc_hdr) \ 79 ((fc_hdr)->fh_d_id[0] << 16 | \ 80 (fc_hdr)->fh_d_id[1] << 8 | \ 81 (fc_hdr)->fh_d_id[2]) 82 83 #define sli4_fctl_from_fc_hdr(fc_hdr) \ 84 ((fc_hdr)->fh_f_ctl[0] << 16 | \ 85 (fc_hdr)->fh_f_ctl[1] << 8 | \ 86 (fc_hdr)->fh_f_ctl[2]) 87 88 #define sli4_type_from_fc_hdr(fc_hdr) \ 89 ((fc_hdr)->fh_type) 90 91 #define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000 92 93 #define INT_FW_UPGRADE 0 94 #define RUN_FW_UPGRADE 1 95 96 enum lpfc_sli4_queue_type { 97 LPFC_EQ, 98 LPFC_GCQ, 99 LPFC_MCQ, 100 LPFC_WCQ, 101 LPFC_RCQ, 102 LPFC_MQ, 103 LPFC_WQ, 104 LPFC_HRQ, 105 LPFC_DRQ 106 }; 107 108 /* The queue sub-type defines the functional purpose of the queue */ 109 enum lpfc_sli4_queue_subtype { 110 LPFC_NONE, 111 LPFC_MBOX, 112 LPFC_IO, 113 LPFC_ELS, 114 LPFC_NVMET, 115 LPFC_NVME_LS, 116 LPFC_USOL 117 }; 118 119 /* RQ buffer list */ 120 struct lpfc_rqb { 121 uint16_t entry_count; /* Current number of RQ slots */ 122 uint16_t buffer_count; /* Current number of buffers posted */ 123 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */ 124 /* Callback for HBQ buffer allocation */ 125 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *); 126 /* Callback for HBQ buffer free */ 127 void (*rqb_free_buffer)(struct lpfc_hba *, 128 struct rqb_dmabuf *); 129 }; 130 131 struct lpfc_queue { 132 struct list_head list; 133 struct list_head wq_list; 134 struct list_head wqfull_list; 135 enum lpfc_sli4_queue_type type; 136 enum lpfc_sli4_queue_subtype subtype; 137 struct lpfc_hba *phba; 138 struct list_head child_list; 139 struct list_head page_list; 140 struct list_head sgl_list; 141 struct list_head cpu_list; 142 uint32_t entry_count; /* Number of entries to support on the queue */ 143 uint32_t entry_size; /* Size of each queue entry. */ 144 uint32_t entry_cnt_per_pg; 145 uint32_t notify_interval; /* Queue Notification Interval 146 * For chip->host queues (EQ, CQ, RQ): 147 * specifies the interval (number of 148 * entries) where the doorbell is rung to 149 * notify the chip of entry consumption. 150 * For host->chip queues (WQ): 151 * specifies the interval (number of 152 * entries) where consumption CQE is 153 * requested to indicate WQ entries 154 * consumed by the chip. 155 * Not used on an MQ. 156 */ 157 #define LPFC_EQ_NOTIFY_INTRVL 16 158 #define LPFC_CQ_NOTIFY_INTRVL 16 159 #define LPFC_WQ_NOTIFY_INTRVL 16 160 #define LPFC_RQ_NOTIFY_INTRVL 16 161 uint32_t max_proc_limit; /* Queue Processing Limit 162 * For chip->host queues (EQ, CQ): 163 * specifies the maximum number of 164 * entries to be consumed in one 165 * processing iteration sequence. Queue 166 * will be rearmed after each iteration. 167 * Not used on an MQ, RQ or WQ. 168 */ 169 #define LPFC_EQ_MAX_PROC_LIMIT 256 170 #define LPFC_CQ_MIN_PROC_LIMIT 64 171 #define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096 172 #define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024 173 #define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64 174 #define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT 175 #define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT 176 uint32_t queue_claimed; /* indicates queue is being processed */ 177 uint32_t queue_id; /* Queue ID assigned by the hardware */ 178 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */ 179 uint32_t host_index; /* The host's index for putting or getting */ 180 uint32_t hba_index; /* The last known hba index for get or put */ 181 uint32_t q_mode; 182 183 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */ 184 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */ 185 186 uint16_t page_count; /* Number of pages allocated for this queue */ 187 uint16_t page_size; /* size of page allocated for this queue */ 188 #define LPFC_EXPANDED_PAGE_SIZE 16384 189 #define LPFC_DEFAULT_PAGE_SIZE 4096 190 uint16_t chann; /* Hardware Queue association WQ/CQ */ 191 /* CPU affinity for EQ */ 192 #define LPFC_FIND_BY_EQ 0 193 #define LPFC_FIND_BY_HDWQ 1 194 uint8_t db_format; 195 #define LPFC_DB_RING_FORMAT 0x01 196 #define LPFC_DB_LIST_FORMAT 0x02 197 uint8_t q_flag; 198 #define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */ 199 #define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */ 200 #define LPFC_NVMET_CQ_NOTIFY 4 201 void __iomem *db_regaddr; 202 uint16_t dpp_enable; 203 uint16_t dpp_id; 204 void __iomem *dpp_regaddr; 205 206 /* For q stats */ 207 uint32_t q_cnt_1; 208 uint32_t q_cnt_2; 209 uint32_t q_cnt_3; 210 uint64_t q_cnt_4; 211 /* defines for EQ stats */ 212 #define EQ_max_eqe q_cnt_1 213 #define EQ_no_entry q_cnt_2 214 #define EQ_cqe_cnt q_cnt_3 215 #define EQ_processed q_cnt_4 216 217 /* defines for CQ stats */ 218 #define CQ_mbox q_cnt_1 219 #define CQ_max_cqe q_cnt_1 220 #define CQ_release_wqe q_cnt_2 221 #define CQ_xri_aborted q_cnt_3 222 #define CQ_wq q_cnt_4 223 224 /* defines for WQ stats */ 225 #define WQ_overflow q_cnt_1 226 #define WQ_posted q_cnt_4 227 228 /* defines for RQ stats */ 229 #define RQ_no_posted_buf q_cnt_1 230 #define RQ_no_buf_found q_cnt_2 231 #define RQ_buf_posted q_cnt_3 232 #define RQ_rcv_buf q_cnt_4 233 234 struct work_struct irqwork; 235 struct work_struct spwork; 236 struct delayed_work sched_irqwork; 237 struct delayed_work sched_spwork; 238 239 uint64_t isr_timestamp; 240 uint16_t hdwq; 241 uint16_t last_cpu; /* most recent cpu */ 242 uint8_t qe_valid; 243 struct lpfc_queue *assoc_qp; 244 void **q_pgs; /* array to index entries per page */ 245 }; 246 247 struct lpfc_sli4_link { 248 uint32_t speed; 249 uint8_t duplex; 250 uint8_t status; 251 uint8_t type; 252 uint8_t number; 253 uint8_t fault; 254 uint32_t logical_speed; 255 uint16_t topology; 256 }; 257 258 struct lpfc_fcf_rec { 259 uint8_t fabric_name[8]; 260 uint8_t switch_name[8]; 261 uint8_t mac_addr[6]; 262 uint16_t fcf_indx; 263 uint32_t priority; 264 uint16_t vlan_id; 265 uint32_t addr_mode; 266 uint32_t flag; 267 #define BOOT_ENABLE 0x01 268 #define RECORD_VALID 0x02 269 }; 270 271 struct lpfc_fcf_pri_rec { 272 uint16_t fcf_index; 273 #define LPFC_FCF_ON_PRI_LIST 0x0001 274 #define LPFC_FCF_FLOGI_FAILED 0x0002 275 uint16_t flag; 276 uint32_t priority; 277 }; 278 279 struct lpfc_fcf_pri { 280 struct list_head list; 281 struct lpfc_fcf_pri_rec fcf_rec; 282 }; 283 284 /* 285 * Maximum FCF table index, it is for driver internal book keeping, it 286 * just needs to be no less than the supported HBA's FCF table size. 287 */ 288 #define LPFC_SLI4_FCF_TBL_INDX_MAX 32 289 290 struct lpfc_fcf { 291 uint16_t fcfi; 292 uint32_t fcf_flag; 293 #define FCF_AVAILABLE 0x01 /* FCF available for discovery */ 294 #define FCF_REGISTERED 0x02 /* FCF registered with FW */ 295 #define FCF_SCAN_DONE 0x04 /* FCF table scan done */ 296 #define FCF_IN_USE 0x08 /* Atleast one discovery completed */ 297 #define FCF_INIT_DISC 0x10 /* Initial FCF discovery */ 298 #define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */ 299 #define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */ 300 #define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC) 301 #define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */ 302 #define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */ 303 #define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */ 304 #define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT) 305 uint16_t fcf_redisc_attempted; 306 uint32_t addr_mode; 307 uint32_t eligible_fcf_cnt; 308 struct lpfc_fcf_rec current_rec; 309 struct lpfc_fcf_rec failover_rec; 310 struct list_head fcf_pri_list; 311 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX]; 312 uint32_t current_fcf_scan_pri; 313 struct timer_list redisc_wait; 314 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */ 315 }; 316 317 318 #define LPFC_REGION23_SIGNATURE "RG23" 319 #define LPFC_REGION23_VERSION 1 320 #define LPFC_REGION23_LAST_REC 0xff 321 #define DRIVER_SPECIFIC_TYPE 0xA2 322 #define LINUX_DRIVER_ID 0x20 323 #define PORT_STE_TYPE 0x1 324 325 struct lpfc_fip_param_hdr { 326 uint8_t type; 327 #define FCOE_PARAM_TYPE 0xA0 328 uint8_t length; 329 #define FCOE_PARAM_LENGTH 2 330 uint8_t parm_version; 331 #define FIPP_VERSION 0x01 332 uint8_t parm_flags; 333 #define lpfc_fip_param_hdr_fipp_mode_SHIFT 6 334 #define lpfc_fip_param_hdr_fipp_mode_MASK 0x3 335 #define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags 336 #define FIPP_MODE_ON 0x1 337 #define FIPP_MODE_OFF 0x0 338 #define FIPP_VLAN_VALID 0x1 339 }; 340 341 struct lpfc_fcoe_params { 342 uint8_t fc_map[3]; 343 uint8_t reserved1; 344 uint16_t vlan_tag; 345 uint8_t reserved[2]; 346 }; 347 348 struct lpfc_fcf_conn_hdr { 349 uint8_t type; 350 #define FCOE_CONN_TBL_TYPE 0xA1 351 uint8_t length; /* words */ 352 uint8_t reserved[2]; 353 }; 354 355 struct lpfc_fcf_conn_rec { 356 uint16_t flags; 357 #define FCFCNCT_VALID 0x0001 358 #define FCFCNCT_BOOT 0x0002 359 #define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */ 360 #define FCFCNCT_FBNM_VALID 0x0008 361 #define FCFCNCT_SWNM_VALID 0x0010 362 #define FCFCNCT_VLAN_VALID 0x0020 363 #define FCFCNCT_AM_VALID 0x0040 364 #define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */ 365 #define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */ 366 367 uint16_t vlan_tag; 368 uint8_t fabric_name[8]; 369 uint8_t switch_name[8]; 370 }; 371 372 struct lpfc_fcf_conn_entry { 373 struct list_head list; 374 struct lpfc_fcf_conn_rec conn_rec; 375 }; 376 377 /* 378 * Define the host's bootstrap mailbox. This structure contains 379 * the member attributes needed to create, use, and destroy the 380 * bootstrap mailbox region. 381 * 382 * The macro definitions for the bmbx data structure are defined 383 * in lpfc_hw4.h with the register definition. 384 */ 385 struct lpfc_bmbx { 386 struct lpfc_dmabuf *dmabuf; 387 struct dma_address dma_address; 388 void *avirt; 389 dma_addr_t aphys; 390 uint32_t bmbx_size; 391 }; 392 393 #define LPFC_EQE_SIZE LPFC_EQE_SIZE_4 394 395 #define LPFC_EQE_SIZE_4B 4 396 #define LPFC_EQE_SIZE_16B 16 397 #define LPFC_CQE_SIZE 16 398 #define LPFC_WQE_SIZE 64 399 #define LPFC_WQE128_SIZE 128 400 #define LPFC_MQE_SIZE 256 401 #define LPFC_RQE_SIZE 8 402 403 #define LPFC_EQE_DEF_COUNT 1024 404 #define LPFC_CQE_DEF_COUNT 1024 405 #define LPFC_CQE_EXP_COUNT 4096 406 #define LPFC_WQE_DEF_COUNT 256 407 #define LPFC_WQE_EXP_COUNT 1024 408 #define LPFC_MQE_DEF_COUNT 16 409 #define LPFC_RQE_DEF_COUNT 512 410 411 #define LPFC_QUEUE_NOARM false 412 #define LPFC_QUEUE_REARM true 413 414 415 /* 416 * SLI4 CT field defines 417 */ 418 #define SLI4_CT_RPI 0 419 #define SLI4_CT_VPI 1 420 #define SLI4_CT_VFI 2 421 #define SLI4_CT_FCFI 3 422 423 /* 424 * SLI4 specific data structures 425 */ 426 struct lpfc_max_cfg_param { 427 uint16_t max_xri; 428 uint16_t xri_base; 429 uint16_t xri_used; 430 uint16_t max_rpi; 431 uint16_t rpi_base; 432 uint16_t rpi_used; 433 uint16_t max_vpi; 434 uint16_t vpi_base; 435 uint16_t vpi_used; 436 uint16_t max_vfi; 437 uint16_t vfi_base; 438 uint16_t vfi_used; 439 uint16_t max_fcfi; 440 uint16_t fcfi_used; 441 uint16_t max_eq; 442 uint16_t max_rq; 443 uint16_t max_cq; 444 uint16_t max_wq; 445 }; 446 447 struct lpfc_hba; 448 /* SLI4 HBA multi-fcp queue handler struct */ 449 #define LPFC_SLI4_HANDLER_NAME_SZ 16 450 struct lpfc_hba_eq_hdl { 451 uint32_t idx; 452 char handler_name[LPFC_SLI4_HANDLER_NAME_SZ]; 453 struct lpfc_hba *phba; 454 struct lpfc_queue *eq; 455 }; 456 457 /*BB Credit recovery value*/ 458 struct lpfc_bbscn_params { 459 uint32_t word0; 460 #define lpfc_bbscn_min_SHIFT 0 461 #define lpfc_bbscn_min_MASK 0x0000000F 462 #define lpfc_bbscn_min_WORD word0 463 #define lpfc_bbscn_max_SHIFT 4 464 #define lpfc_bbscn_max_MASK 0x0000000F 465 #define lpfc_bbscn_max_WORD word0 466 #define lpfc_bbscn_def_SHIFT 8 467 #define lpfc_bbscn_def_MASK 0x0000000F 468 #define lpfc_bbscn_def_WORD word0 469 }; 470 471 /* Port Capabilities for SLI4 Parameters */ 472 struct lpfc_pc_sli4_params { 473 uint32_t supported; 474 uint32_t if_type; 475 uint32_t sli_rev; 476 uint32_t sli_family; 477 uint32_t featurelevel_1; 478 uint32_t featurelevel_2; 479 uint32_t proto_types; 480 #define LPFC_SLI4_PROTO_FCOE 0x0000001 481 #define LPFC_SLI4_PROTO_FC 0x0000002 482 #define LPFC_SLI4_PROTO_NIC 0x0000004 483 #define LPFC_SLI4_PROTO_ISCSI 0x0000008 484 #define LPFC_SLI4_PROTO_RDMA 0x0000010 485 uint32_t sge_supp_len; 486 uint32_t if_page_sz; 487 uint32_t rq_db_window; 488 uint32_t loopbk_scope; 489 uint32_t oas_supported; 490 uint32_t eq_pages_max; 491 uint32_t eqe_size; 492 uint32_t cq_pages_max; 493 uint32_t cqe_size; 494 uint32_t mq_pages_max; 495 uint32_t mqe_size; 496 uint32_t mq_elem_cnt; 497 uint32_t wq_pages_max; 498 uint32_t wqe_size; 499 uint32_t rq_pages_max; 500 uint32_t rqe_size; 501 uint32_t hdr_pages_max; 502 uint32_t hdr_size; 503 uint32_t hdr_pp_align; 504 uint32_t sgl_pages_max; 505 uint32_t sgl_pp_align; 506 uint8_t cqv; 507 uint8_t mqv; 508 uint8_t wqv; 509 uint8_t rqv; 510 uint8_t eqav; 511 uint8_t cqav; 512 uint8_t wqsize; 513 uint8_t bv1s; 514 #define LPFC_WQ_SZ64_SUPPORT 1 515 #define LPFC_WQ_SZ128_SUPPORT 2 516 uint8_t wqpcnt; 517 uint8_t nvme; 518 }; 519 520 #define LPFC_CQ_4K_PAGE_SZ 0x1 521 #define LPFC_CQ_16K_PAGE_SZ 0x4 522 #define LPFC_WQ_4K_PAGE_SZ 0x1 523 #define LPFC_WQ_16K_PAGE_SZ 0x4 524 525 struct lpfc_iov { 526 uint32_t pf_number; 527 uint32_t vf_number; 528 }; 529 530 struct lpfc_sli4_lnk_info { 531 uint8_t lnk_dv; 532 #define LPFC_LNK_DAT_INVAL 0 533 #define LPFC_LNK_DAT_VAL 1 534 uint8_t lnk_tp; 535 #define LPFC_LNK_GE 0x0 /* FCoE */ 536 #define LPFC_LNK_FC 0x1 /* FC */ 537 #define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */ 538 uint8_t lnk_no; 539 uint8_t optic_state; 540 }; 541 542 #define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \ 543 LPFC_FOF_IO_CHAN_NUM) 544 545 /* Used for IRQ vector to CPU mapping */ 546 struct lpfc_vector_map_info { 547 uint16_t phys_id; 548 uint16_t core_id; 549 uint16_t irq; 550 uint16_t eq; 551 uint16_t hdwq; 552 uint16_t flag; 553 #define LPFC_CPU_MAP_HYPER 0x1 554 #define LPFC_CPU_MAP_UNASSIGN 0x2 555 #define LPFC_CPU_FIRST_IRQ 0x4 556 }; 557 #define LPFC_VECTOR_MAP_EMPTY 0xffff 558 559 /* Multi-XRI pool */ 560 #define XRI_BATCH 8 561 562 struct lpfc_pbl_pool { 563 struct list_head list; 564 u32 count; 565 spinlock_t lock; /* lock for pbl_pool*/ 566 }; 567 568 struct lpfc_pvt_pool { 569 u32 low_watermark; 570 u32 high_watermark; 571 572 struct list_head list; 573 u32 count; 574 spinlock_t lock; /* lock for pvt_pool */ 575 }; 576 577 struct lpfc_multixri_pool { 578 u32 xri_limit; 579 580 /* Starting point when searching a pbl_pool with round-robin method */ 581 u32 rrb_next_hwqid; 582 583 /* Used by lpfc_adjust_pvt_pool_count. 584 * io_req_count is incremented by 1 during IO submission. The heartbeat 585 * handler uses these two variables to determine if pvt_pool is idle or 586 * busy. 587 */ 588 u32 prev_io_req_count; 589 u32 io_req_count; 590 591 /* statistics */ 592 u32 pbl_empty_count; 593 #ifdef LPFC_MXP_STAT 594 u32 above_limit_count; 595 u32 below_limit_count; 596 u32 local_pbl_hit_count; 597 u32 other_pbl_hit_count; 598 u32 stat_max_hwm; 599 600 #define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */ 601 u32 stat_pbl_count; 602 u32 stat_pvt_count; 603 u32 stat_busy_count; 604 u32 stat_snapshot_taken; 605 #endif 606 607 /* TODO: Separate pvt_pool into get and put list */ 608 struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */ 609 struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */ 610 }; 611 612 struct lpfc_fc4_ctrl_stat { 613 u32 input_requests; 614 u32 output_requests; 615 u32 control_requests; 616 u32 io_cmpls; 617 }; 618 619 #ifdef LPFC_HDWQ_LOCK_STAT 620 struct lpfc_lock_stat { 621 uint32_t alloc_xri_get; 622 uint32_t alloc_xri_put; 623 uint32_t free_xri; 624 uint32_t wq_access; 625 uint32_t alloc_pvt_pool; 626 uint32_t mv_from_pvt_pool; 627 uint32_t mv_to_pub_pool; 628 uint32_t mv_to_pvt_pool; 629 uint32_t free_pub_pool; 630 uint32_t free_pvt_pool; 631 }; 632 #endif 633 634 struct lpfc_eq_intr_info { 635 struct list_head list; 636 uint32_t icnt; 637 }; 638 639 /* SLI4 HBA data structure entries */ 640 struct lpfc_sli4_hdw_queue { 641 /* Pointers to the constructed SLI4 queues */ 642 struct lpfc_queue *hba_eq; /* Event queues for HBA */ 643 struct lpfc_queue *io_cq; /* Fast-path FCP & NVME compl queue */ 644 struct lpfc_queue *io_wq; /* Fast-path FCP & NVME work queue */ 645 uint16_t io_cq_map; 646 647 /* Keep track of IO buffers for this hardware queue */ 648 spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */ 649 struct list_head lpfc_io_buf_list_get; 650 spinlock_t io_buf_list_put_lock; /* Common buf free list lock */ 651 struct list_head lpfc_io_buf_list_put; 652 spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */ 653 struct list_head lpfc_abts_io_buf_list; 654 uint32_t total_io_bufs; 655 uint32_t get_io_bufs; 656 uint32_t put_io_bufs; 657 uint32_t empty_io_bufs; 658 uint32_t abts_scsi_io_bufs; 659 uint32_t abts_nvme_io_bufs; 660 661 /* Multi-XRI pool per HWQ */ 662 struct lpfc_multixri_pool *p_multixri_pool; 663 664 /* FC-4 Stats counters */ 665 struct lpfc_fc4_ctrl_stat nvme_cstat; 666 struct lpfc_fc4_ctrl_stat scsi_cstat; 667 #ifdef LPFC_HDWQ_LOCK_STAT 668 struct lpfc_lock_stat lock_conflict; 669 #endif 670 671 #ifdef CONFIG_SCSI_LPFC_DEBUG_FS 672 #define LPFC_CHECK_CPU_CNT 128 673 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT]; 674 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT]; 675 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT]; 676 #endif 677 678 /* Per HDWQ pool resources */ 679 struct list_head sgl_list; 680 struct list_head cmd_rsp_buf_list; 681 682 /* Lock for syncing Per HDWQ pool resources */ 683 spinlock_t hdwq_lock; 684 }; 685 686 #ifdef LPFC_HDWQ_LOCK_STAT 687 /* compile time trylock stats */ 688 #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \ 689 { \ 690 int only_once = 1; \ 691 while (spin_trylock_irqsave(lock, flag) == 0) { \ 692 if (only_once) { \ 693 only_once = 0; \ 694 qp->lock_conflict.lstat++; \ 695 } \ 696 } \ 697 } 698 #define lpfc_qp_spin_lock(lock, qp, lstat) \ 699 { \ 700 int only_once = 1; \ 701 while (spin_trylock(lock) == 0) { \ 702 if (only_once) { \ 703 only_once = 0; \ 704 qp->lock_conflict.lstat++; \ 705 } \ 706 } \ 707 } 708 #else 709 #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \ 710 spin_lock_irqsave(lock, flag) 711 #define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock) 712 #endif 713 714 struct lpfc_sli4_hba { 715 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for 716 * config space registers 717 */ 718 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for 719 * control registers 720 */ 721 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for 722 * doorbell registers 723 */ 724 void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for 725 * dpp registers 726 */ 727 union { 728 struct { 729 /* IF Type 0, BAR 0 PCI cfg space reg mem map */ 730 void __iomem *UERRLOregaddr; 731 void __iomem *UERRHIregaddr; 732 void __iomem *UEMASKLOregaddr; 733 void __iomem *UEMASKHIregaddr; 734 } if_type0; 735 struct { 736 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */ 737 void __iomem *STATUSregaddr; 738 void __iomem *CTRLregaddr; 739 void __iomem *ERR1regaddr; 740 #define SLIPORT_ERR1_REG_ERR_CODE_1 0x1 741 #define SLIPORT_ERR1_REG_ERR_CODE_2 0x2 742 void __iomem *ERR2regaddr; 743 #define SLIPORT_ERR2_REG_FW_RESTART 0x0 744 #define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1 745 #define SLIPORT_ERR2_REG_FORCED_DUMP 0x2 746 #define SLIPORT_ERR2_REG_FAILURE_EQ 0x3 747 #define SLIPORT_ERR2_REG_FAILURE_CQ 0x4 748 #define SLIPORT_ERR2_REG_FAILURE_BUS 0x5 749 #define SLIPORT_ERR2_REG_FAILURE_RQ 0x6 750 void __iomem *EQDregaddr; 751 } if_type2; 752 } u; 753 754 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */ 755 void __iomem *PSMPHRregaddr; 756 757 /* Well-known SLI INTF register memory map. */ 758 void __iomem *SLIINTFregaddr; 759 760 /* IF type 0, BAR 1 function CSR register memory map */ 761 void __iomem *ISRregaddr; /* HST_ISR register */ 762 void __iomem *IMRregaddr; /* HST_IMR register */ 763 void __iomem *ISCRregaddr; /* HST_ISCR register */ 764 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */ 765 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */ 766 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */ 767 void __iomem *CQDBregaddr; /* CQ_DOORBELL register */ 768 void __iomem *EQDBregaddr; /* EQ_DOORBELL register */ 769 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */ 770 void __iomem *BMBXregaddr; /* BootStrap MBX register */ 771 772 uint32_t ue_mask_lo; 773 uint32_t ue_mask_hi; 774 uint32_t ue_to_sr; 775 uint32_t ue_to_rp; 776 struct lpfc_register sli_intf; 777 struct lpfc_pc_sli4_params pc_sli4_params; 778 struct lpfc_bbscn_params bbscn_params; 779 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */ 780 781 void (*sli4_eq_clr_intr)(struct lpfc_queue *q); 782 void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq, 783 uint32_t count, bool arm); 784 void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq, 785 uint32_t count, bool arm); 786 787 /* Pointers to the constructed SLI4 queues */ 788 struct lpfc_sli4_hdw_queue *hdwq; 789 struct list_head lpfc_wq_list; 790 791 /* Pointers to the constructed SLI4 queues for NVMET */ 792 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */ 793 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */ 794 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */ 795 796 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */ 797 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */ 798 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */ 799 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */ 800 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */ 801 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */ 802 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */ 803 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */ 804 805 struct lpfc_name wwnn; 806 struct lpfc_name wwpn; 807 808 uint32_t fw_func_mode; /* FW function protocol mode */ 809 uint32_t ulp0_mode; /* ULP0 protocol mode */ 810 uint32_t ulp1_mode; /* ULP1 protocol mode */ 811 812 /* Optimized Access Storage specific queues/structures */ 813 uint64_t oas_next_lun; 814 uint8_t oas_next_tgt_wwpn[8]; 815 uint8_t oas_next_vpt_wwpn[8]; 816 817 /* Setup information for various queue parameters */ 818 int eq_esize; 819 int eq_ecount; 820 int cq_esize; 821 int cq_ecount; 822 int wq_esize; 823 int wq_ecount; 824 int mq_esize; 825 int mq_ecount; 826 int rq_esize; 827 int rq_ecount; 828 #define LPFC_SP_EQ_MAX_INTR_SEC 10000 829 #define LPFC_FP_EQ_MAX_INTR_SEC 10000 830 831 uint32_t intr_enable; 832 struct lpfc_bmbx bmbx; 833 struct lpfc_max_cfg_param max_cfg_param; 834 uint16_t extents_in_use; /* must allocate resource extents. */ 835 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */ 836 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */ 837 uint16_t next_rpi; 838 uint16_t io_xri_max; 839 uint16_t io_xri_cnt; 840 uint16_t io_xri_start; 841 uint16_t els_xri_cnt; 842 uint16_t nvmet_xri_cnt; 843 uint16_t nvmet_io_wait_cnt; 844 uint16_t nvmet_io_wait_total; 845 uint16_t cq_max; 846 struct lpfc_queue **cq_lookup; 847 struct list_head lpfc_els_sgl_list; 848 struct list_head lpfc_abts_els_sgl_list; 849 spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */ 850 struct list_head lpfc_abts_io_buf_list; 851 struct list_head lpfc_nvmet_sgl_list; 852 spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */ 853 struct list_head lpfc_abts_nvmet_ctx_list; 854 spinlock_t t_active_list_lock; /* list of active NVMET IOs */ 855 struct list_head t_active_ctx_list; 856 struct list_head lpfc_nvmet_io_wait_list; 857 struct lpfc_nvmet_ctx_info *nvmet_ctx_info; 858 struct lpfc_sglq **lpfc_sglq_active_list; 859 struct list_head lpfc_rpi_hdr_list; 860 unsigned long *rpi_bmask; 861 uint16_t *rpi_ids; 862 uint16_t rpi_count; 863 struct list_head lpfc_rpi_blk_list; 864 unsigned long *xri_bmask; 865 uint16_t *xri_ids; 866 struct list_head lpfc_xri_blk_list; 867 unsigned long *vfi_bmask; 868 uint16_t *vfi_ids; 869 uint16_t vfi_count; 870 struct list_head lpfc_vfi_blk_list; 871 struct lpfc_sli4_flags sli4_flags; 872 struct list_head sp_queue_event; 873 struct list_head sp_cqe_event_pool; 874 struct list_head sp_asynce_work_queue; 875 struct list_head sp_fcp_xri_aborted_work_queue; 876 struct list_head sp_els_xri_aborted_work_queue; 877 struct list_head sp_unsol_work_queue; 878 struct lpfc_sli4_link link_state; 879 struct lpfc_sli4_lnk_info lnk_info; 880 uint32_t pport_name_sta; 881 #define LPFC_SLI4_PPNAME_NON 0 882 #define LPFC_SLI4_PPNAME_GET 1 883 struct lpfc_iov iov; 884 spinlock_t sgl_list_lock; /* list of aborted els IOs */ 885 spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */ 886 uint32_t physical_port; 887 888 /* CPU to vector mapping information */ 889 struct lpfc_vector_map_info *cpu_map; 890 uint16_t num_possible_cpu; 891 uint16_t num_present_cpu; 892 uint16_t curr_disp_cpu; 893 struct lpfc_eq_intr_info __percpu *eq_info; 894 uint32_t conf_trunk; 895 #define lpfc_conf_trunk_port0_WORD conf_trunk 896 #define lpfc_conf_trunk_port0_SHIFT 0 897 #define lpfc_conf_trunk_port0_MASK 0x1 898 #define lpfc_conf_trunk_port1_WORD conf_trunk 899 #define lpfc_conf_trunk_port1_SHIFT 1 900 #define lpfc_conf_trunk_port1_MASK 0x1 901 #define lpfc_conf_trunk_port2_WORD conf_trunk 902 #define lpfc_conf_trunk_port2_SHIFT 2 903 #define lpfc_conf_trunk_port2_MASK 0x1 904 #define lpfc_conf_trunk_port3_WORD conf_trunk 905 #define lpfc_conf_trunk_port3_SHIFT 3 906 #define lpfc_conf_trunk_port3_MASK 0x1 907 #define lpfc_conf_trunk_port0_nd_WORD conf_trunk 908 #define lpfc_conf_trunk_port0_nd_SHIFT 4 909 #define lpfc_conf_trunk_port0_nd_MASK 0x1 910 #define lpfc_conf_trunk_port1_nd_WORD conf_trunk 911 #define lpfc_conf_trunk_port1_nd_SHIFT 5 912 #define lpfc_conf_trunk_port1_nd_MASK 0x1 913 #define lpfc_conf_trunk_port2_nd_WORD conf_trunk 914 #define lpfc_conf_trunk_port2_nd_SHIFT 6 915 #define lpfc_conf_trunk_port2_nd_MASK 0x1 916 #define lpfc_conf_trunk_port3_nd_WORD conf_trunk 917 #define lpfc_conf_trunk_port3_nd_SHIFT 7 918 #define lpfc_conf_trunk_port3_nd_MASK 0x1 919 }; 920 921 enum lpfc_sge_type { 922 GEN_BUFF_TYPE, 923 SCSI_BUFF_TYPE, 924 NVMET_BUFF_TYPE 925 }; 926 927 enum lpfc_sgl_state { 928 SGL_FREED, 929 SGL_ALLOCATED, 930 SGL_XRI_ABORTED 931 }; 932 933 struct lpfc_sglq { 934 /* lpfc_sglqs are used in double linked lists */ 935 struct list_head list; 936 struct list_head clist; 937 enum lpfc_sge_type buff_type; /* is this a scsi sgl */ 938 enum lpfc_sgl_state state; 939 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */ 940 uint16_t iotag; /* pre-assigned IO tag */ 941 uint16_t sli4_lxritag; /* logical pre-assigned xri. */ 942 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */ 943 struct sli4_sge *sgl; /* pre-assigned SGL */ 944 void *virt; /* virtual address. */ 945 dma_addr_t phys; /* physical address */ 946 }; 947 948 struct lpfc_rpi_hdr { 949 struct list_head list; 950 uint32_t len; 951 struct lpfc_dmabuf *dmabuf; 952 uint32_t page_count; 953 uint32_t start_rpi; 954 uint16_t next_rpi; 955 }; 956 957 struct lpfc_rsrc_blks { 958 struct list_head list; 959 uint16_t rsrc_start; 960 uint16_t rsrc_size; 961 uint16_t rsrc_used; 962 }; 963 964 struct lpfc_rdp_context { 965 struct lpfc_nodelist *ndlp; 966 uint16_t ox_id; 967 uint16_t rx_id; 968 READ_LNK_VAR link_stat; 969 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE]; 970 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE]; 971 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int); 972 }; 973 974 struct lpfc_lcb_context { 975 uint8_t sub_command; 976 uint8_t type; 977 uint8_t capability; 978 uint8_t frequency; 979 uint16_t duration; 980 uint16_t ox_id; 981 uint16_t rx_id; 982 struct lpfc_nodelist *ndlp; 983 }; 984 985 986 /* 987 * SLI4 specific function prototypes 988 */ 989 int lpfc_pci_function_reset(struct lpfc_hba *); 990 int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *); 991 int lpfc_sli4_hba_setup(struct lpfc_hba *); 992 int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t, 993 uint8_t, uint32_t, bool); 994 void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *); 995 void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t); 996 void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t, 997 struct lpfc_mbx_sge *); 998 int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *, 999 uint16_t); 1000 1001 void lpfc_sli4_hba_reset(struct lpfc_hba *); 1002 struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba, 1003 uint32_t page_size, 1004 uint32_t entry_size, 1005 uint32_t entry_count, int cpu); 1006 void lpfc_sli4_queue_free(struct lpfc_queue *); 1007 int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t); 1008 void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq, 1009 uint32_t numq, uint32_t usdelay); 1010 int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *, 1011 struct lpfc_queue *, uint32_t, uint32_t); 1012 int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp, 1013 struct lpfc_sli4_hdw_queue *hdwq, uint32_t type, 1014 uint32_t subtype); 1015 int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *, 1016 struct lpfc_queue *, uint32_t); 1017 int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *, 1018 struct lpfc_queue *, uint32_t); 1019 int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *, 1020 struct lpfc_queue *, struct lpfc_queue *, uint32_t); 1021 int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp, 1022 struct lpfc_queue **drqp, struct lpfc_queue **cqp, 1023 uint32_t subtype); 1024 int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1025 int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1026 int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1027 int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1028 int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *, 1029 struct lpfc_queue *); 1030 int lpfc_sli4_queue_setup(struct lpfc_hba *); 1031 void lpfc_sli4_queue_unset(struct lpfc_hba *); 1032 int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t); 1033 int lpfc_repost_io_sgl_list(struct lpfc_hba *phba); 1034 uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *); 1035 void lpfc_sli4_free_xri(struct lpfc_hba *, int); 1036 int lpfc_sli4_post_async_mbox(struct lpfc_hba *); 1037 struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *); 1038 struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *); 1039 void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *); 1040 void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *); 1041 int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *); 1042 int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *); 1043 int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *); 1044 struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *); 1045 void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *); 1046 int lpfc_sli4_alloc_rpi(struct lpfc_hba *); 1047 void lpfc_sli4_free_rpi(struct lpfc_hba *, int); 1048 void lpfc_sli4_remove_rpis(struct lpfc_hba *); 1049 void lpfc_sli4_async_event_proc(struct lpfc_hba *); 1050 void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *); 1051 int lpfc_sli4_resume_rpi(struct lpfc_nodelist *, 1052 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *); 1053 void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *); 1054 void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *); 1055 void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba, 1056 struct sli4_wcqe_xri_aborted *axri, 1057 struct lpfc_io_buf *lpfc_ncmd); 1058 void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba, 1059 struct sli4_wcqe_xri_aborted *axri, int idx); 1060 void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba, 1061 struct sli4_wcqe_xri_aborted *axri); 1062 void lpfc_sli4_els_xri_aborted(struct lpfc_hba *, 1063 struct sli4_wcqe_xri_aborted *); 1064 void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *); 1065 void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *); 1066 int lpfc_sli4_brdreset(struct lpfc_hba *); 1067 int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *); 1068 void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *); 1069 int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *); 1070 int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba); 1071 int lpfc_sli4_init_vpi(struct lpfc_vport *); 1072 void lpfc_sli4_eq_clr_intr(struct lpfc_queue *); 1073 void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1074 uint32_t count, bool arm); 1075 void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1076 uint32_t count, bool arm); 1077 void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q); 1078 void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1079 uint32_t count, bool arm); 1080 void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1081 uint32_t count, bool arm); 1082 void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t); 1083 int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t); 1084 int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t); 1085 int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t); 1086 void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); 1087 void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); 1088 void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); 1089 int lpfc_sli4_unregister_fcf(struct lpfc_hba *); 1090 int lpfc_sli4_post_status_check(struct lpfc_hba *); 1091 uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *); 1092 uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *); 1093 void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba); 1094 struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba, 1095 struct lpfc_io_buf *buf); 1096 struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba, 1097 struct lpfc_io_buf *buf); 1098 int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf); 1099 int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba, 1100 struct lpfc_io_buf *buf); 1101 void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba, 1102 struct lpfc_sli4_hdw_queue *hdwq); 1103 void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba, 1104 struct lpfc_sli4_hdw_queue *hdwq); 1105 static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx) 1106 { 1107 return q->q_pgs[idx / q->entry_cnt_per_pg] + 1108 (q->entry_size * (idx % q->entry_cnt_per_pg)); 1109 } 1110