1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * * Neither the name of Intel Corporation nor the names of its 40 * contributors may be used to endorse or promote products derived 41 * from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 #include <linux/circ_buf.h> 56 #include <linux/device.h> 57 #include <scsi/sas.h> 58 #include "host.h" 59 #include "isci.h" 60 #include "port.h" 61 #include "probe_roms.h" 62 #include "remote_device.h" 63 #include "request.h" 64 #include "scu_completion_codes.h" 65 #include "scu_event_codes.h" 66 #include "registers.h" 67 #include "scu_remote_node_context.h" 68 #include "scu_task_context.h" 69 70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200 71 72 #define smu_max_ports(dcc_value) \ 73 (\ 74 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \ 75 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \ 76 ) 77 78 #define smu_max_task_contexts(dcc_value) \ 79 (\ 80 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \ 81 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \ 82 ) 83 84 #define smu_max_rncs(dcc_value) \ 85 (\ 86 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \ 87 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \ 88 ) 89 90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100 91 92 /** 93 * 94 * 95 * The number of milliseconds to wait while a given phy is consuming power 96 * before allowing another set of phys to consume power. Ultimately, this will 97 * be specified by OEM parameter. 98 */ 99 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500 100 101 /** 102 * NORMALIZE_PUT_POINTER() - 103 * 104 * This macro will normalize the completion queue put pointer so its value can 105 * be used as an array inde 106 */ 107 #define NORMALIZE_PUT_POINTER(x) \ 108 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK) 109 110 111 /** 112 * NORMALIZE_EVENT_POINTER() - 113 * 114 * This macro will normalize the completion queue event entry so its value can 115 * be used as an index. 116 */ 117 #define NORMALIZE_EVENT_POINTER(x) \ 118 (\ 119 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \ 120 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \ 121 ) 122 123 /** 124 * NORMALIZE_GET_POINTER() - 125 * 126 * This macro will normalize the completion queue get pointer so its value can 127 * be used as an index into an array 128 */ 129 #define NORMALIZE_GET_POINTER(x) \ 130 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK) 131 132 /** 133 * NORMALIZE_GET_POINTER_CYCLE_BIT() - 134 * 135 * This macro will normalize the completion queue cycle pointer so it matches 136 * the completion queue cycle bit 137 */ 138 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \ 139 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT)) 140 141 /** 142 * COMPLETION_QUEUE_CYCLE_BIT() - 143 * 144 * This macro will return the cycle bit of the completion queue entry 145 */ 146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000) 147 148 /* Init the state machine and call the state entry function (if any) */ 149 void sci_init_sm(struct sci_base_state_machine *sm, 150 const struct sci_base_state *state_table, u32 initial_state) 151 { 152 sci_state_transition_t handler; 153 154 sm->initial_state_id = initial_state; 155 sm->previous_state_id = initial_state; 156 sm->current_state_id = initial_state; 157 sm->state_table = state_table; 158 159 handler = sm->state_table[initial_state].enter_state; 160 if (handler) 161 handler(sm); 162 } 163 164 /* Call the state exit fn, update the current state, call the state entry fn */ 165 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state) 166 { 167 sci_state_transition_t handler; 168 169 handler = sm->state_table[sm->current_state_id].exit_state; 170 if (handler) 171 handler(sm); 172 173 sm->previous_state_id = sm->current_state_id; 174 sm->current_state_id = next_state; 175 176 handler = sm->state_table[sm->current_state_id].enter_state; 177 if (handler) 178 handler(sm); 179 } 180 181 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost) 182 { 183 u32 get_value = ihost->completion_queue_get; 184 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK; 185 186 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) == 187 COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])) 188 return true; 189 190 return false; 191 } 192 193 static bool sci_controller_isr(struct isci_host *ihost) 194 { 195 if (sci_controller_completion_queue_has_entries(ihost)) { 196 return true; 197 } else { 198 /* 199 * we have a spurious interrupt it could be that we have already 200 * emptied the completion queue from a previous interrupt */ 201 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); 202 203 /* 204 * There is a race in the hardware that could cause us not to be notified 205 * of an interrupt completion if we do not take this step. We will mask 206 * then unmask the interrupts so if there is another interrupt pending 207 * the clearing of the interrupt source we get the next interrupt message. */ 208 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); 209 writel(0, &ihost->smu_registers->interrupt_mask); 210 } 211 212 return false; 213 } 214 215 irqreturn_t isci_msix_isr(int vec, void *data) 216 { 217 struct isci_host *ihost = data; 218 219 if (sci_controller_isr(ihost)) 220 tasklet_schedule(&ihost->completion_tasklet); 221 222 return IRQ_HANDLED; 223 } 224 225 static bool sci_controller_error_isr(struct isci_host *ihost) 226 { 227 u32 interrupt_status; 228 229 interrupt_status = 230 readl(&ihost->smu_registers->interrupt_status); 231 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND); 232 233 if (interrupt_status != 0) { 234 /* 235 * There is an error interrupt pending so let it through and handle 236 * in the callback */ 237 return true; 238 } 239 240 /* 241 * There is a race in the hardware that could cause us not to be notified 242 * of an interrupt completion if we do not take this step. We will mask 243 * then unmask the error interrupts so if there was another interrupt 244 * pending we will be notified. 245 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */ 246 writel(0xff, &ihost->smu_registers->interrupt_mask); 247 writel(0, &ihost->smu_registers->interrupt_mask); 248 249 return false; 250 } 251 252 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent) 253 { 254 u32 index = SCU_GET_COMPLETION_INDEX(ent); 255 struct isci_request *ireq = ihost->reqs[index]; 256 257 /* Make sure that we really want to process this IO request */ 258 if (test_bit(IREQ_ACTIVE, &ireq->flags) && 259 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG && 260 ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index]) 261 /* Yep this is a valid io request pass it along to the 262 * io request handler 263 */ 264 sci_io_request_tc_completion(ireq, ent); 265 } 266 267 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent) 268 { 269 u32 index; 270 struct isci_request *ireq; 271 struct isci_remote_device *idev; 272 273 index = SCU_GET_COMPLETION_INDEX(ent); 274 275 switch (scu_get_command_request_type(ent)) { 276 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC: 277 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC: 278 ireq = ihost->reqs[index]; 279 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n", 280 __func__, ent, ireq); 281 /* @todo For a post TC operation we need to fail the IO 282 * request 283 */ 284 break; 285 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC: 286 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC: 287 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC: 288 idev = ihost->device_table[index]; 289 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n", 290 __func__, ent, idev); 291 /* @todo For a port RNC operation we need to fail the 292 * device 293 */ 294 break; 295 default: 296 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n", 297 __func__, ent); 298 break; 299 } 300 } 301 302 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent) 303 { 304 u32 index; 305 u32 frame_index; 306 307 struct scu_unsolicited_frame_header *frame_header; 308 struct isci_phy *iphy; 309 struct isci_remote_device *idev; 310 311 enum sci_status result = SCI_FAILURE; 312 313 frame_index = SCU_GET_FRAME_INDEX(ent); 314 315 frame_header = ihost->uf_control.buffers.array[frame_index].header; 316 ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE; 317 318 if (SCU_GET_FRAME_ERROR(ent)) { 319 /* 320 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will 321 * / this cause a problem? We expect the phy initialization will 322 * / fail if there is an error in the frame. */ 323 sci_controller_release_frame(ihost, frame_index); 324 return; 325 } 326 327 if (frame_header->is_address_frame) { 328 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); 329 iphy = &ihost->phys[index]; 330 result = sci_phy_frame_handler(iphy, frame_index); 331 } else { 332 333 index = SCU_GET_COMPLETION_INDEX(ent); 334 335 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { 336 /* 337 * This is a signature fis or a frame from a direct attached SATA 338 * device that has not yet been created. In either case forwared 339 * the frame to the PE and let it take care of the frame data. */ 340 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); 341 iphy = &ihost->phys[index]; 342 result = sci_phy_frame_handler(iphy, frame_index); 343 } else { 344 if (index < ihost->remote_node_entries) 345 idev = ihost->device_table[index]; 346 else 347 idev = NULL; 348 349 if (idev != NULL) 350 result = sci_remote_device_frame_handler(idev, frame_index); 351 else 352 sci_controller_release_frame(ihost, frame_index); 353 } 354 } 355 356 if (result != SCI_SUCCESS) { 357 /* 358 * / @todo Is there any reason to report some additional error message 359 * / when we get this failure notifiction? */ 360 } 361 } 362 363 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent) 364 { 365 struct isci_remote_device *idev; 366 struct isci_request *ireq; 367 struct isci_phy *iphy; 368 u32 index; 369 370 index = SCU_GET_COMPLETION_INDEX(ent); 371 372 switch (scu_get_event_type(ent)) { 373 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR: 374 /* / @todo The driver did something wrong and we need to fix the condtion. */ 375 dev_err(&ihost->pdev->dev, 376 "%s: SCIC Controller 0x%p received SMU command error " 377 "0x%x\n", 378 __func__, 379 ihost, 380 ent); 381 break; 382 383 case SCU_EVENT_TYPE_SMU_PCQ_ERROR: 384 case SCU_EVENT_TYPE_SMU_ERROR: 385 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR: 386 /* 387 * / @todo This is a hardware failure and its likely that we want to 388 * / reset the controller. */ 389 dev_err(&ihost->pdev->dev, 390 "%s: SCIC Controller 0x%p received fatal controller " 391 "event 0x%x\n", 392 __func__, 393 ihost, 394 ent); 395 break; 396 397 case SCU_EVENT_TYPE_TRANSPORT_ERROR: 398 ireq = ihost->reqs[index]; 399 sci_io_request_event_handler(ireq, ent); 400 break; 401 402 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT: 403 switch (scu_get_event_specifier(ent)) { 404 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE: 405 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT: 406 ireq = ihost->reqs[index]; 407 if (ireq != NULL) 408 sci_io_request_event_handler(ireq, ent); 409 else 410 dev_warn(&ihost->pdev->dev, 411 "%s: SCIC Controller 0x%p received " 412 "event 0x%x for io request object " 413 "that doesnt exist.\n", 414 __func__, 415 ihost, 416 ent); 417 418 break; 419 420 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT: 421 idev = ihost->device_table[index]; 422 if (idev != NULL) 423 sci_remote_device_event_handler(idev, ent); 424 else 425 dev_warn(&ihost->pdev->dev, 426 "%s: SCIC Controller 0x%p received " 427 "event 0x%x for remote device object " 428 "that doesnt exist.\n", 429 __func__, 430 ihost, 431 ent); 432 433 break; 434 } 435 break; 436 437 case SCU_EVENT_TYPE_BROADCAST_CHANGE: 438 /* 439 * direct the broadcast change event to the phy first and then let 440 * the phy redirect the broadcast change to the port object */ 441 case SCU_EVENT_TYPE_ERR_CNT_EVENT: 442 /* 443 * direct error counter event to the phy object since that is where 444 * we get the event notification. This is a type 4 event. */ 445 case SCU_EVENT_TYPE_OSSP_EVENT: 446 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); 447 iphy = &ihost->phys[index]; 448 sci_phy_event_handler(iphy, ent); 449 break; 450 451 case SCU_EVENT_TYPE_RNC_SUSPEND_TX: 452 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX: 453 case SCU_EVENT_TYPE_RNC_OPS_MISC: 454 if (index < ihost->remote_node_entries) { 455 idev = ihost->device_table[index]; 456 457 if (idev != NULL) 458 sci_remote_device_event_handler(idev, ent); 459 } else 460 dev_err(&ihost->pdev->dev, 461 "%s: SCIC Controller 0x%p received event 0x%x " 462 "for remote device object 0x%0x that doesnt " 463 "exist.\n", 464 __func__, 465 ihost, 466 ent, 467 index); 468 469 break; 470 471 default: 472 dev_warn(&ihost->pdev->dev, 473 "%s: SCIC Controller received unknown event code %x\n", 474 __func__, 475 ent); 476 break; 477 } 478 } 479 480 static void sci_controller_process_completions(struct isci_host *ihost) 481 { 482 u32 completion_count = 0; 483 u32 ent; 484 u32 get_index; 485 u32 get_cycle; 486 u32 event_get; 487 u32 event_cycle; 488 489 dev_dbg(&ihost->pdev->dev, 490 "%s: completion queue begining get:0x%08x\n", 491 __func__, 492 ihost->completion_queue_get); 493 494 /* Get the component parts of the completion queue */ 495 get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get); 496 get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get; 497 498 event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get); 499 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get; 500 501 while ( 502 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle) 503 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]) 504 ) { 505 completion_count++; 506 507 ent = ihost->completion_queue[get_index]; 508 509 /* increment the get pointer and check for rollover to toggle the cycle bit */ 510 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) << 511 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT); 512 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1); 513 514 dev_dbg(&ihost->pdev->dev, 515 "%s: completion queue entry:0x%08x\n", 516 __func__, 517 ent); 518 519 switch (SCU_GET_COMPLETION_TYPE(ent)) { 520 case SCU_COMPLETION_TYPE_TASK: 521 sci_controller_task_completion(ihost, ent); 522 break; 523 524 case SCU_COMPLETION_TYPE_SDMA: 525 sci_controller_sdma_completion(ihost, ent); 526 break; 527 528 case SCU_COMPLETION_TYPE_UFI: 529 sci_controller_unsolicited_frame(ihost, ent); 530 break; 531 532 case SCU_COMPLETION_TYPE_EVENT: 533 sci_controller_event_completion(ihost, ent); 534 break; 535 536 case SCU_COMPLETION_TYPE_NOTIFY: { 537 event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) << 538 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT); 539 event_get = (event_get+1) & (SCU_MAX_EVENTS-1); 540 541 sci_controller_event_completion(ihost, ent); 542 break; 543 } 544 default: 545 dev_warn(&ihost->pdev->dev, 546 "%s: SCIC Controller received unknown " 547 "completion type %x\n", 548 __func__, 549 ent); 550 break; 551 } 552 } 553 554 /* Update the get register if we completed one or more entries */ 555 if (completion_count > 0) { 556 ihost->completion_queue_get = 557 SMU_CQGR_GEN_BIT(ENABLE) | 558 SMU_CQGR_GEN_BIT(EVENT_ENABLE) | 559 event_cycle | 560 SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) | 561 get_cycle | 562 SMU_CQGR_GEN_VAL(POINTER, get_index); 563 564 writel(ihost->completion_queue_get, 565 &ihost->smu_registers->completion_queue_get); 566 567 } 568 569 dev_dbg(&ihost->pdev->dev, 570 "%s: completion queue ending get:0x%08x\n", 571 __func__, 572 ihost->completion_queue_get); 573 574 } 575 576 static void sci_controller_error_handler(struct isci_host *ihost) 577 { 578 u32 interrupt_status; 579 580 interrupt_status = 581 readl(&ihost->smu_registers->interrupt_status); 582 583 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) && 584 sci_controller_completion_queue_has_entries(ihost)) { 585 586 sci_controller_process_completions(ihost); 587 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status); 588 } else { 589 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__, 590 interrupt_status); 591 592 sci_change_state(&ihost->sm, SCIC_FAILED); 593 594 return; 595 } 596 597 /* If we dont process any completions I am not sure that we want to do this. 598 * We are in the middle of a hardware fault and should probably be reset. 599 */ 600 writel(0, &ihost->smu_registers->interrupt_mask); 601 } 602 603 irqreturn_t isci_intx_isr(int vec, void *data) 604 { 605 irqreturn_t ret = IRQ_NONE; 606 struct isci_host *ihost = data; 607 608 if (sci_controller_isr(ihost)) { 609 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); 610 tasklet_schedule(&ihost->completion_tasklet); 611 ret = IRQ_HANDLED; 612 } else if (sci_controller_error_isr(ihost)) { 613 spin_lock(&ihost->scic_lock); 614 sci_controller_error_handler(ihost); 615 spin_unlock(&ihost->scic_lock); 616 ret = IRQ_HANDLED; 617 } 618 619 return ret; 620 } 621 622 irqreturn_t isci_error_isr(int vec, void *data) 623 { 624 struct isci_host *ihost = data; 625 626 if (sci_controller_error_isr(ihost)) 627 sci_controller_error_handler(ihost); 628 629 return IRQ_HANDLED; 630 } 631 632 /** 633 * isci_host_start_complete() - This function is called by the core library, 634 * through the ISCI Module, to indicate controller start status. 635 * @isci_host: This parameter specifies the ISCI host object 636 * @completion_status: This parameter specifies the completion status from the 637 * core library. 638 * 639 */ 640 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status) 641 { 642 if (completion_status != SCI_SUCCESS) 643 dev_info(&ihost->pdev->dev, 644 "controller start timed out, continuing...\n"); 645 clear_bit(IHOST_START_PENDING, &ihost->flags); 646 wake_up(&ihost->eventq); 647 } 648 649 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time) 650 { 651 struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost); 652 struct isci_host *ihost = ha->lldd_ha; 653 654 if (test_bit(IHOST_START_PENDING, &ihost->flags)) 655 return 0; 656 657 sas_drain_work(ha); 658 659 return 1; 660 } 661 662 /** 663 * sci_controller_get_suggested_start_timeout() - This method returns the 664 * suggested sci_controller_start() timeout amount. The user is free to 665 * use any timeout value, but this method provides the suggested minimum 666 * start timeout value. The returned value is based upon empirical 667 * information determined as a result of interoperability testing. 668 * @controller: the handle to the controller object for which to return the 669 * suggested start timeout. 670 * 671 * This method returns the number of milliseconds for the suggested start 672 * operation timeout. 673 */ 674 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost) 675 { 676 /* Validate the user supplied parameters. */ 677 if (!ihost) 678 return 0; 679 680 /* 681 * The suggested minimum timeout value for a controller start operation: 682 * 683 * Signature FIS Timeout 684 * + Phy Start Timeout 685 * + Number of Phy Spin Up Intervals 686 * --------------------------------- 687 * Number of milliseconds for the controller start operation. 688 * 689 * NOTE: The number of phy spin up intervals will be equivalent 690 * to the number of phys divided by the number phys allowed 691 * per interval - 1 (once OEM parameters are supported). 692 * Currently we assume only 1 phy per interval. */ 693 694 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT 695 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 696 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 697 } 698 699 static void sci_controller_enable_interrupts(struct isci_host *ihost) 700 { 701 BUG_ON(ihost->smu_registers == NULL); 702 writel(0, &ihost->smu_registers->interrupt_mask); 703 } 704 705 void sci_controller_disable_interrupts(struct isci_host *ihost) 706 { 707 BUG_ON(ihost->smu_registers == NULL); 708 writel(0xffffffff, &ihost->smu_registers->interrupt_mask); 709 } 710 711 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost) 712 { 713 u32 port_task_scheduler_value; 714 715 port_task_scheduler_value = 716 readl(&ihost->scu_registers->peg0.ptsg.control); 717 port_task_scheduler_value |= 718 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | 719 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE)); 720 writel(port_task_scheduler_value, 721 &ihost->scu_registers->peg0.ptsg.control); 722 } 723 724 static void sci_controller_assign_task_entries(struct isci_host *ihost) 725 { 726 u32 task_assignment; 727 728 /* 729 * Assign all the TCs to function 0 730 * TODO: Do we actually need to read this register to write it back? 731 */ 732 733 task_assignment = 734 readl(&ihost->smu_registers->task_context_assignment[0]); 735 736 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) | 737 (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) | 738 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE)); 739 740 writel(task_assignment, 741 &ihost->smu_registers->task_context_assignment[0]); 742 743 } 744 745 static void sci_controller_initialize_completion_queue(struct isci_host *ihost) 746 { 747 u32 index; 748 u32 completion_queue_control_value; 749 u32 completion_queue_get_value; 750 u32 completion_queue_put_value; 751 752 ihost->completion_queue_get = 0; 753 754 completion_queue_control_value = 755 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) | 756 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1)); 757 758 writel(completion_queue_control_value, 759 &ihost->smu_registers->completion_queue_control); 760 761 762 /* Set the completion queue get pointer and enable the queue */ 763 completion_queue_get_value = ( 764 (SMU_CQGR_GEN_VAL(POINTER, 0)) 765 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0)) 766 | (SMU_CQGR_GEN_BIT(ENABLE)) 767 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE)) 768 ); 769 770 writel(completion_queue_get_value, 771 &ihost->smu_registers->completion_queue_get); 772 773 /* Set the completion queue put pointer */ 774 completion_queue_put_value = ( 775 (SMU_CQPR_GEN_VAL(POINTER, 0)) 776 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0)) 777 ); 778 779 writel(completion_queue_put_value, 780 &ihost->smu_registers->completion_queue_put); 781 782 /* Initialize the cycle bit of the completion queue entries */ 783 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) { 784 /* 785 * If get.cycle_bit != completion_queue.cycle_bit 786 * its not a valid completion queue entry 787 * so at system start all entries are invalid */ 788 ihost->completion_queue[index] = 0x80000000; 789 } 790 } 791 792 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost) 793 { 794 u32 frame_queue_control_value; 795 u32 frame_queue_get_value; 796 u32 frame_queue_put_value; 797 798 /* Write the queue size */ 799 frame_queue_control_value = 800 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES); 801 802 writel(frame_queue_control_value, 803 &ihost->scu_registers->sdma.unsolicited_frame_queue_control); 804 805 /* Setup the get pointer for the unsolicited frame queue */ 806 frame_queue_get_value = ( 807 SCU_UFQGP_GEN_VAL(POINTER, 0) 808 | SCU_UFQGP_GEN_BIT(ENABLE_BIT) 809 ); 810 811 writel(frame_queue_get_value, 812 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); 813 /* Setup the put pointer for the unsolicited frame queue */ 814 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); 815 writel(frame_queue_put_value, 816 &ihost->scu_registers->sdma.unsolicited_frame_put_pointer); 817 } 818 819 static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status) 820 { 821 if (ihost->sm.current_state_id == SCIC_STARTING) { 822 /* 823 * We move into the ready state, because some of the phys/ports 824 * may be up and operational. 825 */ 826 sci_change_state(&ihost->sm, SCIC_READY); 827 828 isci_host_start_complete(ihost, status); 829 } 830 } 831 832 static bool is_phy_starting(struct isci_phy *iphy) 833 { 834 enum sci_phy_states state; 835 836 state = iphy->sm.current_state_id; 837 switch (state) { 838 case SCI_PHY_STARTING: 839 case SCI_PHY_SUB_INITIAL: 840 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: 841 case SCI_PHY_SUB_AWAIT_IAF_UF: 842 case SCI_PHY_SUB_AWAIT_SAS_POWER: 843 case SCI_PHY_SUB_AWAIT_SATA_POWER: 844 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: 845 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: 846 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: 847 case SCI_PHY_SUB_FINAL: 848 return true; 849 default: 850 return false; 851 } 852 } 853 854 /** 855 * sci_controller_start_next_phy - start phy 856 * @scic: controller 857 * 858 * If all the phys have been started, then attempt to transition the 859 * controller to the READY state and inform the user 860 * (sci_cb_controller_start_complete()). 861 */ 862 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost) 863 { 864 struct sci_oem_params *oem = &ihost->oem_parameters; 865 struct isci_phy *iphy; 866 enum sci_status status; 867 868 status = SCI_SUCCESS; 869 870 if (ihost->phy_startup_timer_pending) 871 return status; 872 873 if (ihost->next_phy_to_start >= SCI_MAX_PHYS) { 874 bool is_controller_start_complete = true; 875 u32 state; 876 u8 index; 877 878 for (index = 0; index < SCI_MAX_PHYS; index++) { 879 iphy = &ihost->phys[index]; 880 state = iphy->sm.current_state_id; 881 882 if (!phy_get_non_dummy_port(iphy)) 883 continue; 884 885 /* The controller start operation is complete iff: 886 * - all links have been given an opportunity to start 887 * - have no indication of a connected device 888 * - have an indication of a connected device and it has 889 * finished the link training process. 890 */ 891 if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) || 892 (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) || 893 (iphy->is_in_link_training == true && is_phy_starting(iphy)) || 894 (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) { 895 is_controller_start_complete = false; 896 break; 897 } 898 } 899 900 /* 901 * The controller has successfully finished the start process. 902 * Inform the SCI Core user and transition to the READY state. */ 903 if (is_controller_start_complete == true) { 904 sci_controller_transition_to_ready(ihost, SCI_SUCCESS); 905 sci_del_timer(&ihost->phy_timer); 906 ihost->phy_startup_timer_pending = false; 907 } 908 } else { 909 iphy = &ihost->phys[ihost->next_phy_to_start]; 910 911 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { 912 if (phy_get_non_dummy_port(iphy) == NULL) { 913 ihost->next_phy_to_start++; 914 915 /* Caution recursion ahead be forwarned 916 * 917 * The PHY was never added to a PORT in MPC mode 918 * so start the next phy in sequence This phy 919 * will never go link up and will not draw power 920 * the OEM parameters either configured the phy 921 * incorrectly for the PORT or it was never 922 * assigned to a PORT 923 */ 924 return sci_controller_start_next_phy(ihost); 925 } 926 } 927 928 status = sci_phy_start(iphy); 929 930 if (status == SCI_SUCCESS) { 931 sci_mod_timer(&ihost->phy_timer, 932 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT); 933 ihost->phy_startup_timer_pending = true; 934 } else { 935 dev_warn(&ihost->pdev->dev, 936 "%s: Controller stop operation failed " 937 "to stop phy %d because of status " 938 "%d.\n", 939 __func__, 940 ihost->phys[ihost->next_phy_to_start].phy_index, 941 status); 942 } 943 944 ihost->next_phy_to_start++; 945 } 946 947 return status; 948 } 949 950 static void phy_startup_timeout(unsigned long data) 951 { 952 struct sci_timer *tmr = (struct sci_timer *)data; 953 struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer); 954 unsigned long flags; 955 enum sci_status status; 956 957 spin_lock_irqsave(&ihost->scic_lock, flags); 958 959 if (tmr->cancel) 960 goto done; 961 962 ihost->phy_startup_timer_pending = false; 963 964 do { 965 status = sci_controller_start_next_phy(ihost); 966 } while (status != SCI_SUCCESS); 967 968 done: 969 spin_unlock_irqrestore(&ihost->scic_lock, flags); 970 } 971 972 static u16 isci_tci_active(struct isci_host *ihost) 973 { 974 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); 975 } 976 977 static enum sci_status sci_controller_start(struct isci_host *ihost, 978 u32 timeout) 979 { 980 enum sci_status result; 981 u16 index; 982 983 if (ihost->sm.current_state_id != SCIC_INITIALIZED) { 984 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 985 __func__, ihost->sm.current_state_id); 986 return SCI_FAILURE_INVALID_STATE; 987 } 988 989 /* Build the TCi free pool */ 990 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8); 991 ihost->tci_head = 0; 992 ihost->tci_tail = 0; 993 for (index = 0; index < ihost->task_context_entries; index++) 994 isci_tci_free(ihost, index); 995 996 /* Build the RNi free pool */ 997 sci_remote_node_table_initialize(&ihost->available_remote_nodes, 998 ihost->remote_node_entries); 999 1000 /* 1001 * Before anything else lets make sure we will not be 1002 * interrupted by the hardware. 1003 */ 1004 sci_controller_disable_interrupts(ihost); 1005 1006 /* Enable the port task scheduler */ 1007 sci_controller_enable_port_task_scheduler(ihost); 1008 1009 /* Assign all the task entries to ihost physical function */ 1010 sci_controller_assign_task_entries(ihost); 1011 1012 /* Now initialize the completion queue */ 1013 sci_controller_initialize_completion_queue(ihost); 1014 1015 /* Initialize the unsolicited frame queue for use */ 1016 sci_controller_initialize_unsolicited_frame_queue(ihost); 1017 1018 /* Start all of the ports on this controller */ 1019 for (index = 0; index < ihost->logical_port_entries; index++) { 1020 struct isci_port *iport = &ihost->ports[index]; 1021 1022 result = sci_port_start(iport); 1023 if (result) 1024 return result; 1025 } 1026 1027 sci_controller_start_next_phy(ihost); 1028 1029 sci_mod_timer(&ihost->timer, timeout); 1030 1031 sci_change_state(&ihost->sm, SCIC_STARTING); 1032 1033 return SCI_SUCCESS; 1034 } 1035 1036 void isci_host_scan_start(struct Scsi_Host *shost) 1037 { 1038 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; 1039 unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost); 1040 1041 set_bit(IHOST_START_PENDING, &ihost->flags); 1042 1043 spin_lock_irq(&ihost->scic_lock); 1044 sci_controller_start(ihost, tmo); 1045 sci_controller_enable_interrupts(ihost); 1046 spin_unlock_irq(&ihost->scic_lock); 1047 } 1048 1049 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status) 1050 { 1051 sci_controller_disable_interrupts(ihost); 1052 clear_bit(IHOST_STOP_PENDING, &ihost->flags); 1053 wake_up(&ihost->eventq); 1054 } 1055 1056 static void sci_controller_completion_handler(struct isci_host *ihost) 1057 { 1058 /* Empty out the completion queue */ 1059 if (sci_controller_completion_queue_has_entries(ihost)) 1060 sci_controller_process_completions(ihost); 1061 1062 /* Clear the interrupt and enable all interrupts again */ 1063 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); 1064 /* Could we write the value of SMU_ISR_COMPLETION? */ 1065 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); 1066 writel(0, &ihost->smu_registers->interrupt_mask); 1067 } 1068 1069 /** 1070 * isci_host_completion_routine() - This function is the delayed service 1071 * routine that calls the sci core library's completion handler. It's 1072 * scheduled as a tasklet from the interrupt service routine when interrupts 1073 * in use, or set as the timeout function in polled mode. 1074 * @data: This parameter specifies the ISCI host object 1075 * 1076 */ 1077 static void isci_host_completion_routine(unsigned long data) 1078 { 1079 struct isci_host *ihost = (struct isci_host *)data; 1080 struct list_head completed_request_list; 1081 struct list_head errored_request_list; 1082 struct list_head *current_position; 1083 struct list_head *next_position; 1084 struct isci_request *request; 1085 struct isci_request *next_request; 1086 struct sas_task *task; 1087 u16 active; 1088 1089 INIT_LIST_HEAD(&completed_request_list); 1090 INIT_LIST_HEAD(&errored_request_list); 1091 1092 spin_lock_irq(&ihost->scic_lock); 1093 1094 sci_controller_completion_handler(ihost); 1095 1096 /* Take the lists of completed I/Os from the host. */ 1097 1098 list_splice_init(&ihost->requests_to_complete, 1099 &completed_request_list); 1100 1101 /* Take the list of errored I/Os from the host. */ 1102 list_splice_init(&ihost->requests_to_errorback, 1103 &errored_request_list); 1104 1105 spin_unlock_irq(&ihost->scic_lock); 1106 1107 /* Process any completions in the lists. */ 1108 list_for_each_safe(current_position, next_position, 1109 &completed_request_list) { 1110 1111 request = list_entry(current_position, struct isci_request, 1112 completed_node); 1113 task = isci_request_access_task(request); 1114 1115 /* Normal notification (task_done) */ 1116 dev_dbg(&ihost->pdev->dev, 1117 "%s: Normal - request/task = %p/%p\n", 1118 __func__, 1119 request, 1120 task); 1121 1122 /* Return the task to libsas */ 1123 if (task != NULL) { 1124 1125 task->lldd_task = NULL; 1126 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) { 1127 1128 /* If the task is already in the abort path, 1129 * the task_done callback cannot be called. 1130 */ 1131 task->task_done(task); 1132 } 1133 } 1134 1135 spin_lock_irq(&ihost->scic_lock); 1136 isci_free_tag(ihost, request->io_tag); 1137 spin_unlock_irq(&ihost->scic_lock); 1138 } 1139 list_for_each_entry_safe(request, next_request, &errored_request_list, 1140 completed_node) { 1141 1142 task = isci_request_access_task(request); 1143 1144 /* Use sas_task_abort */ 1145 dev_warn(&ihost->pdev->dev, 1146 "%s: Error - request/task = %p/%p\n", 1147 __func__, 1148 request, 1149 task); 1150 1151 if (task != NULL) { 1152 1153 /* Put the task into the abort path if it's not there 1154 * already. 1155 */ 1156 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) 1157 sas_task_abort(task); 1158 1159 } else { 1160 /* This is a case where the request has completed with a 1161 * status such that it needed further target servicing, 1162 * but the sas_task reference has already been removed 1163 * from the request. Since it was errored, it was not 1164 * being aborted, so there is nothing to do except free 1165 * it. 1166 */ 1167 1168 spin_lock_irq(&ihost->scic_lock); 1169 /* Remove the request from the remote device's list 1170 * of pending requests. 1171 */ 1172 list_del_init(&request->dev_node); 1173 isci_free_tag(ihost, request->io_tag); 1174 spin_unlock_irq(&ihost->scic_lock); 1175 } 1176 } 1177 1178 /* the coalesence timeout doubles at each encoding step, so 1179 * update it based on the ilog2 value of the outstanding requests 1180 */ 1181 active = isci_tci_active(ihost); 1182 writel(SMU_ICC_GEN_VAL(NUMBER, active) | 1183 SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)), 1184 &ihost->smu_registers->interrupt_coalesce_control); 1185 } 1186 1187 /** 1188 * sci_controller_stop() - This method will stop an individual controller 1189 * object.This method will invoke the associated user callback upon 1190 * completion. The completion callback is called when the following 1191 * conditions are met: -# the method return status is SCI_SUCCESS. -# the 1192 * controller has been quiesced. This method will ensure that all IO 1193 * requests are quiesced, phys are stopped, and all additional operation by 1194 * the hardware is halted. 1195 * @controller: the handle to the controller object to stop. 1196 * @timeout: This parameter specifies the number of milliseconds in which the 1197 * stop operation should complete. 1198 * 1199 * The controller must be in the STARTED or STOPPED state. Indicate if the 1200 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the 1201 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the 1202 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the 1203 * controller is not either in the STARTED or STOPPED states. 1204 */ 1205 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout) 1206 { 1207 if (ihost->sm.current_state_id != SCIC_READY) { 1208 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 1209 __func__, ihost->sm.current_state_id); 1210 return SCI_FAILURE_INVALID_STATE; 1211 } 1212 1213 sci_mod_timer(&ihost->timer, timeout); 1214 sci_change_state(&ihost->sm, SCIC_STOPPING); 1215 return SCI_SUCCESS; 1216 } 1217 1218 /** 1219 * sci_controller_reset() - This method will reset the supplied core 1220 * controller regardless of the state of said controller. This operation is 1221 * considered destructive. In other words, all current operations are wiped 1222 * out. No IO completions for outstanding devices occur. Outstanding IO 1223 * requests are not aborted or completed at the actual remote device. 1224 * @controller: the handle to the controller object to reset. 1225 * 1226 * Indicate if the controller reset method succeeded or failed in some way. 1227 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if 1228 * the controller reset operation is unable to complete. 1229 */ 1230 static enum sci_status sci_controller_reset(struct isci_host *ihost) 1231 { 1232 switch (ihost->sm.current_state_id) { 1233 case SCIC_RESET: 1234 case SCIC_READY: 1235 case SCIC_STOPPED: 1236 case SCIC_FAILED: 1237 /* 1238 * The reset operation is not a graceful cleanup, just 1239 * perform the state transition. 1240 */ 1241 sci_change_state(&ihost->sm, SCIC_RESETTING); 1242 return SCI_SUCCESS; 1243 default: 1244 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 1245 __func__, ihost->sm.current_state_id); 1246 return SCI_FAILURE_INVALID_STATE; 1247 } 1248 } 1249 1250 void isci_host_deinit(struct isci_host *ihost) 1251 { 1252 int i; 1253 1254 /* disable output data selects */ 1255 for (i = 0; i < isci_gpio_count(ihost); i++) 1256 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]); 1257 1258 for (i = 0; i < SCI_MAX_PORTS; i++) { 1259 struct isci_port *iport = &ihost->ports[i]; 1260 struct isci_remote_device *idev, *d; 1261 1262 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) { 1263 if (test_bit(IDEV_ALLOCATED, &idev->flags)) 1264 isci_remote_device_stop(ihost, idev); 1265 } 1266 } 1267 1268 set_bit(IHOST_STOP_PENDING, &ihost->flags); 1269 1270 spin_lock_irq(&ihost->scic_lock); 1271 sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT); 1272 spin_unlock_irq(&ihost->scic_lock); 1273 1274 wait_for_stop(ihost); 1275 1276 /* disable sgpio: where the above wait should give time for the 1277 * enclosure to sample the gpios going inactive 1278 */ 1279 writel(0, &ihost->scu_registers->peg0.sgpio.interface_control); 1280 1281 sci_controller_reset(ihost); 1282 1283 /* Cancel any/all outstanding port timers */ 1284 for (i = 0; i < ihost->logical_port_entries; i++) { 1285 struct isci_port *iport = &ihost->ports[i]; 1286 del_timer_sync(&iport->timer.timer); 1287 } 1288 1289 /* Cancel any/all outstanding phy timers */ 1290 for (i = 0; i < SCI_MAX_PHYS; i++) { 1291 struct isci_phy *iphy = &ihost->phys[i]; 1292 del_timer_sync(&iphy->sata_timer.timer); 1293 } 1294 1295 del_timer_sync(&ihost->port_agent.timer.timer); 1296 1297 del_timer_sync(&ihost->power_control.timer.timer); 1298 1299 del_timer_sync(&ihost->timer.timer); 1300 1301 del_timer_sync(&ihost->phy_timer.timer); 1302 } 1303 1304 static void __iomem *scu_base(struct isci_host *isci_host) 1305 { 1306 struct pci_dev *pdev = isci_host->pdev; 1307 int id = isci_host->id; 1308 1309 return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id; 1310 } 1311 1312 static void __iomem *smu_base(struct isci_host *isci_host) 1313 { 1314 struct pci_dev *pdev = isci_host->pdev; 1315 int id = isci_host->id; 1316 1317 return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id; 1318 } 1319 1320 static void isci_user_parameters_get(struct sci_user_parameters *u) 1321 { 1322 int i; 1323 1324 for (i = 0; i < SCI_MAX_PHYS; i++) { 1325 struct sci_phy_user_params *u_phy = &u->phys[i]; 1326 1327 u_phy->max_speed_generation = phy_gen; 1328 1329 /* we are not exporting these for now */ 1330 u_phy->align_insertion_frequency = 0x7f; 1331 u_phy->in_connection_align_insertion_frequency = 0xff; 1332 u_phy->notify_enable_spin_up_insertion_frequency = 0x33; 1333 } 1334 1335 u->stp_inactivity_timeout = stp_inactive_to; 1336 u->ssp_inactivity_timeout = ssp_inactive_to; 1337 u->stp_max_occupancy_timeout = stp_max_occ_to; 1338 u->ssp_max_occupancy_timeout = ssp_max_occ_to; 1339 u->no_outbound_task_timeout = no_outbound_task_to; 1340 u->max_concurr_spinup = max_concurr_spinup; 1341 } 1342 1343 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm) 1344 { 1345 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1346 1347 sci_change_state(&ihost->sm, SCIC_RESET); 1348 } 1349 1350 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm) 1351 { 1352 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1353 1354 sci_del_timer(&ihost->timer); 1355 } 1356 1357 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853 1358 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280 1359 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000 1360 #define INTERRUPT_COALESCE_NUMBER_MAX 256 1361 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7 1362 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28 1363 1364 /** 1365 * sci_controller_set_interrupt_coalescence() - This method allows the user to 1366 * configure the interrupt coalescence. 1367 * @controller: This parameter represents the handle to the controller object 1368 * for which its interrupt coalesce register is overridden. 1369 * @coalesce_number: Used to control the number of entries in the Completion 1370 * Queue before an interrupt is generated. If the number of entries exceed 1371 * this number, an interrupt will be generated. The valid range of the input 1372 * is [0, 256]. A setting of 0 results in coalescing being disabled. 1373 * @coalesce_timeout: Timeout value in microseconds. The valid range of the 1374 * input is [0, 2700000] . A setting of 0 is allowed and results in no 1375 * interrupt coalescing timeout. 1376 * 1377 * Indicate if the user successfully set the interrupt coalesce parameters. 1378 * SCI_SUCCESS The user successfully updated the interrutp coalescence. 1379 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range. 1380 */ 1381 static enum sci_status 1382 sci_controller_set_interrupt_coalescence(struct isci_host *ihost, 1383 u32 coalesce_number, 1384 u32 coalesce_timeout) 1385 { 1386 u8 timeout_encode = 0; 1387 u32 min = 0; 1388 u32 max = 0; 1389 1390 /* Check if the input parameters fall in the range. */ 1391 if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX) 1392 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 1393 1394 /* 1395 * Defined encoding for interrupt coalescing timeout: 1396 * Value Min Max Units 1397 * ----- --- --- ----- 1398 * 0 - - Disabled 1399 * 1 13.3 20.0 ns 1400 * 2 26.7 40.0 1401 * 3 53.3 80.0 1402 * 4 106.7 160.0 1403 * 5 213.3 320.0 1404 * 6 426.7 640.0 1405 * 7 853.3 1280.0 1406 * 8 1.7 2.6 us 1407 * 9 3.4 5.1 1408 * 10 6.8 10.2 1409 * 11 13.7 20.5 1410 * 12 27.3 41.0 1411 * 13 54.6 81.9 1412 * 14 109.2 163.8 1413 * 15 218.5 327.7 1414 * 16 436.9 655.4 1415 * 17 873.8 1310.7 1416 * 18 1.7 2.6 ms 1417 * 19 3.5 5.2 1418 * 20 7.0 10.5 1419 * 21 14.0 21.0 1420 * 22 28.0 41.9 1421 * 23 55.9 83.9 1422 * 24 111.8 167.8 1423 * 25 223.7 335.5 1424 * 26 447.4 671.1 1425 * 27 894.8 1342.2 1426 * 28 1.8 2.7 s 1427 * Others Undefined */ 1428 1429 /* 1430 * Use the table above to decide the encode of interrupt coalescing timeout 1431 * value for register writing. */ 1432 if (coalesce_timeout == 0) 1433 timeout_encode = 0; 1434 else{ 1435 /* make the timeout value in unit of (10 ns). */ 1436 coalesce_timeout = coalesce_timeout * 100; 1437 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10; 1438 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10; 1439 1440 /* get the encode of timeout for register writing. */ 1441 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN; 1442 timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX; 1443 timeout_encode++) { 1444 if (min <= coalesce_timeout && max > coalesce_timeout) 1445 break; 1446 else if (coalesce_timeout >= max && coalesce_timeout < min * 2 1447 && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) { 1448 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout)) 1449 break; 1450 else{ 1451 timeout_encode++; 1452 break; 1453 } 1454 } else { 1455 max = max * 2; 1456 min = min * 2; 1457 } 1458 } 1459 1460 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1) 1461 /* the value is out of range. */ 1462 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 1463 } 1464 1465 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) | 1466 SMU_ICC_GEN_VAL(TIMER, timeout_encode), 1467 &ihost->smu_registers->interrupt_coalesce_control); 1468 1469 1470 ihost->interrupt_coalesce_number = (u16)coalesce_number; 1471 ihost->interrupt_coalesce_timeout = coalesce_timeout / 100; 1472 1473 return SCI_SUCCESS; 1474 } 1475 1476 1477 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm) 1478 { 1479 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1480 u32 val; 1481 1482 /* enable clock gating for power control of the scu unit */ 1483 val = readl(&ihost->smu_registers->clock_gating_control); 1484 val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) | 1485 SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) | 1486 SMU_CGUCR_GEN_BIT(XCLK_ENABLE)); 1487 val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE); 1488 writel(val, &ihost->smu_registers->clock_gating_control); 1489 1490 /* set the default interrupt coalescence number and timeout value. */ 1491 sci_controller_set_interrupt_coalescence(ihost, 0, 0); 1492 } 1493 1494 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm) 1495 { 1496 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1497 1498 /* disable interrupt coalescence. */ 1499 sci_controller_set_interrupt_coalescence(ihost, 0, 0); 1500 } 1501 1502 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost) 1503 { 1504 u32 index; 1505 enum sci_status status; 1506 enum sci_status phy_status; 1507 1508 status = SCI_SUCCESS; 1509 1510 for (index = 0; index < SCI_MAX_PHYS; index++) { 1511 phy_status = sci_phy_stop(&ihost->phys[index]); 1512 1513 if (phy_status != SCI_SUCCESS && 1514 phy_status != SCI_FAILURE_INVALID_STATE) { 1515 status = SCI_FAILURE; 1516 1517 dev_warn(&ihost->pdev->dev, 1518 "%s: Controller stop operation failed to stop " 1519 "phy %d because of status %d.\n", 1520 __func__, 1521 ihost->phys[index].phy_index, phy_status); 1522 } 1523 } 1524 1525 return status; 1526 } 1527 1528 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost) 1529 { 1530 u32 index; 1531 enum sci_status port_status; 1532 enum sci_status status = SCI_SUCCESS; 1533 1534 for (index = 0; index < ihost->logical_port_entries; index++) { 1535 struct isci_port *iport = &ihost->ports[index]; 1536 1537 port_status = sci_port_stop(iport); 1538 1539 if ((port_status != SCI_SUCCESS) && 1540 (port_status != SCI_FAILURE_INVALID_STATE)) { 1541 status = SCI_FAILURE; 1542 1543 dev_warn(&ihost->pdev->dev, 1544 "%s: Controller stop operation failed to " 1545 "stop port %d because of status %d.\n", 1546 __func__, 1547 iport->logical_port_index, 1548 port_status); 1549 } 1550 } 1551 1552 return status; 1553 } 1554 1555 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost) 1556 { 1557 u32 index; 1558 enum sci_status status; 1559 enum sci_status device_status; 1560 1561 status = SCI_SUCCESS; 1562 1563 for (index = 0; index < ihost->remote_node_entries; index++) { 1564 if (ihost->device_table[index] != NULL) { 1565 /* / @todo What timeout value do we want to provide to this request? */ 1566 device_status = sci_remote_device_stop(ihost->device_table[index], 0); 1567 1568 if ((device_status != SCI_SUCCESS) && 1569 (device_status != SCI_FAILURE_INVALID_STATE)) { 1570 dev_warn(&ihost->pdev->dev, 1571 "%s: Controller stop operation failed " 1572 "to stop device 0x%p because of " 1573 "status %d.\n", 1574 __func__, 1575 ihost->device_table[index], device_status); 1576 } 1577 } 1578 } 1579 1580 return status; 1581 } 1582 1583 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm) 1584 { 1585 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1586 1587 /* Stop all of the components for this controller */ 1588 sci_controller_stop_phys(ihost); 1589 sci_controller_stop_ports(ihost); 1590 sci_controller_stop_devices(ihost); 1591 } 1592 1593 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm) 1594 { 1595 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1596 1597 sci_del_timer(&ihost->timer); 1598 } 1599 1600 static void sci_controller_reset_hardware(struct isci_host *ihost) 1601 { 1602 /* Disable interrupts so we dont take any spurious interrupts */ 1603 sci_controller_disable_interrupts(ihost); 1604 1605 /* Reset the SCU */ 1606 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control); 1607 1608 /* Delay for 1ms to before clearing the CQP and UFQPR. */ 1609 udelay(1000); 1610 1611 /* The write to the CQGR clears the CQP */ 1612 writel(0x00000000, &ihost->smu_registers->completion_queue_get); 1613 1614 /* The write to the UFQGP clears the UFQPR */ 1615 writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); 1616 } 1617 1618 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm) 1619 { 1620 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1621 1622 sci_controller_reset_hardware(ihost); 1623 sci_change_state(&ihost->sm, SCIC_RESET); 1624 } 1625 1626 static const struct sci_base_state sci_controller_state_table[] = { 1627 [SCIC_INITIAL] = { 1628 .enter_state = sci_controller_initial_state_enter, 1629 }, 1630 [SCIC_RESET] = {}, 1631 [SCIC_INITIALIZING] = {}, 1632 [SCIC_INITIALIZED] = {}, 1633 [SCIC_STARTING] = { 1634 .exit_state = sci_controller_starting_state_exit, 1635 }, 1636 [SCIC_READY] = { 1637 .enter_state = sci_controller_ready_state_enter, 1638 .exit_state = sci_controller_ready_state_exit, 1639 }, 1640 [SCIC_RESETTING] = { 1641 .enter_state = sci_controller_resetting_state_enter, 1642 }, 1643 [SCIC_STOPPING] = { 1644 .enter_state = sci_controller_stopping_state_enter, 1645 .exit_state = sci_controller_stopping_state_exit, 1646 }, 1647 [SCIC_STOPPED] = {}, 1648 [SCIC_FAILED] = {} 1649 }; 1650 1651 static void sci_controller_set_default_config_parameters(struct isci_host *ihost) 1652 { 1653 /* these defaults are overridden by the platform / firmware */ 1654 u16 index; 1655 1656 /* Default to APC mode. */ 1657 ihost->oem_parameters.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE; 1658 1659 /* Default to APC mode. */ 1660 ihost->oem_parameters.controller.max_concurr_spin_up = 1; 1661 1662 /* Default to no SSC operation. */ 1663 ihost->oem_parameters.controller.do_enable_ssc = false; 1664 1665 /* Default to short cables on all phys. */ 1666 ihost->oem_parameters.controller.cable_selection_mask = 0; 1667 1668 /* Initialize all of the port parameter information to narrow ports. */ 1669 for (index = 0; index < SCI_MAX_PORTS; index++) { 1670 ihost->oem_parameters.ports[index].phy_mask = 0; 1671 } 1672 1673 /* Initialize all of the phy parameter information. */ 1674 for (index = 0; index < SCI_MAX_PHYS; index++) { 1675 /* Default to 3G (i.e. Gen 2). */ 1676 ihost->user_parameters.phys[index].max_speed_generation = 1677 SCIC_SDS_PARM_GEN2_SPEED; 1678 1679 /* the frequencies cannot be 0 */ 1680 ihost->user_parameters.phys[index].align_insertion_frequency = 0x7f; 1681 ihost->user_parameters.phys[index].in_connection_align_insertion_frequency = 0xff; 1682 ihost->user_parameters.phys[index].notify_enable_spin_up_insertion_frequency = 0x33; 1683 1684 /* 1685 * Previous Vitesse based expanders had a arbitration issue that 1686 * is worked around by having the upper 32-bits of SAS address 1687 * with a value greater then the Vitesse company identifier. 1688 * Hence, usage of 0x5FCFFFFF. */ 1689 ihost->oem_parameters.phys[index].sas_address.low = 0x1 + ihost->id; 1690 ihost->oem_parameters.phys[index].sas_address.high = 0x5FCFFFFF; 1691 } 1692 1693 ihost->user_parameters.stp_inactivity_timeout = 5; 1694 ihost->user_parameters.ssp_inactivity_timeout = 5; 1695 ihost->user_parameters.stp_max_occupancy_timeout = 5; 1696 ihost->user_parameters.ssp_max_occupancy_timeout = 20; 1697 ihost->user_parameters.no_outbound_task_timeout = 2; 1698 } 1699 1700 static void controller_timeout(unsigned long data) 1701 { 1702 struct sci_timer *tmr = (struct sci_timer *)data; 1703 struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer); 1704 struct sci_base_state_machine *sm = &ihost->sm; 1705 unsigned long flags; 1706 1707 spin_lock_irqsave(&ihost->scic_lock, flags); 1708 1709 if (tmr->cancel) 1710 goto done; 1711 1712 if (sm->current_state_id == SCIC_STARTING) 1713 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT); 1714 else if (sm->current_state_id == SCIC_STOPPING) { 1715 sci_change_state(sm, SCIC_FAILED); 1716 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT); 1717 } else /* / @todo Now what do we want to do in this case? */ 1718 dev_err(&ihost->pdev->dev, 1719 "%s: Controller timer fired when controller was not " 1720 "in a state being timed.\n", 1721 __func__); 1722 1723 done: 1724 spin_unlock_irqrestore(&ihost->scic_lock, flags); 1725 } 1726 1727 static enum sci_status sci_controller_construct(struct isci_host *ihost, 1728 void __iomem *scu_base, 1729 void __iomem *smu_base) 1730 { 1731 u8 i; 1732 1733 sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL); 1734 1735 ihost->scu_registers = scu_base; 1736 ihost->smu_registers = smu_base; 1737 1738 sci_port_configuration_agent_construct(&ihost->port_agent); 1739 1740 /* Construct the ports for this controller */ 1741 for (i = 0; i < SCI_MAX_PORTS; i++) 1742 sci_port_construct(&ihost->ports[i], i, ihost); 1743 sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost); 1744 1745 /* Construct the phys for this controller */ 1746 for (i = 0; i < SCI_MAX_PHYS; i++) { 1747 /* Add all the PHYs to the dummy port */ 1748 sci_phy_construct(&ihost->phys[i], 1749 &ihost->ports[SCI_MAX_PORTS], i); 1750 } 1751 1752 ihost->invalid_phy_mask = 0; 1753 1754 sci_init_timer(&ihost->timer, controller_timeout); 1755 1756 /* Initialize the User and OEM parameters to default values. */ 1757 sci_controller_set_default_config_parameters(ihost); 1758 1759 return sci_controller_reset(ihost); 1760 } 1761 1762 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version) 1763 { 1764 int i; 1765 1766 for (i = 0; i < SCI_MAX_PORTS; i++) 1767 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) 1768 return -EINVAL; 1769 1770 for (i = 0; i < SCI_MAX_PHYS; i++) 1771 if (oem->phys[i].sas_address.high == 0 && 1772 oem->phys[i].sas_address.low == 0) 1773 return -EINVAL; 1774 1775 if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) { 1776 for (i = 0; i < SCI_MAX_PHYS; i++) 1777 if (oem->ports[i].phy_mask != 0) 1778 return -EINVAL; 1779 } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { 1780 u8 phy_mask = 0; 1781 1782 for (i = 0; i < SCI_MAX_PHYS; i++) 1783 phy_mask |= oem->ports[i].phy_mask; 1784 1785 if (phy_mask == 0) 1786 return -EINVAL; 1787 } else 1788 return -EINVAL; 1789 1790 if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT || 1791 oem->controller.max_concurr_spin_up < 1) 1792 return -EINVAL; 1793 1794 if (oem->controller.do_enable_ssc) { 1795 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1) 1796 return -EINVAL; 1797 1798 if (version >= ISCI_ROM_VER_1_1) { 1799 u8 test = oem->controller.ssc_sata_tx_spread_level; 1800 1801 switch (test) { 1802 case 0: 1803 case 2: 1804 case 3: 1805 case 6: 1806 case 7: 1807 break; 1808 default: 1809 return -EINVAL; 1810 } 1811 1812 test = oem->controller.ssc_sas_tx_spread_level; 1813 if (oem->controller.ssc_sas_tx_type == 0) { 1814 switch (test) { 1815 case 0: 1816 case 2: 1817 case 3: 1818 break; 1819 default: 1820 return -EINVAL; 1821 } 1822 } else if (oem->controller.ssc_sas_tx_type == 1) { 1823 switch (test) { 1824 case 0: 1825 case 3: 1826 case 6: 1827 break; 1828 default: 1829 return -EINVAL; 1830 } 1831 } 1832 } 1833 } 1834 1835 return 0; 1836 } 1837 1838 static enum sci_status sci_oem_parameters_set(struct isci_host *ihost) 1839 { 1840 u32 state = ihost->sm.current_state_id; 1841 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev); 1842 1843 if (state == SCIC_RESET || 1844 state == SCIC_INITIALIZING || 1845 state == SCIC_INITIALIZED) { 1846 u8 oem_version = pci_info->orom ? pci_info->orom->hdr.version : 1847 ISCI_ROM_VER_1_0; 1848 1849 if (sci_oem_parameters_validate(&ihost->oem_parameters, 1850 oem_version)) 1851 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 1852 1853 return SCI_SUCCESS; 1854 } 1855 1856 return SCI_FAILURE_INVALID_STATE; 1857 } 1858 1859 static u8 max_spin_up(struct isci_host *ihost) 1860 { 1861 if (ihost->user_parameters.max_concurr_spinup) 1862 return min_t(u8, ihost->user_parameters.max_concurr_spinup, 1863 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT); 1864 else 1865 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up, 1866 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT); 1867 } 1868 1869 static void power_control_timeout(unsigned long data) 1870 { 1871 struct sci_timer *tmr = (struct sci_timer *)data; 1872 struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer); 1873 struct isci_phy *iphy; 1874 unsigned long flags; 1875 u8 i; 1876 1877 spin_lock_irqsave(&ihost->scic_lock, flags); 1878 1879 if (tmr->cancel) 1880 goto done; 1881 1882 ihost->power_control.phys_granted_power = 0; 1883 1884 if (ihost->power_control.phys_waiting == 0) { 1885 ihost->power_control.timer_started = false; 1886 goto done; 1887 } 1888 1889 for (i = 0; i < SCI_MAX_PHYS; i++) { 1890 1891 if (ihost->power_control.phys_waiting == 0) 1892 break; 1893 1894 iphy = ihost->power_control.requesters[i]; 1895 if (iphy == NULL) 1896 continue; 1897 1898 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost)) 1899 break; 1900 1901 ihost->power_control.requesters[i] = NULL; 1902 ihost->power_control.phys_waiting--; 1903 ihost->power_control.phys_granted_power++; 1904 sci_phy_consume_power_handler(iphy); 1905 1906 if (iphy->protocol == SAS_PROTOCOL_SSP) { 1907 u8 j; 1908 1909 for (j = 0; j < SCI_MAX_PHYS; j++) { 1910 struct isci_phy *requester = ihost->power_control.requesters[j]; 1911 1912 /* 1913 * Search the power_control queue to see if there are other phys 1914 * attached to the same remote device. If found, take all of 1915 * them out of await_sas_power state. 1916 */ 1917 if (requester != NULL && requester != iphy) { 1918 u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr, 1919 iphy->frame_rcvd.iaf.sas_addr, 1920 sizeof(requester->frame_rcvd.iaf.sas_addr)); 1921 1922 if (other == 0) { 1923 ihost->power_control.requesters[j] = NULL; 1924 ihost->power_control.phys_waiting--; 1925 sci_phy_consume_power_handler(requester); 1926 } 1927 } 1928 } 1929 } 1930 } 1931 1932 /* 1933 * It doesn't matter if the power list is empty, we need to start the 1934 * timer in case another phy becomes ready. 1935 */ 1936 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 1937 ihost->power_control.timer_started = true; 1938 1939 done: 1940 spin_unlock_irqrestore(&ihost->scic_lock, flags); 1941 } 1942 1943 void sci_controller_power_control_queue_insert(struct isci_host *ihost, 1944 struct isci_phy *iphy) 1945 { 1946 BUG_ON(iphy == NULL); 1947 1948 if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) { 1949 ihost->power_control.phys_granted_power++; 1950 sci_phy_consume_power_handler(iphy); 1951 1952 /* 1953 * stop and start the power_control timer. When the timer fires, the 1954 * no_of_phys_granted_power will be set to 0 1955 */ 1956 if (ihost->power_control.timer_started) 1957 sci_del_timer(&ihost->power_control.timer); 1958 1959 sci_mod_timer(&ihost->power_control.timer, 1960 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 1961 ihost->power_control.timer_started = true; 1962 1963 } else { 1964 /* 1965 * There are phys, attached to the same sas address as this phy, are 1966 * already in READY state, this phy don't need wait. 1967 */ 1968 u8 i; 1969 struct isci_phy *current_phy; 1970 1971 for (i = 0; i < SCI_MAX_PHYS; i++) { 1972 u8 other; 1973 current_phy = &ihost->phys[i]; 1974 1975 other = memcmp(current_phy->frame_rcvd.iaf.sas_addr, 1976 iphy->frame_rcvd.iaf.sas_addr, 1977 sizeof(current_phy->frame_rcvd.iaf.sas_addr)); 1978 1979 if (current_phy->sm.current_state_id == SCI_PHY_READY && 1980 current_phy->protocol == SAS_PROTOCOL_SSP && 1981 other == 0) { 1982 sci_phy_consume_power_handler(iphy); 1983 break; 1984 } 1985 } 1986 1987 if (i == SCI_MAX_PHYS) { 1988 /* Add the phy in the waiting list */ 1989 ihost->power_control.requesters[iphy->phy_index] = iphy; 1990 ihost->power_control.phys_waiting++; 1991 } 1992 } 1993 } 1994 1995 void sci_controller_power_control_queue_remove(struct isci_host *ihost, 1996 struct isci_phy *iphy) 1997 { 1998 BUG_ON(iphy == NULL); 1999 2000 if (ihost->power_control.requesters[iphy->phy_index]) 2001 ihost->power_control.phys_waiting--; 2002 2003 ihost->power_control.requesters[iphy->phy_index] = NULL; 2004 } 2005 2006 static int is_long_cable(int phy, unsigned char selection_byte) 2007 { 2008 return !!(selection_byte & (1 << phy)); 2009 } 2010 2011 static int is_medium_cable(int phy, unsigned char selection_byte) 2012 { 2013 return !!(selection_byte & (1 << (phy + 4))); 2014 } 2015 2016 static enum cable_selections decode_selection_byte( 2017 int phy, 2018 unsigned char selection_byte) 2019 { 2020 return ((selection_byte & (1 << phy)) ? 1 : 0) 2021 + (selection_byte & (1 << (phy + 4)) ? 2 : 0); 2022 } 2023 2024 static unsigned char *to_cable_select(struct isci_host *ihost) 2025 { 2026 if (is_cable_select_overridden()) 2027 return ((unsigned char *)&cable_selection_override) 2028 + ihost->id; 2029 else 2030 return &ihost->oem_parameters.controller.cable_selection_mask; 2031 } 2032 2033 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy) 2034 { 2035 return decode_selection_byte(phy, *to_cable_select(ihost)); 2036 } 2037 2038 char *lookup_cable_names(enum cable_selections selection) 2039 { 2040 static char *cable_names[] = { 2041 [short_cable] = "short", 2042 [long_cable] = "long", 2043 [medium_cable] = "medium", 2044 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */ 2045 }; 2046 return (selection <= undefined_cable) ? cable_names[selection] 2047 : cable_names[undefined_cable]; 2048 } 2049 2050 #define AFE_REGISTER_WRITE_DELAY 10 2051 2052 static void sci_controller_afe_initialization(struct isci_host *ihost) 2053 { 2054 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe; 2055 const struct sci_oem_params *oem = &ihost->oem_parameters; 2056 struct pci_dev *pdev = ihost->pdev; 2057 u32 afe_status; 2058 u32 phy_id; 2059 unsigned char cable_selection_mask = *to_cable_select(ihost); 2060 2061 /* Clear DFX Status registers */ 2062 writel(0x0081000f, &afe->afe_dfx_master_control0); 2063 udelay(AFE_REGISTER_WRITE_DELAY); 2064 2065 if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) { 2066 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement 2067 * Timer, PM Stagger Timer 2068 */ 2069 writel(0x0007FFFF, &afe->afe_pmsn_master_control2); 2070 udelay(AFE_REGISTER_WRITE_DELAY); 2071 } 2072 2073 /* Configure bias currents to normal */ 2074 if (is_a2(pdev)) 2075 writel(0x00005A00, &afe->afe_bias_control); 2076 else if (is_b0(pdev) || is_c0(pdev)) 2077 writel(0x00005F00, &afe->afe_bias_control); 2078 else if (is_c1(pdev)) 2079 writel(0x00005500, &afe->afe_bias_control); 2080 2081 udelay(AFE_REGISTER_WRITE_DELAY); 2082 2083 /* Enable PLL */ 2084 if (is_a2(pdev)) 2085 writel(0x80040908, &afe->afe_pll_control0); 2086 else if (is_b0(pdev) || is_c0(pdev)) 2087 writel(0x80040A08, &afe->afe_pll_control0); 2088 else if (is_c1(pdev)) { 2089 writel(0x80000B08, &afe->afe_pll_control0); 2090 udelay(AFE_REGISTER_WRITE_DELAY); 2091 writel(0x00000B08, &afe->afe_pll_control0); 2092 udelay(AFE_REGISTER_WRITE_DELAY); 2093 writel(0x80000B08, &afe->afe_pll_control0); 2094 } 2095 2096 udelay(AFE_REGISTER_WRITE_DELAY); 2097 2098 /* Wait for the PLL to lock */ 2099 do { 2100 afe_status = readl(&afe->afe_common_block_status); 2101 udelay(AFE_REGISTER_WRITE_DELAY); 2102 } while ((afe_status & 0x00001000) == 0); 2103 2104 if (is_a2(pdev)) { 2105 /* Shorten SAS SNW lock time (RxLock timer value from 76 2106 * us to 50 us) 2107 */ 2108 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0); 2109 udelay(AFE_REGISTER_WRITE_DELAY); 2110 } 2111 2112 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { 2113 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id]; 2114 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; 2115 int cable_length_long = 2116 is_long_cable(phy_id, cable_selection_mask); 2117 int cable_length_medium = 2118 is_medium_cable(phy_id, cable_selection_mask); 2119 2120 if (is_a2(pdev)) { 2121 /* All defaults, except the Receive Word 2122 * Alignament/Comma Detect Enable....(0xe800) 2123 */ 2124 writel(0x00004512, &xcvr->afe_xcvr_control0); 2125 udelay(AFE_REGISTER_WRITE_DELAY); 2126 2127 writel(0x0050100F, &xcvr->afe_xcvr_control1); 2128 udelay(AFE_REGISTER_WRITE_DELAY); 2129 } else if (is_b0(pdev)) { 2130 /* Configure transmitter SSC parameters */ 2131 writel(0x00030000, &xcvr->afe_tx_ssc_control); 2132 udelay(AFE_REGISTER_WRITE_DELAY); 2133 } else if (is_c0(pdev)) { 2134 /* Configure transmitter SSC parameters */ 2135 writel(0x00010202, &xcvr->afe_tx_ssc_control); 2136 udelay(AFE_REGISTER_WRITE_DELAY); 2137 2138 /* All defaults, except the Receive Word 2139 * Alignament/Comma Detect Enable....(0xe800) 2140 */ 2141 writel(0x00014500, &xcvr->afe_xcvr_control0); 2142 udelay(AFE_REGISTER_WRITE_DELAY); 2143 } else if (is_c1(pdev)) { 2144 /* Configure transmitter SSC parameters */ 2145 writel(0x00010202, &xcvr->afe_tx_ssc_control); 2146 udelay(AFE_REGISTER_WRITE_DELAY); 2147 2148 /* All defaults, except the Receive Word 2149 * Alignament/Comma Detect Enable....(0xe800) 2150 */ 2151 writel(0x0001C500, &xcvr->afe_xcvr_control0); 2152 udelay(AFE_REGISTER_WRITE_DELAY); 2153 } 2154 2155 /* Power up TX and RX out from power down (PWRDNTX and 2156 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c) 2157 */ 2158 if (is_a2(pdev)) 2159 writel(0x000003F0, &xcvr->afe_channel_control); 2160 else if (is_b0(pdev)) { 2161 writel(0x000003D7, &xcvr->afe_channel_control); 2162 udelay(AFE_REGISTER_WRITE_DELAY); 2163 2164 writel(0x000003D4, &xcvr->afe_channel_control); 2165 } else if (is_c0(pdev)) { 2166 writel(0x000001E7, &xcvr->afe_channel_control); 2167 udelay(AFE_REGISTER_WRITE_DELAY); 2168 2169 writel(0x000001E4, &xcvr->afe_channel_control); 2170 } else if (is_c1(pdev)) { 2171 writel(cable_length_long ? 0x000002F7 : 0x000001F7, 2172 &xcvr->afe_channel_control); 2173 udelay(AFE_REGISTER_WRITE_DELAY); 2174 2175 writel(cable_length_long ? 0x000002F4 : 0x000001F4, 2176 &xcvr->afe_channel_control); 2177 } 2178 udelay(AFE_REGISTER_WRITE_DELAY); 2179 2180 if (is_a2(pdev)) { 2181 /* Enable TX equalization (0xe824) */ 2182 writel(0x00040000, &xcvr->afe_tx_control); 2183 udelay(AFE_REGISTER_WRITE_DELAY); 2184 } 2185 2186 if (is_a2(pdev) || is_b0(pdev)) 2187 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, 2188 * TPD=0x0(TX Power On), RDD=0x0(RX Detect 2189 * Enabled) ....(0xe800) 2190 */ 2191 writel(0x00004100, &xcvr->afe_xcvr_control0); 2192 else if (is_c0(pdev)) 2193 writel(0x00014100, &xcvr->afe_xcvr_control0); 2194 else if (is_c1(pdev)) 2195 writel(0x0001C100, &xcvr->afe_xcvr_control0); 2196 udelay(AFE_REGISTER_WRITE_DELAY); 2197 2198 /* Leave DFE/FFE on */ 2199 if (is_a2(pdev)) 2200 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0); 2201 else if (is_b0(pdev)) { 2202 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0); 2203 udelay(AFE_REGISTER_WRITE_DELAY); 2204 /* Enable TX equalization (0xe824) */ 2205 writel(0x00040000, &xcvr->afe_tx_control); 2206 } else if (is_c0(pdev)) { 2207 writel(0x01400C0F, &xcvr->afe_rx_ssc_control1); 2208 udelay(AFE_REGISTER_WRITE_DELAY); 2209 2210 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0); 2211 udelay(AFE_REGISTER_WRITE_DELAY); 2212 2213 /* Enable TX equalization (0xe824) */ 2214 writel(0x00040000, &xcvr->afe_tx_control); 2215 } else if (is_c1(pdev)) { 2216 writel(cable_length_long ? 0x01500C0C : 2217 cable_length_medium ? 0x01400C0D : 0x02400C0D, 2218 &xcvr->afe_xcvr_control1); 2219 udelay(AFE_REGISTER_WRITE_DELAY); 2220 2221 writel(0x000003E0, &xcvr->afe_dfx_rx_control1); 2222 udelay(AFE_REGISTER_WRITE_DELAY); 2223 2224 writel(cable_length_long ? 0x33091C1F : 2225 cable_length_medium ? 0x3315181F : 0x2B17161F, 2226 &xcvr->afe_rx_ssc_control0); 2227 udelay(AFE_REGISTER_WRITE_DELAY); 2228 2229 /* Enable TX equalization (0xe824) */ 2230 writel(0x00040000, &xcvr->afe_tx_control); 2231 } 2232 2233 udelay(AFE_REGISTER_WRITE_DELAY); 2234 2235 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0); 2236 udelay(AFE_REGISTER_WRITE_DELAY); 2237 2238 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1); 2239 udelay(AFE_REGISTER_WRITE_DELAY); 2240 2241 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2); 2242 udelay(AFE_REGISTER_WRITE_DELAY); 2243 2244 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3); 2245 udelay(AFE_REGISTER_WRITE_DELAY); 2246 } 2247 2248 /* Transfer control to the PEs */ 2249 writel(0x00010f00, &afe->afe_dfx_master_control0); 2250 udelay(AFE_REGISTER_WRITE_DELAY); 2251 } 2252 2253 static void sci_controller_initialize_power_control(struct isci_host *ihost) 2254 { 2255 sci_init_timer(&ihost->power_control.timer, power_control_timeout); 2256 2257 memset(ihost->power_control.requesters, 0, 2258 sizeof(ihost->power_control.requesters)); 2259 2260 ihost->power_control.phys_waiting = 0; 2261 ihost->power_control.phys_granted_power = 0; 2262 } 2263 2264 static enum sci_status sci_controller_initialize(struct isci_host *ihost) 2265 { 2266 struct sci_base_state_machine *sm = &ihost->sm; 2267 enum sci_status result = SCI_FAILURE; 2268 unsigned long i, state, val; 2269 2270 if (ihost->sm.current_state_id != SCIC_RESET) { 2271 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 2272 __func__, ihost->sm.current_state_id); 2273 return SCI_FAILURE_INVALID_STATE; 2274 } 2275 2276 sci_change_state(sm, SCIC_INITIALIZING); 2277 2278 sci_init_timer(&ihost->phy_timer, phy_startup_timeout); 2279 2280 ihost->next_phy_to_start = 0; 2281 ihost->phy_startup_timer_pending = false; 2282 2283 sci_controller_initialize_power_control(ihost); 2284 2285 /* 2286 * There is nothing to do here for B0 since we do not have to 2287 * program the AFE registers. 2288 * / @todo The AFE settings are supposed to be correct for the B0 but 2289 * / presently they seem to be wrong. */ 2290 sci_controller_afe_initialization(ihost); 2291 2292 2293 /* Take the hardware out of reset */ 2294 writel(0, &ihost->smu_registers->soft_reset_control); 2295 2296 /* 2297 * / @todo Provide meaningfull error code for hardware failure 2298 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */ 2299 for (i = 100; i >= 1; i--) { 2300 u32 status; 2301 2302 /* Loop until the hardware reports success */ 2303 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME); 2304 status = readl(&ihost->smu_registers->control_status); 2305 2306 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED) 2307 break; 2308 } 2309 if (i == 0) 2310 goto out; 2311 2312 /* 2313 * Determine what are the actaul device capacities that the 2314 * hardware will support */ 2315 val = readl(&ihost->smu_registers->device_context_capacity); 2316 2317 /* Record the smaller of the two capacity values */ 2318 ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS); 2319 ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS); 2320 ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES); 2321 2322 /* 2323 * Make all PEs that are unassigned match up with the 2324 * logical ports 2325 */ 2326 for (i = 0; i < ihost->logical_port_entries; i++) { 2327 struct scu_port_task_scheduler_group_registers __iomem 2328 *ptsg = &ihost->scu_registers->peg0.ptsg; 2329 2330 writel(i, &ptsg->protocol_engine[i]); 2331 } 2332 2333 /* Initialize hardware PCI Relaxed ordering in DMA engines */ 2334 val = readl(&ihost->scu_registers->sdma.pdma_configuration); 2335 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); 2336 writel(val, &ihost->scu_registers->sdma.pdma_configuration); 2337 2338 val = readl(&ihost->scu_registers->sdma.cdma_configuration); 2339 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); 2340 writel(val, &ihost->scu_registers->sdma.cdma_configuration); 2341 2342 /* 2343 * Initialize the PHYs before the PORTs because the PHY registers 2344 * are accessed during the port initialization. 2345 */ 2346 for (i = 0; i < SCI_MAX_PHYS; i++) { 2347 result = sci_phy_initialize(&ihost->phys[i], 2348 &ihost->scu_registers->peg0.pe[i].tl, 2349 &ihost->scu_registers->peg0.pe[i].ll); 2350 if (result != SCI_SUCCESS) 2351 goto out; 2352 } 2353 2354 for (i = 0; i < ihost->logical_port_entries; i++) { 2355 struct isci_port *iport = &ihost->ports[i]; 2356 2357 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i]; 2358 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0]; 2359 iport->viit_registers = &ihost->scu_registers->peg0.viit[i]; 2360 } 2361 2362 result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent); 2363 2364 out: 2365 /* Advance the controller state machine */ 2366 if (result == SCI_SUCCESS) 2367 state = SCIC_INITIALIZED; 2368 else 2369 state = SCIC_FAILED; 2370 sci_change_state(sm, state); 2371 2372 return result; 2373 } 2374 2375 static enum sci_status sci_user_parameters_set(struct isci_host *ihost, 2376 struct sci_user_parameters *sci_parms) 2377 { 2378 u32 state = ihost->sm.current_state_id; 2379 2380 if (state == SCIC_RESET || 2381 state == SCIC_INITIALIZING || 2382 state == SCIC_INITIALIZED) { 2383 u16 index; 2384 2385 /* 2386 * Validate the user parameters. If they are not legal, then 2387 * return a failure. 2388 */ 2389 for (index = 0; index < SCI_MAX_PHYS; index++) { 2390 struct sci_phy_user_params *user_phy; 2391 2392 user_phy = &sci_parms->phys[index]; 2393 2394 if (!((user_phy->max_speed_generation <= 2395 SCIC_SDS_PARM_MAX_SPEED) && 2396 (user_phy->max_speed_generation > 2397 SCIC_SDS_PARM_NO_SPEED))) 2398 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 2399 2400 if (user_phy->in_connection_align_insertion_frequency < 2401 3) 2402 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 2403 2404 if ((user_phy->in_connection_align_insertion_frequency < 2405 3) || 2406 (user_phy->align_insertion_frequency == 0) || 2407 (user_phy-> 2408 notify_enable_spin_up_insertion_frequency == 2409 0)) 2410 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 2411 } 2412 2413 if ((sci_parms->stp_inactivity_timeout == 0) || 2414 (sci_parms->ssp_inactivity_timeout == 0) || 2415 (sci_parms->stp_max_occupancy_timeout == 0) || 2416 (sci_parms->ssp_max_occupancy_timeout == 0) || 2417 (sci_parms->no_outbound_task_timeout == 0)) 2418 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 2419 2420 memcpy(&ihost->user_parameters, sci_parms, sizeof(*sci_parms)); 2421 2422 return SCI_SUCCESS; 2423 } 2424 2425 return SCI_FAILURE_INVALID_STATE; 2426 } 2427 2428 static int sci_controller_mem_init(struct isci_host *ihost) 2429 { 2430 struct device *dev = &ihost->pdev->dev; 2431 dma_addr_t dma; 2432 size_t size; 2433 int err; 2434 2435 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32); 2436 ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL); 2437 if (!ihost->completion_queue) 2438 return -ENOMEM; 2439 2440 writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower); 2441 writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper); 2442 2443 size = ihost->remote_node_entries * sizeof(union scu_remote_node_context); 2444 ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma, 2445 GFP_KERNEL); 2446 if (!ihost->remote_node_context_table) 2447 return -ENOMEM; 2448 2449 writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower); 2450 writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper); 2451 2452 size = ihost->task_context_entries * sizeof(struct scu_task_context), 2453 ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL); 2454 if (!ihost->task_context_table) 2455 return -ENOMEM; 2456 2457 ihost->task_context_dma = dma; 2458 writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower); 2459 writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper); 2460 2461 err = sci_unsolicited_frame_control_construct(ihost); 2462 if (err) 2463 return err; 2464 2465 /* 2466 * Inform the silicon as to the location of the UF headers and 2467 * address table. 2468 */ 2469 writel(lower_32_bits(ihost->uf_control.headers.physical_address), 2470 &ihost->scu_registers->sdma.uf_header_base_address_lower); 2471 writel(upper_32_bits(ihost->uf_control.headers.physical_address), 2472 &ihost->scu_registers->sdma.uf_header_base_address_upper); 2473 2474 writel(lower_32_bits(ihost->uf_control.address_table.physical_address), 2475 &ihost->scu_registers->sdma.uf_address_table_lower); 2476 writel(upper_32_bits(ihost->uf_control.address_table.physical_address), 2477 &ihost->scu_registers->sdma.uf_address_table_upper); 2478 2479 return 0; 2480 } 2481 2482 int isci_host_init(struct isci_host *ihost) 2483 { 2484 int err = 0, i; 2485 enum sci_status status; 2486 struct sci_user_parameters sci_user_params; 2487 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev); 2488 2489 spin_lock_init(&ihost->scic_lock); 2490 init_waitqueue_head(&ihost->eventq); 2491 2492 status = sci_controller_construct(ihost, scu_base(ihost), 2493 smu_base(ihost)); 2494 2495 if (status != SCI_SUCCESS) { 2496 dev_err(&ihost->pdev->dev, 2497 "%s: sci_controller_construct failed - status = %x\n", 2498 __func__, 2499 status); 2500 return -ENODEV; 2501 } 2502 2503 ihost->sas_ha.dev = &ihost->pdev->dev; 2504 ihost->sas_ha.lldd_ha = ihost; 2505 2506 /* 2507 * grab initial values stored in the controller object for OEM and USER 2508 * parameters 2509 */ 2510 isci_user_parameters_get(&sci_user_params); 2511 status = sci_user_parameters_set(ihost, &sci_user_params); 2512 if (status != SCI_SUCCESS) { 2513 dev_warn(&ihost->pdev->dev, 2514 "%s: sci_user_parameters_set failed\n", 2515 __func__); 2516 return -ENODEV; 2517 } 2518 2519 /* grab any OEM parameters specified in orom */ 2520 if (pci_info->orom) { 2521 status = isci_parse_oem_parameters(&ihost->oem_parameters, 2522 pci_info->orom, 2523 ihost->id); 2524 if (status != SCI_SUCCESS) { 2525 dev_warn(&ihost->pdev->dev, 2526 "parsing firmware oem parameters failed\n"); 2527 return -EINVAL; 2528 } 2529 } 2530 2531 status = sci_oem_parameters_set(ihost); 2532 if (status != SCI_SUCCESS) { 2533 dev_warn(&ihost->pdev->dev, 2534 "%s: sci_oem_parameters_set failed\n", 2535 __func__); 2536 return -ENODEV; 2537 } 2538 2539 tasklet_init(&ihost->completion_tasklet, 2540 isci_host_completion_routine, (unsigned long)ihost); 2541 2542 INIT_LIST_HEAD(&ihost->requests_to_complete); 2543 INIT_LIST_HEAD(&ihost->requests_to_errorback); 2544 2545 spin_lock_irq(&ihost->scic_lock); 2546 status = sci_controller_initialize(ihost); 2547 spin_unlock_irq(&ihost->scic_lock); 2548 if (status != SCI_SUCCESS) { 2549 dev_warn(&ihost->pdev->dev, 2550 "%s: sci_controller_initialize failed -" 2551 " status = 0x%x\n", 2552 __func__, status); 2553 return -ENODEV; 2554 } 2555 2556 err = sci_controller_mem_init(ihost); 2557 if (err) 2558 return err; 2559 2560 for (i = 0; i < SCI_MAX_PORTS; i++) { 2561 struct isci_port *iport = &ihost->ports[i]; 2562 2563 INIT_LIST_HEAD(&iport->remote_dev_list); 2564 iport->isci_host = ihost; 2565 } 2566 2567 for (i = 0; i < SCI_MAX_PHYS; i++) 2568 isci_phy_init(&ihost->phys[i], ihost, i); 2569 2570 /* enable sgpio */ 2571 writel(1, &ihost->scu_registers->peg0.sgpio.interface_control); 2572 for (i = 0; i < isci_gpio_count(ihost); i++) 2573 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]); 2574 writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code); 2575 2576 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) { 2577 struct isci_remote_device *idev = &ihost->devices[i]; 2578 2579 INIT_LIST_HEAD(&idev->reqs_in_process); 2580 INIT_LIST_HEAD(&idev->node); 2581 } 2582 2583 for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) { 2584 struct isci_request *ireq; 2585 dma_addr_t dma; 2586 2587 ireq = dmam_alloc_coherent(&ihost->pdev->dev, 2588 sizeof(struct isci_request), &dma, 2589 GFP_KERNEL); 2590 if (!ireq) 2591 return -ENOMEM; 2592 2593 ireq->tc = &ihost->task_context_table[i]; 2594 ireq->owning_controller = ihost; 2595 spin_lock_init(&ireq->state_lock); 2596 ireq->request_daddr = dma; 2597 ireq->isci_host = ihost; 2598 ihost->reqs[i] = ireq; 2599 } 2600 2601 return 0; 2602 } 2603 2604 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport, 2605 struct isci_phy *iphy) 2606 { 2607 switch (ihost->sm.current_state_id) { 2608 case SCIC_STARTING: 2609 sci_del_timer(&ihost->phy_timer); 2610 ihost->phy_startup_timer_pending = false; 2611 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent, 2612 iport, iphy); 2613 sci_controller_start_next_phy(ihost); 2614 break; 2615 case SCIC_READY: 2616 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent, 2617 iport, iphy); 2618 break; 2619 default: 2620 dev_dbg(&ihost->pdev->dev, 2621 "%s: SCIC Controller linkup event from phy %d in " 2622 "unexpected state %d\n", __func__, iphy->phy_index, 2623 ihost->sm.current_state_id); 2624 } 2625 } 2626 2627 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport, 2628 struct isci_phy *iphy) 2629 { 2630 switch (ihost->sm.current_state_id) { 2631 case SCIC_STARTING: 2632 case SCIC_READY: 2633 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent, 2634 iport, iphy); 2635 break; 2636 default: 2637 dev_dbg(&ihost->pdev->dev, 2638 "%s: SCIC Controller linkdown event from phy %d in " 2639 "unexpected state %d\n", 2640 __func__, 2641 iphy->phy_index, 2642 ihost->sm.current_state_id); 2643 } 2644 } 2645 2646 static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost) 2647 { 2648 u32 index; 2649 2650 for (index = 0; index < ihost->remote_node_entries; index++) { 2651 if ((ihost->device_table[index] != NULL) && 2652 (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING)) 2653 return true; 2654 } 2655 2656 return false; 2657 } 2658 2659 void sci_controller_remote_device_stopped(struct isci_host *ihost, 2660 struct isci_remote_device *idev) 2661 { 2662 if (ihost->sm.current_state_id != SCIC_STOPPING) { 2663 dev_dbg(&ihost->pdev->dev, 2664 "SCIC Controller 0x%p remote device stopped event " 2665 "from device 0x%p in unexpected state %d\n", 2666 ihost, idev, 2667 ihost->sm.current_state_id); 2668 return; 2669 } 2670 2671 if (!sci_controller_has_remote_devices_stopping(ihost)) 2672 sci_change_state(&ihost->sm, SCIC_STOPPED); 2673 } 2674 2675 void sci_controller_post_request(struct isci_host *ihost, u32 request) 2676 { 2677 dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n", 2678 __func__, ihost->id, request); 2679 2680 writel(request, &ihost->smu_registers->post_context_port); 2681 } 2682 2683 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag) 2684 { 2685 u16 task_index; 2686 u16 task_sequence; 2687 2688 task_index = ISCI_TAG_TCI(io_tag); 2689 2690 if (task_index < ihost->task_context_entries) { 2691 struct isci_request *ireq = ihost->reqs[task_index]; 2692 2693 if (test_bit(IREQ_ACTIVE, &ireq->flags)) { 2694 task_sequence = ISCI_TAG_SEQ(io_tag); 2695 2696 if (task_sequence == ihost->io_request_sequence[task_index]) 2697 return ireq; 2698 } 2699 } 2700 2701 return NULL; 2702 } 2703 2704 /** 2705 * This method allocates remote node index and the reserves the remote node 2706 * context space for use. This method can fail if there are no more remote 2707 * node index available. 2708 * @scic: This is the controller object which contains the set of 2709 * free remote node ids 2710 * @sci_dev: This is the device object which is requesting the a remote node 2711 * id 2712 * @node_id: This is the remote node id that is assinged to the device if one 2713 * is available 2714 * 2715 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote 2716 * node index available. 2717 */ 2718 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost, 2719 struct isci_remote_device *idev, 2720 u16 *node_id) 2721 { 2722 u16 node_index; 2723 u32 remote_node_count = sci_remote_device_node_count(idev); 2724 2725 node_index = sci_remote_node_table_allocate_remote_node( 2726 &ihost->available_remote_nodes, remote_node_count 2727 ); 2728 2729 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { 2730 ihost->device_table[node_index] = idev; 2731 2732 *node_id = node_index; 2733 2734 return SCI_SUCCESS; 2735 } 2736 2737 return SCI_FAILURE_INSUFFICIENT_RESOURCES; 2738 } 2739 2740 void sci_controller_free_remote_node_context(struct isci_host *ihost, 2741 struct isci_remote_device *idev, 2742 u16 node_id) 2743 { 2744 u32 remote_node_count = sci_remote_device_node_count(idev); 2745 2746 if (ihost->device_table[node_id] == idev) { 2747 ihost->device_table[node_id] = NULL; 2748 2749 sci_remote_node_table_release_remote_node_index( 2750 &ihost->available_remote_nodes, remote_node_count, node_id 2751 ); 2752 } 2753 } 2754 2755 void sci_controller_copy_sata_response(void *response_buffer, 2756 void *frame_header, 2757 void *frame_buffer) 2758 { 2759 /* XXX type safety? */ 2760 memcpy(response_buffer, frame_header, sizeof(u32)); 2761 2762 memcpy(response_buffer + sizeof(u32), 2763 frame_buffer, 2764 sizeof(struct dev_to_host_fis) - sizeof(u32)); 2765 } 2766 2767 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index) 2768 { 2769 if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index)) 2770 writel(ihost->uf_control.get, 2771 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); 2772 } 2773 2774 void isci_tci_free(struct isci_host *ihost, u16 tci) 2775 { 2776 u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1); 2777 2778 ihost->tci_pool[tail] = tci; 2779 ihost->tci_tail = tail + 1; 2780 } 2781 2782 static u16 isci_tci_alloc(struct isci_host *ihost) 2783 { 2784 u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1); 2785 u16 tci = ihost->tci_pool[head]; 2786 2787 ihost->tci_head = head + 1; 2788 return tci; 2789 } 2790 2791 static u16 isci_tci_space(struct isci_host *ihost) 2792 { 2793 return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); 2794 } 2795 2796 u16 isci_alloc_tag(struct isci_host *ihost) 2797 { 2798 if (isci_tci_space(ihost)) { 2799 u16 tci = isci_tci_alloc(ihost); 2800 u8 seq = ihost->io_request_sequence[tci]; 2801 2802 return ISCI_TAG(seq, tci); 2803 } 2804 2805 return SCI_CONTROLLER_INVALID_IO_TAG; 2806 } 2807 2808 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag) 2809 { 2810 u16 tci = ISCI_TAG_TCI(io_tag); 2811 u16 seq = ISCI_TAG_SEQ(io_tag); 2812 2813 /* prevent tail from passing head */ 2814 if (isci_tci_active(ihost) == 0) 2815 return SCI_FAILURE_INVALID_IO_TAG; 2816 2817 if (seq == ihost->io_request_sequence[tci]) { 2818 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1); 2819 2820 isci_tci_free(ihost, tci); 2821 2822 return SCI_SUCCESS; 2823 } 2824 return SCI_FAILURE_INVALID_IO_TAG; 2825 } 2826 2827 enum sci_status sci_controller_start_io(struct isci_host *ihost, 2828 struct isci_remote_device *idev, 2829 struct isci_request *ireq) 2830 { 2831 enum sci_status status; 2832 2833 if (ihost->sm.current_state_id != SCIC_READY) { 2834 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 2835 __func__, ihost->sm.current_state_id); 2836 return SCI_FAILURE_INVALID_STATE; 2837 } 2838 2839 status = sci_remote_device_start_io(ihost, idev, ireq); 2840 if (status != SCI_SUCCESS) 2841 return status; 2842 2843 set_bit(IREQ_ACTIVE, &ireq->flags); 2844 sci_controller_post_request(ihost, ireq->post_context); 2845 return SCI_SUCCESS; 2846 } 2847 2848 enum sci_status sci_controller_terminate_request(struct isci_host *ihost, 2849 struct isci_remote_device *idev, 2850 struct isci_request *ireq) 2851 { 2852 /* terminate an ongoing (i.e. started) core IO request. This does not 2853 * abort the IO request at the target, but rather removes the IO 2854 * request from the host controller. 2855 */ 2856 enum sci_status status; 2857 2858 if (ihost->sm.current_state_id != SCIC_READY) { 2859 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 2860 __func__, ihost->sm.current_state_id); 2861 return SCI_FAILURE_INVALID_STATE; 2862 } 2863 2864 status = sci_io_request_terminate(ireq); 2865 if (status != SCI_SUCCESS) 2866 return status; 2867 2868 /* 2869 * Utilize the original post context command and or in the POST_TC_ABORT 2870 * request sub-type. 2871 */ 2872 sci_controller_post_request(ihost, 2873 ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT); 2874 return SCI_SUCCESS; 2875 } 2876 2877 /** 2878 * sci_controller_complete_io() - This method will perform core specific 2879 * completion operations for an IO request. After this method is invoked, 2880 * the user should consider the IO request as invalid until it is properly 2881 * reused (i.e. re-constructed). 2882 * @ihost: The handle to the controller object for which to complete the 2883 * IO request. 2884 * @idev: The handle to the remote device object for which to complete 2885 * the IO request. 2886 * @ireq: the handle to the io request object to complete. 2887 */ 2888 enum sci_status sci_controller_complete_io(struct isci_host *ihost, 2889 struct isci_remote_device *idev, 2890 struct isci_request *ireq) 2891 { 2892 enum sci_status status; 2893 u16 index; 2894 2895 switch (ihost->sm.current_state_id) { 2896 case SCIC_STOPPING: 2897 /* XXX: Implement this function */ 2898 return SCI_FAILURE; 2899 case SCIC_READY: 2900 status = sci_remote_device_complete_io(ihost, idev, ireq); 2901 if (status != SCI_SUCCESS) 2902 return status; 2903 2904 index = ISCI_TAG_TCI(ireq->io_tag); 2905 clear_bit(IREQ_ACTIVE, &ireq->flags); 2906 return SCI_SUCCESS; 2907 default: 2908 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 2909 __func__, ihost->sm.current_state_id); 2910 return SCI_FAILURE_INVALID_STATE; 2911 } 2912 2913 } 2914 2915 enum sci_status sci_controller_continue_io(struct isci_request *ireq) 2916 { 2917 struct isci_host *ihost = ireq->owning_controller; 2918 2919 if (ihost->sm.current_state_id != SCIC_READY) { 2920 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 2921 __func__, ihost->sm.current_state_id); 2922 return SCI_FAILURE_INVALID_STATE; 2923 } 2924 2925 set_bit(IREQ_ACTIVE, &ireq->flags); 2926 sci_controller_post_request(ihost, ireq->post_context); 2927 return SCI_SUCCESS; 2928 } 2929 2930 /** 2931 * sci_controller_start_task() - This method is called by the SCIC user to 2932 * send/start a framework task management request. 2933 * @controller: the handle to the controller object for which to start the task 2934 * management request. 2935 * @remote_device: the handle to the remote device object for which to start 2936 * the task management request. 2937 * @task_request: the handle to the task request object to start. 2938 */ 2939 enum sci_task_status sci_controller_start_task(struct isci_host *ihost, 2940 struct isci_remote_device *idev, 2941 struct isci_request *ireq) 2942 { 2943 enum sci_status status; 2944 2945 if (ihost->sm.current_state_id != SCIC_READY) { 2946 dev_warn(&ihost->pdev->dev, 2947 "%s: SCIC Controller starting task from invalid " 2948 "state\n", 2949 __func__); 2950 return SCI_TASK_FAILURE_INVALID_STATE; 2951 } 2952 2953 status = sci_remote_device_start_task(ihost, idev, ireq); 2954 switch (status) { 2955 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS: 2956 set_bit(IREQ_ACTIVE, &ireq->flags); 2957 2958 /* 2959 * We will let framework know this task request started successfully, 2960 * although core is still woring on starting the request (to post tc when 2961 * RNC is resumed.) 2962 */ 2963 return SCI_SUCCESS; 2964 case SCI_SUCCESS: 2965 set_bit(IREQ_ACTIVE, &ireq->flags); 2966 sci_controller_post_request(ihost, ireq->post_context); 2967 break; 2968 default: 2969 break; 2970 } 2971 2972 return status; 2973 } 2974 2975 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data) 2976 { 2977 int d; 2978 2979 /* no support for TX_GP_CFG */ 2980 if (reg_index == 0) 2981 return -EINVAL; 2982 2983 for (d = 0; d < isci_gpio_count(ihost); d++) { 2984 u32 val = 0x444; /* all ODx.n clear */ 2985 int i; 2986 2987 for (i = 0; i < 3; i++) { 2988 int bit = (i << 2) + 2; 2989 2990 bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i), 2991 write_data, reg_index, 2992 reg_count); 2993 if (bit < 0) 2994 break; 2995 2996 /* if od is set, clear the 'invert' bit */ 2997 val &= ~(bit << ((i << 2) + 2)); 2998 } 2999 3000 if (i < 3) 3001 break; 3002 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]); 3003 } 3004 3005 /* unless reg_index is > 1, we should always be able to write at 3006 * least one register 3007 */ 3008 return d > 0; 3009 } 3010 3011 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index, 3012 u8 reg_count, u8 *write_data) 3013 { 3014 struct isci_host *ihost = sas_ha->lldd_ha; 3015 int written; 3016 3017 switch (reg_type) { 3018 case SAS_GPIO_REG_TX_GP: 3019 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data); 3020 break; 3021 default: 3022 written = -EINVAL; 3023 } 3024 3025 return written; 3026 } 3027