16f231ddaSDan Williams /* 26f231ddaSDan Williams * This file is provided under a dual BSD/GPLv2 license. When using or 36f231ddaSDan Williams * redistributing this file, you may do so under either license. 46f231ddaSDan Williams * 56f231ddaSDan Williams * GPL LICENSE SUMMARY 66f231ddaSDan Williams * 76f231ddaSDan Williams * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 86f231ddaSDan Williams * 96f231ddaSDan Williams * This program is free software; you can redistribute it and/or modify 106f231ddaSDan Williams * it under the terms of version 2 of the GNU General Public License as 116f231ddaSDan Williams * published by the Free Software Foundation. 126f231ddaSDan Williams * 136f231ddaSDan Williams * This program is distributed in the hope that it will be useful, but 146f231ddaSDan Williams * WITHOUT ANY WARRANTY; without even the implied warranty of 156f231ddaSDan Williams * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 166f231ddaSDan Williams * General Public License for more details. 176f231ddaSDan Williams * 186f231ddaSDan Williams * You should have received a copy of the GNU General Public License 196f231ddaSDan Williams * along with this program; if not, write to the Free Software 206f231ddaSDan Williams * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 216f231ddaSDan Williams * The full GNU General Public License is included in this distribution 226f231ddaSDan Williams * in the file called LICENSE.GPL. 236f231ddaSDan Williams * 246f231ddaSDan Williams * BSD LICENSE 256f231ddaSDan Williams * 266f231ddaSDan Williams * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 276f231ddaSDan Williams * All rights reserved. 286f231ddaSDan Williams * 296f231ddaSDan Williams * Redistribution and use in source and binary forms, with or without 306f231ddaSDan Williams * modification, are permitted provided that the following conditions 316f231ddaSDan Williams * are met: 326f231ddaSDan Williams * 336f231ddaSDan Williams * * Redistributions of source code must retain the above copyright 346f231ddaSDan Williams * notice, this list of conditions and the following disclaimer. 356f231ddaSDan Williams * * Redistributions in binary form must reproduce the above copyright 366f231ddaSDan Williams * notice, this list of conditions and the following disclaimer in 376f231ddaSDan Williams * the documentation and/or other materials provided with the 386f231ddaSDan Williams * distribution. 396f231ddaSDan Williams * * Neither the name of Intel Corporation nor the names of its 406f231ddaSDan Williams * contributors may be used to endorse or promote products derived 416f231ddaSDan Williams * from this software without specific prior written permission. 426f231ddaSDan Williams * 436f231ddaSDan Williams * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 446f231ddaSDan Williams * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 456f231ddaSDan Williams * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 466f231ddaSDan Williams * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 476f231ddaSDan Williams * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 486f231ddaSDan Williams * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 496f231ddaSDan Williams * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 506f231ddaSDan Williams * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 516f231ddaSDan Williams * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 526f231ddaSDan Williams * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 536f231ddaSDan Williams * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 546f231ddaSDan Williams */ 55ac668c69SDan Williams #include <linux/circ_buf.h> 56cc9203bfSDan Williams #include <linux/device.h> 57cc9203bfSDan Williams #include <scsi/sas.h> 58cc9203bfSDan Williams #include "host.h" 596f231ddaSDan Williams #include "isci.h" 606f231ddaSDan Williams #include "port.h" 61d044af17SDan Williams #include "probe_roms.h" 62cc9203bfSDan Williams #include "remote_device.h" 63cc9203bfSDan Williams #include "request.h" 64cc9203bfSDan Williams #include "scu_completion_codes.h" 65cc9203bfSDan Williams #include "scu_event_codes.h" 6663a3a15fSDan Williams #include "registers.h" 67cc9203bfSDan Williams #include "scu_remote_node_context.h" 68cc9203bfSDan Williams #include "scu_task_context.h" 696f231ddaSDan Williams 70cc9203bfSDan Williams #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200 71cc9203bfSDan Williams 727c78da31SDan Williams #define smu_max_ports(dcc_value) \ 73cc9203bfSDan Williams (\ 74cc9203bfSDan Williams (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \ 75cc9203bfSDan Williams >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \ 76cc9203bfSDan Williams ) 77cc9203bfSDan Williams 787c78da31SDan Williams #define smu_max_task_contexts(dcc_value) \ 79cc9203bfSDan Williams (\ 80cc9203bfSDan Williams (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \ 81cc9203bfSDan Williams >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \ 82cc9203bfSDan Williams ) 83cc9203bfSDan Williams 847c78da31SDan Williams #define smu_max_rncs(dcc_value) \ 85cc9203bfSDan Williams (\ 86cc9203bfSDan Williams (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \ 87cc9203bfSDan Williams >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \ 88cc9203bfSDan Williams ) 89cc9203bfSDan Williams 90cc9203bfSDan Williams #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100 91cc9203bfSDan Williams 92*44b7ca96SLee Jones /* 93cc9203bfSDan Williams * The number of milliseconds to wait while a given phy is consuming power 94cc9203bfSDan Williams * before allowing another set of phys to consume power. Ultimately, this will 95cc9203bfSDan Williams * be specified by OEM parameter. 96cc9203bfSDan Williams */ 97cc9203bfSDan Williams #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500 98cc9203bfSDan Williams 99*44b7ca96SLee Jones /* 100cc9203bfSDan Williams * NORMALIZE_PUT_POINTER() - 101cc9203bfSDan Williams * 102cc9203bfSDan Williams * This macro will normalize the completion queue put pointer so its value can 103cc9203bfSDan Williams * be used as an array inde 104cc9203bfSDan Williams */ 105cc9203bfSDan Williams #define NORMALIZE_PUT_POINTER(x) \ 106cc9203bfSDan Williams ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK) 107cc9203bfSDan Williams 108cc9203bfSDan Williams 109*44b7ca96SLee Jones /* 110cc9203bfSDan Williams * NORMALIZE_EVENT_POINTER() - 111cc9203bfSDan Williams * 112cc9203bfSDan Williams * This macro will normalize the completion queue event entry so its value can 113cc9203bfSDan Williams * be used as an index. 114cc9203bfSDan Williams */ 115cc9203bfSDan Williams #define NORMALIZE_EVENT_POINTER(x) \ 116cc9203bfSDan Williams (\ 117cc9203bfSDan Williams ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \ 118cc9203bfSDan Williams >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \ 119cc9203bfSDan Williams ) 120cc9203bfSDan Williams 121*44b7ca96SLee Jones /* 122cc9203bfSDan Williams * NORMALIZE_GET_POINTER() - 123cc9203bfSDan Williams * 124cc9203bfSDan Williams * This macro will normalize the completion queue get pointer so its value can 125cc9203bfSDan Williams * be used as an index into an array 126cc9203bfSDan Williams */ 127cc9203bfSDan Williams #define NORMALIZE_GET_POINTER(x) \ 128cc9203bfSDan Williams ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK) 129cc9203bfSDan Williams 130*44b7ca96SLee Jones /* 131cc9203bfSDan Williams * NORMALIZE_GET_POINTER_CYCLE_BIT() - 132cc9203bfSDan Williams * 133cc9203bfSDan Williams * This macro will normalize the completion queue cycle pointer so it matches 134cc9203bfSDan Williams * the completion queue cycle bit 135cc9203bfSDan Williams */ 136cc9203bfSDan Williams #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \ 137cc9203bfSDan Williams ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT)) 138cc9203bfSDan Williams 139*44b7ca96SLee Jones /* 140cc9203bfSDan Williams * COMPLETION_QUEUE_CYCLE_BIT() - 141cc9203bfSDan Williams * 142cc9203bfSDan Williams * This macro will return the cycle bit of the completion queue entry 143cc9203bfSDan Williams */ 144cc9203bfSDan Williams #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000) 145cc9203bfSDan Williams 14612ef6544SEdmund Nadolski /* Init the state machine and call the state entry function (if any) */ 14712ef6544SEdmund Nadolski void sci_init_sm(struct sci_base_state_machine *sm, 14812ef6544SEdmund Nadolski const struct sci_base_state *state_table, u32 initial_state) 14912ef6544SEdmund Nadolski { 15012ef6544SEdmund Nadolski sci_state_transition_t handler; 15112ef6544SEdmund Nadolski 15212ef6544SEdmund Nadolski sm->initial_state_id = initial_state; 15312ef6544SEdmund Nadolski sm->previous_state_id = initial_state; 15412ef6544SEdmund Nadolski sm->current_state_id = initial_state; 15512ef6544SEdmund Nadolski sm->state_table = state_table; 15612ef6544SEdmund Nadolski 15712ef6544SEdmund Nadolski handler = sm->state_table[initial_state].enter_state; 15812ef6544SEdmund Nadolski if (handler) 15912ef6544SEdmund Nadolski handler(sm); 16012ef6544SEdmund Nadolski } 16112ef6544SEdmund Nadolski 16212ef6544SEdmund Nadolski /* Call the state exit fn, update the current state, call the state entry fn */ 16312ef6544SEdmund Nadolski void sci_change_state(struct sci_base_state_machine *sm, u32 next_state) 16412ef6544SEdmund Nadolski { 16512ef6544SEdmund Nadolski sci_state_transition_t handler; 16612ef6544SEdmund Nadolski 16712ef6544SEdmund Nadolski handler = sm->state_table[sm->current_state_id].exit_state; 16812ef6544SEdmund Nadolski if (handler) 16912ef6544SEdmund Nadolski handler(sm); 17012ef6544SEdmund Nadolski 17112ef6544SEdmund Nadolski sm->previous_state_id = sm->current_state_id; 17212ef6544SEdmund Nadolski sm->current_state_id = next_state; 17312ef6544SEdmund Nadolski 17412ef6544SEdmund Nadolski handler = sm->state_table[sm->current_state_id].enter_state; 17512ef6544SEdmund Nadolski if (handler) 17612ef6544SEdmund Nadolski handler(sm); 17712ef6544SEdmund Nadolski } 17812ef6544SEdmund Nadolski 17989a7301fSDan Williams static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost) 180cc9203bfSDan Williams { 181d9dcb4baSDan Williams u32 get_value = ihost->completion_queue_get; 182cc9203bfSDan Williams u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK; 183cc9203bfSDan Williams 184cc9203bfSDan Williams if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) == 185d9dcb4baSDan Williams COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])) 186cc9203bfSDan Williams return true; 187cc9203bfSDan Williams 188cc9203bfSDan Williams return false; 189cc9203bfSDan Williams } 190cc9203bfSDan Williams 19189a7301fSDan Williams static bool sci_controller_isr(struct isci_host *ihost) 192cc9203bfSDan Williams { 1932396a265SDan Williams if (sci_controller_completion_queue_has_entries(ihost)) 194cc9203bfSDan Williams return true; 1952396a265SDan Williams 1962396a265SDan Williams /* we have a spurious interrupt it could be that we have already 1972396a265SDan Williams * emptied the completion queue from a previous interrupt 1982396a265SDan Williams * FIXME: really!? 1992396a265SDan Williams */ 200d9dcb4baSDan Williams writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); 201cc9203bfSDan Williams 2022396a265SDan Williams /* There is a race in the hardware that could cause us not to be 2032396a265SDan Williams * notified of an interrupt completion if we do not take this 2042396a265SDan Williams * step. We will mask then unmask the interrupts so if there is 2052396a265SDan Williams * another interrupt pending the clearing of the interrupt 2062396a265SDan Williams * source we get the next interrupt message. 2072396a265SDan Williams */ 2082396a265SDan Williams spin_lock(&ihost->scic_lock); 2092396a265SDan Williams if (test_bit(IHOST_IRQ_ENABLED, &ihost->flags)) { 210d9dcb4baSDan Williams writel(0xFF000000, &ihost->smu_registers->interrupt_mask); 211d9dcb4baSDan Williams writel(0, &ihost->smu_registers->interrupt_mask); 212cc9203bfSDan Williams } 2132396a265SDan Williams spin_unlock(&ihost->scic_lock); 214cc9203bfSDan Williams 215cc9203bfSDan Williams return false; 216cc9203bfSDan Williams } 217cc9203bfSDan Williams 218c7ef4031SDan Williams irqreturn_t isci_msix_isr(int vec, void *data) 2196f231ddaSDan Williams { 220c7ef4031SDan Williams struct isci_host *ihost = data; 2216f231ddaSDan Williams 22289a7301fSDan Williams if (sci_controller_isr(ihost)) 223c7ef4031SDan Williams tasklet_schedule(&ihost->completion_tasklet); 2246f231ddaSDan Williams 225c7ef4031SDan Williams return IRQ_HANDLED; 226c7ef4031SDan Williams } 227c7ef4031SDan Williams 22889a7301fSDan Williams static bool sci_controller_error_isr(struct isci_host *ihost) 229cc9203bfSDan Williams { 230cc9203bfSDan Williams u32 interrupt_status; 231cc9203bfSDan Williams 232cc9203bfSDan Williams interrupt_status = 233d9dcb4baSDan Williams readl(&ihost->smu_registers->interrupt_status); 234cc9203bfSDan Williams interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND); 235cc9203bfSDan Williams 236cc9203bfSDan Williams if (interrupt_status != 0) { 237cc9203bfSDan Williams /* 238cc9203bfSDan Williams * There is an error interrupt pending so let it through and handle 239cc9203bfSDan Williams * in the callback */ 240cc9203bfSDan Williams return true; 241cc9203bfSDan Williams } 242cc9203bfSDan Williams 243cc9203bfSDan Williams /* 244cc9203bfSDan Williams * There is a race in the hardware that could cause us not to be notified 245cc9203bfSDan Williams * of an interrupt completion if we do not take this step. We will mask 246cc9203bfSDan Williams * then unmask the error interrupts so if there was another interrupt 247cc9203bfSDan Williams * pending we will be notified. 248cc9203bfSDan Williams * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */ 249d9dcb4baSDan Williams writel(0xff, &ihost->smu_registers->interrupt_mask); 250d9dcb4baSDan Williams writel(0, &ihost->smu_registers->interrupt_mask); 251cc9203bfSDan Williams 252cc9203bfSDan Williams return false; 253cc9203bfSDan Williams } 254cc9203bfSDan Williams 25589a7301fSDan Williams static void sci_controller_task_completion(struct isci_host *ihost, u32 ent) 256cc9203bfSDan Williams { 25789a7301fSDan Williams u32 index = SCU_GET_COMPLETION_INDEX(ent); 258db056250SDan Williams struct isci_request *ireq = ihost->reqs[index]; 259cc9203bfSDan Williams 260cc9203bfSDan Williams /* Make sure that we really want to process this IO request */ 261db056250SDan Williams if (test_bit(IREQ_ACTIVE, &ireq->flags) && 2625076a1a9SDan Williams ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG && 263d9dcb4baSDan Williams ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index]) 26489a7301fSDan Williams /* Yep this is a valid io request pass it along to the 26589a7301fSDan Williams * io request handler 26689a7301fSDan Williams */ 26789a7301fSDan Williams sci_io_request_tc_completion(ireq, ent); 268cc9203bfSDan Williams } 269cc9203bfSDan Williams 27089a7301fSDan Williams static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent) 271cc9203bfSDan Williams { 272cc9203bfSDan Williams u32 index; 2735076a1a9SDan Williams struct isci_request *ireq; 27478a6f06eSDan Williams struct isci_remote_device *idev; 275cc9203bfSDan Williams 27689a7301fSDan Williams index = SCU_GET_COMPLETION_INDEX(ent); 277cc9203bfSDan Williams 27889a7301fSDan Williams switch (scu_get_command_request_type(ent)) { 279cc9203bfSDan Williams case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC: 280cc9203bfSDan Williams case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC: 281d9dcb4baSDan Williams ireq = ihost->reqs[index]; 282d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n", 28389a7301fSDan Williams __func__, ent, ireq); 284cc9203bfSDan Williams /* @todo For a post TC operation we need to fail the IO 285cc9203bfSDan Williams * request 286cc9203bfSDan Williams */ 287cc9203bfSDan Williams break; 288cc9203bfSDan Williams case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC: 289cc9203bfSDan Williams case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC: 290cc9203bfSDan Williams case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC: 291d9dcb4baSDan Williams idev = ihost->device_table[index]; 292d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n", 29389a7301fSDan Williams __func__, ent, idev); 294cc9203bfSDan Williams /* @todo For a port RNC operation we need to fail the 295cc9203bfSDan Williams * device 296cc9203bfSDan Williams */ 297cc9203bfSDan Williams break; 298cc9203bfSDan Williams default: 299d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n", 30089a7301fSDan Williams __func__, ent); 301cc9203bfSDan Williams break; 302cc9203bfSDan Williams } 303cc9203bfSDan Williams } 304cc9203bfSDan Williams 30589a7301fSDan Williams static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent) 306cc9203bfSDan Williams { 307cc9203bfSDan Williams u32 index; 308cc9203bfSDan Williams u32 frame_index; 309cc9203bfSDan Williams 310cc9203bfSDan Williams struct scu_unsolicited_frame_header *frame_header; 31185280955SDan Williams struct isci_phy *iphy; 31278a6f06eSDan Williams struct isci_remote_device *idev; 313cc9203bfSDan Williams 314cc9203bfSDan Williams enum sci_status result = SCI_FAILURE; 315cc9203bfSDan Williams 31689a7301fSDan Williams frame_index = SCU_GET_FRAME_INDEX(ent); 317cc9203bfSDan Williams 318d9dcb4baSDan Williams frame_header = ihost->uf_control.buffers.array[frame_index].header; 319d9dcb4baSDan Williams ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE; 320cc9203bfSDan Williams 32189a7301fSDan Williams if (SCU_GET_FRAME_ERROR(ent)) { 322cc9203bfSDan Williams /* 323cc9203bfSDan Williams * / @todo If the IAF frame or SIGNATURE FIS frame has an error will 324cc9203bfSDan Williams * / this cause a problem? We expect the phy initialization will 325cc9203bfSDan Williams * / fail if there is an error in the frame. */ 32689a7301fSDan Williams sci_controller_release_frame(ihost, frame_index); 327cc9203bfSDan Williams return; 328cc9203bfSDan Williams } 329cc9203bfSDan Williams 330cc9203bfSDan Williams if (frame_header->is_address_frame) { 33189a7301fSDan Williams index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); 33285280955SDan Williams iphy = &ihost->phys[index]; 33389a7301fSDan Williams result = sci_phy_frame_handler(iphy, frame_index); 334cc9203bfSDan Williams } else { 335cc9203bfSDan Williams 33689a7301fSDan Williams index = SCU_GET_COMPLETION_INDEX(ent); 337cc9203bfSDan Williams 338cc9203bfSDan Williams if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { 339cc9203bfSDan Williams /* 340cc9203bfSDan Williams * This is a signature fis or a frame from a direct attached SATA 341cc9203bfSDan Williams * device that has not yet been created. In either case forwared 342cc9203bfSDan Williams * the frame to the PE and let it take care of the frame data. */ 34389a7301fSDan Williams index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); 34485280955SDan Williams iphy = &ihost->phys[index]; 34589a7301fSDan Williams result = sci_phy_frame_handler(iphy, frame_index); 346cc9203bfSDan Williams } else { 347d9dcb4baSDan Williams if (index < ihost->remote_node_entries) 348d9dcb4baSDan Williams idev = ihost->device_table[index]; 349cc9203bfSDan Williams else 35078a6f06eSDan Williams idev = NULL; 351cc9203bfSDan Williams 35278a6f06eSDan Williams if (idev != NULL) 35389a7301fSDan Williams result = sci_remote_device_frame_handler(idev, frame_index); 354cc9203bfSDan Williams else 35589a7301fSDan Williams sci_controller_release_frame(ihost, frame_index); 356cc9203bfSDan Williams } 357cc9203bfSDan Williams } 358cc9203bfSDan Williams 359cc9203bfSDan Williams if (result != SCI_SUCCESS) { 360cc9203bfSDan Williams /* 361cc9203bfSDan Williams * / @todo Is there any reason to report some additional error message 362cc9203bfSDan Williams * / when we get this failure notifiction? */ 363cc9203bfSDan Williams } 364cc9203bfSDan Williams } 365cc9203bfSDan Williams 36689a7301fSDan Williams static void sci_controller_event_completion(struct isci_host *ihost, u32 ent) 367cc9203bfSDan Williams { 36878a6f06eSDan Williams struct isci_remote_device *idev; 3695076a1a9SDan Williams struct isci_request *ireq; 37085280955SDan Williams struct isci_phy *iphy; 371cc9203bfSDan Williams u32 index; 372cc9203bfSDan Williams 37389a7301fSDan Williams index = SCU_GET_COMPLETION_INDEX(ent); 374cc9203bfSDan Williams 37589a7301fSDan Williams switch (scu_get_event_type(ent)) { 376cc9203bfSDan Williams case SCU_EVENT_TYPE_SMU_COMMAND_ERROR: 377cc9203bfSDan Williams /* / @todo The driver did something wrong and we need to fix the condtion. */ 378d9dcb4baSDan Williams dev_err(&ihost->pdev->dev, 379cc9203bfSDan Williams "%s: SCIC Controller 0x%p received SMU command error " 380cc9203bfSDan Williams "0x%x\n", 381cc9203bfSDan Williams __func__, 382d9dcb4baSDan Williams ihost, 38389a7301fSDan Williams ent); 384cc9203bfSDan Williams break; 385cc9203bfSDan Williams 386cc9203bfSDan Williams case SCU_EVENT_TYPE_SMU_PCQ_ERROR: 387cc9203bfSDan Williams case SCU_EVENT_TYPE_SMU_ERROR: 388cc9203bfSDan Williams case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR: 389cc9203bfSDan Williams /* 390cc9203bfSDan Williams * / @todo This is a hardware failure and its likely that we want to 391cc9203bfSDan Williams * / reset the controller. */ 392d9dcb4baSDan Williams dev_err(&ihost->pdev->dev, 393cc9203bfSDan Williams "%s: SCIC Controller 0x%p received fatal controller " 394cc9203bfSDan Williams "event 0x%x\n", 395cc9203bfSDan Williams __func__, 396d9dcb4baSDan Williams ihost, 39789a7301fSDan Williams ent); 398cc9203bfSDan Williams break; 399cc9203bfSDan Williams 400cc9203bfSDan Williams case SCU_EVENT_TYPE_TRANSPORT_ERROR: 4015076a1a9SDan Williams ireq = ihost->reqs[index]; 40289a7301fSDan Williams sci_io_request_event_handler(ireq, ent); 403cc9203bfSDan Williams break; 404cc9203bfSDan Williams 405cc9203bfSDan Williams case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT: 40689a7301fSDan Williams switch (scu_get_event_specifier(ent)) { 407cc9203bfSDan Williams case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE: 408cc9203bfSDan Williams case SCU_EVENT_SPECIFIC_TASK_TIMEOUT: 4095076a1a9SDan Williams ireq = ihost->reqs[index]; 4105076a1a9SDan Williams if (ireq != NULL) 41189a7301fSDan Williams sci_io_request_event_handler(ireq, ent); 412cc9203bfSDan Williams else 413d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 414cc9203bfSDan Williams "%s: SCIC Controller 0x%p received " 415cc9203bfSDan Williams "event 0x%x for io request object " 416cc9203bfSDan Williams "that doesnt exist.\n", 417cc9203bfSDan Williams __func__, 418d9dcb4baSDan Williams ihost, 41989a7301fSDan Williams ent); 420cc9203bfSDan Williams 421cc9203bfSDan Williams break; 422cc9203bfSDan Williams 423cc9203bfSDan Williams case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT: 424d9dcb4baSDan Williams idev = ihost->device_table[index]; 42578a6f06eSDan Williams if (idev != NULL) 42689a7301fSDan Williams sci_remote_device_event_handler(idev, ent); 427cc9203bfSDan Williams else 428d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 429cc9203bfSDan Williams "%s: SCIC Controller 0x%p received " 430cc9203bfSDan Williams "event 0x%x for remote device object " 431cc9203bfSDan Williams "that doesnt exist.\n", 432cc9203bfSDan Williams __func__, 433d9dcb4baSDan Williams ihost, 43489a7301fSDan Williams ent); 435cc9203bfSDan Williams 436cc9203bfSDan Williams break; 437cc9203bfSDan Williams } 438cc9203bfSDan Williams break; 439cc9203bfSDan Williams 440cc9203bfSDan Williams case SCU_EVENT_TYPE_BROADCAST_CHANGE: 441cc9203bfSDan Williams /* 442cc9203bfSDan Williams * direct the broadcast change event to the phy first and then let 443cc9203bfSDan Williams * the phy redirect the broadcast change to the port object */ 444cc9203bfSDan Williams case SCU_EVENT_TYPE_ERR_CNT_EVENT: 445cc9203bfSDan Williams /* 446cc9203bfSDan Williams * direct error counter event to the phy object since that is where 447cc9203bfSDan Williams * we get the event notification. This is a type 4 event. */ 448cc9203bfSDan Williams case SCU_EVENT_TYPE_OSSP_EVENT: 44989a7301fSDan Williams index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); 45085280955SDan Williams iphy = &ihost->phys[index]; 45189a7301fSDan Williams sci_phy_event_handler(iphy, ent); 452cc9203bfSDan Williams break; 453cc9203bfSDan Williams 454cc9203bfSDan Williams case SCU_EVENT_TYPE_RNC_SUSPEND_TX: 455cc9203bfSDan Williams case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX: 456cc9203bfSDan Williams case SCU_EVENT_TYPE_RNC_OPS_MISC: 457d9dcb4baSDan Williams if (index < ihost->remote_node_entries) { 458d9dcb4baSDan Williams idev = ihost->device_table[index]; 459cc9203bfSDan Williams 46078a6f06eSDan Williams if (idev != NULL) 46189a7301fSDan Williams sci_remote_device_event_handler(idev, ent); 462cc9203bfSDan Williams } else 463d9dcb4baSDan Williams dev_err(&ihost->pdev->dev, 464cc9203bfSDan Williams "%s: SCIC Controller 0x%p received event 0x%x " 465cc9203bfSDan Williams "for remote device object 0x%0x that doesnt " 466cc9203bfSDan Williams "exist.\n", 467cc9203bfSDan Williams __func__, 468d9dcb4baSDan Williams ihost, 46989a7301fSDan Williams ent, 470cc9203bfSDan Williams index); 471cc9203bfSDan Williams 472cc9203bfSDan Williams break; 473cc9203bfSDan Williams 474cc9203bfSDan Williams default: 475d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 476cc9203bfSDan Williams "%s: SCIC Controller received unknown event code %x\n", 477cc9203bfSDan Williams __func__, 47889a7301fSDan Williams ent); 479cc9203bfSDan Williams break; 480cc9203bfSDan Williams } 481cc9203bfSDan Williams } 482cc9203bfSDan Williams 48389a7301fSDan Williams static void sci_controller_process_completions(struct isci_host *ihost) 484cc9203bfSDan Williams { 485cc9203bfSDan Williams u32 completion_count = 0; 48689a7301fSDan Williams u32 ent; 487cc9203bfSDan Williams u32 get_index; 488cc9203bfSDan Williams u32 get_cycle; 489994a9303SDan Williams u32 event_get; 490cc9203bfSDan Williams u32 event_cycle; 491cc9203bfSDan Williams 492d9dcb4baSDan Williams dev_dbg(&ihost->pdev->dev, 49359e13d48SMasanari Iida "%s: completion queue beginning get:0x%08x\n", 494cc9203bfSDan Williams __func__, 495d9dcb4baSDan Williams ihost->completion_queue_get); 496cc9203bfSDan Williams 497cc9203bfSDan Williams /* Get the component parts of the completion queue */ 498d9dcb4baSDan Williams get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get); 499d9dcb4baSDan Williams get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get; 500cc9203bfSDan Williams 501d9dcb4baSDan Williams event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get); 502d9dcb4baSDan Williams event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get; 503cc9203bfSDan Williams 504cc9203bfSDan Williams while ( 505cc9203bfSDan Williams NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle) 506d9dcb4baSDan Williams == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]) 507cc9203bfSDan Williams ) { 508cc9203bfSDan Williams completion_count++; 509cc9203bfSDan Williams 51089a7301fSDan Williams ent = ihost->completion_queue[get_index]; 511994a9303SDan Williams 512994a9303SDan Williams /* increment the get pointer and check for rollover to toggle the cycle bit */ 513994a9303SDan Williams get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) << 514994a9303SDan Williams (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT); 515994a9303SDan Williams get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1); 516cc9203bfSDan Williams 517d9dcb4baSDan Williams dev_dbg(&ihost->pdev->dev, 518cc9203bfSDan Williams "%s: completion queue entry:0x%08x\n", 519cc9203bfSDan Williams __func__, 52089a7301fSDan Williams ent); 521cc9203bfSDan Williams 52289a7301fSDan Williams switch (SCU_GET_COMPLETION_TYPE(ent)) { 523cc9203bfSDan Williams case SCU_COMPLETION_TYPE_TASK: 52489a7301fSDan Williams sci_controller_task_completion(ihost, ent); 525cc9203bfSDan Williams break; 526cc9203bfSDan Williams 527cc9203bfSDan Williams case SCU_COMPLETION_TYPE_SDMA: 52889a7301fSDan Williams sci_controller_sdma_completion(ihost, ent); 529cc9203bfSDan Williams break; 530cc9203bfSDan Williams 531cc9203bfSDan Williams case SCU_COMPLETION_TYPE_UFI: 53289a7301fSDan Williams sci_controller_unsolicited_frame(ihost, ent); 533cc9203bfSDan Williams break; 534cc9203bfSDan Williams 535cc9203bfSDan Williams case SCU_COMPLETION_TYPE_EVENT: 53677cd72a5SDan Williams sci_controller_event_completion(ihost, ent); 53777cd72a5SDan Williams break; 53877cd72a5SDan Williams 539994a9303SDan Williams case SCU_COMPLETION_TYPE_NOTIFY: { 540994a9303SDan Williams event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) << 541994a9303SDan Williams (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT); 542994a9303SDan Williams event_get = (event_get+1) & (SCU_MAX_EVENTS-1); 543994a9303SDan Williams 54489a7301fSDan Williams sci_controller_event_completion(ihost, ent); 545cc9203bfSDan Williams break; 546994a9303SDan Williams } 547cc9203bfSDan Williams default: 548d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 549cc9203bfSDan Williams "%s: SCIC Controller received unknown " 550cc9203bfSDan Williams "completion type %x\n", 551cc9203bfSDan Williams __func__, 55289a7301fSDan Williams ent); 553cc9203bfSDan Williams break; 554cc9203bfSDan Williams } 555cc9203bfSDan Williams } 556cc9203bfSDan Williams 557cc9203bfSDan Williams /* Update the get register if we completed one or more entries */ 558cc9203bfSDan Williams if (completion_count > 0) { 559d9dcb4baSDan Williams ihost->completion_queue_get = 560cc9203bfSDan Williams SMU_CQGR_GEN_BIT(ENABLE) | 561cc9203bfSDan Williams SMU_CQGR_GEN_BIT(EVENT_ENABLE) | 562cc9203bfSDan Williams event_cycle | 563994a9303SDan Williams SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) | 564cc9203bfSDan Williams get_cycle | 565cc9203bfSDan Williams SMU_CQGR_GEN_VAL(POINTER, get_index); 566cc9203bfSDan Williams 567d9dcb4baSDan Williams writel(ihost->completion_queue_get, 568d9dcb4baSDan Williams &ihost->smu_registers->completion_queue_get); 569cc9203bfSDan Williams 570cc9203bfSDan Williams } 571cc9203bfSDan Williams 572d9dcb4baSDan Williams dev_dbg(&ihost->pdev->dev, 573cc9203bfSDan Williams "%s: completion queue ending get:0x%08x\n", 574cc9203bfSDan Williams __func__, 575d9dcb4baSDan Williams ihost->completion_queue_get); 576cc9203bfSDan Williams 577cc9203bfSDan Williams } 578cc9203bfSDan Williams 57989a7301fSDan Williams static void sci_controller_error_handler(struct isci_host *ihost) 580cc9203bfSDan Williams { 581cc9203bfSDan Williams u32 interrupt_status; 582cc9203bfSDan Williams 583cc9203bfSDan Williams interrupt_status = 584d9dcb4baSDan Williams readl(&ihost->smu_registers->interrupt_status); 585cc9203bfSDan Williams 586cc9203bfSDan Williams if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) && 58789a7301fSDan Williams sci_controller_completion_queue_has_entries(ihost)) { 588cc9203bfSDan Williams 58989a7301fSDan Williams sci_controller_process_completions(ihost); 590d9dcb4baSDan Williams writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status); 591cc9203bfSDan Williams } else { 592d9dcb4baSDan Williams dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__, 593cc9203bfSDan Williams interrupt_status); 594cc9203bfSDan Williams 595d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_FAILED); 596cc9203bfSDan Williams 597cc9203bfSDan Williams return; 598cc9203bfSDan Williams } 599cc9203bfSDan Williams 600cc9203bfSDan Williams /* If we dont process any completions I am not sure that we want to do this. 601cc9203bfSDan Williams * We are in the middle of a hardware fault and should probably be reset. 602cc9203bfSDan Williams */ 603d9dcb4baSDan Williams writel(0, &ihost->smu_registers->interrupt_mask); 604cc9203bfSDan Williams } 605cc9203bfSDan Williams 606c7ef4031SDan Williams irqreturn_t isci_intx_isr(int vec, void *data) 6076f231ddaSDan Williams { 6086f231ddaSDan Williams irqreturn_t ret = IRQ_NONE; 60931e824edSDan Williams struct isci_host *ihost = data; 6106f231ddaSDan Williams 61189a7301fSDan Williams if (sci_controller_isr(ihost)) { 612d9dcb4baSDan Williams writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); 613c7ef4031SDan Williams tasklet_schedule(&ihost->completion_tasklet); 6146f231ddaSDan Williams ret = IRQ_HANDLED; 61589a7301fSDan Williams } else if (sci_controller_error_isr(ihost)) { 61692f4f0f5SDan Williams spin_lock(&ihost->scic_lock); 61789a7301fSDan Williams sci_controller_error_handler(ihost); 61892f4f0f5SDan Williams spin_unlock(&ihost->scic_lock); 61992f4f0f5SDan Williams ret = IRQ_HANDLED; 6206f231ddaSDan Williams } 62192f4f0f5SDan Williams 6226f231ddaSDan Williams return ret; 6236f231ddaSDan Williams } 6246f231ddaSDan Williams 62592f4f0f5SDan Williams irqreturn_t isci_error_isr(int vec, void *data) 62692f4f0f5SDan Williams { 62792f4f0f5SDan Williams struct isci_host *ihost = data; 62892f4f0f5SDan Williams 62989a7301fSDan Williams if (sci_controller_error_isr(ihost)) 63089a7301fSDan Williams sci_controller_error_handler(ihost); 63192f4f0f5SDan Williams 63292f4f0f5SDan Williams return IRQ_HANDLED; 63392f4f0f5SDan Williams } 6346f231ddaSDan Williams 6356f231ddaSDan Williams /** 6366f231ddaSDan Williams * isci_host_start_complete() - This function is called by the core library, 6376f231ddaSDan Williams * through the ISCI Module, to indicate controller start status. 638*44b7ca96SLee Jones * @ihost: This parameter specifies the ISCI host object 6396f231ddaSDan Williams * @completion_status: This parameter specifies the completion status from the 6406f231ddaSDan Williams * core library. 6416f231ddaSDan Williams * 6426f231ddaSDan Williams */ 643cc9203bfSDan Williams static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status) 6446f231ddaSDan Williams { 6450cf89d1dSDan Williams if (completion_status != SCI_SUCCESS) 6460cf89d1dSDan Williams dev_info(&ihost->pdev->dev, 6470cf89d1dSDan Williams "controller start timed out, continuing...\n"); 6480cf89d1dSDan Williams clear_bit(IHOST_START_PENDING, &ihost->flags); 6490cf89d1dSDan Williams wake_up(&ihost->eventq); 6506f231ddaSDan Williams } 6516f231ddaSDan Williams 652c7ef4031SDan Williams int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time) 6536f231ddaSDan Williams { 654b1124cd3SDan Williams struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost); 655b1124cd3SDan Williams struct isci_host *ihost = ha->lldd_ha; 6566f231ddaSDan Williams 65777950f51SEdmund Nadolski if (test_bit(IHOST_START_PENDING, &ihost->flags)) 6586f231ddaSDan Williams return 0; 6596f231ddaSDan Williams 660b1124cd3SDan Williams sas_drain_work(ha); 6616f231ddaSDan Williams 6626f231ddaSDan Williams return 1; 6636f231ddaSDan Williams } 6646f231ddaSDan Williams 665cc9203bfSDan Williams /** 66689a7301fSDan Williams * sci_controller_get_suggested_start_timeout() - This method returns the 66789a7301fSDan Williams * suggested sci_controller_start() timeout amount. The user is free to 668cc9203bfSDan Williams * use any timeout value, but this method provides the suggested minimum 669cc9203bfSDan Williams * start timeout value. The returned value is based upon empirical 670cc9203bfSDan Williams * information determined as a result of interoperability testing. 671*44b7ca96SLee Jones * @ihost: the handle to the controller object for which to return the 672cc9203bfSDan Williams * suggested start timeout. 673cc9203bfSDan Williams * 674cc9203bfSDan Williams * This method returns the number of milliseconds for the suggested start 675cc9203bfSDan Williams * operation timeout. 676cc9203bfSDan Williams */ 67789a7301fSDan Williams static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost) 678cc9203bfSDan Williams { 679cc9203bfSDan Williams /* Validate the user supplied parameters. */ 680d9dcb4baSDan Williams if (!ihost) 681cc9203bfSDan Williams return 0; 682cc9203bfSDan Williams 683cc9203bfSDan Williams /* 684cc9203bfSDan Williams * The suggested minimum timeout value for a controller start operation: 685cc9203bfSDan Williams * 686cc9203bfSDan Williams * Signature FIS Timeout 687cc9203bfSDan Williams * + Phy Start Timeout 688cc9203bfSDan Williams * + Number of Phy Spin Up Intervals 689cc9203bfSDan Williams * --------------------------------- 690cc9203bfSDan Williams * Number of milliseconds for the controller start operation. 691cc9203bfSDan Williams * 692cc9203bfSDan Williams * NOTE: The number of phy spin up intervals will be equivalent 693cc9203bfSDan Williams * to the number of phys divided by the number phys allowed 694cc9203bfSDan Williams * per interval - 1 (once OEM parameters are supported). 695cc9203bfSDan Williams * Currently we assume only 1 phy per interval. */ 696cc9203bfSDan Williams 697cc9203bfSDan Williams return SCIC_SDS_SIGNATURE_FIS_TIMEOUT 698cc9203bfSDan Williams + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 699cc9203bfSDan Williams + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 700cc9203bfSDan Williams } 701cc9203bfSDan Williams 70289a7301fSDan Williams static void sci_controller_enable_interrupts(struct isci_host *ihost) 703cc9203bfSDan Williams { 7042396a265SDan Williams set_bit(IHOST_IRQ_ENABLED, &ihost->flags); 705d9dcb4baSDan Williams writel(0, &ihost->smu_registers->interrupt_mask); 706cc9203bfSDan Williams } 707cc9203bfSDan Williams 70889a7301fSDan Williams void sci_controller_disable_interrupts(struct isci_host *ihost) 709cc9203bfSDan Williams { 7102396a265SDan Williams clear_bit(IHOST_IRQ_ENABLED, &ihost->flags); 711d9dcb4baSDan Williams writel(0xffffffff, &ihost->smu_registers->interrupt_mask); 7122396a265SDan Williams readl(&ihost->smu_registers->interrupt_mask); /* flush */ 713cc9203bfSDan Williams } 714cc9203bfSDan Williams 71589a7301fSDan Williams static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost) 716cc9203bfSDan Williams { 717cc9203bfSDan Williams u32 port_task_scheduler_value; 718cc9203bfSDan Williams 719cc9203bfSDan Williams port_task_scheduler_value = 720d9dcb4baSDan Williams readl(&ihost->scu_registers->peg0.ptsg.control); 721cc9203bfSDan Williams port_task_scheduler_value |= 722cc9203bfSDan Williams (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | 723cc9203bfSDan Williams SCU_PTSGCR_GEN_BIT(PTSG_ENABLE)); 724cc9203bfSDan Williams writel(port_task_scheduler_value, 725d9dcb4baSDan Williams &ihost->scu_registers->peg0.ptsg.control); 726cc9203bfSDan Williams } 727cc9203bfSDan Williams 72889a7301fSDan Williams static void sci_controller_assign_task_entries(struct isci_host *ihost) 729cc9203bfSDan Williams { 730cc9203bfSDan Williams u32 task_assignment; 731cc9203bfSDan Williams 732cc9203bfSDan Williams /* 733cc9203bfSDan Williams * Assign all the TCs to function 0 734cc9203bfSDan Williams * TODO: Do we actually need to read this register to write it back? 735cc9203bfSDan Williams */ 736cc9203bfSDan Williams 737cc9203bfSDan Williams task_assignment = 738d9dcb4baSDan Williams readl(&ihost->smu_registers->task_context_assignment[0]); 739cc9203bfSDan Williams 740cc9203bfSDan Williams task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) | 741d9dcb4baSDan Williams (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) | 742cc9203bfSDan Williams (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE)); 743cc9203bfSDan Williams 744cc9203bfSDan Williams writel(task_assignment, 745d9dcb4baSDan Williams &ihost->smu_registers->task_context_assignment[0]); 746cc9203bfSDan Williams 747cc9203bfSDan Williams } 748cc9203bfSDan Williams 74989a7301fSDan Williams static void sci_controller_initialize_completion_queue(struct isci_host *ihost) 750cc9203bfSDan Williams { 751cc9203bfSDan Williams u32 index; 752cc9203bfSDan Williams u32 completion_queue_control_value; 753cc9203bfSDan Williams u32 completion_queue_get_value; 754cc9203bfSDan Williams u32 completion_queue_put_value; 755cc9203bfSDan Williams 756d9dcb4baSDan Williams ihost->completion_queue_get = 0; 757cc9203bfSDan Williams 7587c78da31SDan Williams completion_queue_control_value = 7597c78da31SDan Williams (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) | 7607c78da31SDan Williams SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1)); 761cc9203bfSDan Williams 762cc9203bfSDan Williams writel(completion_queue_control_value, 763d9dcb4baSDan Williams &ihost->smu_registers->completion_queue_control); 764cc9203bfSDan Williams 765cc9203bfSDan Williams 766cc9203bfSDan Williams /* Set the completion queue get pointer and enable the queue */ 767cc9203bfSDan Williams completion_queue_get_value = ( 768cc9203bfSDan Williams (SMU_CQGR_GEN_VAL(POINTER, 0)) 769cc9203bfSDan Williams | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0)) 770cc9203bfSDan Williams | (SMU_CQGR_GEN_BIT(ENABLE)) 771cc9203bfSDan Williams | (SMU_CQGR_GEN_BIT(EVENT_ENABLE)) 772cc9203bfSDan Williams ); 773cc9203bfSDan Williams 774cc9203bfSDan Williams writel(completion_queue_get_value, 775d9dcb4baSDan Williams &ihost->smu_registers->completion_queue_get); 776cc9203bfSDan Williams 777cc9203bfSDan Williams /* Set the completion queue put pointer */ 778cc9203bfSDan Williams completion_queue_put_value = ( 779cc9203bfSDan Williams (SMU_CQPR_GEN_VAL(POINTER, 0)) 780cc9203bfSDan Williams | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0)) 781cc9203bfSDan Williams ); 782cc9203bfSDan Williams 783cc9203bfSDan Williams writel(completion_queue_put_value, 784d9dcb4baSDan Williams &ihost->smu_registers->completion_queue_put); 785cc9203bfSDan Williams 786cc9203bfSDan Williams /* Initialize the cycle bit of the completion queue entries */ 7877c78da31SDan Williams for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) { 788cc9203bfSDan Williams /* 789cc9203bfSDan Williams * If get.cycle_bit != completion_queue.cycle_bit 790cc9203bfSDan Williams * its not a valid completion queue entry 791cc9203bfSDan Williams * so at system start all entries are invalid */ 792d9dcb4baSDan Williams ihost->completion_queue[index] = 0x80000000; 793cc9203bfSDan Williams } 794cc9203bfSDan Williams } 795cc9203bfSDan Williams 79689a7301fSDan Williams static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost) 797cc9203bfSDan Williams { 798cc9203bfSDan Williams u32 frame_queue_control_value; 799cc9203bfSDan Williams u32 frame_queue_get_value; 800cc9203bfSDan Williams u32 frame_queue_put_value; 801cc9203bfSDan Williams 802cc9203bfSDan Williams /* Write the queue size */ 803cc9203bfSDan Williams frame_queue_control_value = 8047c78da31SDan Williams SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES); 805cc9203bfSDan Williams 806cc9203bfSDan Williams writel(frame_queue_control_value, 807d9dcb4baSDan Williams &ihost->scu_registers->sdma.unsolicited_frame_queue_control); 808cc9203bfSDan Williams 809cc9203bfSDan Williams /* Setup the get pointer for the unsolicited frame queue */ 810cc9203bfSDan Williams frame_queue_get_value = ( 811cc9203bfSDan Williams SCU_UFQGP_GEN_VAL(POINTER, 0) 812cc9203bfSDan Williams | SCU_UFQGP_GEN_BIT(ENABLE_BIT) 813cc9203bfSDan Williams ); 814cc9203bfSDan Williams 815cc9203bfSDan Williams writel(frame_queue_get_value, 816d9dcb4baSDan Williams &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); 817cc9203bfSDan Williams /* Setup the put pointer for the unsolicited frame queue */ 818cc9203bfSDan Williams frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); 819cc9203bfSDan Williams writel(frame_queue_put_value, 820d9dcb4baSDan Williams &ihost->scu_registers->sdma.unsolicited_frame_put_pointer); 821cc9203bfSDan Williams } 822cc9203bfSDan Williams 82350a92d93SDan Williams void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status) 824cc9203bfSDan Williams { 825d9dcb4baSDan Williams if (ihost->sm.current_state_id == SCIC_STARTING) { 826cc9203bfSDan Williams /* 827cc9203bfSDan Williams * We move into the ready state, because some of the phys/ports 828cc9203bfSDan Williams * may be up and operational. 829cc9203bfSDan Williams */ 830d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_READY); 831cc9203bfSDan Williams 832cc9203bfSDan Williams isci_host_start_complete(ihost, status); 833cc9203bfSDan Williams } 834cc9203bfSDan Williams } 835cc9203bfSDan Williams 83685280955SDan Williams static bool is_phy_starting(struct isci_phy *iphy) 8374a33c525SAdam Gruchala { 83889a7301fSDan Williams enum sci_phy_states state; 8394a33c525SAdam Gruchala 84085280955SDan Williams state = iphy->sm.current_state_id; 8414a33c525SAdam Gruchala switch (state) { 842e301370aSEdmund Nadolski case SCI_PHY_STARTING: 843e301370aSEdmund Nadolski case SCI_PHY_SUB_INITIAL: 844e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: 845e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_IAF_UF: 846e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_SAS_POWER: 847e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_SATA_POWER: 848e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: 849e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: 85050a92d93SDan Williams case SCI_PHY_SUB_AWAIT_OSSP_EN: 851e301370aSEdmund Nadolski case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: 852e301370aSEdmund Nadolski case SCI_PHY_SUB_FINAL: 8534a33c525SAdam Gruchala return true; 8544a33c525SAdam Gruchala default: 8554a33c525SAdam Gruchala return false; 8564a33c525SAdam Gruchala } 8574a33c525SAdam Gruchala } 8584a33c525SAdam Gruchala 85950a92d93SDan Williams bool is_controller_start_complete(struct isci_host *ihost) 86050a92d93SDan Williams { 86150a92d93SDan Williams int i; 86250a92d93SDan Williams 86350a92d93SDan Williams for (i = 0; i < SCI_MAX_PHYS; i++) { 86450a92d93SDan Williams struct isci_phy *iphy = &ihost->phys[i]; 86550a92d93SDan Williams u32 state = iphy->sm.current_state_id; 86650a92d93SDan Williams 86750a92d93SDan Williams /* in apc mode we need to check every phy, in 86850a92d93SDan Williams * mpc mode we only need to check phys that have 86950a92d93SDan Williams * been configured into a port 87050a92d93SDan Williams */ 87150a92d93SDan Williams if (is_port_config_apc(ihost)) 87250a92d93SDan Williams /* pass */; 87350a92d93SDan Williams else if (!phy_get_non_dummy_port(iphy)) 87450a92d93SDan Williams continue; 87550a92d93SDan Williams 87650a92d93SDan Williams /* The controller start operation is complete iff: 87750a92d93SDan Williams * - all links have been given an opportunity to start 87850a92d93SDan Williams * - have no indication of a connected device 87950a92d93SDan Williams * - have an indication of a connected device and it has 88050a92d93SDan Williams * finished the link training process. 88150a92d93SDan Williams */ 88250a92d93SDan Williams if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) || 88350a92d93SDan Williams (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) || 88450a92d93SDan Williams (iphy->is_in_link_training == true && is_phy_starting(iphy)) || 88550a92d93SDan Williams (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) 88650a92d93SDan Williams return false; 88750a92d93SDan Williams } 88850a92d93SDan Williams 88950a92d93SDan Williams return true; 89050a92d93SDan Williams } 89150a92d93SDan Williams 892cc9203bfSDan Williams /** 89389a7301fSDan Williams * sci_controller_start_next_phy - start phy 894*44b7ca96SLee Jones * @ihost: controller 895cc9203bfSDan Williams * 896cc9203bfSDan Williams * If all the phys have been started, then attempt to transition the 897cc9203bfSDan Williams * controller to the READY state and inform the user 89889a7301fSDan Williams * (sci_cb_controller_start_complete()). 899cc9203bfSDan Williams */ 90089a7301fSDan Williams static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost) 901cc9203bfSDan Williams { 90289a7301fSDan Williams struct sci_oem_params *oem = &ihost->oem_parameters; 90385280955SDan Williams struct isci_phy *iphy; 904cc9203bfSDan Williams enum sci_status status; 905cc9203bfSDan Williams 906cc9203bfSDan Williams status = SCI_SUCCESS; 907cc9203bfSDan Williams 908d9dcb4baSDan Williams if (ihost->phy_startup_timer_pending) 909cc9203bfSDan Williams return status; 910cc9203bfSDan Williams 911d9dcb4baSDan Williams if (ihost->next_phy_to_start >= SCI_MAX_PHYS) { 91250a92d93SDan Williams if (is_controller_start_complete(ihost)) { 91389a7301fSDan Williams sci_controller_transition_to_ready(ihost, SCI_SUCCESS); 914d9dcb4baSDan Williams sci_del_timer(&ihost->phy_timer); 915d9dcb4baSDan Williams ihost->phy_startup_timer_pending = false; 916cc9203bfSDan Williams } 917cc9203bfSDan Williams } else { 918d9dcb4baSDan Williams iphy = &ihost->phys[ihost->next_phy_to_start]; 919cc9203bfSDan Williams 920cc9203bfSDan Williams if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { 92185280955SDan Williams if (phy_get_non_dummy_port(iphy) == NULL) { 922d9dcb4baSDan Williams ihost->next_phy_to_start++; 923cc9203bfSDan Williams 924cc9203bfSDan Williams /* Caution recursion ahead be forwarned 925cc9203bfSDan Williams * 926cc9203bfSDan Williams * The PHY was never added to a PORT in MPC mode 927cc9203bfSDan Williams * so start the next phy in sequence This phy 928cc9203bfSDan Williams * will never go link up and will not draw power 929cc9203bfSDan Williams * the OEM parameters either configured the phy 930cc9203bfSDan Williams * incorrectly for the PORT or it was never 931cc9203bfSDan Williams * assigned to a PORT 932cc9203bfSDan Williams */ 93389a7301fSDan Williams return sci_controller_start_next_phy(ihost); 934cc9203bfSDan Williams } 935cc9203bfSDan Williams } 936cc9203bfSDan Williams 93789a7301fSDan Williams status = sci_phy_start(iphy); 938cc9203bfSDan Williams 939cc9203bfSDan Williams if (status == SCI_SUCCESS) { 940d9dcb4baSDan Williams sci_mod_timer(&ihost->phy_timer, 941bb3dbdf6SEdmund Nadolski SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT); 942d9dcb4baSDan Williams ihost->phy_startup_timer_pending = true; 943cc9203bfSDan Williams } else { 944d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 945cc9203bfSDan Williams "%s: Controller stop operation failed " 946cc9203bfSDan Williams "to stop phy %d because of status " 947cc9203bfSDan Williams "%d.\n", 948cc9203bfSDan Williams __func__, 949d9dcb4baSDan Williams ihost->phys[ihost->next_phy_to_start].phy_index, 950cc9203bfSDan Williams status); 951cc9203bfSDan Williams } 952cc9203bfSDan Williams 953d9dcb4baSDan Williams ihost->next_phy_to_start++; 954cc9203bfSDan Williams } 955cc9203bfSDan Williams 956cc9203bfSDan Williams return status; 957cc9203bfSDan Williams } 958cc9203bfSDan Williams 959b0a2dc66SKees Cook static void phy_startup_timeout(struct timer_list *t) 960cc9203bfSDan Williams { 961b0a2dc66SKees Cook struct sci_timer *tmr = from_timer(tmr, t, timer); 962d9dcb4baSDan Williams struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer); 963bb3dbdf6SEdmund Nadolski unsigned long flags; 964cc9203bfSDan Williams enum sci_status status; 965cc9203bfSDan Williams 966bb3dbdf6SEdmund Nadolski spin_lock_irqsave(&ihost->scic_lock, flags); 967bb3dbdf6SEdmund Nadolski 968bb3dbdf6SEdmund Nadolski if (tmr->cancel) 969bb3dbdf6SEdmund Nadolski goto done; 970bb3dbdf6SEdmund Nadolski 971d9dcb4baSDan Williams ihost->phy_startup_timer_pending = false; 972bb3dbdf6SEdmund Nadolski 973bb3dbdf6SEdmund Nadolski do { 97489a7301fSDan Williams status = sci_controller_start_next_phy(ihost); 975bb3dbdf6SEdmund Nadolski } while (status != SCI_SUCCESS); 976bb3dbdf6SEdmund Nadolski 977bb3dbdf6SEdmund Nadolski done: 978bb3dbdf6SEdmund Nadolski spin_unlock_irqrestore(&ihost->scic_lock, flags); 979cc9203bfSDan Williams } 980cc9203bfSDan Williams 981ac668c69SDan Williams static u16 isci_tci_active(struct isci_host *ihost) 982ac668c69SDan Williams { 983ac668c69SDan Williams return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); 984ac668c69SDan Williams } 985ac668c69SDan Williams 98689a7301fSDan Williams static enum sci_status sci_controller_start(struct isci_host *ihost, 987cc9203bfSDan Williams u32 timeout) 988cc9203bfSDan Williams { 989cc9203bfSDan Williams enum sci_status result; 990cc9203bfSDan Williams u16 index; 991cc9203bfSDan Williams 992d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_INITIALIZED) { 99314e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 99414e99b4aSDan Williams __func__, ihost->sm.current_state_id); 995cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 996cc9203bfSDan Williams } 997cc9203bfSDan Williams 998cc9203bfSDan Williams /* Build the TCi free pool */ 999ac668c69SDan Williams BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8); 1000ac668c69SDan Williams ihost->tci_head = 0; 1001ac668c69SDan Williams ihost->tci_tail = 0; 1002d9dcb4baSDan Williams for (index = 0; index < ihost->task_context_entries; index++) 1003ac668c69SDan Williams isci_tci_free(ihost, index); 1004cc9203bfSDan Williams 1005cc9203bfSDan Williams /* Build the RNi free pool */ 100689a7301fSDan Williams sci_remote_node_table_initialize(&ihost->available_remote_nodes, 1007d9dcb4baSDan Williams ihost->remote_node_entries); 1008cc9203bfSDan Williams 1009cc9203bfSDan Williams /* 1010cc9203bfSDan Williams * Before anything else lets make sure we will not be 1011cc9203bfSDan Williams * interrupted by the hardware. 1012cc9203bfSDan Williams */ 101389a7301fSDan Williams sci_controller_disable_interrupts(ihost); 1014cc9203bfSDan Williams 1015cc9203bfSDan Williams /* Enable the port task scheduler */ 101689a7301fSDan Williams sci_controller_enable_port_task_scheduler(ihost); 1017cc9203bfSDan Williams 1018d9dcb4baSDan Williams /* Assign all the task entries to ihost physical function */ 101989a7301fSDan Williams sci_controller_assign_task_entries(ihost); 1020cc9203bfSDan Williams 1021cc9203bfSDan Williams /* Now initialize the completion queue */ 102289a7301fSDan Williams sci_controller_initialize_completion_queue(ihost); 1023cc9203bfSDan Williams 1024cc9203bfSDan Williams /* Initialize the unsolicited frame queue for use */ 102589a7301fSDan Williams sci_controller_initialize_unsolicited_frame_queue(ihost); 1026cc9203bfSDan Williams 1027cc9203bfSDan Williams /* Start all of the ports on this controller */ 1028d9dcb4baSDan Williams for (index = 0; index < ihost->logical_port_entries; index++) { 1029ffe191c9SDan Williams struct isci_port *iport = &ihost->ports[index]; 1030cc9203bfSDan Williams 103189a7301fSDan Williams result = sci_port_start(iport); 1032cc9203bfSDan Williams if (result) 1033cc9203bfSDan Williams return result; 1034cc9203bfSDan Williams } 1035cc9203bfSDan Williams 103689a7301fSDan Williams sci_controller_start_next_phy(ihost); 1037cc9203bfSDan Williams 1038d9dcb4baSDan Williams sci_mod_timer(&ihost->timer, timeout); 1039cc9203bfSDan Williams 1040d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_STARTING); 1041cc9203bfSDan Williams 1042cc9203bfSDan Williams return SCI_SUCCESS; 1043cc9203bfSDan Williams } 1044cc9203bfSDan Williams 1045e468dc11SArtur Wojcik void isci_host_start(struct Scsi_Host *shost) 10466f231ddaSDan Williams { 10474393aa4eSDan Williams struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; 104889a7301fSDan Williams unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost); 10496f231ddaSDan Williams 10500cf89d1dSDan Williams set_bit(IHOST_START_PENDING, &ihost->flags); 105177950f51SEdmund Nadolski 105277950f51SEdmund Nadolski spin_lock_irq(&ihost->scic_lock); 105389a7301fSDan Williams sci_controller_start(ihost, tmo); 105489a7301fSDan Williams sci_controller_enable_interrupts(ihost); 105577950f51SEdmund Nadolski spin_unlock_irq(&ihost->scic_lock); 10566f231ddaSDan Williams } 10576f231ddaSDan Williams 1058eb608c3cSDan Williams static void isci_host_stop_complete(struct isci_host *ihost) 10596f231ddaSDan Williams { 106089a7301fSDan Williams sci_controller_disable_interrupts(ihost); 10610cf89d1dSDan Williams clear_bit(IHOST_STOP_PENDING, &ihost->flags); 10620cf89d1dSDan Williams wake_up(&ihost->eventq); 10636f231ddaSDan Williams } 10646f231ddaSDan Williams 106589a7301fSDan Williams static void sci_controller_completion_handler(struct isci_host *ihost) 1066cc9203bfSDan Williams { 1067cc9203bfSDan Williams /* Empty out the completion queue */ 106889a7301fSDan Williams if (sci_controller_completion_queue_has_entries(ihost)) 106989a7301fSDan Williams sci_controller_process_completions(ihost); 1070cc9203bfSDan Williams 1071cc9203bfSDan Williams /* Clear the interrupt and enable all interrupts again */ 1072d9dcb4baSDan Williams writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); 1073cc9203bfSDan Williams /* Could we write the value of SMU_ISR_COMPLETION? */ 1074d9dcb4baSDan Williams writel(0xFF000000, &ihost->smu_registers->interrupt_mask); 1075d9dcb4baSDan Williams writel(0, &ihost->smu_registers->interrupt_mask); 1076cc9203bfSDan Williams } 1077cc9203bfSDan Williams 1078f8381807SJeff Skirvin void ireq_done(struct isci_host *ihost, struct isci_request *ireq, struct sas_task *task) 1079f8381807SJeff Skirvin { 1080f8381807SJeff Skirvin if (!test_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags) && 1081f8381807SJeff Skirvin !(task->task_state_flags & SAS_TASK_STATE_ABORTED)) { 1082f8381807SJeff Skirvin if (test_bit(IREQ_COMPLETE_IN_TARGET, &ireq->flags)) { 1083f8381807SJeff Skirvin /* Normal notification (task_done) */ 1084f8381807SJeff Skirvin dev_dbg(&ihost->pdev->dev, 1085f8381807SJeff Skirvin "%s: Normal - ireq/task = %p/%p\n", 1086f8381807SJeff Skirvin __func__, ireq, task); 108754b46677SJeff Skirvin task->lldd_task = NULL; 1088f8381807SJeff Skirvin task->task_done(task); 1089f8381807SJeff Skirvin } else { 1090f8381807SJeff Skirvin dev_dbg(&ihost->pdev->dev, 1091f8381807SJeff Skirvin "%s: Error - ireq/task = %p/%p\n", 1092f8381807SJeff Skirvin __func__, ireq, task); 109354b46677SJeff Skirvin if (sas_protocol_ata(task->task_proto)) 109454b46677SJeff Skirvin task->lldd_task = NULL; 1095f8381807SJeff Skirvin sas_task_abort(task); 1096f8381807SJeff Skirvin } 109754b46677SJeff Skirvin } else 109854b46677SJeff Skirvin task->lldd_task = NULL; 109954b46677SJeff Skirvin 1100f8381807SJeff Skirvin if (test_and_clear_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags)) 1101f8381807SJeff Skirvin wake_up_all(&ihost->eventq); 1102f8381807SJeff Skirvin 1103f8381807SJeff Skirvin if (!test_bit(IREQ_NO_AUTO_FREE_TAG, &ireq->flags)) 1104f8381807SJeff Skirvin isci_free_tag(ihost, ireq->io_tag); 1105f8381807SJeff Skirvin } 11066f231ddaSDan Williams /** 11076f231ddaSDan Williams * isci_host_completion_routine() - This function is the delayed service 11086f231ddaSDan Williams * routine that calls the sci core library's completion handler. It's 11096f231ddaSDan Williams * scheduled as a tasklet from the interrupt service routine when interrupts 11106f231ddaSDan Williams * in use, or set as the timeout function in polled mode. 11116f231ddaSDan Williams * @data: This parameter specifies the ISCI host object 11126f231ddaSDan Williams * 11136f231ddaSDan Williams */ 1114abec912dSDan Williams void isci_host_completion_routine(unsigned long data) 11156f231ddaSDan Williams { 1116d9dcb4baSDan Williams struct isci_host *ihost = (struct isci_host *)data; 11179b4be528SDan Williams u16 active; 11186f231ddaSDan Williams 1119d9dcb4baSDan Williams spin_lock_irq(&ihost->scic_lock); 112089a7301fSDan Williams sci_controller_completion_handler(ihost); 1121033d19d2SJeff Skirvin spin_unlock_irq(&ihost->scic_lock); 11226f231ddaSDan Williams 112344ef2bf7SDave Jiang /* 112444ef2bf7SDave Jiang * we subtract SCI_MAX_PORTS to account for the number of dummy TCs 112544ef2bf7SDave Jiang * issued for hardware issue workaround 112644ef2bf7SDave Jiang */ 112744ef2bf7SDave Jiang active = isci_tci_active(ihost) - SCI_MAX_PORTS; 112844ef2bf7SDave Jiang 112944ef2bf7SDave Jiang /* 113044ef2bf7SDave Jiang * the coalesence timeout doubles at each encoding step, so 11319b4be528SDan Williams * update it based on the ilog2 value of the outstanding requests 11329b4be528SDan Williams */ 11339b4be528SDan Williams writel(SMU_ICC_GEN_VAL(NUMBER, active) | 11349b4be528SDan Williams SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)), 11359b4be528SDan Williams &ihost->smu_registers->interrupt_coalesce_control); 11366f231ddaSDan Williams } 11376f231ddaSDan Williams 1138cc9203bfSDan Williams /** 113989a7301fSDan Williams * sci_controller_stop() - This method will stop an individual controller 1140cc9203bfSDan Williams * object.This method will invoke the associated user callback upon 1141cc9203bfSDan Williams * completion. The completion callback is called when the following 1142cc9203bfSDan Williams * conditions are met: -# the method return status is SCI_SUCCESS. -# the 1143cc9203bfSDan Williams * controller has been quiesced. This method will ensure that all IO 1144cc9203bfSDan Williams * requests are quiesced, phys are stopped, and all additional operation by 1145cc9203bfSDan Williams * the hardware is halted. 1146*44b7ca96SLee Jones * @ihost: the handle to the controller object to stop. 1147cc9203bfSDan Williams * @timeout: This parameter specifies the number of milliseconds in which the 1148cc9203bfSDan Williams * stop operation should complete. 1149cc9203bfSDan Williams * 1150cc9203bfSDan Williams * The controller must be in the STARTED or STOPPED state. Indicate if the 1151cc9203bfSDan Williams * controller stop method succeeded or failed in some way. SCI_SUCCESS if the 1152cc9203bfSDan Williams * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the 1153cc9203bfSDan Williams * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the 1154cc9203bfSDan Williams * controller is not either in the STARTED or STOPPED states. 1155cc9203bfSDan Williams */ 115689a7301fSDan Williams static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout) 1157cc9203bfSDan Williams { 1158d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_READY) { 115914e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 116014e99b4aSDan Williams __func__, ihost->sm.current_state_id); 1161cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 1162cc9203bfSDan Williams } 1163cc9203bfSDan Williams 1164d9dcb4baSDan Williams sci_mod_timer(&ihost->timer, timeout); 1165d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_STOPPING); 1166cc9203bfSDan Williams return SCI_SUCCESS; 1167cc9203bfSDan Williams } 1168cc9203bfSDan Williams 1169cc9203bfSDan Williams /** 117089a7301fSDan Williams * sci_controller_reset() - This method will reset the supplied core 1171cc9203bfSDan Williams * controller regardless of the state of said controller. This operation is 1172cc9203bfSDan Williams * considered destructive. In other words, all current operations are wiped 1173cc9203bfSDan Williams * out. No IO completions for outstanding devices occur. Outstanding IO 1174cc9203bfSDan Williams * requests are not aborted or completed at the actual remote device. 1175*44b7ca96SLee Jones * @ihost: the handle to the controller object to reset. 1176cc9203bfSDan Williams * 1177cc9203bfSDan Williams * Indicate if the controller reset method succeeded or failed in some way. 1178cc9203bfSDan Williams * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if 1179cc9203bfSDan Williams * the controller reset operation is unable to complete. 1180cc9203bfSDan Williams */ 118189a7301fSDan Williams static enum sci_status sci_controller_reset(struct isci_host *ihost) 1182cc9203bfSDan Williams { 1183d9dcb4baSDan Williams switch (ihost->sm.current_state_id) { 1184e301370aSEdmund Nadolski case SCIC_RESET: 1185e301370aSEdmund Nadolski case SCIC_READY: 1186eb608c3cSDan Williams case SCIC_STOPPING: 1187e301370aSEdmund Nadolski case SCIC_FAILED: 1188cc9203bfSDan Williams /* 1189cc9203bfSDan Williams * The reset operation is not a graceful cleanup, just 1190cc9203bfSDan Williams * perform the state transition. 1191cc9203bfSDan Williams */ 1192d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_RESETTING); 1193cc9203bfSDan Williams return SCI_SUCCESS; 1194cc9203bfSDan Williams default: 119514e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 119614e99b4aSDan Williams __func__, ihost->sm.current_state_id); 1197cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 1198cc9203bfSDan Williams } 1199cc9203bfSDan Williams } 1200cc9203bfSDan Williams 1201eb608c3cSDan Williams static enum sci_status sci_controller_stop_phys(struct isci_host *ihost) 1202eb608c3cSDan Williams { 1203eb608c3cSDan Williams u32 index; 1204eb608c3cSDan Williams enum sci_status status; 1205eb608c3cSDan Williams enum sci_status phy_status; 1206eb608c3cSDan Williams 1207eb608c3cSDan Williams status = SCI_SUCCESS; 1208eb608c3cSDan Williams 1209eb608c3cSDan Williams for (index = 0; index < SCI_MAX_PHYS; index++) { 1210eb608c3cSDan Williams phy_status = sci_phy_stop(&ihost->phys[index]); 1211eb608c3cSDan Williams 1212eb608c3cSDan Williams if (phy_status != SCI_SUCCESS && 1213eb608c3cSDan Williams phy_status != SCI_FAILURE_INVALID_STATE) { 1214eb608c3cSDan Williams status = SCI_FAILURE; 1215eb608c3cSDan Williams 1216eb608c3cSDan Williams dev_warn(&ihost->pdev->dev, 1217eb608c3cSDan Williams "%s: Controller stop operation failed to stop " 1218eb608c3cSDan Williams "phy %d because of status %d.\n", 1219eb608c3cSDan Williams __func__, 1220eb608c3cSDan Williams ihost->phys[index].phy_index, phy_status); 1221eb608c3cSDan Williams } 1222eb608c3cSDan Williams } 1223eb608c3cSDan Williams 1224eb608c3cSDan Williams return status; 1225eb608c3cSDan Williams } 1226eb608c3cSDan Williams 1227eb608c3cSDan Williams 1228eb608c3cSDan Williams /** 1229eb608c3cSDan Williams * isci_host_deinit - shutdown frame reception and dma 1230eb608c3cSDan Williams * @ihost: host to take down 1231eb608c3cSDan Williams * 1232eb608c3cSDan Williams * This is called in either the driver shutdown or the suspend path. In 1233eb608c3cSDan Williams * the shutdown case libsas went through port teardown and normal device 1234eb608c3cSDan Williams * removal (i.e. physical links stayed up to service scsi_device removal 1235eb608c3cSDan Williams * commands). In the suspend case we disable the hardware without 1236eb608c3cSDan Williams * notifying libsas of the link down events since we want libsas to 1237eb608c3cSDan Williams * remember the domain across the suspend/resume cycle 1238eb608c3cSDan Williams */ 12390cf89d1dSDan Williams void isci_host_deinit(struct isci_host *ihost) 12406f231ddaSDan Williams { 12416f231ddaSDan Williams int i; 12426f231ddaSDan Williams 1243ad4f4c1dSDan Williams /* disable output data selects */ 1244ad4f4c1dSDan Williams for (i = 0; i < isci_gpio_count(ihost); i++) 1245ad4f4c1dSDan Williams writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]); 1246ad4f4c1dSDan Williams 12470cf89d1dSDan Williams set_bit(IHOST_STOP_PENDING, &ihost->flags); 12487c40a803SDan Williams 12497c40a803SDan Williams spin_lock_irq(&ihost->scic_lock); 125089a7301fSDan Williams sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT); 12517c40a803SDan Williams spin_unlock_irq(&ihost->scic_lock); 12527c40a803SDan Williams 12530cf89d1dSDan Williams wait_for_stop(ihost); 1254ad4f4c1dSDan Williams 1255eb608c3cSDan Williams /* phy stop is after controller stop to allow port and device to 1256eb608c3cSDan Williams * go idle before shutting down the phys, but the expectation is 1257eb608c3cSDan Williams * that i/o has been shut off well before we reach this 1258eb608c3cSDan Williams * function. 1259eb608c3cSDan Williams */ 1260eb608c3cSDan Williams sci_controller_stop_phys(ihost); 1261eb608c3cSDan Williams 1262ad4f4c1dSDan Williams /* disable sgpio: where the above wait should give time for the 1263ad4f4c1dSDan Williams * enclosure to sample the gpios going inactive 1264ad4f4c1dSDan Williams */ 1265ad4f4c1dSDan Williams writel(0, &ihost->scu_registers->peg0.sgpio.interface_control); 1266ad4f4c1dSDan Williams 12672396a265SDan Williams spin_lock_irq(&ihost->scic_lock); 126889a7301fSDan Williams sci_controller_reset(ihost); 12692396a265SDan Williams spin_unlock_irq(&ihost->scic_lock); 12705553ba2bSEdmund Nadolski 12715553ba2bSEdmund Nadolski /* Cancel any/all outstanding port timers */ 1272d9dcb4baSDan Williams for (i = 0; i < ihost->logical_port_entries; i++) { 1273ffe191c9SDan Williams struct isci_port *iport = &ihost->ports[i]; 1274ffe191c9SDan Williams del_timer_sync(&iport->timer.timer); 12755553ba2bSEdmund Nadolski } 12765553ba2bSEdmund Nadolski 1277a628d478SEdmund Nadolski /* Cancel any/all outstanding phy timers */ 1278a628d478SEdmund Nadolski for (i = 0; i < SCI_MAX_PHYS; i++) { 127985280955SDan Williams struct isci_phy *iphy = &ihost->phys[i]; 128085280955SDan Williams del_timer_sync(&iphy->sata_timer.timer); 1281a628d478SEdmund Nadolski } 1282a628d478SEdmund Nadolski 1283d9dcb4baSDan Williams del_timer_sync(&ihost->port_agent.timer.timer); 1284ac0eeb4fSEdmund Nadolski 1285d9dcb4baSDan Williams del_timer_sync(&ihost->power_control.timer.timer); 12860473661aSEdmund Nadolski 1287d9dcb4baSDan Williams del_timer_sync(&ihost->timer.timer); 12886cb5853dSEdmund Nadolski 1289d9dcb4baSDan Williams del_timer_sync(&ihost->phy_timer.timer); 12906f231ddaSDan Williams } 12916f231ddaSDan Williams 12926f231ddaSDan Williams static void __iomem *scu_base(struct isci_host *isci_host) 12936f231ddaSDan Williams { 12946f231ddaSDan Williams struct pci_dev *pdev = isci_host->pdev; 12956f231ddaSDan Williams int id = isci_host->id; 12966f231ddaSDan Williams 12976f231ddaSDan Williams return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id; 12986f231ddaSDan Williams } 12996f231ddaSDan Williams 13006f231ddaSDan Williams static void __iomem *smu_base(struct isci_host *isci_host) 13016f231ddaSDan Williams { 13026f231ddaSDan Williams struct pci_dev *pdev = isci_host->pdev; 13036f231ddaSDan Williams int id = isci_host->id; 13046f231ddaSDan Williams 13056f231ddaSDan Williams return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id; 13066f231ddaSDan Williams } 13076f231ddaSDan Williams 130889a7301fSDan Williams static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm) 1309cc9203bfSDan Williams { 1310d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1311cc9203bfSDan Williams 1312d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_RESET); 1313cc9203bfSDan Williams } 1314cc9203bfSDan Williams 131589a7301fSDan Williams static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm) 1316cc9203bfSDan Williams { 1317d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1318cc9203bfSDan Williams 1319d9dcb4baSDan Williams sci_del_timer(&ihost->timer); 1320cc9203bfSDan Williams } 1321cc9203bfSDan Williams 1322cc9203bfSDan Williams #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853 1323cc9203bfSDan Williams #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280 1324cc9203bfSDan Williams #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000 1325cc9203bfSDan Williams #define INTERRUPT_COALESCE_NUMBER_MAX 256 1326cc9203bfSDan Williams #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7 1327cc9203bfSDan Williams #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28 1328cc9203bfSDan Williams 1329cc9203bfSDan Williams /** 133089a7301fSDan Williams * sci_controller_set_interrupt_coalescence() - This method allows the user to 1331cc9203bfSDan Williams * configure the interrupt coalescence. 1332*44b7ca96SLee Jones * @ihost: This parameter represents the handle to the controller object 1333cc9203bfSDan Williams * for which its interrupt coalesce register is overridden. 1334cc9203bfSDan Williams * @coalesce_number: Used to control the number of entries in the Completion 1335cc9203bfSDan Williams * Queue before an interrupt is generated. If the number of entries exceed 1336cc9203bfSDan Williams * this number, an interrupt will be generated. The valid range of the input 1337cc9203bfSDan Williams * is [0, 256]. A setting of 0 results in coalescing being disabled. 1338cc9203bfSDan Williams * @coalesce_timeout: Timeout value in microseconds. The valid range of the 1339cc9203bfSDan Williams * input is [0, 2700000] . A setting of 0 is allowed and results in no 1340cc9203bfSDan Williams * interrupt coalescing timeout. 1341cc9203bfSDan Williams * 1342cc9203bfSDan Williams * Indicate if the user successfully set the interrupt coalesce parameters. 1343cc9203bfSDan Williams * SCI_SUCCESS The user successfully updated the interrutp coalescence. 1344cc9203bfSDan Williams * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range. 1345cc9203bfSDan Williams */ 1346d9dcb4baSDan Williams static enum sci_status 134789a7301fSDan Williams sci_controller_set_interrupt_coalescence(struct isci_host *ihost, 1348cc9203bfSDan Williams u32 coalesce_number, 1349cc9203bfSDan Williams u32 coalesce_timeout) 1350cc9203bfSDan Williams { 1351cc9203bfSDan Williams u8 timeout_encode = 0; 1352cc9203bfSDan Williams u32 min = 0; 1353cc9203bfSDan Williams u32 max = 0; 1354cc9203bfSDan Williams 1355cc9203bfSDan Williams /* Check if the input parameters fall in the range. */ 1356cc9203bfSDan Williams if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX) 1357cc9203bfSDan Williams return SCI_FAILURE_INVALID_PARAMETER_VALUE; 1358cc9203bfSDan Williams 1359cc9203bfSDan Williams /* 1360cc9203bfSDan Williams * Defined encoding for interrupt coalescing timeout: 1361cc9203bfSDan Williams * Value Min Max Units 1362cc9203bfSDan Williams * ----- --- --- ----- 1363cc9203bfSDan Williams * 0 - - Disabled 1364cc9203bfSDan Williams * 1 13.3 20.0 ns 1365cc9203bfSDan Williams * 2 26.7 40.0 1366cc9203bfSDan Williams * 3 53.3 80.0 1367cc9203bfSDan Williams * 4 106.7 160.0 1368cc9203bfSDan Williams * 5 213.3 320.0 1369cc9203bfSDan Williams * 6 426.7 640.0 1370cc9203bfSDan Williams * 7 853.3 1280.0 1371cc9203bfSDan Williams * 8 1.7 2.6 us 1372cc9203bfSDan Williams * 9 3.4 5.1 1373cc9203bfSDan Williams * 10 6.8 10.2 1374cc9203bfSDan Williams * 11 13.7 20.5 1375cc9203bfSDan Williams * 12 27.3 41.0 1376cc9203bfSDan Williams * 13 54.6 81.9 1377cc9203bfSDan Williams * 14 109.2 163.8 1378cc9203bfSDan Williams * 15 218.5 327.7 1379cc9203bfSDan Williams * 16 436.9 655.4 1380cc9203bfSDan Williams * 17 873.8 1310.7 1381cc9203bfSDan Williams * 18 1.7 2.6 ms 1382cc9203bfSDan Williams * 19 3.5 5.2 1383cc9203bfSDan Williams * 20 7.0 10.5 1384cc9203bfSDan Williams * 21 14.0 21.0 1385cc9203bfSDan Williams * 22 28.0 41.9 1386cc9203bfSDan Williams * 23 55.9 83.9 1387cc9203bfSDan Williams * 24 111.8 167.8 1388cc9203bfSDan Williams * 25 223.7 335.5 1389cc9203bfSDan Williams * 26 447.4 671.1 1390cc9203bfSDan Williams * 27 894.8 1342.2 1391cc9203bfSDan Williams * 28 1.8 2.7 s 1392cc9203bfSDan Williams * Others Undefined */ 1393cc9203bfSDan Williams 1394cc9203bfSDan Williams /* 1395cc9203bfSDan Williams * Use the table above to decide the encode of interrupt coalescing timeout 1396cc9203bfSDan Williams * value for register writing. */ 1397cc9203bfSDan Williams if (coalesce_timeout == 0) 1398cc9203bfSDan Williams timeout_encode = 0; 1399cc9203bfSDan Williams else{ 1400cc9203bfSDan Williams /* make the timeout value in unit of (10 ns). */ 1401cc9203bfSDan Williams coalesce_timeout = coalesce_timeout * 100; 1402cc9203bfSDan Williams min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10; 1403cc9203bfSDan Williams max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10; 1404cc9203bfSDan Williams 1405cc9203bfSDan Williams /* get the encode of timeout for register writing. */ 1406cc9203bfSDan Williams for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN; 1407cc9203bfSDan Williams timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX; 1408cc9203bfSDan Williams timeout_encode++) { 1409cc9203bfSDan Williams if (min <= coalesce_timeout && max > coalesce_timeout) 1410cc9203bfSDan Williams break; 1411cc9203bfSDan Williams else if (coalesce_timeout >= max && coalesce_timeout < min * 2 1412cc9203bfSDan Williams && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) { 1413cc9203bfSDan Williams if ((coalesce_timeout - max) < (2 * min - coalesce_timeout)) 1414cc9203bfSDan Williams break; 1415cc9203bfSDan Williams else{ 1416cc9203bfSDan Williams timeout_encode++; 1417cc9203bfSDan Williams break; 1418cc9203bfSDan Williams } 1419cc9203bfSDan Williams } else { 1420cc9203bfSDan Williams max = max * 2; 1421cc9203bfSDan Williams min = min * 2; 1422cc9203bfSDan Williams } 1423cc9203bfSDan Williams } 1424cc9203bfSDan Williams 1425cc9203bfSDan Williams if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1) 1426cc9203bfSDan Williams /* the value is out of range. */ 1427cc9203bfSDan Williams return SCI_FAILURE_INVALID_PARAMETER_VALUE; 1428cc9203bfSDan Williams } 1429cc9203bfSDan Williams 1430cc9203bfSDan Williams writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) | 1431cc9203bfSDan Williams SMU_ICC_GEN_VAL(TIMER, timeout_encode), 1432d9dcb4baSDan Williams &ihost->smu_registers->interrupt_coalesce_control); 1433cc9203bfSDan Williams 1434cc9203bfSDan Williams 1435d9dcb4baSDan Williams ihost->interrupt_coalesce_number = (u16)coalesce_number; 1436d9dcb4baSDan Williams ihost->interrupt_coalesce_timeout = coalesce_timeout / 100; 1437cc9203bfSDan Williams 1438cc9203bfSDan Williams return SCI_SUCCESS; 1439cc9203bfSDan Williams } 1440cc9203bfSDan Williams 1441cc9203bfSDan Williams 144289a7301fSDan Williams static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm) 1443cc9203bfSDan Williams { 1444d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1445e5cc6aa4SMarcin Tomczak u32 val; 1446e5cc6aa4SMarcin Tomczak 1447e5cc6aa4SMarcin Tomczak /* enable clock gating for power control of the scu unit */ 1448e5cc6aa4SMarcin Tomczak val = readl(&ihost->smu_registers->clock_gating_control); 1449e5cc6aa4SMarcin Tomczak val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) | 1450e5cc6aa4SMarcin Tomczak SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) | 1451e5cc6aa4SMarcin Tomczak SMU_CGUCR_GEN_BIT(XCLK_ENABLE)); 1452e5cc6aa4SMarcin Tomczak val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE); 1453e5cc6aa4SMarcin Tomczak writel(val, &ihost->smu_registers->clock_gating_control); 1454cc9203bfSDan Williams 1455cc9203bfSDan Williams /* set the default interrupt coalescence number and timeout value. */ 14569b4be528SDan Williams sci_controller_set_interrupt_coalescence(ihost, 0, 0); 1457cc9203bfSDan Williams } 1458cc9203bfSDan Williams 145989a7301fSDan Williams static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm) 1460cc9203bfSDan Williams { 1461d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1462cc9203bfSDan Williams 1463cc9203bfSDan Williams /* disable interrupt coalescence. */ 146489a7301fSDan Williams sci_controller_set_interrupt_coalescence(ihost, 0, 0); 1465cc9203bfSDan Williams } 1466cc9203bfSDan Williams 146789a7301fSDan Williams static enum sci_status sci_controller_stop_ports(struct isci_host *ihost) 1468cc9203bfSDan Williams { 1469cc9203bfSDan Williams u32 index; 1470cc9203bfSDan Williams enum sci_status port_status; 1471cc9203bfSDan Williams enum sci_status status = SCI_SUCCESS; 1472cc9203bfSDan Williams 1473d9dcb4baSDan Williams for (index = 0; index < ihost->logical_port_entries; index++) { 1474ffe191c9SDan Williams struct isci_port *iport = &ihost->ports[index]; 1475cc9203bfSDan Williams 147689a7301fSDan Williams port_status = sci_port_stop(iport); 1477cc9203bfSDan Williams 1478cc9203bfSDan Williams if ((port_status != SCI_SUCCESS) && 1479cc9203bfSDan Williams (port_status != SCI_FAILURE_INVALID_STATE)) { 1480cc9203bfSDan Williams status = SCI_FAILURE; 1481cc9203bfSDan Williams 1482d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 1483cc9203bfSDan Williams "%s: Controller stop operation failed to " 1484cc9203bfSDan Williams "stop port %d because of status %d.\n", 1485cc9203bfSDan Williams __func__, 1486ffe191c9SDan Williams iport->logical_port_index, 1487cc9203bfSDan Williams port_status); 1488cc9203bfSDan Williams } 1489cc9203bfSDan Williams } 1490cc9203bfSDan Williams 1491cc9203bfSDan Williams return status; 1492cc9203bfSDan Williams } 1493cc9203bfSDan Williams 149489a7301fSDan Williams static enum sci_status sci_controller_stop_devices(struct isci_host *ihost) 1495cc9203bfSDan Williams { 1496cc9203bfSDan Williams u32 index; 1497cc9203bfSDan Williams enum sci_status status; 1498cc9203bfSDan Williams enum sci_status device_status; 1499cc9203bfSDan Williams 1500cc9203bfSDan Williams status = SCI_SUCCESS; 1501cc9203bfSDan Williams 1502d9dcb4baSDan Williams for (index = 0; index < ihost->remote_node_entries; index++) { 1503d9dcb4baSDan Williams if (ihost->device_table[index] != NULL) { 1504cc9203bfSDan Williams /* / @todo What timeout value do we want to provide to this request? */ 150589a7301fSDan Williams device_status = sci_remote_device_stop(ihost->device_table[index], 0); 1506cc9203bfSDan Williams 1507cc9203bfSDan Williams if ((device_status != SCI_SUCCESS) && 1508cc9203bfSDan Williams (device_status != SCI_FAILURE_INVALID_STATE)) { 1509d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 1510cc9203bfSDan Williams "%s: Controller stop operation failed " 1511cc9203bfSDan Williams "to stop device 0x%p because of " 1512cc9203bfSDan Williams "status %d.\n", 1513cc9203bfSDan Williams __func__, 1514d9dcb4baSDan Williams ihost->device_table[index], device_status); 1515cc9203bfSDan Williams } 1516cc9203bfSDan Williams } 1517cc9203bfSDan Williams } 1518cc9203bfSDan Williams 1519cc9203bfSDan Williams return status; 1520cc9203bfSDan Williams } 1521cc9203bfSDan Williams 152289a7301fSDan Williams static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm) 1523cc9203bfSDan Williams { 1524d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1525cc9203bfSDan Williams 152689a7301fSDan Williams sci_controller_stop_devices(ihost); 1527eb608c3cSDan Williams sci_controller_stop_ports(ihost); 1528eb608c3cSDan Williams 1529eb608c3cSDan Williams if (!sci_controller_has_remote_devices_stopping(ihost)) 1530eb608c3cSDan Williams isci_host_stop_complete(ihost); 1531cc9203bfSDan Williams } 1532cc9203bfSDan Williams 153389a7301fSDan Williams static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm) 1534cc9203bfSDan Williams { 1535d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1536cc9203bfSDan Williams 1537d9dcb4baSDan Williams sci_del_timer(&ihost->timer); 1538cc9203bfSDan Williams } 1539cc9203bfSDan Williams 154089a7301fSDan Williams static void sci_controller_reset_hardware(struct isci_host *ihost) 1541cc9203bfSDan Williams { 1542cc9203bfSDan Williams /* Disable interrupts so we dont take any spurious interrupts */ 154389a7301fSDan Williams sci_controller_disable_interrupts(ihost); 1544cc9203bfSDan Williams 1545cc9203bfSDan Williams /* Reset the SCU */ 1546d9dcb4baSDan Williams writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control); 1547cc9203bfSDan Williams 1548cc9203bfSDan Williams /* Delay for 1ms to before clearing the CQP and UFQPR. */ 1549cc9203bfSDan Williams udelay(1000); 1550cc9203bfSDan Williams 1551cc9203bfSDan Williams /* The write to the CQGR clears the CQP */ 1552d9dcb4baSDan Williams writel(0x00000000, &ihost->smu_registers->completion_queue_get); 1553cc9203bfSDan Williams 1554cc9203bfSDan Williams /* The write to the UFQGP clears the UFQPR */ 1555d9dcb4baSDan Williams writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); 15562396a265SDan Williams 15572396a265SDan Williams /* clear all interrupts */ 15582396a265SDan Williams writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status); 1559cc9203bfSDan Williams } 1560cc9203bfSDan Williams 156189a7301fSDan Williams static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm) 1562cc9203bfSDan Williams { 1563d9dcb4baSDan Williams struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); 1564cc9203bfSDan Williams 156589a7301fSDan Williams sci_controller_reset_hardware(ihost); 1566d9dcb4baSDan Williams sci_change_state(&ihost->sm, SCIC_RESET); 1567cc9203bfSDan Williams } 1568cc9203bfSDan Williams 156989a7301fSDan Williams static const struct sci_base_state sci_controller_state_table[] = { 1570e301370aSEdmund Nadolski [SCIC_INITIAL] = { 157189a7301fSDan Williams .enter_state = sci_controller_initial_state_enter, 1572cc9203bfSDan Williams }, 1573e301370aSEdmund Nadolski [SCIC_RESET] = {}, 1574e301370aSEdmund Nadolski [SCIC_INITIALIZING] = {}, 1575e301370aSEdmund Nadolski [SCIC_INITIALIZED] = {}, 1576e301370aSEdmund Nadolski [SCIC_STARTING] = { 157789a7301fSDan Williams .exit_state = sci_controller_starting_state_exit, 1578cc9203bfSDan Williams }, 1579e301370aSEdmund Nadolski [SCIC_READY] = { 158089a7301fSDan Williams .enter_state = sci_controller_ready_state_enter, 158189a7301fSDan Williams .exit_state = sci_controller_ready_state_exit, 1582cc9203bfSDan Williams }, 1583e301370aSEdmund Nadolski [SCIC_RESETTING] = { 158489a7301fSDan Williams .enter_state = sci_controller_resetting_state_enter, 1585cc9203bfSDan Williams }, 1586e301370aSEdmund Nadolski [SCIC_STOPPING] = { 158789a7301fSDan Williams .enter_state = sci_controller_stopping_state_enter, 158889a7301fSDan Williams .exit_state = sci_controller_stopping_state_exit, 1589cc9203bfSDan Williams }, 1590e301370aSEdmund Nadolski [SCIC_FAILED] = {} 1591cc9203bfSDan Williams }; 1592cc9203bfSDan Williams 1593b0a2dc66SKees Cook static void controller_timeout(struct timer_list *t) 15946cb5853dSEdmund Nadolski { 1595b0a2dc66SKees Cook struct sci_timer *tmr = from_timer(tmr, t, timer); 1596d9dcb4baSDan Williams struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer); 1597d9dcb4baSDan Williams struct sci_base_state_machine *sm = &ihost->sm; 15986cb5853dSEdmund Nadolski unsigned long flags; 1599cc9203bfSDan Williams 16006cb5853dSEdmund Nadolski spin_lock_irqsave(&ihost->scic_lock, flags); 16016cb5853dSEdmund Nadolski 16026cb5853dSEdmund Nadolski if (tmr->cancel) 16036cb5853dSEdmund Nadolski goto done; 16046cb5853dSEdmund Nadolski 1605e301370aSEdmund Nadolski if (sm->current_state_id == SCIC_STARTING) 160689a7301fSDan Williams sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT); 1607e301370aSEdmund Nadolski else if (sm->current_state_id == SCIC_STOPPING) { 1608e301370aSEdmund Nadolski sci_change_state(sm, SCIC_FAILED); 1609eb608c3cSDan Williams isci_host_stop_complete(ihost); 16106cb5853dSEdmund Nadolski } else /* / @todo Now what do we want to do in this case? */ 1611d9dcb4baSDan Williams dev_err(&ihost->pdev->dev, 16126cb5853dSEdmund Nadolski "%s: Controller timer fired when controller was not " 16136cb5853dSEdmund Nadolski "in a state being timed.\n", 16146cb5853dSEdmund Nadolski __func__); 16156cb5853dSEdmund Nadolski 16166cb5853dSEdmund Nadolski done: 16176cb5853dSEdmund Nadolski spin_unlock_irqrestore(&ihost->scic_lock, flags); 16186cb5853dSEdmund Nadolski } 1619cc9203bfSDan Williams 162089a7301fSDan Williams static enum sci_status sci_controller_construct(struct isci_host *ihost, 1621cc9203bfSDan Williams void __iomem *scu_base, 1622cc9203bfSDan Williams void __iomem *smu_base) 1623cc9203bfSDan Williams { 1624cc9203bfSDan Williams u8 i; 1625cc9203bfSDan Williams 162689a7301fSDan Williams sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL); 1627cc9203bfSDan Williams 1628d9dcb4baSDan Williams ihost->scu_registers = scu_base; 1629d9dcb4baSDan Williams ihost->smu_registers = smu_base; 1630cc9203bfSDan Williams 163189a7301fSDan Williams sci_port_configuration_agent_construct(&ihost->port_agent); 1632cc9203bfSDan Williams 1633cc9203bfSDan Williams /* Construct the ports for this controller */ 1634cc9203bfSDan Williams for (i = 0; i < SCI_MAX_PORTS; i++) 163589a7301fSDan Williams sci_port_construct(&ihost->ports[i], i, ihost); 163689a7301fSDan Williams sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost); 1637cc9203bfSDan Williams 1638cc9203bfSDan Williams /* Construct the phys for this controller */ 1639cc9203bfSDan Williams for (i = 0; i < SCI_MAX_PHYS; i++) { 1640cc9203bfSDan Williams /* Add all the PHYs to the dummy port */ 164189a7301fSDan Williams sci_phy_construct(&ihost->phys[i], 1642ffe191c9SDan Williams &ihost->ports[SCI_MAX_PORTS], i); 1643cc9203bfSDan Williams } 1644cc9203bfSDan Williams 1645d9dcb4baSDan Williams ihost->invalid_phy_mask = 0; 1646cc9203bfSDan Williams 1647d9dcb4baSDan Williams sci_init_timer(&ihost->timer, controller_timeout); 16486cb5853dSEdmund Nadolski 164989a7301fSDan Williams return sci_controller_reset(ihost); 1650cc9203bfSDan Williams } 1651cc9203bfSDan Williams 1652594e566aSDave Jiang int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version) 1653cc9203bfSDan Williams { 1654cc9203bfSDan Williams int i; 1655cc9203bfSDan Williams 1656cc9203bfSDan Williams for (i = 0; i < SCI_MAX_PORTS; i++) 1657cc9203bfSDan Williams if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) 1658cc9203bfSDan Williams return -EINVAL; 1659cc9203bfSDan Williams 1660cc9203bfSDan Williams for (i = 0; i < SCI_MAX_PHYS; i++) 1661cc9203bfSDan Williams if (oem->phys[i].sas_address.high == 0 && 1662cc9203bfSDan Williams oem->phys[i].sas_address.low == 0) 1663cc9203bfSDan Williams return -EINVAL; 1664cc9203bfSDan Williams 1665cc9203bfSDan Williams if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) { 1666cc9203bfSDan Williams for (i = 0; i < SCI_MAX_PHYS; i++) 1667cc9203bfSDan Williams if (oem->ports[i].phy_mask != 0) 1668cc9203bfSDan Williams return -EINVAL; 1669cc9203bfSDan Williams } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { 1670cc9203bfSDan Williams u8 phy_mask = 0; 1671cc9203bfSDan Williams 1672cc9203bfSDan Williams for (i = 0; i < SCI_MAX_PHYS; i++) 1673cc9203bfSDan Williams phy_mask |= oem->ports[i].phy_mask; 1674cc9203bfSDan Williams 1675cc9203bfSDan Williams if (phy_mask == 0) 1676cc9203bfSDan Williams return -EINVAL; 1677cc9203bfSDan Williams } else 1678cc9203bfSDan Williams return -EINVAL; 1679cc9203bfSDan Williams 16807000f7c7SAndrzej Jakowski if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT || 16817000f7c7SAndrzej Jakowski oem->controller.max_concurr_spin_up < 1) 1682cc9203bfSDan Williams return -EINVAL; 1683cc9203bfSDan Williams 1684594e566aSDave Jiang if (oem->controller.do_enable_ssc) { 1685594e566aSDave Jiang if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1) 1686594e566aSDave Jiang return -EINVAL; 1687594e566aSDave Jiang 1688594e566aSDave Jiang if (version >= ISCI_ROM_VER_1_1) { 1689594e566aSDave Jiang u8 test = oem->controller.ssc_sata_tx_spread_level; 1690594e566aSDave Jiang 1691594e566aSDave Jiang switch (test) { 1692594e566aSDave Jiang case 0: 1693594e566aSDave Jiang case 2: 1694594e566aSDave Jiang case 3: 1695594e566aSDave Jiang case 6: 1696594e566aSDave Jiang case 7: 1697594e566aSDave Jiang break; 1698594e566aSDave Jiang default: 1699594e566aSDave Jiang return -EINVAL; 1700594e566aSDave Jiang } 1701594e566aSDave Jiang 1702594e566aSDave Jiang test = oem->controller.ssc_sas_tx_spread_level; 1703594e566aSDave Jiang if (oem->controller.ssc_sas_tx_type == 0) { 1704594e566aSDave Jiang switch (test) { 1705594e566aSDave Jiang case 0: 1706594e566aSDave Jiang case 2: 1707594e566aSDave Jiang case 3: 1708594e566aSDave Jiang break; 1709594e566aSDave Jiang default: 1710594e566aSDave Jiang return -EINVAL; 1711594e566aSDave Jiang } 1712594e566aSDave Jiang } else if (oem->controller.ssc_sas_tx_type == 1) { 1713594e566aSDave Jiang switch (test) { 1714594e566aSDave Jiang case 0: 1715594e566aSDave Jiang case 3: 1716594e566aSDave Jiang case 6: 1717594e566aSDave Jiang break; 1718594e566aSDave Jiang default: 1719594e566aSDave Jiang return -EINVAL; 1720594e566aSDave Jiang } 1721594e566aSDave Jiang } 1722594e566aSDave Jiang } 1723594e566aSDave Jiang } 1724594e566aSDave Jiang 1725cc9203bfSDan Williams return 0; 1726cc9203bfSDan Williams } 1727cc9203bfSDan Williams 17287000f7c7SAndrzej Jakowski static u8 max_spin_up(struct isci_host *ihost) 17297000f7c7SAndrzej Jakowski { 17307000f7c7SAndrzej Jakowski if (ihost->user_parameters.max_concurr_spinup) 17317000f7c7SAndrzej Jakowski return min_t(u8, ihost->user_parameters.max_concurr_spinup, 17327000f7c7SAndrzej Jakowski MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT); 17337000f7c7SAndrzej Jakowski else 17347000f7c7SAndrzej Jakowski return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up, 17357000f7c7SAndrzej Jakowski MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT); 17367000f7c7SAndrzej Jakowski } 17377000f7c7SAndrzej Jakowski 1738b0a2dc66SKees Cook static void power_control_timeout(struct timer_list *t) 1739cc9203bfSDan Williams { 1740b0a2dc66SKees Cook struct sci_timer *tmr = from_timer(tmr, t, timer); 1741d9dcb4baSDan Williams struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer); 174285280955SDan Williams struct isci_phy *iphy; 17430473661aSEdmund Nadolski unsigned long flags; 17440473661aSEdmund Nadolski u8 i; 1745cc9203bfSDan Williams 17460473661aSEdmund Nadolski spin_lock_irqsave(&ihost->scic_lock, flags); 1747cc9203bfSDan Williams 17480473661aSEdmund Nadolski if (tmr->cancel) 17490473661aSEdmund Nadolski goto done; 1750cc9203bfSDan Williams 1751d9dcb4baSDan Williams ihost->power_control.phys_granted_power = 0; 1752cc9203bfSDan Williams 1753d9dcb4baSDan Williams if (ihost->power_control.phys_waiting == 0) { 1754d9dcb4baSDan Williams ihost->power_control.timer_started = false; 17550473661aSEdmund Nadolski goto done; 17560473661aSEdmund Nadolski } 1757cc9203bfSDan Williams 17580473661aSEdmund Nadolski for (i = 0; i < SCI_MAX_PHYS; i++) { 17590473661aSEdmund Nadolski 1760d9dcb4baSDan Williams if (ihost->power_control.phys_waiting == 0) 17610473661aSEdmund Nadolski break; 17620473661aSEdmund Nadolski 1763d9dcb4baSDan Williams iphy = ihost->power_control.requesters[i]; 176485280955SDan Williams if (iphy == NULL) 17650473661aSEdmund Nadolski continue; 17660473661aSEdmund Nadolski 17677000f7c7SAndrzej Jakowski if (ihost->power_control.phys_granted_power >= max_spin_up(ihost)) 17680473661aSEdmund Nadolski break; 17690473661aSEdmund Nadolski 1770d9dcb4baSDan Williams ihost->power_control.requesters[i] = NULL; 1771d9dcb4baSDan Williams ihost->power_control.phys_waiting--; 1772d9dcb4baSDan Williams ihost->power_control.phys_granted_power++; 177389a7301fSDan Williams sci_phy_consume_power_handler(iphy); 1774be778341SMarcin Tomczak 1775c79dd80dSDan Williams if (iphy->protocol == SAS_PROTOCOL_SSP) { 1776be778341SMarcin Tomczak u8 j; 1777be778341SMarcin Tomczak 1778be778341SMarcin Tomczak for (j = 0; j < SCI_MAX_PHYS; j++) { 1779be778341SMarcin Tomczak struct isci_phy *requester = ihost->power_control.requesters[j]; 1780be778341SMarcin Tomczak 1781be778341SMarcin Tomczak /* 1782be778341SMarcin Tomczak * Search the power_control queue to see if there are other phys 1783be778341SMarcin Tomczak * attached to the same remote device. If found, take all of 1784be778341SMarcin Tomczak * them out of await_sas_power state. 1785be778341SMarcin Tomczak */ 1786be778341SMarcin Tomczak if (requester != NULL && requester != iphy) { 1787be778341SMarcin Tomczak u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr, 1788be778341SMarcin Tomczak iphy->frame_rcvd.iaf.sas_addr, 1789be778341SMarcin Tomczak sizeof(requester->frame_rcvd.iaf.sas_addr)); 1790be778341SMarcin Tomczak 1791be778341SMarcin Tomczak if (other == 0) { 1792be778341SMarcin Tomczak ihost->power_control.requesters[j] = NULL; 1793be778341SMarcin Tomczak ihost->power_control.phys_waiting--; 1794be778341SMarcin Tomczak sci_phy_consume_power_handler(requester); 1795be778341SMarcin Tomczak } 1796be778341SMarcin Tomczak } 1797be778341SMarcin Tomczak } 1798be778341SMarcin Tomczak } 1799cc9203bfSDan Williams } 1800cc9203bfSDan Williams 1801cc9203bfSDan Williams /* 1802cc9203bfSDan Williams * It doesn't matter if the power list is empty, we need to start the 1803cc9203bfSDan Williams * timer in case another phy becomes ready. 1804cc9203bfSDan Williams */ 18050473661aSEdmund Nadolski sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 1806d9dcb4baSDan Williams ihost->power_control.timer_started = true; 18070473661aSEdmund Nadolski 18080473661aSEdmund Nadolski done: 18090473661aSEdmund Nadolski spin_unlock_irqrestore(&ihost->scic_lock, flags); 1810cc9203bfSDan Williams } 1811cc9203bfSDan Williams 181289a7301fSDan Williams void sci_controller_power_control_queue_insert(struct isci_host *ihost, 181385280955SDan Williams struct isci_phy *iphy) 1814cc9203bfSDan Williams { 181585280955SDan Williams BUG_ON(iphy == NULL); 1816cc9203bfSDan Williams 18177000f7c7SAndrzej Jakowski if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) { 1818d9dcb4baSDan Williams ihost->power_control.phys_granted_power++; 181989a7301fSDan Williams sci_phy_consume_power_handler(iphy); 1820cc9203bfSDan Williams 1821cc9203bfSDan Williams /* 1822cc9203bfSDan Williams * stop and start the power_control timer. When the timer fires, the 1823cc9203bfSDan Williams * no_of_phys_granted_power will be set to 0 1824cc9203bfSDan Williams */ 1825d9dcb4baSDan Williams if (ihost->power_control.timer_started) 1826d9dcb4baSDan Williams sci_del_timer(&ihost->power_control.timer); 18270473661aSEdmund Nadolski 1828d9dcb4baSDan Williams sci_mod_timer(&ihost->power_control.timer, 18290473661aSEdmund Nadolski SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 1830d9dcb4baSDan Williams ihost->power_control.timer_started = true; 18310473661aSEdmund Nadolski 1832cc9203bfSDan Williams } else { 1833be778341SMarcin Tomczak /* 1834be778341SMarcin Tomczak * There are phys, attached to the same sas address as this phy, are 1835be778341SMarcin Tomczak * already in READY state, this phy don't need wait. 1836be778341SMarcin Tomczak */ 1837be778341SMarcin Tomczak u8 i; 1838be778341SMarcin Tomczak struct isci_phy *current_phy; 1839be778341SMarcin Tomczak 1840be778341SMarcin Tomczak for (i = 0; i < SCI_MAX_PHYS; i++) { 1841be778341SMarcin Tomczak u8 other; 1842be778341SMarcin Tomczak current_phy = &ihost->phys[i]; 1843be778341SMarcin Tomczak 1844be778341SMarcin Tomczak other = memcmp(current_phy->frame_rcvd.iaf.sas_addr, 1845be778341SMarcin Tomczak iphy->frame_rcvd.iaf.sas_addr, 1846be778341SMarcin Tomczak sizeof(current_phy->frame_rcvd.iaf.sas_addr)); 1847be778341SMarcin Tomczak 1848be778341SMarcin Tomczak if (current_phy->sm.current_state_id == SCI_PHY_READY && 1849c79dd80dSDan Williams current_phy->protocol == SAS_PROTOCOL_SSP && 1850be778341SMarcin Tomczak other == 0) { 1851be778341SMarcin Tomczak sci_phy_consume_power_handler(iphy); 1852be778341SMarcin Tomczak break; 1853be778341SMarcin Tomczak } 1854be778341SMarcin Tomczak } 1855be778341SMarcin Tomczak 1856be778341SMarcin Tomczak if (i == SCI_MAX_PHYS) { 1857cc9203bfSDan Williams /* Add the phy in the waiting list */ 1858d9dcb4baSDan Williams ihost->power_control.requesters[iphy->phy_index] = iphy; 1859d9dcb4baSDan Williams ihost->power_control.phys_waiting++; 1860cc9203bfSDan Williams } 1861cc9203bfSDan Williams } 1862be778341SMarcin Tomczak } 1863cc9203bfSDan Williams 186489a7301fSDan Williams void sci_controller_power_control_queue_remove(struct isci_host *ihost, 186585280955SDan Williams struct isci_phy *iphy) 1866cc9203bfSDan Williams { 186785280955SDan Williams BUG_ON(iphy == NULL); 1868cc9203bfSDan Williams 186989a7301fSDan Williams if (ihost->power_control.requesters[iphy->phy_index]) 1870d9dcb4baSDan Williams ihost->power_control.phys_waiting--; 1871cc9203bfSDan Williams 1872d9dcb4baSDan Williams ihost->power_control.requesters[iphy->phy_index] = NULL; 1873cc9203bfSDan Williams } 1874cc9203bfSDan Williams 1875afd13a1fSJeff Skirvin static int is_long_cable(int phy, unsigned char selection_byte) 1876afd13a1fSJeff Skirvin { 18779fee607fSJeff Skirvin return !!(selection_byte & (1 << phy)); 1878afd13a1fSJeff Skirvin } 1879afd13a1fSJeff Skirvin 1880afd13a1fSJeff Skirvin static int is_medium_cable(int phy, unsigned char selection_byte) 1881afd13a1fSJeff Skirvin { 18829fee607fSJeff Skirvin return !!(selection_byte & (1 << (phy + 4))); 18839fee607fSJeff Skirvin } 18849fee607fSJeff Skirvin 18859fee607fSJeff Skirvin static enum cable_selections decode_selection_byte( 18869fee607fSJeff Skirvin int phy, 18879fee607fSJeff Skirvin unsigned char selection_byte) 18889fee607fSJeff Skirvin { 18899fee607fSJeff Skirvin return ((selection_byte & (1 << phy)) ? 1 : 0) 18909fee607fSJeff Skirvin + (selection_byte & (1 << (phy + 4)) ? 2 : 0); 18919fee607fSJeff Skirvin } 18929fee607fSJeff Skirvin 18939fee607fSJeff Skirvin static unsigned char *to_cable_select(struct isci_host *ihost) 18949fee607fSJeff Skirvin { 18959fee607fSJeff Skirvin if (is_cable_select_overridden()) 18969fee607fSJeff Skirvin return ((unsigned char *)&cable_selection_override) 18979fee607fSJeff Skirvin + ihost->id; 18989fee607fSJeff Skirvin else 18999fee607fSJeff Skirvin return &ihost->oem_parameters.controller.cable_selection_mask; 19009fee607fSJeff Skirvin } 19019fee607fSJeff Skirvin 19029fee607fSJeff Skirvin enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy) 19039fee607fSJeff Skirvin { 19049fee607fSJeff Skirvin return decode_selection_byte(phy, *to_cable_select(ihost)); 19059fee607fSJeff Skirvin } 19069fee607fSJeff Skirvin 19079fee607fSJeff Skirvin char *lookup_cable_names(enum cable_selections selection) 19089fee607fSJeff Skirvin { 19099fee607fSJeff Skirvin static char *cable_names[] = { 19109fee607fSJeff Skirvin [short_cable] = "short", 19119fee607fSJeff Skirvin [long_cable] = "long", 19129fee607fSJeff Skirvin [medium_cable] = "medium", 19139fee607fSJeff Skirvin [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */ 19149fee607fSJeff Skirvin }; 19159fee607fSJeff Skirvin return (selection <= undefined_cable) ? cable_names[selection] 19169fee607fSJeff Skirvin : cable_names[undefined_cable]; 1917afd13a1fSJeff Skirvin } 1918afd13a1fSJeff Skirvin 1919cc9203bfSDan Williams #define AFE_REGISTER_WRITE_DELAY 10 1920cc9203bfSDan Williams 192189a7301fSDan Williams static void sci_controller_afe_initialization(struct isci_host *ihost) 1922cc9203bfSDan Williams { 19232e5da889SDan Williams struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe; 192489a7301fSDan Williams const struct sci_oem_params *oem = &ihost->oem_parameters; 1925dc00c8b6SDan Williams struct pci_dev *pdev = ihost->pdev; 1926cc9203bfSDan Williams u32 afe_status; 1927cc9203bfSDan Williams u32 phy_id; 19289fee607fSJeff Skirvin unsigned char cable_selection_mask = *to_cable_select(ihost); 1929cc9203bfSDan Williams 1930cc9203bfSDan Williams /* Clear DFX Status registers */ 19312e5da889SDan Williams writel(0x0081000f, &afe->afe_dfx_master_control0); 1932cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1933cc9203bfSDan Williams 1934afd13a1fSJeff Skirvin if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) { 1935cc9203bfSDan Williams /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement 19362e5da889SDan Williams * Timer, PM Stagger Timer 19372e5da889SDan Williams */ 1938afd13a1fSJeff Skirvin writel(0x0007FFFF, &afe->afe_pmsn_master_control2); 1939cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1940cc9203bfSDan Williams } 1941cc9203bfSDan Williams 1942cc9203bfSDan Williams /* Configure bias currents to normal */ 1943dc00c8b6SDan Williams if (is_a2(pdev)) 19442e5da889SDan Williams writel(0x00005A00, &afe->afe_bias_control); 1945dc00c8b6SDan Williams else if (is_b0(pdev) || is_c0(pdev)) 19462e5da889SDan Williams writel(0x00005F00, &afe->afe_bias_control); 1947afd13a1fSJeff Skirvin else if (is_c1(pdev)) 1948afd13a1fSJeff Skirvin writel(0x00005500, &afe->afe_bias_control); 1949cc9203bfSDan Williams 1950cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1951cc9203bfSDan Williams 1952cc9203bfSDan Williams /* Enable PLL */ 1953afd13a1fSJeff Skirvin if (is_a2(pdev)) 19542e5da889SDan Williams writel(0x80040908, &afe->afe_pll_control0); 1955afd13a1fSJeff Skirvin else if (is_b0(pdev) || is_c0(pdev)) 1956afd13a1fSJeff Skirvin writel(0x80040A08, &afe->afe_pll_control0); 1957afd13a1fSJeff Skirvin else if (is_c1(pdev)) { 1958afd13a1fSJeff Skirvin writel(0x80000B08, &afe->afe_pll_control0); 1959afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 1960afd13a1fSJeff Skirvin writel(0x00000B08, &afe->afe_pll_control0); 1961afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 1962afd13a1fSJeff Skirvin writel(0x80000B08, &afe->afe_pll_control0); 1963afd13a1fSJeff Skirvin } 1964cc9203bfSDan Williams 1965cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1966cc9203bfSDan Williams 1967cc9203bfSDan Williams /* Wait for the PLL to lock */ 1968cc9203bfSDan Williams do { 19692e5da889SDan Williams afe_status = readl(&afe->afe_common_block_status); 1970cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1971cc9203bfSDan Williams } while ((afe_status & 0x00001000) == 0); 1972cc9203bfSDan Williams 1973dc00c8b6SDan Williams if (is_a2(pdev)) { 19742e5da889SDan Williams /* Shorten SAS SNW lock time (RxLock timer value from 76 19752e5da889SDan Williams * us to 50 us) 19762e5da889SDan Williams */ 19772e5da889SDan Williams writel(0x7bcc96ad, &afe->afe_pmsn_master_control0); 1978cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1979cc9203bfSDan Williams } 1980cc9203bfSDan Williams 1981cc9203bfSDan Williams for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { 19826734092eSDan Carpenter struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_id]; 1983cc9203bfSDan Williams const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; 1984afd13a1fSJeff Skirvin int cable_length_long = 1985afd13a1fSJeff Skirvin is_long_cable(phy_id, cable_selection_mask); 1986afd13a1fSJeff Skirvin int cable_length_medium = 1987afd13a1fSJeff Skirvin is_medium_cable(phy_id, cable_selection_mask); 1988cc9203bfSDan Williams 1989afd13a1fSJeff Skirvin if (is_a2(pdev)) { 19902e5da889SDan Williams /* All defaults, except the Receive Word 19912e5da889SDan Williams * Alignament/Comma Detect Enable....(0xe800) 19922e5da889SDan Williams */ 19932e5da889SDan Williams writel(0x00004512, &xcvr->afe_xcvr_control0); 1994cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1995cc9203bfSDan Williams 19962e5da889SDan Williams writel(0x0050100F, &xcvr->afe_xcvr_control1); 1997cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 1998afd13a1fSJeff Skirvin } else if (is_b0(pdev)) { 1999afd13a1fSJeff Skirvin /* Configure transmitter SSC parameters */ 2000afd13a1fSJeff Skirvin writel(0x00030000, &xcvr->afe_tx_ssc_control); 2001afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2002afd13a1fSJeff Skirvin } else if (is_c0(pdev)) { 2003afd13a1fSJeff Skirvin /* Configure transmitter SSC parameters */ 2004afd13a1fSJeff Skirvin writel(0x00010202, &xcvr->afe_tx_ssc_control); 2005afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2006afd13a1fSJeff Skirvin 2007afd13a1fSJeff Skirvin /* All defaults, except the Receive Word 2008afd13a1fSJeff Skirvin * Alignament/Comma Detect Enable....(0xe800) 2009afd13a1fSJeff Skirvin */ 2010afd13a1fSJeff Skirvin writel(0x00014500, &xcvr->afe_xcvr_control0); 2011afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2012afd13a1fSJeff Skirvin } else if (is_c1(pdev)) { 2013afd13a1fSJeff Skirvin /* Configure transmitter SSC parameters */ 2014afd13a1fSJeff Skirvin writel(0x00010202, &xcvr->afe_tx_ssc_control); 2015afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2016afd13a1fSJeff Skirvin 2017afd13a1fSJeff Skirvin /* All defaults, except the Receive Word 2018afd13a1fSJeff Skirvin * Alignament/Comma Detect Enable....(0xe800) 2019afd13a1fSJeff Skirvin */ 2020afd13a1fSJeff Skirvin writel(0x0001C500, &xcvr->afe_xcvr_control0); 2021afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2022cc9203bfSDan Williams } 2023cc9203bfSDan Williams 2024afd13a1fSJeff Skirvin /* Power up TX and RX out from power down (PWRDNTX and 2025afd13a1fSJeff Skirvin * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c) 20262e5da889SDan Williams */ 2027dc00c8b6SDan Williams if (is_a2(pdev)) 20282e5da889SDan Williams writel(0x000003F0, &xcvr->afe_channel_control); 2029dc00c8b6SDan Williams else if (is_b0(pdev)) { 20302e5da889SDan Williams writel(0x000003D7, &xcvr->afe_channel_control); 2031cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2032afd13a1fSJeff Skirvin 20332e5da889SDan Williams writel(0x000003D4, &xcvr->afe_channel_control); 2034afd13a1fSJeff Skirvin } else if (is_c0(pdev)) { 20352e5da889SDan Williams writel(0x000001E7, &xcvr->afe_channel_control); 2036dbb0743aSAdam Gruchala udelay(AFE_REGISTER_WRITE_DELAY); 2037afd13a1fSJeff Skirvin 20382e5da889SDan Williams writel(0x000001E4, &xcvr->afe_channel_control); 2039afd13a1fSJeff Skirvin } else if (is_c1(pdev)) { 2040afd13a1fSJeff Skirvin writel(cable_length_long ? 0x000002F7 : 0x000001F7, 2041afd13a1fSJeff Skirvin &xcvr->afe_channel_control); 2042afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2043afd13a1fSJeff Skirvin 2044afd13a1fSJeff Skirvin writel(cable_length_long ? 0x000002F4 : 0x000001F4, 2045afd13a1fSJeff Skirvin &xcvr->afe_channel_control); 2046cc9203bfSDan Williams } 2047cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2048cc9203bfSDan Williams 2049dc00c8b6SDan Williams if (is_a2(pdev)) { 2050cc9203bfSDan Williams /* Enable TX equalization (0xe824) */ 20512e5da889SDan Williams writel(0x00040000, &xcvr->afe_tx_control); 2052cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2053cc9203bfSDan Williams } 2054cc9203bfSDan Williams 2055afd13a1fSJeff Skirvin if (is_a2(pdev) || is_b0(pdev)) 2056afd13a1fSJeff Skirvin /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, 2057afd13a1fSJeff Skirvin * TPD=0x0(TX Power On), RDD=0x0(RX Detect 2058afd13a1fSJeff Skirvin * Enabled) ....(0xe800) 2059afd13a1fSJeff Skirvin */ 20602e5da889SDan Williams writel(0x00004100, &xcvr->afe_xcvr_control0); 2061afd13a1fSJeff Skirvin else if (is_c0(pdev)) 2062afd13a1fSJeff Skirvin writel(0x00014100, &xcvr->afe_xcvr_control0); 2063afd13a1fSJeff Skirvin else if (is_c1(pdev)) 2064afd13a1fSJeff Skirvin writel(0x0001C100, &xcvr->afe_xcvr_control0); 2065cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2066cc9203bfSDan Williams 2067cc9203bfSDan Williams /* Leave DFE/FFE on */ 2068dc00c8b6SDan Williams if (is_a2(pdev)) 20692e5da889SDan Williams writel(0x3F11103F, &xcvr->afe_rx_ssc_control0); 2070dc00c8b6SDan Williams else if (is_b0(pdev)) { 20712e5da889SDan Williams writel(0x3F11103F, &xcvr->afe_rx_ssc_control0); 2072cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2073cc9203bfSDan Williams /* Enable TX equalization (0xe824) */ 20742e5da889SDan Williams writel(0x00040000, &xcvr->afe_tx_control); 2075afd13a1fSJeff Skirvin } else if (is_c0(pdev)) { 2076afd13a1fSJeff Skirvin writel(0x01400C0F, &xcvr->afe_rx_ssc_control1); 2077dbb0743aSAdam Gruchala udelay(AFE_REGISTER_WRITE_DELAY); 2078dbb0743aSAdam Gruchala 20792e5da889SDan Williams writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0); 2080dbb0743aSAdam Gruchala udelay(AFE_REGISTER_WRITE_DELAY); 2081dbb0743aSAdam Gruchala 2082dbb0743aSAdam Gruchala /* Enable TX equalization (0xe824) */ 20832e5da889SDan Williams writel(0x00040000, &xcvr->afe_tx_control); 2084afd13a1fSJeff Skirvin } else if (is_c1(pdev)) { 2085afd13a1fSJeff Skirvin writel(cable_length_long ? 0x01500C0C : 2086afd13a1fSJeff Skirvin cable_length_medium ? 0x01400C0D : 0x02400C0D, 2087afd13a1fSJeff Skirvin &xcvr->afe_xcvr_control1); 2088afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2089afd13a1fSJeff Skirvin 2090afd13a1fSJeff Skirvin writel(0x000003E0, &xcvr->afe_dfx_rx_control1); 2091afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2092afd13a1fSJeff Skirvin 2093afd13a1fSJeff Skirvin writel(cable_length_long ? 0x33091C1F : 2094afd13a1fSJeff Skirvin cable_length_medium ? 0x3315181F : 0x2B17161F, 2095afd13a1fSJeff Skirvin &xcvr->afe_rx_ssc_control0); 2096afd13a1fSJeff Skirvin udelay(AFE_REGISTER_WRITE_DELAY); 2097afd13a1fSJeff Skirvin 2098afd13a1fSJeff Skirvin /* Enable TX equalization (0xe824) */ 2099afd13a1fSJeff Skirvin writel(0x00040000, &xcvr->afe_tx_control); 2100cc9203bfSDan Williams } 2101dbb0743aSAdam Gruchala 2102cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2103cc9203bfSDan Williams 21042e5da889SDan Williams writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0); 2105cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2106cc9203bfSDan Williams 21072e5da889SDan Williams writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1); 2108cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2109cc9203bfSDan Williams 21102e5da889SDan Williams writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2); 2111cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2112cc9203bfSDan Williams 21132e5da889SDan Williams writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3); 2114cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2115cc9203bfSDan Williams } 2116cc9203bfSDan Williams 2117cc9203bfSDan Williams /* Transfer control to the PEs */ 21182e5da889SDan Williams writel(0x00010f00, &afe->afe_dfx_master_control0); 2119cc9203bfSDan Williams udelay(AFE_REGISTER_WRITE_DELAY); 2120cc9203bfSDan Williams } 2121cc9203bfSDan Williams 212289a7301fSDan Williams static void sci_controller_initialize_power_control(struct isci_host *ihost) 2123cc9203bfSDan Williams { 2124d9dcb4baSDan Williams sci_init_timer(&ihost->power_control.timer, power_control_timeout); 2125cc9203bfSDan Williams 2126d9dcb4baSDan Williams memset(ihost->power_control.requesters, 0, 2127d9dcb4baSDan Williams sizeof(ihost->power_control.requesters)); 2128cc9203bfSDan Williams 2129d9dcb4baSDan Williams ihost->power_control.phys_waiting = 0; 2130d9dcb4baSDan Williams ihost->power_control.phys_granted_power = 0; 2131cc9203bfSDan Williams } 2132cc9203bfSDan Williams 213389a7301fSDan Williams static enum sci_status sci_controller_initialize(struct isci_host *ihost) 2134cc9203bfSDan Williams { 2135d9dcb4baSDan Williams struct sci_base_state_machine *sm = &ihost->sm; 21367c78da31SDan Williams enum sci_status result = SCI_FAILURE; 21377c78da31SDan Williams unsigned long i, state, val; 2138cc9203bfSDan Williams 2139d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_RESET) { 214014e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 214114e99b4aSDan Williams __func__, ihost->sm.current_state_id); 2142cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 2143cc9203bfSDan Williams } 2144cc9203bfSDan Williams 2145e301370aSEdmund Nadolski sci_change_state(sm, SCIC_INITIALIZING); 2146cc9203bfSDan Williams 2147d9dcb4baSDan Williams sci_init_timer(&ihost->phy_timer, phy_startup_timeout); 2148bb3dbdf6SEdmund Nadolski 2149d9dcb4baSDan Williams ihost->next_phy_to_start = 0; 2150d9dcb4baSDan Williams ihost->phy_startup_timer_pending = false; 2151cc9203bfSDan Williams 215289a7301fSDan Williams sci_controller_initialize_power_control(ihost); 2153cc9203bfSDan Williams 2154cc9203bfSDan Williams /* 2155cc9203bfSDan Williams * There is nothing to do here for B0 since we do not have to 2156cc9203bfSDan Williams * program the AFE registers. 2157cc9203bfSDan Williams * / @todo The AFE settings are supposed to be correct for the B0 but 2158cc9203bfSDan Williams * / presently they seem to be wrong. */ 215989a7301fSDan Williams sci_controller_afe_initialization(ihost); 2160cc9203bfSDan Williams 2161cc9203bfSDan Williams 2162cc9203bfSDan Williams /* Take the hardware out of reset */ 2163d9dcb4baSDan Williams writel(0, &ihost->smu_registers->soft_reset_control); 2164cc9203bfSDan Williams 2165cc9203bfSDan Williams /* 2166cc9203bfSDan Williams * / @todo Provide meaningfull error code for hardware failure 2167cc9203bfSDan Williams * result = SCI_FAILURE_CONTROLLER_HARDWARE; */ 21687c78da31SDan Williams for (i = 100; i >= 1; i--) { 21697c78da31SDan Williams u32 status; 2170cc9203bfSDan Williams 2171cc9203bfSDan Williams /* Loop until the hardware reports success */ 2172cc9203bfSDan Williams udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME); 2173d9dcb4baSDan Williams status = readl(&ihost->smu_registers->control_status); 2174cc9203bfSDan Williams 21757c78da31SDan Williams if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED) 21767c78da31SDan Williams break; 2177cc9203bfSDan Williams } 21787c78da31SDan Williams if (i == 0) 21797c78da31SDan Williams goto out; 2180cc9203bfSDan Williams 2181cc9203bfSDan Williams /* 2182cc9203bfSDan Williams * Determine what are the actaul device capacities that the 2183cc9203bfSDan Williams * hardware will support */ 2184d9dcb4baSDan Williams val = readl(&ihost->smu_registers->device_context_capacity); 2185cc9203bfSDan Williams 21867c78da31SDan Williams /* Record the smaller of the two capacity values */ 2187d9dcb4baSDan Williams ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS); 2188d9dcb4baSDan Williams ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS); 2189d9dcb4baSDan Williams ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES); 2190cc9203bfSDan Williams 2191cc9203bfSDan Williams /* 2192cc9203bfSDan Williams * Make all PEs that are unassigned match up with the 2193cc9203bfSDan Williams * logical ports 2194cc9203bfSDan Williams */ 2195d9dcb4baSDan Williams for (i = 0; i < ihost->logical_port_entries; i++) { 2196cc9203bfSDan Williams struct scu_port_task_scheduler_group_registers __iomem 2197d9dcb4baSDan Williams *ptsg = &ihost->scu_registers->peg0.ptsg; 2198cc9203bfSDan Williams 21997c78da31SDan Williams writel(i, &ptsg->protocol_engine[i]); 2200cc9203bfSDan Williams } 2201cc9203bfSDan Williams 2202cc9203bfSDan Williams /* Initialize hardware PCI Relaxed ordering in DMA engines */ 2203d9dcb4baSDan Williams val = readl(&ihost->scu_registers->sdma.pdma_configuration); 22047c78da31SDan Williams val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); 2205d9dcb4baSDan Williams writel(val, &ihost->scu_registers->sdma.pdma_configuration); 2206cc9203bfSDan Williams 2207d9dcb4baSDan Williams val = readl(&ihost->scu_registers->sdma.cdma_configuration); 22087c78da31SDan Williams val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); 2209d9dcb4baSDan Williams writel(val, &ihost->scu_registers->sdma.cdma_configuration); 2210cc9203bfSDan Williams 2211cc9203bfSDan Williams /* 2212cc9203bfSDan Williams * Initialize the PHYs before the PORTs because the PHY registers 2213cc9203bfSDan Williams * are accessed during the port initialization. 2214cc9203bfSDan Williams */ 22157c78da31SDan Williams for (i = 0; i < SCI_MAX_PHYS; i++) { 221689a7301fSDan Williams result = sci_phy_initialize(&ihost->phys[i], 2217d9dcb4baSDan Williams &ihost->scu_registers->peg0.pe[i].tl, 2218d9dcb4baSDan Williams &ihost->scu_registers->peg0.pe[i].ll); 22197c78da31SDan Williams if (result != SCI_SUCCESS) 22207c78da31SDan Williams goto out; 2221cc9203bfSDan Williams } 2222cc9203bfSDan Williams 2223d9dcb4baSDan Williams for (i = 0; i < ihost->logical_port_entries; i++) { 222489a7301fSDan Williams struct isci_port *iport = &ihost->ports[i]; 22257c78da31SDan Williams 222689a7301fSDan Williams iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i]; 222789a7301fSDan Williams iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0]; 222889a7301fSDan Williams iport->viit_registers = &ihost->scu_registers->peg0.viit[i]; 2229cc9203bfSDan Williams } 2230cc9203bfSDan Williams 223189a7301fSDan Williams result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent); 2232cc9203bfSDan Williams 22337c78da31SDan Williams out: 2234cc9203bfSDan Williams /* Advance the controller state machine */ 2235cc9203bfSDan Williams if (result == SCI_SUCCESS) 2236e301370aSEdmund Nadolski state = SCIC_INITIALIZED; 2237cc9203bfSDan Williams else 2238e301370aSEdmund Nadolski state = SCIC_FAILED; 2239e301370aSEdmund Nadolski sci_change_state(sm, state); 2240cc9203bfSDan Williams 2241cc9203bfSDan Williams return result; 2242cc9203bfSDan Williams } 2243cc9203bfSDan Williams 2244abec912dSDan Williams static int sci_controller_dma_alloc(struct isci_host *ihost) 2245cc9203bfSDan Williams { 2246abec912dSDan Williams struct device *dev = &ihost->pdev->dev; 2247abec912dSDan Williams size_t size; 2248abec912dSDan Williams int i; 2249cc9203bfSDan Williams 2250abec912dSDan Williams /* detect re-initialization */ 2251abec912dSDan Williams if (ihost->completion_queue) 2252abec912dSDan Williams return 0; 2253cc9203bfSDan Williams 2254abec912dSDan Williams size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32); 2255abec912dSDan Williams ihost->completion_queue = dmam_alloc_coherent(dev, size, &ihost->cq_dma, 2256abec912dSDan Williams GFP_KERNEL); 2257abec912dSDan Williams if (!ihost->completion_queue) 2258abec912dSDan Williams return -ENOMEM; 2259cc9203bfSDan Williams 2260abec912dSDan Williams size = ihost->remote_node_entries * sizeof(union scu_remote_node_context); 2261abec912dSDan Williams ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &ihost->rnc_dma, 2262abec912dSDan Williams GFP_KERNEL); 2263cc9203bfSDan Williams 2264abec912dSDan Williams if (!ihost->remote_node_context_table) 2265abec912dSDan Williams return -ENOMEM; 2266cc9203bfSDan Williams 2267abec912dSDan Williams size = ihost->task_context_entries * sizeof(struct scu_task_context), 2268abec912dSDan Williams ihost->task_context_table = dmam_alloc_coherent(dev, size, &ihost->tc_dma, 2269abec912dSDan Williams GFP_KERNEL); 2270abec912dSDan Williams if (!ihost->task_context_table) 2271abec912dSDan Williams return -ENOMEM; 2272cc9203bfSDan Williams 2273abec912dSDan Williams size = SCI_UFI_TOTAL_SIZE; 2274abec912dSDan Williams ihost->ufi_buf = dmam_alloc_coherent(dev, size, &ihost->ufi_dma, GFP_KERNEL); 2275abec912dSDan Williams if (!ihost->ufi_buf) 2276abec912dSDan Williams return -ENOMEM; 2277abec912dSDan Williams 2278abec912dSDan Williams for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) { 2279abec912dSDan Williams struct isci_request *ireq; 2280abec912dSDan Williams dma_addr_t dma; 2281abec912dSDan Williams 2282abec912dSDan Williams ireq = dmam_alloc_coherent(dev, sizeof(*ireq), &dma, GFP_KERNEL); 2283abec912dSDan Williams if (!ireq) 2284abec912dSDan Williams return -ENOMEM; 2285abec912dSDan Williams 2286abec912dSDan Williams ireq->tc = &ihost->task_context_table[i]; 2287abec912dSDan Williams ireq->owning_controller = ihost; 2288abec912dSDan Williams ireq->request_daddr = dma; 2289abec912dSDan Williams ireq->isci_host = ihost; 2290abec912dSDan Williams ihost->reqs[i] = ireq; 2291cc9203bfSDan Williams } 2292cc9203bfSDan Williams 2293abec912dSDan Williams return 0; 2294cc9203bfSDan Williams } 2295cc9203bfSDan Williams 229689a7301fSDan Williams static int sci_controller_mem_init(struct isci_host *ihost) 2297cc9203bfSDan Williams { 2298abec912dSDan Williams int err = sci_controller_dma_alloc(ihost); 2299cc9203bfSDan Williams 23007c78da31SDan Williams if (err) 23017c78da31SDan Williams return err; 2302cc9203bfSDan Williams 2303abec912dSDan Williams writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower); 2304abec912dSDan Williams writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper); 2305abec912dSDan Williams 2306abec912dSDan Williams writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower); 2307abec912dSDan Williams writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper); 2308abec912dSDan Williams 2309abec912dSDan Williams writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower); 2310abec912dSDan Williams writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper); 2311abec912dSDan Williams 2312abec912dSDan Williams sci_unsolicited_frame_control_construct(ihost); 2313abec912dSDan Williams 2314cc9203bfSDan Williams /* 2315cc9203bfSDan Williams * Inform the silicon as to the location of the UF headers and 2316cc9203bfSDan Williams * address table. 2317cc9203bfSDan Williams */ 2318d9dcb4baSDan Williams writel(lower_32_bits(ihost->uf_control.headers.physical_address), 2319d9dcb4baSDan Williams &ihost->scu_registers->sdma.uf_header_base_address_lower); 2320d9dcb4baSDan Williams writel(upper_32_bits(ihost->uf_control.headers.physical_address), 2321d9dcb4baSDan Williams &ihost->scu_registers->sdma.uf_header_base_address_upper); 2322cc9203bfSDan Williams 2323d9dcb4baSDan Williams writel(lower_32_bits(ihost->uf_control.address_table.physical_address), 2324d9dcb4baSDan Williams &ihost->scu_registers->sdma.uf_address_table_lower); 2325d9dcb4baSDan Williams writel(upper_32_bits(ihost->uf_control.address_table.physical_address), 2326d9dcb4baSDan Williams &ihost->scu_registers->sdma.uf_address_table_upper); 2327cc9203bfSDan Williams 2328cc9203bfSDan Williams return 0; 2329cc9203bfSDan Williams } 2330cc9203bfSDan Williams 2331abec912dSDan Williams /** 2332abec912dSDan Williams * isci_host_init - (re-)initialize hardware and internal (private) state 2333abec912dSDan Williams * @ihost: host to init 2334abec912dSDan Williams * 2335abec912dSDan Williams * Any public facing objects (like asd_sas_port, and asd_sas_phys), or 2336abec912dSDan Williams * one-time initialization objects like locks and waitqueues, are 2337abec912dSDan Williams * not touched (they are initialized in isci_host_alloc) 2338abec912dSDan Williams */ 2339d9dcb4baSDan Williams int isci_host_init(struct isci_host *ihost) 23406f231ddaSDan Williams { 2341abec912dSDan Williams int i, err; 23426f231ddaSDan Williams enum sci_status status; 23436f231ddaSDan Williams 23442396a265SDan Williams spin_lock_irq(&ihost->scic_lock); 2345abec912dSDan Williams status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost)); 23462396a265SDan Williams spin_unlock_irq(&ihost->scic_lock); 23476f231ddaSDan Williams if (status != SCI_SUCCESS) { 2348d9dcb4baSDan Williams dev_err(&ihost->pdev->dev, 234989a7301fSDan Williams "%s: sci_controller_construct failed - status = %x\n", 23506f231ddaSDan Williams __func__, 23516f231ddaSDan Williams status); 2352858d4aa7SDave Jiang return -ENODEV; 23536f231ddaSDan Williams } 23546f231ddaSDan Williams 2355d9dcb4baSDan Williams spin_lock_irq(&ihost->scic_lock); 235689a7301fSDan Williams status = sci_controller_initialize(ihost); 2357d9dcb4baSDan Williams spin_unlock_irq(&ihost->scic_lock); 23587c40a803SDan Williams if (status != SCI_SUCCESS) { 2359d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 236089a7301fSDan Williams "%s: sci_controller_initialize failed -" 23617c40a803SDan Williams " status = 0x%x\n", 23627c40a803SDan Williams __func__, status); 23637c40a803SDan Williams return -ENODEV; 23647c40a803SDan Williams } 23657c40a803SDan Williams 236689a7301fSDan Williams err = sci_controller_mem_init(ihost); 23676f231ddaSDan Williams if (err) 2368858d4aa7SDave Jiang return err; 23696f231ddaSDan Williams 2370ad4f4c1dSDan Williams /* enable sgpio */ 2371ad4f4c1dSDan Williams writel(1, &ihost->scu_registers->peg0.sgpio.interface_control); 2372ad4f4c1dSDan Williams for (i = 0; i < isci_gpio_count(ihost); i++) 2373ad4f4c1dSDan Williams writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]); 2374ad4f4c1dSDan Williams writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code); 2375ad4f4c1dSDan Williams 2376858d4aa7SDave Jiang return 0; 23776f231ddaSDan Williams } 2378cc9203bfSDan Williams 237989a7301fSDan Williams void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport, 238089a7301fSDan Williams struct isci_phy *iphy) 2381cc9203bfSDan Williams { 2382d9dcb4baSDan Williams switch (ihost->sm.current_state_id) { 2383e301370aSEdmund Nadolski case SCIC_STARTING: 2384d9dcb4baSDan Williams sci_del_timer(&ihost->phy_timer); 2385d9dcb4baSDan Williams ihost->phy_startup_timer_pending = false; 2386d9dcb4baSDan Williams ihost->port_agent.link_up_handler(ihost, &ihost->port_agent, 2387ffe191c9SDan Williams iport, iphy); 238889a7301fSDan Williams sci_controller_start_next_phy(ihost); 2389cc9203bfSDan Williams break; 2390e301370aSEdmund Nadolski case SCIC_READY: 2391d9dcb4baSDan Williams ihost->port_agent.link_up_handler(ihost, &ihost->port_agent, 2392ffe191c9SDan Williams iport, iphy); 2393cc9203bfSDan Williams break; 2394cc9203bfSDan Williams default: 2395d9dcb4baSDan Williams dev_dbg(&ihost->pdev->dev, 2396cc9203bfSDan Williams "%s: SCIC Controller linkup event from phy %d in " 239785280955SDan Williams "unexpected state %d\n", __func__, iphy->phy_index, 2398d9dcb4baSDan Williams ihost->sm.current_state_id); 2399cc9203bfSDan Williams } 2400cc9203bfSDan Williams } 2401cc9203bfSDan Williams 240289a7301fSDan Williams void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport, 240389a7301fSDan Williams struct isci_phy *iphy) 2404cc9203bfSDan Williams { 2405d9dcb4baSDan Williams switch (ihost->sm.current_state_id) { 2406e301370aSEdmund Nadolski case SCIC_STARTING: 2407e301370aSEdmund Nadolski case SCIC_READY: 2408d9dcb4baSDan Williams ihost->port_agent.link_down_handler(ihost, &ihost->port_agent, 2409ffe191c9SDan Williams iport, iphy); 2410cc9203bfSDan Williams break; 2411cc9203bfSDan Williams default: 2412d9dcb4baSDan Williams dev_dbg(&ihost->pdev->dev, 2413cc9203bfSDan Williams "%s: SCIC Controller linkdown event from phy %d in " 2414cc9203bfSDan Williams "unexpected state %d\n", 2415cc9203bfSDan Williams __func__, 241685280955SDan Williams iphy->phy_index, 2417d9dcb4baSDan Williams ihost->sm.current_state_id); 2418cc9203bfSDan Williams } 2419cc9203bfSDan Williams } 2420cc9203bfSDan Williams 2421eb608c3cSDan Williams bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost) 2422cc9203bfSDan Williams { 2423cc9203bfSDan Williams u32 index; 2424cc9203bfSDan Williams 2425d9dcb4baSDan Williams for (index = 0; index < ihost->remote_node_entries; index++) { 2426d9dcb4baSDan Williams if ((ihost->device_table[index] != NULL) && 2427d9dcb4baSDan Williams (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING)) 2428cc9203bfSDan Williams return true; 2429cc9203bfSDan Williams } 2430cc9203bfSDan Williams 2431cc9203bfSDan Williams return false; 2432cc9203bfSDan Williams } 2433cc9203bfSDan Williams 243489a7301fSDan Williams void sci_controller_remote_device_stopped(struct isci_host *ihost, 243578a6f06eSDan Williams struct isci_remote_device *idev) 2436cc9203bfSDan Williams { 2437d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_STOPPING) { 2438d9dcb4baSDan Williams dev_dbg(&ihost->pdev->dev, 2439cc9203bfSDan Williams "SCIC Controller 0x%p remote device stopped event " 2440cc9203bfSDan Williams "from device 0x%p in unexpected state %d\n", 2441d9dcb4baSDan Williams ihost, idev, 2442d9dcb4baSDan Williams ihost->sm.current_state_id); 2443cc9203bfSDan Williams return; 2444cc9203bfSDan Williams } 2445cc9203bfSDan Williams 244689a7301fSDan Williams if (!sci_controller_has_remote_devices_stopping(ihost)) 2447eb608c3cSDan Williams isci_host_stop_complete(ihost); 2448cc9203bfSDan Williams } 2449cc9203bfSDan Williams 245089a7301fSDan Williams void sci_controller_post_request(struct isci_host *ihost, u32 request) 2451cc9203bfSDan Williams { 245289a7301fSDan Williams dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n", 245389a7301fSDan Williams __func__, ihost->id, request); 2454cc9203bfSDan Williams 2455d9dcb4baSDan Williams writel(request, &ihost->smu_registers->post_context_port); 2456cc9203bfSDan Williams } 2457cc9203bfSDan Williams 245889a7301fSDan Williams struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag) 2459cc9203bfSDan Williams { 2460cc9203bfSDan Williams u16 task_index; 2461cc9203bfSDan Williams u16 task_sequence; 2462cc9203bfSDan Williams 2463dd047c8eSDan Williams task_index = ISCI_TAG_TCI(io_tag); 2464cc9203bfSDan Williams 2465d9dcb4baSDan Williams if (task_index < ihost->task_context_entries) { 2466d9dcb4baSDan Williams struct isci_request *ireq = ihost->reqs[task_index]; 2467db056250SDan Williams 2468db056250SDan Williams if (test_bit(IREQ_ACTIVE, &ireq->flags)) { 2469dd047c8eSDan Williams task_sequence = ISCI_TAG_SEQ(io_tag); 2470cc9203bfSDan Williams 2471d9dcb4baSDan Williams if (task_sequence == ihost->io_request_sequence[task_index]) 24725076a1a9SDan Williams return ireq; 2473cc9203bfSDan Williams } 2474cc9203bfSDan Williams } 2475cc9203bfSDan Williams 2476cc9203bfSDan Williams return NULL; 2477cc9203bfSDan Williams } 2478cc9203bfSDan Williams 2479cc9203bfSDan Williams /** 2480*44b7ca96SLee Jones * sci_controller_allocate_remote_node_context() 2481cc9203bfSDan Williams * This method allocates remote node index and the reserves the remote node 2482cc9203bfSDan Williams * context space for use. This method can fail if there are no more remote 2483cc9203bfSDan Williams * node index available. 2484*44b7ca96SLee Jones * @ihost: This is the controller object which contains the set of 2485cc9203bfSDan Williams * free remote node ids 2486*44b7ca96SLee Jones * @idev: This is the device object which is requesting the a remote node 2487cc9203bfSDan Williams * id 2488cc9203bfSDan Williams * @node_id: This is the remote node id that is assinged to the device if one 2489cc9203bfSDan Williams * is available 2490cc9203bfSDan Williams * 2491cc9203bfSDan Williams * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote 2492cc9203bfSDan Williams * node index available. 2493cc9203bfSDan Williams */ 249489a7301fSDan Williams enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost, 249578a6f06eSDan Williams struct isci_remote_device *idev, 2496cc9203bfSDan Williams u16 *node_id) 2497cc9203bfSDan Williams { 2498cc9203bfSDan Williams u16 node_index; 249989a7301fSDan Williams u32 remote_node_count = sci_remote_device_node_count(idev); 2500cc9203bfSDan Williams 250189a7301fSDan Williams node_index = sci_remote_node_table_allocate_remote_node( 2502d9dcb4baSDan Williams &ihost->available_remote_nodes, remote_node_count 2503cc9203bfSDan Williams ); 2504cc9203bfSDan Williams 2505cc9203bfSDan Williams if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { 2506d9dcb4baSDan Williams ihost->device_table[node_index] = idev; 2507cc9203bfSDan Williams 2508cc9203bfSDan Williams *node_id = node_index; 2509cc9203bfSDan Williams 2510cc9203bfSDan Williams return SCI_SUCCESS; 2511cc9203bfSDan Williams } 2512cc9203bfSDan Williams 2513cc9203bfSDan Williams return SCI_FAILURE_INSUFFICIENT_RESOURCES; 2514cc9203bfSDan Williams } 2515cc9203bfSDan Williams 251689a7301fSDan Williams void sci_controller_free_remote_node_context(struct isci_host *ihost, 251778a6f06eSDan Williams struct isci_remote_device *idev, 2518cc9203bfSDan Williams u16 node_id) 2519cc9203bfSDan Williams { 252089a7301fSDan Williams u32 remote_node_count = sci_remote_device_node_count(idev); 2521cc9203bfSDan Williams 2522d9dcb4baSDan Williams if (ihost->device_table[node_id] == idev) { 2523d9dcb4baSDan Williams ihost->device_table[node_id] = NULL; 2524cc9203bfSDan Williams 252589a7301fSDan Williams sci_remote_node_table_release_remote_node_index( 2526d9dcb4baSDan Williams &ihost->available_remote_nodes, remote_node_count, node_id 2527cc9203bfSDan Williams ); 2528cc9203bfSDan Williams } 2529cc9203bfSDan Williams } 2530cc9203bfSDan Williams 253189a7301fSDan Williams void sci_controller_copy_sata_response(void *response_buffer, 2532cc9203bfSDan Williams void *frame_header, 2533cc9203bfSDan Williams void *frame_buffer) 2534cc9203bfSDan Williams { 253589a7301fSDan Williams /* XXX type safety? */ 2536cc9203bfSDan Williams memcpy(response_buffer, frame_header, sizeof(u32)); 2537cc9203bfSDan Williams 2538cc9203bfSDan Williams memcpy(response_buffer + sizeof(u32), 2539cc9203bfSDan Williams frame_buffer, 2540cc9203bfSDan Williams sizeof(struct dev_to_host_fis) - sizeof(u32)); 2541cc9203bfSDan Williams } 2542cc9203bfSDan Williams 254389a7301fSDan Williams void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index) 2544cc9203bfSDan Williams { 254589a7301fSDan Williams if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index)) 2546d9dcb4baSDan Williams writel(ihost->uf_control.get, 2547d9dcb4baSDan Williams &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); 2548cc9203bfSDan Williams } 2549cc9203bfSDan Williams 2550312e0c24SDan Williams void isci_tci_free(struct isci_host *ihost, u16 tci) 2551312e0c24SDan Williams { 2552312e0c24SDan Williams u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1); 2553312e0c24SDan Williams 2554312e0c24SDan Williams ihost->tci_pool[tail] = tci; 2555312e0c24SDan Williams ihost->tci_tail = tail + 1; 2556312e0c24SDan Williams } 2557312e0c24SDan Williams 2558312e0c24SDan Williams static u16 isci_tci_alloc(struct isci_host *ihost) 2559312e0c24SDan Williams { 2560312e0c24SDan Williams u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1); 2561312e0c24SDan Williams u16 tci = ihost->tci_pool[head]; 2562312e0c24SDan Williams 2563312e0c24SDan Williams ihost->tci_head = head + 1; 2564312e0c24SDan Williams return tci; 2565312e0c24SDan Williams } 2566312e0c24SDan Williams 2567312e0c24SDan Williams static u16 isci_tci_space(struct isci_host *ihost) 2568312e0c24SDan Williams { 2569312e0c24SDan Williams return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); 2570312e0c24SDan Williams } 2571312e0c24SDan Williams 2572312e0c24SDan Williams u16 isci_alloc_tag(struct isci_host *ihost) 2573312e0c24SDan Williams { 2574312e0c24SDan Williams if (isci_tci_space(ihost)) { 2575312e0c24SDan Williams u16 tci = isci_tci_alloc(ihost); 2576d9dcb4baSDan Williams u8 seq = ihost->io_request_sequence[tci]; 2577312e0c24SDan Williams 2578312e0c24SDan Williams return ISCI_TAG(seq, tci); 2579312e0c24SDan Williams } 2580312e0c24SDan Williams 2581312e0c24SDan Williams return SCI_CONTROLLER_INVALID_IO_TAG; 2582312e0c24SDan Williams } 2583312e0c24SDan Williams 2584312e0c24SDan Williams enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag) 2585312e0c24SDan Williams { 2586312e0c24SDan Williams u16 tci = ISCI_TAG_TCI(io_tag); 2587312e0c24SDan Williams u16 seq = ISCI_TAG_SEQ(io_tag); 2588312e0c24SDan Williams 2589312e0c24SDan Williams /* prevent tail from passing head */ 2590312e0c24SDan Williams if (isci_tci_active(ihost) == 0) 2591312e0c24SDan Williams return SCI_FAILURE_INVALID_IO_TAG; 2592312e0c24SDan Williams 2593d9dcb4baSDan Williams if (seq == ihost->io_request_sequence[tci]) { 2594d9dcb4baSDan Williams ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1); 2595312e0c24SDan Williams 2596312e0c24SDan Williams isci_tci_free(ihost, tci); 2597312e0c24SDan Williams 2598312e0c24SDan Williams return SCI_SUCCESS; 2599312e0c24SDan Williams } 2600312e0c24SDan Williams return SCI_FAILURE_INVALID_IO_TAG; 2601312e0c24SDan Williams } 2602312e0c24SDan Williams 260389a7301fSDan Williams enum sci_status sci_controller_start_io(struct isci_host *ihost, 260478a6f06eSDan Williams struct isci_remote_device *idev, 26055076a1a9SDan Williams struct isci_request *ireq) 2606cc9203bfSDan Williams { 2607cc9203bfSDan Williams enum sci_status status; 2608cc9203bfSDan Williams 2609d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_READY) { 261014e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 261114e99b4aSDan Williams __func__, ihost->sm.current_state_id); 2612cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 2613cc9203bfSDan Williams } 2614cc9203bfSDan Williams 261589a7301fSDan Williams status = sci_remote_device_start_io(ihost, idev, ireq); 2616cc9203bfSDan Williams if (status != SCI_SUCCESS) 2617cc9203bfSDan Williams return status; 2618cc9203bfSDan Williams 26195076a1a9SDan Williams set_bit(IREQ_ACTIVE, &ireq->flags); 262034a99158SDan Williams sci_controller_post_request(ihost, ireq->post_context); 2621cc9203bfSDan Williams return SCI_SUCCESS; 2622cc9203bfSDan Williams } 2623cc9203bfSDan Williams 262489a7301fSDan Williams enum sci_status sci_controller_terminate_request(struct isci_host *ihost, 262578a6f06eSDan Williams struct isci_remote_device *idev, 26265076a1a9SDan Williams struct isci_request *ireq) 2627cc9203bfSDan Williams { 262889a7301fSDan Williams /* terminate an ongoing (i.e. started) core IO request. This does not 262989a7301fSDan Williams * abort the IO request at the target, but rather removes the IO 263089a7301fSDan Williams * request from the host controller. 263189a7301fSDan Williams */ 2632cc9203bfSDan Williams enum sci_status status; 2633cc9203bfSDan Williams 2634d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_READY) { 263514e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 263614e99b4aSDan Williams __func__, ihost->sm.current_state_id); 2637cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 2638cc9203bfSDan Williams } 263989a7301fSDan Williams status = sci_io_request_terminate(ireq); 264014aaa9f0SJeff Skirvin 264114aaa9f0SJeff Skirvin dev_dbg(&ihost->pdev->dev, "%s: status=%d; ireq=%p; flags=%lx\n", 264214aaa9f0SJeff Skirvin __func__, status, ireq, ireq->flags); 264314aaa9f0SJeff Skirvin 2644726980d5SJeff Skirvin if ((status == SCI_SUCCESS) && 2645726980d5SJeff Skirvin !test_bit(IREQ_PENDING_ABORT, &ireq->flags) && 2646726980d5SJeff Skirvin !test_and_set_bit(IREQ_TC_ABORT_POSTED, &ireq->flags)) { 2647726980d5SJeff Skirvin /* Utilize the original post context command and or in the 2648726980d5SJeff Skirvin * POST_TC_ABORT request sub-type. 2649cc9203bfSDan Williams */ 2650726980d5SJeff Skirvin sci_controller_post_request( 2651726980d5SJeff Skirvin ihost, ireq->post_context | 2652726980d5SJeff Skirvin SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT); 2653726980d5SJeff Skirvin } 2654726980d5SJeff Skirvin return status; 2655cc9203bfSDan Williams } 2656cc9203bfSDan Williams 2657cc9203bfSDan Williams /** 265889a7301fSDan Williams * sci_controller_complete_io() - This method will perform core specific 2659cc9203bfSDan Williams * completion operations for an IO request. After this method is invoked, 2660cc9203bfSDan Williams * the user should consider the IO request as invalid until it is properly 2661cc9203bfSDan Williams * reused (i.e. re-constructed). 266289a7301fSDan Williams * @ihost: The handle to the controller object for which to complete the 2663cc9203bfSDan Williams * IO request. 266489a7301fSDan Williams * @idev: The handle to the remote device object for which to complete 2665cc9203bfSDan Williams * the IO request. 266689a7301fSDan Williams * @ireq: the handle to the io request object to complete. 2667cc9203bfSDan Williams */ 266889a7301fSDan Williams enum sci_status sci_controller_complete_io(struct isci_host *ihost, 266978a6f06eSDan Williams struct isci_remote_device *idev, 26705076a1a9SDan Williams struct isci_request *ireq) 2671cc9203bfSDan Williams { 2672cc9203bfSDan Williams enum sci_status status; 2673cc9203bfSDan Williams 2674d9dcb4baSDan Williams switch (ihost->sm.current_state_id) { 2675e301370aSEdmund Nadolski case SCIC_STOPPING: 2676cc9203bfSDan Williams /* XXX: Implement this function */ 2677cc9203bfSDan Williams return SCI_FAILURE; 2678e301370aSEdmund Nadolski case SCIC_READY: 267989a7301fSDan Williams status = sci_remote_device_complete_io(ihost, idev, ireq); 2680cc9203bfSDan Williams if (status != SCI_SUCCESS) 2681cc9203bfSDan Williams return status; 2682cc9203bfSDan Williams 26835076a1a9SDan Williams clear_bit(IREQ_ACTIVE, &ireq->flags); 2684cc9203bfSDan Williams return SCI_SUCCESS; 2685cc9203bfSDan Williams default: 268614e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 268714e99b4aSDan Williams __func__, ihost->sm.current_state_id); 2688cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 2689cc9203bfSDan Williams } 2690cc9203bfSDan Williams 2691cc9203bfSDan Williams } 2692cc9203bfSDan Williams 269389a7301fSDan Williams enum sci_status sci_controller_continue_io(struct isci_request *ireq) 2694cc9203bfSDan Williams { 2695d9dcb4baSDan Williams struct isci_host *ihost = ireq->owning_controller; 2696cc9203bfSDan Williams 2697d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_READY) { 269814e99b4aSDan Williams dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n", 269914e99b4aSDan Williams __func__, ihost->sm.current_state_id); 2700cc9203bfSDan Williams return SCI_FAILURE_INVALID_STATE; 2701cc9203bfSDan Williams } 2702cc9203bfSDan Williams 27035076a1a9SDan Williams set_bit(IREQ_ACTIVE, &ireq->flags); 270434a99158SDan Williams sci_controller_post_request(ihost, ireq->post_context); 2705cc9203bfSDan Williams return SCI_SUCCESS; 2706cc9203bfSDan Williams } 2707cc9203bfSDan Williams 2708cc9203bfSDan Williams /** 270989a7301fSDan Williams * sci_controller_start_task() - This method is called by the SCIC user to 2710cc9203bfSDan Williams * send/start a framework task management request. 2711*44b7ca96SLee Jones * @ihost: the handle to the controller object for which to start the task 2712cc9203bfSDan Williams * management request. 2713*44b7ca96SLee Jones * @idev: the handle to the remote device object for which to start 2714cc9203bfSDan Williams * the task management request. 2715*44b7ca96SLee Jones * @ireq: the handle to the task request object to start. 2716cc9203bfSDan Williams */ 2717362b5da3SNathan Chancellor enum sci_status sci_controller_start_task(struct isci_host *ihost, 271878a6f06eSDan Williams struct isci_remote_device *idev, 27195076a1a9SDan Williams struct isci_request *ireq) 2720cc9203bfSDan Williams { 2721cc9203bfSDan Williams enum sci_status status; 2722cc9203bfSDan Williams 2723d9dcb4baSDan Williams if (ihost->sm.current_state_id != SCIC_READY) { 2724d9dcb4baSDan Williams dev_warn(&ihost->pdev->dev, 2725cc9203bfSDan Williams "%s: SCIC Controller starting task from invalid " 2726cc9203bfSDan Williams "state\n", 2727cc9203bfSDan Williams __func__); 2728362b5da3SNathan Chancellor return SCI_FAILURE_INVALID_STATE; 2729cc9203bfSDan Williams } 2730cc9203bfSDan Williams 273189a7301fSDan Williams status = sci_remote_device_start_task(ihost, idev, ireq); 2732cc9203bfSDan Williams switch (status) { 2733cc9203bfSDan Williams case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS: 2734db056250SDan Williams set_bit(IREQ_ACTIVE, &ireq->flags); 2735cc9203bfSDan Williams 2736cc9203bfSDan Williams /* 2737cc9203bfSDan Williams * We will let framework know this task request started successfully, 2738cc9203bfSDan Williams * although core is still woring on starting the request (to post tc when 2739cc9203bfSDan Williams * RNC is resumed.) 2740cc9203bfSDan Williams */ 2741cc9203bfSDan Williams return SCI_SUCCESS; 2742cc9203bfSDan Williams case SCI_SUCCESS: 2743db056250SDan Williams set_bit(IREQ_ACTIVE, &ireq->flags); 274434a99158SDan Williams sci_controller_post_request(ihost, ireq->post_context); 2745cc9203bfSDan Williams break; 2746cc9203bfSDan Williams default: 2747cc9203bfSDan Williams break; 2748cc9203bfSDan Williams } 2749cc9203bfSDan Williams 2750cc9203bfSDan Williams return status; 2751cc9203bfSDan Williams } 2752ad4f4c1dSDan Williams 2753ad4f4c1dSDan Williams static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data) 2754ad4f4c1dSDan Williams { 2755ad4f4c1dSDan Williams int d; 2756ad4f4c1dSDan Williams 2757ad4f4c1dSDan Williams /* no support for TX_GP_CFG */ 2758ad4f4c1dSDan Williams if (reg_index == 0) 2759ad4f4c1dSDan Williams return -EINVAL; 2760ad4f4c1dSDan Williams 2761ad4f4c1dSDan Williams for (d = 0; d < isci_gpio_count(ihost); d++) { 2762ad4f4c1dSDan Williams u32 val = 0x444; /* all ODx.n clear */ 2763ad4f4c1dSDan Williams int i; 2764ad4f4c1dSDan Williams 2765ad4f4c1dSDan Williams for (i = 0; i < 3; i++) { 27662976fbb6SColin Ian King int bit; 2767ad4f4c1dSDan Williams 2768ad4f4c1dSDan Williams bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i), 2769ad4f4c1dSDan Williams write_data, reg_index, 2770ad4f4c1dSDan Williams reg_count); 2771ad4f4c1dSDan Williams if (bit < 0) 2772ad4f4c1dSDan Williams break; 2773ad4f4c1dSDan Williams 2774ad4f4c1dSDan Williams /* if od is set, clear the 'invert' bit */ 2775ad4f4c1dSDan Williams val &= ~(bit << ((i << 2) + 2)); 2776ad4f4c1dSDan Williams } 2777ad4f4c1dSDan Williams 2778ad4f4c1dSDan Williams if (i < 3) 2779ad4f4c1dSDan Williams break; 2780ad4f4c1dSDan Williams writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]); 2781ad4f4c1dSDan Williams } 2782ad4f4c1dSDan Williams 2783ad4f4c1dSDan Williams /* unless reg_index is > 1, we should always be able to write at 2784ad4f4c1dSDan Williams * least one register 2785ad4f4c1dSDan Williams */ 2786ad4f4c1dSDan Williams return d > 0; 2787ad4f4c1dSDan Williams } 2788ad4f4c1dSDan Williams 2789ad4f4c1dSDan Williams int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index, 2790ad4f4c1dSDan Williams u8 reg_count, u8 *write_data) 2791ad4f4c1dSDan Williams { 2792ad4f4c1dSDan Williams struct isci_host *ihost = sas_ha->lldd_ha; 2793ad4f4c1dSDan Williams int written; 2794ad4f4c1dSDan Williams 2795ad4f4c1dSDan Williams switch (reg_type) { 2796ad4f4c1dSDan Williams case SAS_GPIO_REG_TX_GP: 2797ad4f4c1dSDan Williams written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data); 2798ad4f4c1dSDan Williams break; 2799ad4f4c1dSDan Williams default: 2800ad4f4c1dSDan Williams written = -EINVAL; 2801ad4f4c1dSDan Williams } 2802ad4f4c1dSDan Williams 2803ad4f4c1dSDan Williams return written; 2804ad4f4c1dSDan Williams } 2805